TW201725574A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device is disclosed and comprises: a data driver is configured for receiving a data signal and a clock signal to output at least one pixel signals and a output signal; and a gate driver electrically connected to the data driver wherein the gate driver is configured for receiving the output signal to output at least one gate driving signals and a control signal to the data driver.

Description

LCD Monitor

The present invention relates to the field of display technology, and in particular to a liquid crystal display in which a data driving integrated circuit and a gate driving circuit are integrated on a substrate.

In view of the advantages of lightness, thinness and low radiation, liquid crystal displays have gradually replaced cathode ray tube (CRT) displays and become the mainstream of computer screens and televisions. Typical liquid crystal displays typically include a glass substrate, a source driver, a gate driver, a printed circuit board, and a flexible circuit board. The source driving integrated circuit and the gate driving integrated circuit are disposed on the glass substrate and electrically coupled to the printed circuit board through the flexible circuit board. A timing controller is disposed on the printed circuit board to output a plurality of control signals and transmitted to the source driving integrated circuit and the gate driving integrated circuit through the flexible circuit board. In recent years, due to advances in technology, it has become more and more common to fabricate the above-described source driver and gate driver on a glass substrate, generally referred to as system on glass.

Referring to Figure 1, in order to further reduce power consumption, the system on glass (SOG) architecture will be equipped with a partial update (Partial update) function, generally using a decoder 104 (Decoder) to implement the gate drive circuit, so that you can borrow The control signal given by the system (the number of control signals depends on the resolution of the panel) determines which gate line to turn on, and can achieve partial update function. Since the decoder must provide the control signal from the system end, the more control signals need to be provided on the system side under the condition that the resolution requirement is continuously increased, the panel resolution 148*205 is taken as an example. The eight decoder control signals require only a few more control signals from the system side than the design using the shift register.

Therefore, under the trend of increasing demand for resolution, how to reduce the number of decoder control lines is an urgent problem to be solved in the field.

SUMMARY OF THE INVENTION The object of the present invention is to provide a new liquid crystal display architecture that utilizes a sample and hold circuit inherent in the data drive circuit to generate the control signals required by the decoder to overcome the problem of increased decoder control signals with resolution.

Other objects and advantages of the present invention will become apparent from the technical features disclosed herein.

In an embodiment of the present invention, a liquid crystal display includes a source driving circuit for receiving a data signal and a clock signal to output at least one pixel. a signal and a first output signal; and a gate driving circuit electrically coupled to the source driving circuit; wherein the gate driving circuit receives the first output signal output by the source driving circuit to output a plurality of gate driving The signal and a first control signal to the source driving circuit.

In an embodiment of the present invention, the source driving circuit receives the first control signal to output the at least one pixel signal, wherein the source driving circuit includes a plurality of frequency adjusting circuits and a plurality of a sample and hold circuit, the plurality of sample and hold circuits are electrically coupled to the corresponding frequency adjustment circuit and receive the data signal, a second output signal of the frequency adjustment circuit, and the first control signal to output the pixel signals .

In another embodiment of the present invention, the gate driving circuit of the liquid crystal display includes: a control signal generating circuit electrically coupled to the source driving circuit to receive the first output signal and output the first control signal respectively a second control signal and a switch control signal; a second sample and hold circuit electrically coupled to the control signal generating circuit to receive the data signal, the second control signal and the switch control signal to output a decoded signal; and a decoding The circuit is electrically coupled to the second sample and hold circuit to receive the decoded signal to output a plurality of gate drive signals.

A liquid crystal display according to another embodiment of the present invention, wherein the second sampling conversion circuit comprises: a first temporary storage circuit receiving the data signal and temporarily storing the data signal according to the second control signal; and a second temporary storage circuit The first temporary storage unit is coupled to the first temporary storage unit and the second temporary storage unit is electrically coupled to the second temporary storage unit and the second end. The decoding circuit is electrically coupled.

In an embodiment of the present invention, the first temporary storage circuit includes: a first switch circuit receiving the data signal and turning on the first switch according to the second control signal; and a second switch circuit Electrically having an output end and an input end, the input end is electrically coupled to the first switch circuit and turns on the switch circuit according to the reverse second control signal; and a reverse circuit has a first end and a The second end is electrically coupled to the input end of the second switch circuit, and the second end is electrically coupled to the output end of the second switch circuit.

In another embodiment of the present invention, the second temporary storage circuit of the liquid crystal display includes: a third switch circuit having a data receiving end and a data output end, the data receiving end receiving the data signal and according to The switch signal turns on the third switch; and a data latch circuit is electrically coupled to the data output end of the third switch.

A liquid crystal display according to another embodiment of the present invention, wherein the first sampling and holding circuit comprises: a third temporary storage circuit receiving the data signal and temporarily storing the data signal according to the second output signal; and a fourth temporary storage circuit The third temporary storage unit is coupled to the first control signal to temporarily store the data signal; and a second thrust enhancement circuit is electrically coupled to the fourth temporary storage unit to output the pixel signals.

In an embodiment of the present invention, the third temporary storage circuit includes: a third switch circuit receiving the data signal and turning on the first switch according to the second output signal; a fourth switch The circuit has an output end and an input end, the input end is electrically coupled to the first switch circuit and turns on the switch circuit according to the reversed second output signal; and a reverse circuit has a first end The second end is electrically coupled to the input end of the fourth switch circuit, and the second end is electrically coupled to the output end of the fourth switch circuit.

In another embodiment of the present invention, the liquid crystal display, wherein the fourth temporary storage circuit comprises: a fifth switch circuit having a data receiving end and a data output end, the data receiving end receiving the data signal and The third switch is turned on according to the first control signal; and a data latch circuit is electrically coupled to the data output end of the fifth switch.

In another embodiment of the invention, the liquid crystal display, wherein the first output signal is an output signal after the clock signal passes through at least one of the frequency adjustment circuits.

In another embodiment of the present invention, the liquid crystal display, wherein the decoding signal is switched from being enabled to disabled, the time before the last pixel signal is changed from being enabled to disabled, and the second time is at least one clock signal. The width.

The embodiment of the invention only needs to transmit a control signal to the gate driving circuit by the data driving circuit, and then generate a plurality of control signals by the circuit operation inside the gate driving integrated circuit to realize the control gate driving integrated circuit. Control the data drive circuit outside the normal operation; therefore, the control signal line provided by the system side can be reduced, so that the number of control signal lines does not increase greatly with the increase of the resolution, and the small size can be achieved. The need for resolution.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Referring to FIG. 2 and FIG. 3, a liquid crystal display 200 according to an embodiment of the present invention includes a display area 201, a source and source driving circuit 202, and a gate driving circuit 203. The display area 201, the source and source driving circuit 202, and the gate driving circuit 203 are disposed on the substrate 204. The substrate may be glass, soft, or a metal substrate. Each of the source driving circuits 202 is configured to provide image data to a plurality of data lines (not shown) formed on the substrate 204 and electrically coupled thereto; the gate driving system is electrically coupled to the source driving The circuit is configured to sequentially provide a gate pulse signal to a plurality of gate lines (not shown) formed on the substrate 204 and electrically coupled thereto to electrically couple the thin film transistors electrically connected to the gate lines ( The liquid crystal display device 201 further includes a system circuit 213 electrically coupled to the source driving circuit 14 and providing data signals and clocks through the data signal lines SDI1 S SDI6 and the clock signal line HCLK. The signal is supplied to the source driving circuit 202, and the gate driving circuit 203 also receives the data signals SDI1 S SDI4 as input signals and the gate driving circuit 203, wherein the system circuit 213 can be fabricated on the substrate 204 or an external system outside the substrate 204. .

The source driving circuit 202 includes a frequency adjusting circuit 208 and a plurality of first sample and hold circuits 207 electrically coupled thereto. The frequency adjusting circuit 208 can be composed of a plurality of frequency dividing circuits or a plurality of delay circuits connected in series. Taking the delay unit as an example, the clock signal provided by the system circuit 213 is received and a plurality of second output signals are outputted, and the first output signal OUT1 is outputted by the last stage, wherein the plurality of second output signals OUT2 are respectively output to Corresponding first sample and hold circuit 207, and the first output signal is output to the gate drive circuit; the plurality of first sample and hold circuits 207 receive the plurality of second output signals OUT2, data signals SDI1 S SDI6, and the gate The first control signal CTL1 outputted by the driving circuit outputs a pixel data signal to the data lines.

The gate driving circuit 203 includes a control signal generating circuit 209, a second sample and hold circuit 210, a level conversion circuit 210, and a decoding circuit 211. The control signal generating circuit 209 receives the first output output by the frequency adjusting circuit 208. The signal OUT1 outputs a first control signal CTL1, a second control signal CTL2, and a switch control signal SW. The second sampling circuit is electrically coupled to the signal generating circuit 209 and receives the second control signal CTL2, the switch control signal SW, and the data signal. SDI1~SDI4 output decoding signals D0~D3, and the number of receiving data lines is related to the number of gate lines. For example, 16 gate lines require 16 gate driving signals, so four second sampling and holding circuits are required. Each second sample-and-hold circuit needs to connect a data sequence line as an input signal, so it is necessary to receive four data signals SDI1 to SDI4. Therefore, if the number of second sample-and-hold circuits is N and the number of gate lines is M, Then, the relationship between the two is M=2 ^N ; the level conversion circuit 212 converts the level conversion of the decoded signal to the signal level used by the decoding circuit 211, and decodes the signal. The circuit 211 outputs a corresponding gate line driving signal according to the decoding signals D0-SD3 to turn on the pixel corresponding to the gate line. The level conversion circuit 212 can be selectively used according to different requirements, if the level of the decoded signal is The bit criteria applicable to the decoding circuit may not require the use of the level conversion circuit 212. Conversely, the level conversion circuit 212 may not be used if the level of the decoded signal is applied to the bit order of the decoding circuit.

Referring to FIG. 3, the control signal generating circuit 303 includes a plurality of delay circuits. The first delay circuit 301 is electrically coupled to the frequency adjusting circuit 208 to receive the first output OUT1 signal to output the second control signal CLT2 and the first delay signal De1. The second delay circuit 302 is electrically coupled to the first delay circuit and receives the first delay signal De1 to output the switch control signal SW and the second delay signal De2. The third delay circuit 303 is electrically coupled to the second delay circuit. The second delay signal De2 is received to output the first control signal CTL1.

Referring to FIG. 4, a display having 16 gate lines is taken as an example. The gate driving circuit has four second sample and hold circuits 400 electrically coupled to the data signal lines SDI1 S SDI4, and each second sample and hold circuit 400. The first temporary storage unit 401 is electrically coupled to the corresponding data signal line and temporarily stores the data signal outputted by the corresponding data signal line according to the second control signal CTL2 (HSR[20]), and the second temporary storage circuit 402 is electrically Coupling the first temporary storage unit and temporarily storing the data signal according to the switch control signal SW (HSR[21]), and the thrust enhancement circuit 403 has a first end electrically coupled to the second temporary storage unit 402 and a first For example, the second sampling and holding circuit is electrically coupled to the second sampling and holding circuit of the data line SDI1. The first register 401 is electrically coupled to the corresponding data signal line SDI1 and according to the second control signal CTL2 ( HSR[20]) temporarily stores the data signal outputted by the corresponding data signal line SDI1. The second temporary storage circuit is electrically coupled to the first temporary storage unit 401 and is temporarily controlled according to the switch control signal SW (HSR[21]). Storing the data signal and the thrust enhancement circuit 403 has a first Electrically coupled to the second register unit 402 and a second terminal electrically coupled to the decoding circuit outputs the decoded signal D0. The first temporary storage circuit 401 includes a first switching circuit SWT1, for example, a Complementary Metal-Oxide Semiconductor Field Effect Transistor (CMOSFET) switch, and electrical coupling data. The signal line SDI1 receives the data signal and turns on the first switch SWT1 according to the second control signal CTL2 (HSR[20]). The second switch circuit SWT2 has an output end and an input end. The input end is electrically coupled. The first switch circuit SWT1 is connected to the switch circuit and the reverse circuit INV1 according to the reverse second control signal CTL2 (XHSR[20]). For example, two reverse circuits can be connected in series, and have a first The second end is electrically coupled to the input end of the second switch circuit SWT2; the second end is electrically coupled to the output end of the second switch circuit SWT2, and the second temporary storage circuit includes The third switch circuit SWT3 and the fourth switch circuit SWT4, the third switch circuit SWT3 has a first data receiving end and a first data output end, and the fourth switch circuit SWT4 has a second data receiving end and a second The data receiving end is electrically coupled to the output end of the second inverting circuit in the inverting circuit INV1, and the second data receiving end is electrically coupled to the first inverting circuit in the inverting circuit INV1 The output terminal turns on the third switch and the fourth switch according to the switching signal SW (HSR[21]), the data latch circuit LAT1 has third and fourth reverse circuits, and the output of the third inverter and the fourth The input end of the inverter is electrically coupled to the first data output end, and the output end of the fourth inverter is electrically coupled to the input end of the third inverter. The data output end latches the data signal, and the thrust enhancement circuit 403 can be electrically connected in series with a plurality of reverse circuits, and is coupled to the first data output terminal for outputting the latched data. The structure of the first sample-and-hold circuit is the same as that of the second sample-and-hold circuit. The only difference is that the received signals are different. The first sample-and-hold circuit corresponds to the first switch circuit and the second switch circuit to receive the first output signal. OUT1 (HSR[22]) determines whether the switch is turned on. The part corresponding to the third switch circuit receives the first control signal CTL1 (HSR[20]) to determine whether to turn on the switch. For the sake of simplicity, the first sample will not be described again. The circuit is held, and the switching circuit is not limited to being implemented using only a switch, and an N-type metal oxide semiconductor (NMOS) switch, a P-type metal oxide semiconductor (PMOS) switch, or a CMOS switch can also be used.

Referring to FIGS. 5 to 9, the principle of operation will be described by taking the first stage of the first sample and hold circuit and the first stage of the second sample and hold circuit as an example. Referring to FIG. 5, HSR17~HSR19 are the output signals of the last three stages of the frequency adjustment circuit 208, and HSR20 (second control signal), HSR21 (switch control signal), and HSR22 (first control signal) are outputs of the control signal generating circuit 209. Signals, SDI1 ~ SDI4 are data signals.

In the T1 time period, HSR18 is at a high level, HSR19 to HSR22 are both low levels, and the first S1, the third S3, and the fourth S4 switch circuit and the second S5 switch circuit of the first sample and hold circuit are fifth S5, The six S6 and the seventh S7 switch circuits are all in a closed state, so the output of the first sample hold circuit is the previous state R35, and the output of the second sample hold circuit is the previous state D0.

Next, referring to FIG. 6, in the T2 time period, the HSR 19 is at a high level, the HSR 18 and the HSR 20 ～ HSR 22 are at a low level, the first switching circuit S1 of the first sample and hold circuit is turned on, and the second switching circuit S2 and the third switch are turned on. The circuit S3 and the fourth switching circuit S4 are turned off, so the data R37 to the A end point of the SDI1 are read in. At the same time, since the third switching circuit S3 and the fourth switching circuit S4 are turned off, the output terminal is still R35, and the fifth sampling and holding circuit is fifth. The switch circuit S5 is turned off, the sixth switch circuit S6 is turned on, the seventh switch circuit S7 is turned off, and the eighth switch circuit S8 is turned off, so the output is still in the previous state D0.

Referring to FIG. 7, in the T3 time period, the HSRs 18 to 19 are at low levels, the HSR 20 is at a high level, and the HSRs 21 to 22 are at low levels. The first switching circuit S1 of the first sample and hold circuit is turned off, and the second switching circuit S2 is closed. Turning on, the third switch circuit S3 and the fourth switch circuit S4 are turned off, so the data R37 read into SDI1 is latched at the A end point. Since the third switch circuit S3 and the fourth switch circuit S4 are turned off, the output terminal is still R35 (previous State), the fifth switch circuit S5 of the second sample hold circuit is turned on, the sixth switch circuit S6 is turned off, the seventh switch circuit S7 is turned off, and the eighth switch circuit S8 is turned off, and the data D0 to the end point B of the SDI1 are read, due to the The seven-switch circuit S7 and the eighth switch circuit S8 are turned off so that the output terminal is still D0 (previous state).

Referring to FIG. 8, in the T4 time period, the HSRs 18 to 20 are at low levels, the HSR 21 is at a high level, and the HSR 22 is at a low level. The first switching circuit S1 of the first sampling and holding circuit is turned off, and the second switching circuit S2 is turned on. The three-switch circuit S3 and the fourth switch circuit S4 are turned off, so the data R37 read into SDI1 continues to be latched at the A terminal. Since the third switch circuit S3 and the fourth switch circuit S4 are turned off, the output terminal is still R35 (previous state). The fifth switch circuit S5 of the second sample hold circuit is turned off, the sixth switch circuit S6 is turned on, the seventh switch circuit S7 and the eighth switch circuit S8 are turned on, and the data D0 read into the SDI1 is output from the end point B to the output end to decode Circuit.

Referring to FIG. 9, in the T5 time period, the HSRs 18-21 are at a low level, the HSR 22 is at a high level, the first switch circuit S1 of the first sample and hold circuit is turned off, the second switch circuit S2 is turned on, and the third switch circuit S3 and the The four-switch circuit S4 is turned on, the data signal R37 latched at the A end point is output to the output terminal through the switch circuit S4, the fifth switch circuit S5 of the second sample hold circuit is turned off, the sixth switch circuit S6 is turned on, and the seventh switch circuit S7 is turned on. The closing and the eighth switching circuit S8 are turned off, and since the seventh switching circuit S7 and the eighth switching circuit S8 are turned off, the output terminal is still D0. After the end of the T5 period, the first sample and hold circuit can output the data signal R37, and the second sample and hold circuit can output the decoded signal D0.

Referring to FIG. 10, a complete analog signal diagram of the second sample-and-hold circuit is shown. SDI1 to SDI4 are data signals output by the input signal line, second control signal (HSR20) and switch control signal (HSR21), and S115-S118 are decoded signals D0. ~D3, you can see that the switch control signal HSR21 can output the corresponding decoded signal every time it is at the high level. Continue to refer to Figure 11, S115~S118 (D0~D3) are the decoded signals, and GL1~GL16 are the gate drive signals. It can be seen that the gate drive signal can be correctly output according to the decoded signal; referring to FIG. 12A, in order to prevent the problem that the gate signal line is turned on and the data switching occurs at the same time, the data is mischarged due to the delay effect, so the output of D0 is intentionally deviated here. The transformation is arranged before the output conversion of R37. In order to further explain the interception of TA and TB time points, FIG. 12B is an enlarged view of the TA point, S114 is the data signal, S115 represents the decoding signal D0, and it can be seen that the HSR21 is low level. Change to a high level and S115 also changes from a low level to a high level. It can be seen that S114 is still at a low level and S115 is opened earlier than S114, so it can be avoided. For the problem of mischarge, refer to FIG. 12C for an enlarged view of the TB point. S114 is the data signal, and S115 represents the decoded signal D0. It can be seen that the HSR21 changes from the low level to the high level and the S115 also changes from the high level to the high level. At low level, it can be seen that S114 is still at a high level at this time, and S115 is turned off earlier than S114, so that the problem of mischarge can be avoided.

In summary, the embodiment of the present invention only needs to transmit one first output signal and four data signals to the gate driving circuit, and then the signal generating circuit, the second sampling and holding circuit, and the decoder circuit inside the gate driving circuit. To generate a plurality of gate driving signals to realize the function of the gate driving circuit; therefore, the control signal line provided by the system end can be reduced, so that the number of control signal lines does not increase greatly with the increase of the resolution. The need for small, high-resolution system panels is achieved.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

201‧‧‧ display area
202‧‧‧Source drive circuit
203‧‧ ‧ gate drive circuit
204‧‧‧Substrate
205‧‧‧Information signal line
206‧‧‧clock signal line
207‧‧‧First sample hold circuit
208‧‧‧frequency adjustment circuit
209‧‧‧Control signal generation circuit
210‧‧‧Second sample-and-hold circuit
SDI1～SDI6‧‧‧Information Signal
D0~D3‧‧‧ decoding signal
HCLK‧‧‧ clock signal
OUT1‧‧‧ first output signal
OUT2‧‧‧second output signal
CTL1‧‧‧ first control signal
CTL2‧‧‧second control signal
SW‧‧‧ switch control signal
De1‧‧‧first delay signal
De2‧‧‧second delay signal

1 is a structural view of a related art liquid crystal display. 2 is a structural view of a liquid crystal display according to an embodiment. FIG. 3 is an enlarged view of a portion of the gate driving circuit and the source driving circuit shown in FIG. 4 is a circuit diagram of a first sample hold circuit and a second sample hold circuit of another embodiment. 5 to 9 are circuit diagrams of the first sample hold circuit and the second sample hold circuit. Figure 10 is a simulation diagram of the decoded signal output. FIG. 11 is a simulation diagram of outputting a gate driving signal according to a decoded signal. 12A to 12C are simulation diagrams of decoded signal and data conversion signal output.

201‧‧‧ display area

202‧‧‧Source drive circuit

203‧‧ ‧ gate drive circuit

204‧‧‧Substrate

205‧‧‧Information signal line

206‧‧‧clock signal line

207‧‧‧First sample hold circuit

208‧‧‧frequency adjustment circuit

209‧‧‧Control signal generation circuit

210‧‧‧Second sample-and-hold circuit

Claims (14)

A liquid crystal display comprising: a source driving circuit for receiving a data signal and a clock signal for outputting at least one pixel signal and a first output signal; and a gate driving circuit electrically coupled to the drain driving And the gate driving circuit receives the first output signal outputted by the source driving circuit to output a plurality of gate driving signals and a first control signal to the source driving circuit. The liquid crystal display of claim 1, wherein the source driving circuit receives the first control signal to output the at least one pixel signal. The liquid crystal display of claim 2, wherein the source driving circuit comprises a frequency adjusting circuit and a plurality of first sample and hold circuits, wherein the plurality of sample and hold circuits are electrically coupled to the corresponding frequency adjusting circuit and Receiving the data signal, a second output signal of the frequency adjustment circuit, and the first control signal to output the pixel signals. The liquid crystal display of claim 2, wherein the gate driving circuit comprises: a control signal generating circuit electrically coupled to the source driving circuit to receive the first output signal, respectively outputting the first control signal, a second control signal and a switch control signal; a second sample and hold circuit electrically coupled to the control signal generating circuit to receive the data signal, the second control signal and the switch control signal to output a decoded signal; and a decoding circuit The second sample and hold circuit receives the decoded signal to output a plurality of gate drive signals. The liquid crystal display of claim 4, wherein the control signal generating circuit comprises: a first delay circuit receiving the first output signal and outputting the second control signal and a first delay signal; a second delay The circuit receives the first delay signal and outputs a second delay signal and the switch control signal; and a third delay circuit receives the second delay signal and outputs the first control signal. The liquid crystal display according to claim 5, wherein the number of the second sampling conversion circuits is N and the number of the gate lines is M, and the relationship between the two is M=2 ^N , wherein N, M are A positive integer greater than one. The liquid crystal display of claim 6, wherein the second sampling conversion circuit comprises: a first temporary storage circuit receiving the data signal and temporarily storing the data signal according to the second control signal; and a second temporary storage circuit Electrically coupling the first temporary storage unit and temporarily storing the data signal according to the switch control signal; and a thrust enhancement circuit having a first end electrically coupled to the second temporary storage unit and a second end electrically coupled Connect to the decoding circuit. The liquid crystal display of claim 7, wherein the first temporary storage circuit comprises: a first switching circuit receiving the data signal and conducting the first switch according to the second control signal; and a second switching circuit having An output end electrically coupled to the first switch circuit and conducting the switch circuit according to the reverse second control signal; and a reverse circuit having a first end and a second end The first end is electrically coupled to the input end of the second switch circuit, and the second end is electrically coupled to the output end of the second switch circuit. The liquid crystal display of claim 7, wherein the second temporary storage circuit comprises: a third switching circuit having a data receiving end and a data output end, the data receiving end receiving the data signal and according to the switch The signal is turned on by the third switch; and a data latch circuit is electrically coupled to the data output end of the third switch. The liquid crystal display of claim 2, wherein the first sampling conversion circuit comprises: a third temporary storage circuit receiving the data signal and temporarily storing the data signal according to the second output signal; and a fourth temporary storage circuit The third temporary storage unit is electrically coupled to the first control signal to temporarily store the data signal; and a second thrust enhancement circuit is electrically coupled to the fourth temporary storage unit to output the pixel signals. The liquid crystal display of claim 10, wherein the third temporary storage circuit comprises: a third switching circuit receiving the data signal and turning on the first switch according to the second output signal; and a fourth switching circuit Having an output end and an input end, the input end is electrically coupled to the first switch circuit and turns on the switch circuit according to the reversed second output signal; and a reverse circuit has a first end and a first end The second end is electrically coupled to the input end of the fourth switch circuit, and the second end is electrically coupled to the output end of the fourth switch circuit. The liquid crystal display of claim 10, wherein the fourth temporary storage circuit comprises: a fifth switch circuit having a data receiving end and a data output end, the data receiving end receiving the data signal and according to the first A control signal turns on the third switch; and a data latch circuit is electrically coupled to the data output end of the fifth switch. The liquid crystal display of claim 1, wherein the first output signal is an output signal after the clock signal passes through at least one of the frequency adjustment circuits. The liquid crystal display of claim 1, wherein the time from the enabling of the decoding signal to the inactivation is earlier than the width of the at least one clock signal from the enabling of the last pixel signal to the second time.