TW201721966A - Method for manufacturing chip signal element - Google Patents

Abstract

A method for manufacturing chip signal element is provided. The method comprises steps: providing a substrate having an upper and lower metallic layers; forming a plurality of through holes in the substrate, and forming side pores on two sides of the through holes; forming a plurality of conductive layers on the through holes by panel plating to connect the upper and lower metallic layers; increasing a thickness of the conductive layer by pattern plating; forming a first and second pattern layers on the upper and lower metallic layers of the substrate by wet etching or dry etching; forming a spiral radiator by connecting the first and second pattern layers and the conductive layers; providing ink on the substrate and covering the radiator to form a solder resist layer; making end electrodes by an electroless nickel immersion gold process and tin plating; and forming chip signal elements that are the substrate having the spiral radiator therein by cutting the substrate.

Description

Chip signal component manufacturing method

The invention relates to an antenna, in particular to a method for fabricating a chip signal component having a receiving and transmitting signal.

With the development of wireless communication technology, portable electronic devices such as notebook computers, mobile phones, and personal digital assistants (PDAs) are designed and developed toward thin and light. The size of the antenna used to transmit and receive radio signals is relatively small, or the antenna structure can be changed to be built into the electronic product.

A multi-band multi-band antenna commonly used on the market currently has a chip antenna and a substrate. The wafer antenna is made of a ceramic material into a square substrate, and a radiation body is formed on the surface of the substrate by a printing technique or a lithography or wet etching technique. When the wafer antenna is electrically connected to the carrier, the radiator of the wafer antenna is electrically connected to the microstrip line on the carrier, and after the microstrip line is electrically connected to the copper shaft cable, After receiving the signal, the radiating metal part transmits the signal to the copper shaft cable through the microstrip line, and then the copper shaft cable is transmitted to the motherboard of the electronic device for processing, so as to achieve the purpose of communication.

Since the radiation system on the above wafer antenna is fabricated by printing technology or lithography or wet etching technology, although the wafer antenna volume is much smaller than that of the conventional antenna, the carrier board used in combination with the wafer antenna has A preferred matching characteristic is that the carrier has a volume that is several times larger than the wafer antenna. Therefore, when the volume of the wafer antenna cannot be reduced, the volume of the relatively matched carrier can no longer be reduced, so that it is impossible to use the mobile electronic device designed to be thin, light and short at the present stage.

Therefore, the main object of the present invention is to provide a new manufacturing method for fabricating a radiation body coated on a wafer signal component by dry etching or wet etching, so that the volume of the wafer signal component is reduced compared with the conventional one, so that the matching load is made. The board is also reduced in size and can be used on smaller mobile electronic devices.

To achieve the above object, the present invention provides a method of fabricating a wafer signal component, comprising: providing a substrate having an upper metal layer on a top surface thereof and a lower metal layer on the bottom surface of the substrate, each of the predetermined wafers a plurality of correspondingly arranged through holes are drilled in the region of the signal component to first plate the metal walls of the through holes of the copper to form a first conductive layer of the plurality of conductive layers, and the first The conductive layer is electrically connected to the upper metal layer and the lower metal layer, and the second conductive layer of the conductive layers is formed on the surface of the first conductive layer by a second copper plating metal; then, by wet etching or The dry etching technique has a first pattern layer formed on the upper metal layer of the substrate, and a second pattern layer formed on the lower metal layer of the substrate, wherein the first pattern layer and the second pattern layer are connected to the conductive layer Forming a spiral radiator, forming an ink on a top surface and a bottom surface of the substrate, and covering the radiator to form a solder resist layer, and only exposing both ends of the radiator to a gold plating process On both ends of the substrate Forming a flat first metal layer on the top surface and the bottom surface, wherein the first metal layer is electrically connected to the two ends of the radiator, and the second metal layer is plated on the surface of the first metal layer. To form the terminal electrodes of the wafer signal elements; finally, to cut the plurality of wafer signal elements in each column of the substrate to form a single one of the wafer signal elements having a spiral radiator.

In one embodiment of the invention, side apertures are formed on both sides of the wafer signal elements of each column.

In an embodiment of the invention, the side holes are elongated or circular.

In an embodiment of the invention, the through holes have a diameter of 0.15 mm.

In an embodiment of the invention, the distance between the adjacent via holes is 0.20 mm.

In an embodiment of the invention, the first pattern layer is composed of a plurality of straight lines to electrically connect the conductive layers in the through holes.

In an embodiment of the invention, the second pattern layer is composed of a plurality of oblique diagonal lines electrically connecting the conductive layers in the through holes diagonally.

In an embodiment of the invention, the oblique diagonal lines and the straight lines have a line width of 0.05 mm, and the line spacing is 0.05 mm.

In an embodiment of the invention, the ink of the solder mask is a black insulating material.

In an embodiment of the invention, the first metal layer comprises a copper material, a nickel material and a gold material, and the second metal layer comprises a tin material and a copper material.

In one embodiment of the invention, the cutting error is ±0.05 mm.

In an embodiment of the invention, the white ink is further printed on the surface of the solder mask of the top surface to form an identification pattern layer of the identification direction, and the identification pattern layer is a letter, a number or a figure.

In one embodiment of the present invention, a cutting line is disposed between the single one of the wafer signal elements adjacent to the other of the wafer signal elements, and after cutting, the through holes are The substrate is formed with a specific distance from the side of the cut.

In an embodiment of the present invention, after the lateral cutting, the cutting tool is aligned with the cutting tool to align the center of the side holes of the wafer signal elements on each side of the column on the substrate to form a spiral shape. The radiator is embedded in a single wafer signal component on the substrate.

In an embodiment of the invention, the cutting lines are disposed on the through holes of each of the wafer signal elements, and after the cutting, the conductive layers of the through holes are exposed.

In an embodiment of the present invention, after the lateral cutting, the cutting tool is used to align the end electrodes of the wafer signal elements of each column with the center of the terminal electrodes of the other wafer elements of the other column. To form a single one of the wafer signal elements wound on the substrate with a spiral shaped radiator.

The technical content and detailed description of the present invention are as follows:

Please refer to FIG. 1 , which is a schematic diagram of the fabrication process of the wafer signal component of the present invention and a schematic structural diagram of each process of FIGS. 2-10 . Referring to FIG. 2 to FIG. 10 together, as shown in the figure, in the method for fabricating the wafer signal component of the first embodiment of the present invention, first, as shown in step S100, a substrate 1 having a top surface on the top surface of the substrate 1 is provided. The upper metal layer 2a and the bottom surface have a lower metal layer 2b (see FIGS. 2 and 3). In the present drawing, the substrate 1 is a printed circuit board.

In step S102, drilling is performed to drill a plurality of correspondingly arranged through holes 11 (see FIG. 2) in a region of the single chip signal component 10 (FIG. 10) predetermined by the processing tool. In the present drawing, the through holes 11 have a diameter of 0.15 mm, and the through holes 11 have a hole distance of 0.20 mm.

Step S104, digging or drilling the side holes, after the above-mentioned through holes 11 are completed, the side holes 12 are dug or drilled on both sides of the wafer signal elements 10 of each column by using a digging or drilling tool. The side holes 12 and the through holes 11 are perpendicular to each other on the substrate 1 (see FIG. 2). In the figure, the side holes 12 are elongated on both sides of each of the through holes 11.

Step S106, performing a first copper plating process, and sputtering a copper metal material on the hole walls 11a of the through holes 11 to form a first conductive layer 23a of the plurality of conductive layers 23, The first conductive layer 23a is electrically connected to the upper metal layer 2a and the lower metal layer 2b (see FIGS. 3 and 4).

In step S108, a second copper plating is performed, and the second conductive layer 23b of the conductive layers 23 is formed on the surface of the first conductive layers 23a by sputtering or electroplating. 4) to increase the thickness of the conductive layers 23.

Step S110, performing an etching process, using wet chemical etching or dry laser direct laser direct imaging (LDI) technology, forming a first pattern on the upper metal layer 2a of the top surface of the substrate 1. a layer 21 (such as FIG. 5), the first pattern layer 21 is composed of a plurality of straight lines 211 and a plurality of electrode lines 212. The straight lines 211 are electrically connected to the through holes 11 and then irradiated with laser light. A second pattern layer 22 (such as FIG. 6) is formed on the lower metal layer 2b of the bottom surface of the substrate 1. The second pattern layer 22 is composed of a plurality of diagonal diagonal lines 221 and a plurality of electrode portions 222. The corner lines 221 are electrically connected to the through holes 11 connected to the through holes 11 , and the first pattern layer 21 and the second pattern layer 22 are electrically connected to the conductive layer 23 to form a spiral shape. Radiator 2. In the figure, the oblique diagonal lines 221 and the straight lines 211 have a line width of 0.05 mm, and the line pitch is 0.05 mm.

Step S112, the first ink layer is formed. After the radiation body 2 is completed, the black ink is printed on the top surface and the bottom surface of the substrate 1 by a printing technique, and covers the spiral portion of the radiator 2 to form the solder resist layer 3. (FIG. 7), the solder resist layer 3 exposes only the electrode lines 212 and the electrode portions 222 at both ends of the radiator 2. In the figure, the black ink is an insulating material.

Step S114, the second ink layer is formed, and after the first ink layer is formed, the white ink is printed on the surface of the top surface of the solder resist layer 3 by the printing technique to form the identification pattern layer 4 of the identification direction ( As shown in Figure 8). In the figure, the identification pattern layer is a letter, a number or a figure.

In step S116, the terminal electrode is formed. After the identification pattern layer 4 is formed, a first metal layer with good flatness is formed on the top surface and the bottom surface of the substrate 1 through the gold plating process. The metal layer is electrically connected to the electrode line 212 and the electrode portion 222 exposed at both ends of the radiator 2. A second metal layer is plated on the surface of the first metal layer to form the terminal electrode 5 of the wafer signal element 10 (see FIGS. 8, 9). In the figure, the first metal layer comprises copper, nickel and gold, and the second metal layer comprises tin and copper.

In step S118, after the fabrication of the terminal electrode 5 is completed, a single one of the wafer signal component 10 on the substrate 1 and the adjacent via holes 11 of the other wafer signal component 10 are provided. The cutting line 6 is cut by the cutting tool 6 aligned with the cutting line 6 on the substrate 1 (as shown in FIG. 9 ), and the through holes 11 are formed with a specific distance 12 from the side of the substrate 1 to be cut. A single wafer signal element 10 (see FIG. 10) having a spiral radiator 2 embedded in the substrate 1 is formed. In this figure, the cutting error is ±0.05 mm.

Please refer to FIG. 11, which is a schematic diagram of a carrier signal of a wafer signal component and an antenna according to a first embodiment of the present invention. As shown in the figure, after the wafer signal component 10 of the present invention is completed, the wafer signal component 10 is electrically connected to the carrier 20, and the wafer signal component 10 is electrically connected to a carrier 20 having a clearance area. Description.

The front surface of the carrier 20 has a first grounding metal layer 201 and a bare space 202. The bare space 202 has a fixed end 203 and a signal feeding line 204. The number of the feeding lines 204 includes a first signal. a feed line 204a, a second signal feed line 204b, and a spacing 204c between the first signal feed line 204a and the second signal feed line 204b, and the first signal feed line 204a and the second signal feed line The gap 205 between the 204b and the first ground metal layer 201 can be electrically connected through a matching circuit (not shown) for impedance and frequency adjustment. In addition, the back side of the carrier 20 has a second grounding metal layer (not shown) and a clearing area (not shown). When the chip signal component 10 is electrically coupled to the carrier 20, the terminal electrode 5 of the chip signal component 10 is electrically coupled to the fixed terminal 203 and one end of the first signal feed line 204a. The other end of the feed line 204b is electrically connected to a coaxial cable (not shown), and is transmitted from the coaxial cable to the signal feed line 204 when the antenna receives a signal or transmits a signal, or is fed by the signal. 204 transmits a signal to the coaxial cable to transmit and receive signals.

Please refer to FIG. 12 and FIG. 13 , which are schematic diagrams showing the cutting and appearance of the wafer signal component according to the second embodiment of the present invention. As shown in the figure, the wafer signal component 10a in this embodiment is substantially the same as the wafer signal component 10 of FIGS. 1 to 11, except that the cutting line 6a is disposed in the through holes 11 during the cutting process. Then, after the cutting, the conductive layer 2 is exposed to the outside of the substrate 1 to form a single wafer signal element 10a having a spiral body 2 spirally wound around the substrate 1. In this figure, the cutting error is ±0.05 mm.

Please refer to FIG. 14, which is a top plan view of a substrate according to a third embodiment of the present invention. As shown in the figure, the manufacturing steps of the third embodiment are substantially the same as those of the first embodiment, except that the side holes 12 of the step S104 of the first embodiment are excavated and located in each column. The two sides of the wafer signal element 10, and the circular side holes 12a of the third embodiment are located on both sides of each of the wafer signal elements 10. After the subsequent wet or dry etching, the side holes 12a are located. The top electrode line 212 and the electrode portion 22 are provided. And the technique of the side hole 12a of the third embodiment can also be applied to the second embodiment.

When cutting, the cutting tool cuts according to the cutting line 6 between the single wafer signal component 10 on the substrate 1 and the adjacent through holes 11 of the other wafer signal component 10, so that the cutting tools 6 The through hole 11 is formed with a specific distance 12 from the side of the substrate 1 where the substrate 1 is cut. After the lateral cutting, the cutting tool 61 is again cut by the cutting tool on the substrate 1 at the center of the side hole 12a of the wafer signal component 10, so that the wafer signal component 10 is formed into a spiral shape. Radiator 2.

15 and FIG. 16 are schematic diagrams showing a process of fabricating a wafer signal component and a top surface of a substrate according to a fourth embodiment of the present invention. As shown in the figure, the fourth embodiment is substantially the same as the first embodiment, except that the fourth embodiment eliminates the steps of fabricating the digging or drilling side holes 12, 12a as in step S104 in the first embodiment. After the drilling 11, the subsequent steps of the first copper plating or the like of the step S204 are directly entered.

When cutting, the cutting tool cuts according to the cutting line 6 between the single wafer signal component 10 on the substrate 1 and the adjacent through holes 11 of the other wafer signal component 10, so that the cutting tools 6 The through hole 11 is formed with a specific distance 12 from the side of the substrate 1 where the substrate 1 is cut. After the lateral cutting, the cutting tool is again aligned with the cutting line 62 at the center between the end electrode 5 of each column of the wafer signal element 10 and the terminal electrode 5 of the other column of the wafer signal element 10 to make the wafer. The signal element 10 forms a radiator 2 having a spiral shape. Further, the technique of the fourth embodiment without digging or drilling the side holes 12, 12a can also be applied to the second embodiment.

The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. That is, the equivalent changes and modifications made by the scope of the patent application of the present invention are covered by the scope of the invention.

S100~S118‧‧‧Steps

S200~S216‧‧‧Steps

10, 10a‧‧‧ wafer signal components

1‧‧‧Substrate

11‧‧‧through hole

11a‧‧‧ hole wall

12, 12a‧‧‧ side hole

2a‧‧‧Upper metal layer

2b‧‧‧ lower metal layer

2‧‧‧ radiator

21‧‧‧First pattern layer

211‧‧‧ Straight line

212‧‧‧Electrode lines

22‧‧‧Second pattern layer

221‧‧‧ diagonal diagonal

222‧‧‧Electrode

23‧‧‧ Conductive layer

23a‧‧‧First conductive layer

23b‧‧‧Second conductive layer

3‧‧‧ solder mask

4‧‧‧ Identification pattern layer

5‧‧‧ terminal electrode

6, 6a, 61, 62‧‧‧ cutting line

20‧‧‧ Carrier Board

201‧‧‧First grounded metal layer

202‧‧‧ naked room

203‧‧‧Fixed end

204‧‧‧ signal feed line

204c‧‧‧ spacing

205‧‧‧ gap

FIG. 1 is a schematic view showing a process of fabricating a wafer signal component according to a first embodiment of the present invention.

Figure 2 is a top plan view of a substrate of a first embodiment of the present invention.

Figure 3 is a side elevational view of Figure 2.

Figure 4 is a schematic view showing the fabrication of a conductive layer in the first embodiment of the present invention.

FIG. 5 is a schematic top view of the substrate after laser light etching of the upper metal layer on the top surface of the substrate according to the first embodiment of the present invention.

Fig. 6 is a schematic view showing the bottom surface of the substrate after laser light etching of the lower metal layer on the bottom surface of the substrate according to the first embodiment of the present invention.

Figure 7 is a side elevational view showing the manufacture of the solder resist layer of the first embodiment of the present invention.

Figure 8 is a side elevational view showing the fabrication of the identification pattern layer of the first embodiment of the present invention.

Figure 9 is a schematic view showing the fabrication of the terminal electrode of the first embodiment of the present invention.

Figure 10 is a perspective view showing the appearance of a single-chip signal component after cutting according to the first embodiment of the present invention.

Figure 11 is a schematic view showing the state of use of the carrier of the wafer signal component and the antenna of the first embodiment of the present invention.

Figure 12 is a schematic view showing the cutting of the wafer signal element of the second embodiment of the present invention.

Figure 13 is a perspective view showing the appearance of a wafer signal component of a second embodiment of the present invention.

Figure 14 is a top plan view showing a substrate of a third embodiment of the present invention.

Figure 15 is a flow chart showing the fabrication process of the wafer signal component of the fourth embodiment of the present invention.

Figure 16 is a top plan view showing a substrate of a fourth embodiment of the present invention.

S100~S118‧‧‧Steps

Claims (16)

A method for fabricating a wafer signal component, comprising: a) preparing a substrate having an upper metal layer on a top surface thereof and a lower metal layer on a bottom surface of the substrate; b) a predetermined signal component for each of the wafers A plurality of through holes arranged in a corresponding manner are drilled in the region; c) a first copper plated metal is formed on the hole walls of the through holes to form a first conductive layer of the plurality of conductive layers, and the first a conductive layer electrically connecting the upper metal layer and the lower metal layer; d) a second copper plating metal forming a second conductive layer of the conductive layers on the surface of the first conductive layer; e) Or a first etching layer is formed on the upper metal layer of the substrate, and a second pattern layer is formed on the lower metal layer of the substrate, and the first pattern layer and the second pattern layer are transparent to the conductive layer a joint to form a spiral radiator; f) forming an ink on a top surface and a bottom surface of the substrate, and covering the radiator to form a solder resist layer, only exposing both ends of the radiator; ), the top surface and the bottom of the substrate on the substrate Forming a flat first metal layer, wherein the first metal layer and the two ends of the radiating body are electrically connected, wherein a surface of the first metal layer is coated with a second metal layer to form the a terminal electrode of the wafer signal component; and h) for cutting the plurality of wafer signal elements in each column of the substrate to form a single one of the wafer signal elements having a spiral radiator. The method for fabricating a wafer signal component according to claim 1, wherein a step b1 is further formed between steps b and c, and the step b1 is formed on both sides of the wafer signal components of each column. Side hole. The method for fabricating a wafer signal component according to claim 2, wherein the side hole is elongated or circular. The method for fabricating a wafer signal component according to claim 2, wherein the through holes have a diameter of 0.15 mm. The method for fabricating a wafer signal component according to claim 2, wherein a hole distance between the adjacent via holes is 0.20 mm. The method for fabricating a wafer signal component according to claim 2, wherein the first pattern layer is composed of a plurality of straight lines and a plurality of electrode lines to electrically connect the conductive lines in the through holes. Floor. The method for fabricating a wafer signal component according to claim 6, wherein the second pattern layer is composed of a plurality of diagonal diagonal lines and a plurality of electrode portions, and the through holes are electrically connected diagonally and diagonally. Medium conductive layer. The method for fabricating a wafer signal component according to claim 7, wherein the oblique diagonal lines and the straight lines have a line width of 0.05 mm, and the line pitch is 0.05 mm. The method of fabricating a wafer signal component according to claim 2, wherein the ink of the solder resist layer is a black insulating material. The method for fabricating a wafer signal component according to claim 2, wherein the first metal layer comprises a copper material, a nickel material, and a gold material, and the second metal layer comprises a tin material and a copper material. The method for fabricating a wafer signal component according to claim 2, wherein the cutting error is ±0.05 mm. The method for fabricating a wafer signal component according to claim 2, wherein a f1 step is further included between the f step and the g step, the f1 step printing the white ink on the solder mask of the top surface On the surface, an identification pattern layer is formed to form an identification direction, and the identification pattern layer is a character, a number, or a graphic. The method for fabricating a chip signal component according to the second aspect of the invention, wherein the cutting of the step h is performed, and the cutting line is disposed on the single one of the wafer signal component adjacent to the other of the chip signal components. Between the through holes, after the cutting, the through holes are formed at a specific distance from the sides of the substrate where the substrate is cut. The method for fabricating a wafer signal component according to claim 13 , wherein the step h further comprises: after laterally cutting, aligning the plurality of the chip signal components in each column on the substrate with a cutting tool; The side of the side edge hole is cut to form a single wafer signal component having a spiral radiator embedded on the substrate. The method for fabricating a chip signal component according to the second aspect of the invention, wherein the cutting of the step h is performed on the through holes of each of the chip signal components, and after cutting, The conductive layers of the through holes are exposed. The method for fabricating a wafer signal component according to claim 15, wherein the step h further comprises: after the lateral cutting, the end electrode of the wafer signal components aligned with each of the columns by the cutting tool and the other A row of the wafer elements of the column is cut at the center between the terminal electrodes to form a single one of the wafer signal elements having a spiral of radiation wrapped around the substrate.