TW201705482A - 集成於垂直閘極鰭式場效二極體之靜電放電及被動結構 - Google Patents
集成於垂直閘極鰭式場效二極體之靜電放電及被動結構 Download PDFInfo
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Abstract
本發明涉及集成於垂直閘極鰭式場效二極體的靜電放電及被動結構。具體涉及場效二極體結構利用具有L形截面的接面結構(自平面部分延展的鰭片)。陽極置於鰭片的頂面,而陰極置於平面部分的端面。鰭片與平面部分的垂直性造成陽極與陰極彼此垂直。第一閘極絕緣體接觸介於頂面與平面部分之間的鰭片。第一閘極導體接觸第一閘極絕緣體,而第一閘極絕緣體介於第一閘極導體與鰭片的表面之間。另外,第二閘極絕緣體接觸介於端面與鰭片之間的平面部分。第二閘極導體接觸第二閘極絕緣體,而第二閘極絕緣體系介於第二閘極導體與平面部分的表面之間。
Description
本揭露大體上關於二極體,並且更具體地說,關於鰭式積體電路結構中的垂直二極體。
鰭式場效電晶體(FinFET)利用鰭形半導體本體作為主要的電晶體元件。鰭片的中心(通道)乃是半導體,且鰭片的端部乃是導體,而上覆閘極供應電壓場以改變鰭片中心的導電性。
二極體包含容許電流在陽極與陰極之間沿著指定方向流動的p-n接面。二極體有許多類型;然而,二極體在可讓電流通過之前,大體上需要先超過初始臨限值。一些二極體可利用一或多個閘極來控制,用以判定讓電流可通過二極體的輕易程度。
電晶體具有單一通道以及導電性源極與汲極結構,一旦上覆閘極或閘極氧化物在鰭形結構上方形成,導電性源極與汲極結構便可輕易地摻有雜質,然而,與電
晶體不同的是,二極體不容易受鰭形結構控制,因為二極體利用多個相隔緊密的雜質,而這些相隔緊密的雜質不易對準(雙閘極場效二極體尤其如此)。因此,二極體不易使用鰭式電晶體結構來形成。
本文中場效二極體結構的例示性具體實施例利用具有L形截面的接面結構。接面結構包含平面部分及鰭片部分。更具體地說,鰭片部分自平面部分(沿著第一方向)延展。平面部分沿著垂直於第一方向的第二方向延展。鰭片部分具有沿著第一方向遠離平面部分的頂面。頂面與平面部分共面,但頂面橫置於有別於平面部分的平面中。平面部分具有沿著第二方向遠離鰭片部分的端面。端面與鰭片部分共面,但端面橫置於有別於鰭片部分的平面中。陽極置於鰭片部分的頂面,而陰極置於平面部分的端面。鰭片部分與平面部分的垂直性造成陽極與陰極彼此垂直。
第一閘極絕緣體接觸沿著第一方向延展的鰭片部分的表面。具體而言,第一閘極絕緣體接觸介於頂面與平面部分之間的鰭片部分的表面。第一閘極導體接觸第一閘極絕緣體,而第一閘極絕緣體置於第一閘極導體與鰭片部分的表面之間。第一閘極導體可包含環繞閘極導體,此環繞閘極導體圍繞沿著第一方向延展的矩形鰭片部分的全部四個側面。此外,第一閘極絕緣體介於矩形鰭片部分的四個側面與環繞閘極導體之間。
另外,第二閘極絕緣體接觸沿著第二方向延展的平面部分的表面。第二閘極絕緣體接觸介於端面與鰭片部分之間的平面部分的表面。第二閘極導體接觸第二閘極絕緣體,而第二閘極絕緣體置於第二閘極導體與平面部分的表面之間。按照這種方式,第二閘極導體包含靜電放電保護裝置。
由於多個閘極的關係,接面結構包含介於陽極與陰極之間的多個p-n接面。舉例而言,接面結構包含介於陽極與第一閘極導體之間的第一暫時p-n接面、介於鰭片部分與第二閘極導體之間的第二暫時p-n接面、以及介於陰極與第二閘極導體之間的第三永久p-n接面。
在一些結構中,接面結構包含半導體。陽極包含具有第一類型雜質的導體,而陰極包含具有第二類型雜質的導體(其中第一類型雜質具有與第二類型雜質相反的極性)。因此,接面結構包含基於第一閘極導體與第二閘極導體之間的電壓差的介於陽極與陰極之間的導體。
本文中的附加場效二極體結構具體實施例包含亦具有L形截面的接面結構,其中接面結構包含平面部分及鰭片部分。此外,鰭片部分自平面部分沿著第一方向延展,而平面部分沿著垂直於第一方向的第二方向延展。鰭片部分具有沿著第一方向遠離平面部分的頂面,其中頂面與平面部分共面。頂面橫置於有別於平面部分的平面中。平面部分具有沿著第二方向遠離鰭片部分的端面。端面與鰭片部分共面,並且端面橫置於有別於鰭片部分的平
面中。
類似的是,陽極置於鰭片部分的頂面,而陰極置於平面部分的端面。第一閘極絕緣體接觸沿著第一方向延展的鰭片部分的表面。具體而言,第一閘極絕緣體接觸介於頂面與平面部分之間的鰭片部分的表面。第一閘極導體接觸第一閘極絕緣體。第一閘極絕緣體置於第一閘極導體與鰭片部分的表面之間。第二閘極絕緣體接觸沿著第二方向延展的平面部分的表面。第二閘極絕緣體接觸介於端面與鰭片部分之間的平面部分的表面。鎮流電阻器接觸第二閘極絕緣體,而第二閘極絕緣體置於鎮流電阻器與平面部分的表面之間。
本文中的其它場效二極體結構包含位在L形鰭片的垂直部分上的多晶矽接面結構。正如先前論述的結構,L形鰭片包含平面部分及鰭片部分。鰭片部分還自平面部分沿著第一方向延展,而平面部分沿著垂直於第一方向的第二方向延展。鰭片部分具有沿著第一方向遠離平面部分的頂面。頂面與平面部分共面,但頂面橫置於有別於平面部分的平面中。平面部分具有沿著第二方向遠離鰭片部分的端面。端面與鰭片部分共面,但端面橫置於有別於鰭片部分的平面中。陽極置於鰭片部分的頂面,而陰極置於平面部分的端面。閘極絕緣體接觸沿著第一方向延展的鰭片部分的表面。閘極絕緣體接觸介於頂面與平面部分之間的鰭片部分的表面。閘極導體接觸閘極絕緣體,而閘極絕緣體置於閘極導體與鰭片部分的表面之間。
102‧‧‧基材
104‧‧‧絕緣體層
106‧‧‧接面結構、L形鰭片、鰭形結構
108‧‧‧陰極
110‧‧‧絕緣體層、絕緣體
112‧‧‧第二閘極導體
116‧‧‧第一閘極導體、閘極
120‧‧‧陽極
122‧‧‧絕緣體
124‧‧‧第二閘極絕緣體
126‧‧‧第一閘極絕緣體
130‧‧‧陽極
132‧‧‧鎮流電阻器、鎮流電阻器/閘極
134‧‧‧鰭片部分
136‧‧‧平面部分
138‧‧‧頂面
140‧‧‧端面
156‧‧‧多晶矽接面結構、多晶矽
本文中的具體實施例將會參照圖式經由以下詳細說明而更加讓人瞭解,這些圖式不必然按照比例繪製,其中:第1圖是以透視圖繪示場效二極體的示意圖;第2圖是以透視圖繪示第1圖所示場效二極體的示意圖,以透明圖展示出環繞閘極;第3圖是以截面圖繪示第1圖所示場效二極體的示意圖;第4圖是以平面圖或俯視圖繪示第1圖所示場效二極體的示意圖;第5圖是以透視圖繪示場效二極體的示意圖;第6圖是以透視圖繪示第5圖所示場效二極體的示意圖,以透明圖展示出環繞閘極;第7圖是以截面圖繪示第5圖所示場效二極體的示意圖;第8圖是以平面圖或俯視圖繪示第5圖所示場效二極體的示意圖;第9圖是以透視圖繪示場效二極體的示意圖;第10圖是以透視圖繪示第9圖所示場效二極體的示意圖,以透明圖展示出環繞閘極;
第11圖是以截面圖繪示第9圖所示場效二極體的示意圖;第12圖是以平面圖或俯視圖繪示第9圖所示場效二極體的示意圖;第13圖是繪示部分形成的場效二極體的示意性透視圖;第14圖是繪示部分形成的場效二極體的示意性透視圖;第15圖是繪示部分形成的場效二極體的示意性透視圖,該部分形成的場效二極體將會導致第1圖至第4圖所示的場效二極體;第16圖是繪示部分形成的場效二極體的示意性透視圖,該部分形成的場效二極體將會導致第1圖至第4圖所示的場效二極體;第17圖是繪示部分形成的場效二極體的示意性透視圖,該部分形成的場效二極體將會導致第5圖至第8圖所示的場效二極體;第18圖是繪示部分形成的場效二極體的示意性透視圖,該部分形成的場效二極體將會導致第5圖至第8圖所示的場效二極體;第19圖是繪示部分形成的場效二極體的示意性透視圖,該部分形成的場效二極體將會導致第9圖至第12圖所示的場效二極體;第20圖是繪示部分形成的場效二極體的示
意性透視圖,該部分形成的場效二極體將會導致第9圖至第12圖所示的場效二極體;第21圖是繪示部分形成的場效二極體的示意性透視圖,該部分形成的場效二極體將會導致第9圖至第12圖所示的場效二極體;以及第22圖是繪示部分形成的場效二極體的示意性透視圖,該部分形成的場效二極體將會導致第9圖至第12圖所示的場效二極體。
如上所述,二極體不易使用鰭式電晶體結構來形成。因此,本揭露以鰭形結構呈現閘控二極體;然而,本揭露使用垂直鰭形結構(有時在本文中稱為L形鰭形結構),並且在鰭片的頂端上形成陽極、並在垂直於鰭片的平面結構的端部形成陰極,而不是嘗試在鰭片內形成多個、相隔緊密的植入物及閘極的困難工作。這容許鰭式場效二極體(FinFED)具有一個或兩個閘極,並且容許雜質與閘極更加容易在陰極與陽極區內形成並對準。再者,二極體的多個閘極在這裡可以用不同方式來施作(例如:一個閘極可以是鎮流閘極)而可以得到附加靜電放電效能增益。
因此,本文中的例示性場效二極體結構利用具有L形截面的接面結構。第1圖是以透視圖繪示場效二極體的示意圖。第2圖是以透視圖繪示第1圖所示場效二極體的示意圖,以透明圖展示出環繞閘極。第3圖是以截面圖繪示第1圖所示場效二極體的示意圖。第4圖是以平
面圖或俯視圖繪示第1圖所示場效二極體的示意圖。在本文的圖式中,相同的識別符號代表相同或類似的結構。舉例而言,如第1圖至第4圖所示,半導體接面結構106包含平面部分136及鰭片部分134。
儘管為了避免造成不必要的混淆而沒有在所有圖式中展示,如本領域的技術人員瞭解,L形鰭片106的各個部分(或整個L形鰭片)可經選擇性摻雜而包含電晶體結構的一或多個半導體井區(例如:N區或P區),L形鰭片106乃是此電晶體結構的一部分。為達本文目的,“半導體”是可包括經布植或原位雜質的材料或結構,此雜質基於電子與電洞載子濃度,容許此材料有時成為導體而有時成為絕緣體。“布植程序”於本文中使用時,可採用任何適當形式(無論是目前已知或未來才開發的形式),並且舉例而言,可包含離子布植等。在閘控二極體中,半導體區於受到閘極所建立的電場控制時,可在陽極與陰極之間建立多個p-n接面。
更具體地說,鰭片部分134自平面部分136(沿著第一方向)延展。平面部分136沿著垂直於第一方向的第二方向延展。鰭片部分134具有沿著第一方向遠離平面部分136的頂面138。頂面138與平面部分136共面,但頂面138橫置於有別於平面部分136的平面中。平面部分136具有沿著第二方向遠離鰭片部分134的端面140。端面140與鰭片部分134共面,但端面140橫置於有別於鰭片部分134的平面中。
(例如:具有P+摻雜極性/濃度的)導電陽極120置於鰭片部分134的頂面138,而(例如:具有N+摻雜極性/濃度的)導電陰極108置於平面部分136的端面140。鰭片部分134與平面部分136的垂直性造成陽極120與陰極108彼此垂直。
本文中所述的導體可由諸如多結晶矽(多晶矽)、非晶矽、非晶矽與多晶矽的組合、及多晶矽-鍺等任何導電材料所構成,因存在合適的摻質而具有導電性。替代地,本文中的導體可以是一或多種諸如鎢、鉿、鉭、鉬、鈦、或鎳等金屬、或此類金屬的金屬矽化物、合金,並且可使用物理氣相沉積、化學氣相沉積、或任何其它技術領域已知的技術來沉積。
第一閘極絕緣體(例如:氧化物)126接觸(直接位在上面)沿著第一方向延展的鰭片部分134的平坦表面。具體而言,第一閘極絕緣體126接觸介於頂面138與平面部分136之間的鰭片部分134的該表面。第一閘極導體116接觸(直接位在上面)第一閘極絕緣體126,而第一閘極絕緣體126置於第一閘極導體116與鰭片部分134的該表面之間。第一閘極導體116可包含環繞閘極導體,此環繞閘極導體圍繞沿著第一方向延展的矩形鰭片部分134的全部四個側面、或圍繞單一平面型導體閘極條。此外,第一閘極絕緣體126介於矩形鰭片部分134的四個側面與環繞閘極導體之間。
另外,第二閘極絕緣體(例如:氧化物)124
接觸(直接位在上面)沿著第二方向延展的平面部分136的一表面。具體而言,第二閘極絕緣體124接觸介於端面140與鰭片部分134之間的平面部分136的該表面。第二閘極導體112接觸(直接位在上面)第二閘極絕緣體124,而第二閘極絕緣體124置於第二閘極導體112與平面部分136的該表面之間。項目122代表將二極體與相鄰結構隔離的相鄰的不同結構及/或絕緣體。如本領域的技術人員瞭解,可透過絕緣體122形成各種接點及其它結構而與所示二極體的不同組件接觸。
因此,如上所示,第二閘極導體112包含靜電放電保護裝置。由於多個閘極112、116的關係,接面結構106包含介於陽極120與陰極108之間的多個p-n接面。舉例而言,取決於閘極的電壓,接面結構106包含介於陽極120與第一閘極導體116之間的第一暫時p-n接面J1、介於鰭片部分134與第二閘極導體112之間的第二暫時p-n接面J2、以及介於陰極108與第二閘極導體112之間的第三永久p-n接面J3。如本領域的技術人員瞭解,閘極中的電壓可將二極體完全斷開、可形成p-n接面、可形成p-n-p-n接面等。
在上述結構中,接面結構106包含半導體。陽極120包含具有第一類型雜質的導體,而陰極108包含具有第二類型雜質的導體(其中第一類型雜質具有與第二類型雜質相反的極性)。因此,接面結構106包含基於第一閘極導體116與第二閘極導體112之間的電壓差的介於陽
極120與陰極108之間的導體。
第5圖至第8圖中所示是附加場效二極體結構。具體而言,第5圖是以透視圖繪示場效二極體的示意圖。第6圖是以透視圖繪示第5圖所示場效二極體的示意圖,以透明圖展示出環繞閘極。第7圖是以截面圖繪示第5圖所示場效二極體的示意圖。第8圖是以平面圖或俯視圖繪示第5圖所示場效二極體的示意圖。
如第5圖至第8圖所示,本文中的附加結構包括含有鎮流電阻器的鰭式場效二極體。更具體地說,第5圖至第8圖中的結構包括亦具有L形截面的接面結構106,其中接面結構包含平面部分136及鰭片部分134。此外,鰭片部分134自平面部分136沿著第一方向延展,而平面部分136沿著垂直於第一方向的第二方向延展。鰭片部分134具有沿著第一方向遠離平面部分136的頂面138,其中頂面138與平面部分136共面。頂面138橫置於有別於平面部分136的平面中。平面部分136具有沿著第二方向遠離鰭片部分134的端面140。端面140與鰭片部分134共面,並且端面140橫置於有別於鰭片部分134的平面中。
類似的是,(例如:具有N+摻雜極性/濃度的)陽極136置於鰭片部分134的頂面138,而陰極108置於平面部分136的端面140。第一閘極絕緣體126接觸沿著第一方向延展的鰭片部分134的一表面。具體而言,第一閘極絕緣體126接觸介於頂面138與平面部分136之間的鰭片部分134的該表面。第一閘極導體116接觸第一閘極絕
緣體126。第一閘極絕緣體126置於第一閘極導體116與鰭片部分134的該表面之間。第二閘極絕緣體124接觸沿著第二方向延展的平面部分136的一表面。第二閘極絕緣體124接觸介於端面140與鰭片部分134之間的平面部分136的該表面。鎮流電阻器132接觸第二閘極絕緣體124,而第二閘極絕緣體124置於鎮流電阻器132與平面部分136的該表面之間。鎮流電阻器132的形式可以是任何電阻器,並且舉例而言,可包含矽化物阻隔層(SBLK)。鎮流電阻器132有助於電流均勻分佈,並且避免電流縮在窄小區域中,從而避免在更低電流情況下出現裝置故障。
如第9圖至第12圖所示,本文中的附加結構包含鰭式多晶矽場效二極體。更具體地說,第9圖是以透視圖繪示場效二極體的示意圖。第10圖是以透視圖繪示第9圖所示場效二極體的示意圖,以透明圖展示出環繞閘極。第11圖是以截面圖繪示第9圖所示場效二極體的示意圖。第12圖是以平面圖或俯視圖繪示第9圖所示場效二極體的示意圖。
因此,第9至12圖所示的結構包括置於垂直鰭片部分134的多晶矽接面結構156,而垂直鰭片部分134的其餘部分是井區(NW)。因此,多晶矽接面結構156置於垂直鰭片部分134上。鰭片部分134還自平面部分136沿著第一方向延展。鰭片部分134具有沿著第一方向遠離平面部分136的頂面138。頂面138與平面部分136共面,但頂面138橫置於有別於平面部分136的平面中。平面部分
136具有沿著第二方向遠離鰭片部分134的端面140。端面140與鰭片部分134共面,但端面140橫置於有別於鰭片部分134的平面中。
陽極120置於鰭片部分134的頂面138,而陰極108置於平面部分136的端面140。閘極絕緣體126接觸多晶矽接面結構156的一表面。閘極絕緣體126接觸介於頂面138與平面部分136之間的多晶矽接面結構156的該表面。閘極導體116接觸閘極絕緣體126,而閘極絕緣體126置於閘極導體116與鰭片部分134的該表面之間。
儘管以上結構可使用本領域的技術人員已知的許多不同方法來形成,仍將第13圖至第22圖呈現為繪示可藉以製造以上結構的一些方式。具體而言,第13圖及第14圖是繪示部分形成的場效二極體的示意性透視圖。在第13圖中,絕緣體層104使用眾所周知的層形成及沉積程序在基材102上形成。另外,使用眾所周知的微影遮罩、沉積、圖案化、及成形程序形成鰭形結構106。保形絕緣體層110是在鰭形結構106上形成或生長。其次,如第14圖所示,絕緣體110使用眾所周知的微影遮罩、圖案化、及成形程序來圖案化。
為達本文目的,“絕緣體”是一相對用語,意為容許流動的電流比“導體”實質更小(<95%)的材料或結構。本文中所述的介電質(絕緣體)舉例而言,可自幹氧環境或氧流生長,並且接著予以圖案化。替代地本文中的介電質可由許多候選的高介電常數(高k)材料中任一
種形成,包括但不局限於氮化矽、氮氧化矽、SiO2與Si3N4的堆迭、及與氧化鉭相似的金屬氧化物。本文中介電質的厚度可因所要求的裝置效能而異。
當圖案化本文中的任何材料時,待圖案化的材料可按照已知方式來生長或沉積,而圖案化層(例如:有機光阻)可在此材料上方形成。圖案化層(阻劑)可曝露至光曝照圖案中所提供的光輻射(例如:圖案化曝照、雷射曝照等)的某圖型,然後阻劑使用化學劑來顯影。此程序改變阻劑曝露至光的部分的物理特性。接著,可將阻劑的一部分清洗掉,留下阻劑要保護待圖案化材料的其它部分(阻劑遭清洗掉的部分取決於阻劑是正阻劑(經照明部分留下)還是負阻劑(經照明部分遭清洗掉))。接著進行材料移除程序(例如:電漿蝕刻等)以移除材料在待圖案化阻劑下面未獲保護的部分。隨後移除阻劑以留下根據光曝照圖型(或其負影像)進行圖案化的下層材料。
第15圖及第16圖是繪示部分形成的場效二極體的示意性透視圖,該部分形成的場效二極體將會導致第1圖至第4圖所示的場效二極體。更具體地說,在第15圖中,閘極112及116也使用眾所周知的微影遮罩、沉積、圖案化及成形程序在圖案化絕緣體110內形成。在第16圖中,陽極120及陰極108透過眾所周知的程序來形成,此等程序引進雜質(以箭號表示)以將鰭形結構106的材料變成陽極與陰極材料。
大體上,電晶體結構通過將雜質沉積到或植
入基材以形成至少一個半導體通道區而形成,通過基材的頂端(上)表面下面的淺溝槽隔離區來設立邊界。本文中的“基材”可包含任何適用於給定目的的材料(無論是現在已知者或未來才開發者),並且舉例而言,可包含Si、SiC、SiGe、SiGeC、其它III-V族或II-VI族化合物半導體、或有機半導體結構等。淺溝槽隔離(STI)結構乃屬本領域的技術人員眾所周知,並且大體上是通過在基材內圖案化開口/溝槽、並以高度絕緣材料生長或填充開口(如此容許基材的不同主動區彼此電隔離)來形成。
正型電晶體“P型材料”在本質半導體材料內使用諸如硼、鋁或鎵等雜質(造成價電子不足)當作半導體區。類似的是,“N型材料”是在本質半導體材料內使用諸如銻、砷或磷等雜質(造成價電子過剩)當作半導體區的負型電晶體。再者,“+”及“-”符號表示相對雜質濃度。
第17及18圖是繪示部分形成的場效二極體的示意性透視圖,該部分形成的場效二極體將會導致第5至8圖所示的場效二極體。再始於第14圖所示的結構,此時在第17圖中,鎮流電阻器/閘極132及閘極116也使用眾所周知的微影遮罩、沉積、圖案化及成形程序在圖案化絕緣體110內形成。在第18圖中,陽極130及陰極108透過眾所周知的程序來形成,這些程序引進雜質(以箭號表示)以將鰭形結構106的材料變成陽極與陰極材料。
第19及22圖是繪示部分形成的場效二極體
的示意性透視圖,該部分形成的場效二極體將會導致第9至12圖所示的場效二極體。具體而言,在第19圖中,絕緣體層104使用眾所周知的層形成及沉積程序在基材102上形成。如以上所述,使用眾所周知的微影遮罩、沉積、圖案化、及成形程序形成鰭形結構106。保形絕緣體層110是在鰭形結構106上形成或生長。絕緣體110亦使用眾所周知的微影遮罩、圖案化、及成形程序來圖案化。其次,如第20圖所示,多晶矽156是在鰭形結構106的垂直部分134上形成。在第21圖中,閘極絕緣體126及環繞閘極116也使用眾所周知的微影遮罩、沉積、圖案化及成形程序在圖案化絕緣體110內形成。在第22圖中,陽極120及陰極108透過眾所周知的程序來形成,這些程序引進雜質(以箭號表示)以將鰭形結構106的材料變成陽極與陰極材料。
前述結構可包括於集成電路芯片內。產生的集成電路芯片可由製作商以空白晶圓形式(亦即,如具有多個未封裝芯片的單一晶圓)來分佈,如裸晶粒、或已封裝形式。在後例中,芯片嵌裝於單芯片封裝(例如:塑膠載體,具有黏貼至主機板或其它更高層次載體的引線)中、或嵌裝於多芯片封裝(例如:具有表面互連或埋置型互連任一者或兩者的陶瓷載體)中。在任一例中,芯片接著是與其它芯片、離散電路元件及/或其它信號處理裝置集成成(a)諸如主機板的中間產品、或(b)最終產品中任一者的部分。最終產品可以是任何包括集成電路芯片的產品,範圍囊括玩具與其它低端應用至具有顯示器、鍵盤或其它輸入
裝置及中央處理器的進階電腦產品。
在閘控二極體內,半導體p-n接面置於導電性“陽極”區與類似導電性“陰極”區之間,而且當半導體處於導電狀態時,半導體容許電流沿著特定方向在陽極與陰極之間流動。“閘極”是通過“閘極氧化物”(其乃是絕緣體)與半導體電氣分隔的導電元件,而閘極內的電流/電壓會改變半導體區的導電性。
儘管圖式中僅繪示一個或有限數目的電晶體,本領域的技術人員將瞭解的是,許多不同類型電晶體可利用本文中的具體實施例來同時形成,並且圖式的用意在於展示同時形成多個不同類型的電晶體;然而,圖式已簡化成為了厘清而僅展示有限數目的電晶體,並且讓讀者可以更輕易認識所示的不同特徵。用意不在於限制本揭露,因為如本領域的技術人員將瞭解,本揭露適用於包括有許多圖式中所示各類型電晶體的結構。
另外,瞭解本文中所使用諸如“右”、“左”、“垂直”、“水平”、“頂端”、“底端”、“上”、“下”、“底下”、“下面”、“下層”、“上方”、“上層”、“平行”、“垂直”等用語在於說明此等用語在圖式中取向及繪示時的相對位置(除非另有所指)。諸如“觸及”、“上”、“直接接觸”、“毗連”、“直接相鄰於”等用語意為至少一個元件實體接觸另一元件(此等所述元件之間沒有用其它元件來分隔)。
本文中使用的術語目的只是為了說明特定具
體實施例,用意不在於限制本揭露。單數形之“一”(及其變形)及“該”於本文中使用時,用意在於同樣包括複數形,除非內容另有清楚指示。將進一步瞭解的是,“包含”(及/或其變形)等詞於本說明書中使用時,指明所述特徵、整體、步驟、操作、元件及/或組件的存在,但並未排除一或多個其它特徵、整體、步驟、操作、元件、組件及/或其群組的存在或新增。
本發明各項具體實施例的說明已基於說明目的而介紹,但用意不在於窮舉說明或局限於揭示的具體實施例。許多修改及變動對本領域的技術人員將會顯而易見,但不會脫離所述具體實施例的範疇及精神。本文中使用的術語在選擇上,是為了對市場現有技術最佳闡釋具體實施例的原理、實務應用或技術改良,或使其它領域的技術人員能夠理解本文中揭示的具體實施例。
102‧‧‧基材
104‧‧‧絕緣體層
106‧‧‧接面結構、L形鰭片、鰭形結構
108‧‧‧陰極
110‧‧‧絕緣體層、絕緣體
112‧‧‧第二閘極導體
116‧‧‧第一閘極導體、閘極
120‧‧‧陽極
122‧‧‧絕緣體
124‧‧‧第二閘極絕緣體
126‧‧‧第一閘極絕緣體
134‧‧‧鰭片部分
136‧‧‧平面部分
138‧‧‧頂面
140‧‧‧端面
Claims (20)
- 一種場效二極體,其包含:具有L形截面的接面結構,該接面結構包含平面部分及鰭片部分,該鰭片部分自該平面部分沿著第一方向延展,該平面部分沿著垂直於該第一方向的第二方向延展,該鰭片部分具有沿著該第一方向遠離該平面部分的頂面,該頂面與該平面部分共面,該頂面橫置於有別於該平面部分的平面中,該平面部分具有沿著該第二方向遠離該鰭片部分的端面,該端面與該鰭片部分共面,並且該端面橫置於有別於該鰭片部分的平面中;陽極,其置於該鰭片部分的該頂面;陰極,其置於該平面部分的該端面;第一閘極絕緣體,其接觸沿著該第一方向延展的該鰭片部分的表面,該第一閘極絕緣體接觸介於該頂面與該平面部分之間的該鰭片部分的該表面;第一閘極導體,其接觸該第一閘極絕緣體,該第一閘極絕緣體置於該第一閘極導體與該鰭片部分的該表面之間;第二閘極絕緣體,其接觸沿著該第二方向延展的該平面部分的表面,該第二閘極絕緣體接觸介於該端面與該鰭片部分之間的該平面部分的該表面;以及第二閘極導體,其接觸該第二閘極絕緣體,該第二閘極絕緣體置於該第二閘極導體與該平面部分的該表面之間。
- 如申請專利範圍第1項所述的場效二極體,該接面結構包含介於該陽極與該陰極之間的多個p-n接面。
- 如申請專利範圍第1項所述的場效二極體,該接面結構包含:第一暫時p-n接面,其介於該陽極與該第一閘極導體之間;第二暫時p-n接面,其介於該鰭片部分與該第二閘極導體之間;以及第三永久p-n接面,其介於該陰極與該第二閘極導體之間。
- 如申請專利範圍第1項所述的場效二極體,該接面結構包含半導體,該陽極包含具有第一類型雜質的導體,該陰極包含具有第二類型雜質的導體,並且該第一類型雜質具有與該第二類型雜質相反的極性。
- 如申請專利範圍第1項所述的場效二極體,該第一閘極導體包含環繞閘極導體,該環繞閘極導體圍繞沿著該第一方向延展的該鰭片部分的側面,並且該第一閘極絕緣體介於該鰭片部分的該側面與該環繞閘極導體之間。
- 如申請專利範圍第1項所述的場效二極體,該第二閘極導體包含靜電放電保護裝置。
- 如申請專利範圍第1項所述的場效二極體,該接面結構包含基於該第一閘極導體與該第二閘極導體之間的電壓差的介於該陽極與該陰極之間的導體。
- 一種場效二極體,其包含: 具有L形截面的接面結構,該接面結構包含平面部分及鰭片部分,該鰭片部分自該平面部分沿著第一方向延展,該平面部分沿著垂直於該第一方向的第二方向延展,該鰭片部分具有沿著該第一方向遠離該平面部分的頂面,該頂面與該平面部分共面,該頂面橫置於有別於該平面部分的平面中,該平面部分具有沿著該第二方向遠離該鰭片部分的端面,該端面與該鰭片部分共面,並且該端面橫置於有別於該鰭片部分的平面中;陽極,其置於該鰭片部分的該頂面;陰極,其置於該平面部分的該端面;第一閘極絕緣體,其接觸沿著該第一方向延展的該鰭片部分的表面,該第一閘極絕緣體接觸介於該頂面與該平面部分之間的該鰭片部分的該表面;第一閘極導體,其接觸該第一閘極絕緣體,該第一閘極絕緣體置於該第一閘極導體與該鰭片部分的該表面之間;第二閘極絕緣體,其接觸沿著該第二方向延展的該平面部分的表面,該第二閘極絕緣體接觸介於該端面與該鰭片部分之間的該平面部分的該表面;以及鎮流電阻器,其接觸該第二閘極絕緣體,該第二閘極絕緣體置於該鎮流電阻器與該平面部分的該表面之間。
- 如申請專利範圍第8項所述的場效二極體,該接面結構包含介於該陽極與該陰極之間的多個p-n接面。
- 如申請專利範圍第8項所述的場效二極體,該接面結構包含:第一暫時p-n接面,其介於該陽極與該第一閘極導體之間;第二暫時p-n接面,其介於該鰭片部分與該鎮流電阻器之間;以及第三永久p-n接面,其介於該陰極與該鎮流電阻器之間。
- 如申請專利範圍第8項所述的場效二極體,該接面結構包含半導體,該陽極包含具有第一類型雜質的導體,該陰極包含具有第二類型雜質的導體,並且該第一類型雜質具有與該第二類型雜質相反的極性。
- 如申請專利範圍第8項所述的場效二極體,該第一閘極導體包含環繞閘極導體,該環繞閘極導體圍繞沿著該第一方向延展的該鰭片部分的側面,並且該第一閘極絕緣體介於該鰭片部分的該側面與該環繞閘極導體之間。
- 如申請專利範圍第8項所述的場效二極體,該鎮流電阻器包含靜電放電保護裝置。
- 如申請專利範圍第8項所述的場效二極體,該接面結構包含基於該第一閘極導體與該鎮流電阻器之間的電壓差的介於該陽極與該陰極之間的導體。
- 一種場效二極體,其包含:具有L形截面的接面結構,該接面結構包含平面部分及鰭片部分,該鰭片部分自該平面部分沿著第一方 向延展,該平面部分沿著垂直於該第一方向的第二方向延展,該鰭片部分具有沿著該第一方向遠離該平面部分的頂面,該頂面與該平面部分共面,該頂面橫置於有別於該平面部分的平面中,該平面部分具有沿著該第二方向遠離該鰭片部分的端面,該端面與該鰭片部分共面,並且該端面橫置於有別於該鰭片部分的平面中;陽極,其置於該鰭片部分的該頂面;陰極,其置於該平面部分的該端面;多晶矽,其置於該鰭片部分上;閘極絕緣體,其接觸該多晶矽的表面,該閘極絕緣體接觸介於該頂面與該平面部分之間的該多晶矽的該表面;以及閘極導體,其接觸該閘極絕緣體,該閘極絕緣體置於該閘極導體與該鰭片部分的該表面之間。
- 如申請專利範圍第15項所述的場效二極體,該接面結構包含介於該陽極與該陰極之間的多個p-n接面。
- 如申請專利範圍第15項所述的場效二極體,該接面結構包含:第一暫時p-n接面,其介於該陽極與該閘極導體之間;以及第二永久p-n接面,其介於該陰極與該閘極導體之間。
- 如申請專利範圍第15項所述的場效二極體,該接面結構包含半導體,該陽極包含具有第一類型雜質的導體, 該陰極包含具有第二類型雜質的導體,並且該第一類型雜質具有與該第二類型雜質相反的極性。
- 如申請專利範圍第15項所述的場效二極體,該閘極導體包含環繞閘極導體,該環繞閘極導體圍繞沿著該第一方向延展的該鰭片部分的側面,並且該閘極絕緣體介於該鰭片部分的該側面與該環繞閘極導體之間。
- 如申請專利範圍第15項所述的場效二極體,該接面結構包含基於該閘極導體的電壓的介於該陽極與該陰極之間的導體。
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US10276714B2 (en) * | 2017-08-09 | 2019-04-30 | International Business Machines Corporation | Twin gate field effect diode |
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Publication number | Priority date | Publication date | Assignee | Title |
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US6537921B2 (en) | 2001-05-23 | 2003-03-25 | Vram Technologies, Llc | Vertical metal oxide silicon field effect semiconductor diodes |
KR100515061B1 (ko) | 2003-10-31 | 2005-09-14 | 삼성전자주식회사 | 핀 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 형성방법 |
US7180134B2 (en) | 2004-01-30 | 2007-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and structures for planar and multiple-gate transistors formed on SOI |
US7060539B2 (en) * | 2004-03-01 | 2006-06-13 | International Business Machines Corporation | Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby |
US6949768B1 (en) * | 2004-10-18 | 2005-09-27 | International Business Machines Corporation | Planar substrate devices integrated with finfets and method of manufacture |
US7397089B2 (en) | 2005-08-10 | 2008-07-08 | Skyworks Solutions, Inc. | ESD protection structure using contact-via chains as ballast resistors |
US7589387B2 (en) * | 2005-10-05 | 2009-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | SONOS type two-bit FinFET flash memory cell |
US7452768B2 (en) | 2005-10-25 | 2008-11-18 | Freescale Semiconductor, Inc. | Multiple device types including an inverted-T channel transistor and method therefor |
DE102006022105B4 (de) * | 2006-05-11 | 2012-03-08 | Infineon Technologies Ag | ESD-Schutz-Element und ESD-Schutz-Einrichtung zur Verwendung in einem elektrischen Schaltkreis |
DE102006022126B4 (de) * | 2006-05-11 | 2015-04-09 | Infineon Technologies Ag | Verfahren zum Herstellen eines elektronischen Bauelementes |
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US20080265343A1 (en) | 2007-04-26 | 2008-10-30 | International Business Machines Corporation | Field effect transistor with inverted t shaped gate electrode and methods for fabrication thereof |
US8440517B2 (en) * | 2010-10-13 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of fabricating the same |
US8729627B2 (en) * | 2010-05-14 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel integrated circuit devices |
DE102010029527B4 (de) * | 2010-05-31 | 2012-04-05 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung eines selbstjustierenden Transistors mit Mehrfachgate auf einem Vollsubstrat |
US8435845B2 (en) * | 2011-04-06 | 2013-05-07 | International Business Machines Corporation | Junction field effect transistor with an epitaxially grown gate structure |
CN102867751B (zh) | 2011-07-08 | 2015-09-09 | 中国科学院微电子研究所 | 一种全硅化金属栅体硅多栅鳍型场效应晶体管的制备方法 |
US8916426B2 (en) | 2012-03-27 | 2014-12-23 | International Business Machines Corporation | Passive devices for FinFET integrated circuit technologies |
US8785968B2 (en) | 2012-10-08 | 2014-07-22 | Intel Mobile Communications GmbH | Silicon controlled rectifier (SCR) device for bulk FinFET technology |
US9093304B2 (en) * | 2012-10-12 | 2015-07-28 | Finscale Inc. | Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication |
JP6309299B2 (ja) * | 2013-02-27 | 2018-04-11 | ルネサスエレクトロニクス株式会社 | 圧縮歪みチャネル領域を有する半導体装置及びその製造方法 |
US9356023B2 (en) | 2013-03-30 | 2016-05-31 | Intel Corporation | Planar device on fin-based transistor architecture |
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US20170229443A1 (en) | 2017-08-10 |
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US20160379972A1 (en) | 2016-12-29 |
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