TW201642437A - Stacked chip on film package structure and manufacturing method thereof - Google Patents
Stacked chip on film package structure and manufacturing method thereof Download PDFInfo
- Publication number
- TW201642437A TW201642437A TW104116427A TW104116427A TW201642437A TW 201642437 A TW201642437 A TW 201642437A TW 104116427 A TW104116427 A TW 104116427A TW 104116427 A TW104116427 A TW 104116427A TW 201642437 A TW201642437 A TW 201642437A
- Authority
- TW
- Taiwan
- Prior art keywords
- chip package
- flip chip
- film flip
- layer
- adhesive layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
本發明係關於一種薄膜覆晶封裝堆疊結構及其製作方法,特別地,本發明係關於一種可兼具節省空間及避免電磁干擾之功效的薄膜覆晶封裝堆疊結構及其製作方法。 The invention relates to a film flip chip package stack structure and a manufacturing method thereof. In particular, the present invention relates to a film flip chip package stack structure which can save space and avoid electromagnetic interference, and a manufacturing method thereof.
晶片封裝製程乃是用來保護晶片不受外界物理或化學變動因素所影響,並提供晶片絕緣保護以避免配線受到外界干擾或互相干擾。於驅動IC領域,特別是於液晶顯示螢幕(Liquid Crystal Display,LCD)的應用,一般常以捲帶承載封裝(Tape Carrier Package,TCP)、薄膜覆晶封裝(Chip on Film,COF)、玻璃覆晶封裝(Chip On Glass)等三種封裝方法對驅動IC進行封裝。基於成本考量、腳距、基板可撓性等各種因素,薄膜覆晶封裝幾乎已取代了捲帶承載封裝而成為主流趨勢。 The chip packaging process is used to protect the wafer from external physical or chemical fluctuations and to provide wafer insulation protection to protect the wiring from external interference or mutual interference. In the field of driver ICs, especially for liquid crystal display (LCD) applications, tape carrier (TCP), chip on film (COF), and glass are often used. The driver IC is packaged in three package methods, such as Chip On Glass. Based on cost considerations, pitch, substrate flexibility and other factors, the film flip chip package has almost replaced the tape carrier package and has become the mainstream trend.
由於現今電子產品要求越來越高的反應速度以及越來越複雜的功能,而外觀部分則不斷訴求輕便薄化,因此驅動電路也趨向高積體密度,也就是說,在一定的空間中要置入比以前更多的電路或晶片。越來越密集的積體電路設計,使得有限空間中的晶片數量增加且晶片間的距離越來越接近,而導致電磁干擾也越來越嚴重。 As today's electronic products demand higher and higher reaction speeds and more and more complex functions, and the appearance part is constantly demanding light and thin, the drive circuit also tends to a high integrated density, that is, in a certain space Place more circuits or chips than before. The increasingly dense integrated circuit design increases the number of wafers in a limited space and the distance between wafers becomes closer and closer, resulting in more and more serious electromagnetic interference.
基於上述問題,有必要研發一種能在一定空間內置入更多積體電路並能阻隔電磁干擾現象的薄膜覆晶封裝堆疊結構及其製作方法。 Based on the above problems, it is necessary to develop a film flip chip package stack structure capable of incorporating more integrated circuits in a certain space and blocking electromagnetic interference phenomenon and a manufacturing method thereof.
本發明的一範疇在於提供一種薄膜覆晶封裝堆疊結構。根據本發明的一具體實施例,薄膜覆晶封裝堆疊結構包含第一可撓性基板、第二可撓性基板、第一導線層、第二導線層、第一晶片、第二晶片以及黏膠層。於本具體實施例中,第一可撓性基板具有相對的第一功能面及第一背面,而第二可撓性基板則具有相對的第二功能面及第二背面。第一導線層設置於第一功能面上,且第二導線層設置於第二功能面上。第一晶片設置於第一功能面上並電性連接第一導線層,第二晶片則設置於第二功能面上並連接第二導線層。第一可撓性基板的第一背面面對第二可撓性基板的第二背面,並且,第一背面及第二背面以黏膠層互相連接。黏膠層內包含多個電磁屏蔽粒子,可幫助阻隔第一晶片及第二晶片間的電磁干擾。 One aspect of the present invention is to provide a thin film flip chip package stack structure. According to an embodiment of the present invention, a thin film flip chip package stack structure includes a first flexible substrate, a second flexible substrate, a first wire layer, a second wire layer, a first wafer, a second wafer, and an adhesive Floor. In this embodiment, the first flexible substrate has a first first functional surface and a first back surface, and the second flexible substrate has a second second functional surface and a second back surface. The first wire layer is disposed on the first functional surface, and the second wire layer is disposed on the second functional surface. The first wafer is disposed on the first functional surface and electrically connected to the first wire layer, and the second wafer is disposed on the second functional surface and connected to the second wire layer. The first back surface of the first flexible substrate faces the second back surface of the second flexible substrate, and the first back surface and the second back surface are connected to each other by an adhesive layer. The adhesive layer contains a plurality of electromagnetic shielding particles to help block electromagnetic interference between the first wafer and the second wafer.
本發明之另一範疇在於提供一種薄膜覆晶封裝堆疊結構之製作方法。根據本發明之一具體實施例,本發明之薄膜覆晶封裝堆疊結構的製作方法包含下列步驟:提供第一薄膜覆晶封裝體,第一薄膜覆晶封裝體包含具有第一背面之第一可撓性基板;提供第二薄膜覆晶封裝體,第二薄膜覆晶封裝體包含具有第二背面之第二可撓性基板;設置黏膠層於第一可撓性基板之第一背面上;佈設多個電磁屏蔽粒子於黏膠層上;以及將第一薄膜覆晶封裝體及第二薄膜覆晶封裝體 以背對背方式壓合,使得黏膠層連接第一背面與第二背面。 Another aspect of the present invention is to provide a method of fabricating a thin film flip chip package stack structure. According to an embodiment of the present invention, a method for fabricating a thin film flip chip package structure of the present invention comprises the steps of: providing a first thin film flip chip package, the first film flip chip package comprising a first surface having a first back surface a flexible substrate; a second film flip chip package, the second film flip chip package comprising a second flexible substrate having a second back surface; and an adhesive layer disposed on the first back surface of the first flexible substrate; Deploying a plurality of electromagnetic shielding particles on the adhesive layer; and disposing the first thin film flip chip package and the second thin film flip chip package The pressing is performed in a back-to-back manner such that the adhesive layer connects the first back surface and the second back surface.
本具體實施例之方法所製作出來的薄膜覆晶封裝堆疊結構具有內含電磁屏蔽粒子的黏膠層,此黏膠層可協助阻隔第一薄膜覆晶封裝體及第二薄膜覆晶封裝體間的電磁干擾。 The film flip chip package stack structure produced by the method of the embodiment has an adhesive layer containing electromagnetic shielding particles, and the adhesive layer can assist between the first film flip chip package and the second film flip chip package Electromagnetic interference.
關於本發明之優點與精神可以藉由以下的發明詳述以及所附圖式得到進一步的了解。 The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.
1‧‧‧薄膜覆晶封裝堆疊結構 1‧‧‧ Film flip chip package stack structure
10‧‧‧第一可撓性基板 10‧‧‧First flexible substrate
20‧‧‧第二可撓性基板 20‧‧‧Second flexible substrate
12‧‧‧第一導線層 12‧‧‧First wire layer
22‧‧‧第二導線層 22‧‧‧Second wire layer
14‧‧‧第一晶片 14‧‧‧First chip
24‧‧‧第二晶片 24‧‧‧second chip
16‧‧‧第一防銲層 16‧‧‧First solder mask
26‧‧‧第二防銲層 26‧‧‧Second solder mask
18‧‧‧第一封裝膠體 18‧‧‧First encapsulant
28‧‧‧第二封裝膠體 28‧‧‧Second encapsulant
100‧‧‧第一功能面 100‧‧‧ first function surface
102‧‧‧第一背面 102‧‧‧ first back
200‧‧‧第二功能面 200‧‧‧second function surface
202‧‧‧第二背面 202‧‧‧ second back
30‧‧‧黏膠層 30‧‧‧Adhesive layer
32‧‧‧電磁屏蔽粒子 32‧‧‧Electromagnetic shielding particles
圖一係繪示根據本發明之一具體實施例之薄膜覆晶封裝堆疊結構的示意圖。 1 is a schematic view showing a stacked structure of a film flip chip package according to an embodiment of the present invention.
圖二A至圖二F係繪示根據本發明之一具體實施例之薄膜覆晶封裝堆疊結構之製作方法各步驟的結構示意圖。 2A to 2F are structural diagrams showing the steps of a method for fabricating a stacked silicon wafer package according to an embodiment of the present invention.
圖三A至圖三G係繪示根據本發明之另一具體實施例之薄膜覆晶封裝堆疊結構之製作方法各步驟的結構示意圖。 FIG. 3A to FIG. 3G are structural diagrams showing steps of a method for fabricating a film flip chip package stack according to another embodiment of the present invention.
請參閱圖一,圖一係繪示根據本發明之一具體實施例之薄膜覆晶封裝堆疊結構1的示意圖。如圖一所示,薄膜覆晶封裝堆疊結構1包含第一可撓性基板10、第二可撓性基板20、第一導線層12、第二導線層22、第一晶片14、第二晶片24以及黏膠層30,上述各元件互相堆疊連接而形成薄膜覆晶封裝堆疊結構1。 Referring to FIG. 1, FIG. 1 is a schematic diagram showing a film flip chip package stack structure 1 according to an embodiment of the present invention. As shown in FIG. 1 , the film flip chip package stack structure 1 includes a first flexible substrate 10 , a second flexible substrate 20 , a first wire layer 12 , a second wire layer 22 , a first wafer 14 , and a second wafer . 24 and the adhesive layer 30, the above elements are stacked on each other to form a thin film flip chip package stack structure 1.
於本具體實施例中,第一可撓性基板10具有第一功能面100以及相對於第一功能面100之第一背面102,同樣地,第二可撓性基板20也具有相對的第二功能面200及第二背面202。可撓性基板10的第 一功能面100與可撓性基板20的第二功能面200,可用來設置晶片、導線層等功能性結構層。 In the embodiment, the first flexible substrate 10 has a first functional surface 100 and a first back surface 102 opposite to the first functional surface 100. Similarly, the second flexible substrate 20 also has an opposite second. Functional surface 200 and second back surface 202. The first of the flexible substrate 10 A functional surface 100 and a second functional surface 200 of the flexible substrate 20 can be used to provide a functional structural layer such as a wafer or a wiring layer.
如上所述,第一導線層12係設置在第一可撓性基板10的第一功能面100上,第二導線層22係設置於第二可撓性基板20的第二功能面200之上。第一晶片14設置於第一功能面100上並電性連接第一導線層12,更詳細地說,第一晶片14設置於第一功能面100所預先規劃出的晶片設置區中,並且可藉由凸塊與第一導線層12電性連接。同樣地,第二晶片24設置於第二功能面200所預先規劃出的晶片設置區中,並且可藉由凸塊與第二導線層22電性連接。第一導線層12與第二導線層22分別自上述的晶片設置區中延伸到第一功能面100與第二功能面200的外緣,使得第一晶片14與第二晶片24能分別透過第一導線層12與第二導線層22與外部電路進行電連接。 As described above, the first wire layer 12 is disposed on the first functional surface 100 of the first flexible substrate 10, and the second wire layer 22 is disposed on the second functional surface 200 of the second flexible substrate 20. . The first wafer 14 is disposed on the first functional surface 100 and electrically connected to the first wire layer 12 . In more detail, the first wafer 14 is disposed in the pre-planned wafer setting area of the first functional surface 100 and can be The bumps are electrically connected to the first wire layer 12. Similarly, the second wafer 24 is disposed in the pre-planned wafer setting area of the second functional surface 200, and is electrically connected to the second wiring layer 22 by bumps. The first wire layer 12 and the second wire layer 22 respectively extend from the wafer setting area to the outer edges of the first functional surface 100 and the second functional surface 200, so that the first wafer 14 and the second wafer 24 can respectively pass through the first A wire layer 12 and a second wire layer 22 are electrically connected to an external circuit.
除了上述各堆疊層之外,在第一導線層12與第二導線層22上還分別設置第一防銲層16以及第二防銲層26,第一防銲層16以及第二防銲層26分別覆蓋第一導線層12與第二導線層22,以對第一導線層12及第二導線層22提供保護效果,第一防銲層16以及第二防銲層26並分別暴露出局部的第一導線層12與第二導線層22,以供導線層與晶片和外部電路電性連接。此外,在第一晶片14、與第一功能面100之間、第二晶片24與第二功能200之間的空間更分別填充有第一封裝膠體18以及第二封裝膠體28,以對晶片和導線層之電性接點(即凸塊)提供保護效果。 In addition to the above stacked layers, a first solder resist layer 16 and a second solder resist layer 26, a first solder resist layer 16 and a second solder resist layer are respectively disposed on the first wiring layer 12 and the second wiring layer 22. The first wire layer 12 and the second wire layer 22 are respectively covered to provide a protective effect on the first wire layer 12 and the second wire layer 22, and the first solder resist layer 16 and the second solder resist layer 26 respectively expose a portion. The first wire layer 12 and the second wire layer 22 are electrically connected to the wire layer and the external circuit. In addition, a space between the first wafer 14 and the first functional surface 100 and between the second wafer 24 and the second function 200 is further filled with a first encapsulant 18 and a second encapsulant 28, respectively, to the wafer and Electrical contacts (ie, bumps) of the wire layer provide protection.
第一可撓性基板10的第一背面102與第二可撓性基板20 的第二背面202互相面對,並且兩者間以黏膠層30接合。黏膠層30內部包含多個電磁屏蔽粒子32,可對上下堆疊的第一晶片14及第二晶片24產生電磁屏蔽效果,以協助薄膜覆晶封裝堆疊結構1阻隔電磁干擾。於實務中,電磁屏蔽粒子32可選自金屬粒子或其他任何能產生電磁屏蔽效應的粒子,金屬粒子可包含銀、鐵、銅、銅/鎳、銅/銀、金、鋁、鎳、黃銅、不鏽鋼等,其他種類的粒子可包含鐵氧體(Ferrite)、石墨、碳黑、奈米碳管、奈米碳球、碳纖維、鍍鎳石墨、鍍鎳碳纖維以及鍍銅/鎳碳纖維等。 The first back surface 102 of the first flexible substrate 10 and the second flexible substrate 20 The second back faces 202 face each other and are joined by an adhesive layer 30 therebetween. The adhesive layer 30 internally includes a plurality of electromagnetic shielding particles 32, which can electromagnetically shield the first wafer 14 and the second wafer 24 stacked on top of each other to assist the film flip chip package structure 1 to block electromagnetic interference. In practice, the electromagnetic shielding particles 32 may be selected from metal particles or any other particle capable of producing an electromagnetic shielding effect, and the metal particles may include silver, iron, copper, copper/nickel, copper/silver, gold, aluminum, nickel, brass. Other types of particles may include ferrite, graphite, carbon black, carbon nanotubes, carbon spheres, carbon fibers, nickel-plated graphite, nickel-plated carbon fibers, and copper/nickel carbon fibers.
如圖一所示,本具體實施例之薄膜覆晶封裝堆疊結構1的電磁屏蔽粒子32於黏膠層30中可為緊密分佈而形成電磁屏蔽薄膜,而電磁屏蔽薄膜可位於黏膠層30靠近第二背面202之一側。電磁屏蔽粒子32於黏膠層30中的密度越靠近第一背面102則越低。電磁屏蔽薄膜能有效地阻隔第一晶片14與第二晶片24之間的電磁干擾現象。 As shown in FIG. 1, the electromagnetic shielding particles 32 of the film flip-chip package stack structure 1 of the present embodiment can be closely distributed in the adhesive layer 30 to form an electromagnetic shielding film, and the electromagnetic shielding film can be located near the adhesive layer 30. One side of the second back surface 202. The closer the density of the electromagnetic shielding particles 32 in the adhesive layer 30 is to the first back surface 102, the lower. The electromagnetic shielding film can effectively block electromagnetic interference between the first wafer 14 and the second wafer 24.
如上所述,本發明之薄膜覆晶封裝堆疊結構係呈兩薄膜覆晶封裝體背對背上下堆疊連接的型態,除了可提高電性接點、節省空間之外,用來連接兩薄膜覆晶封裝體的黏膠層內還包含有電磁屏蔽粒子,可阻隔兩薄膜覆晶封裝體間的電磁干擾,因此符合LCD驅動IC中晶片的高積體密度趨勢並避免其帶來的電磁干擾缺點。 As described above, the film flip-chip package stack structure of the present invention is a pattern in which two thin film flip chip packages are stacked back-to-back, which can be used to connect two thin film flip chip packages in addition to improving electrical contacts and saving space. The body of the adhesive layer also contains electromagnetic shielding particles, which can block the electromagnetic interference between the two film flip-chip packages, so it conforms to the high bulk density trend of the wafer in the LCD driver IC and avoids the electromagnetic interference disadvantage.
請參閱圖二A至圖二F,圖二A至圖二F係繪示根據本發明之一具體實施例之製作方法各步驟的結構示意圖。利用本具體實施例之製作方法可製作出如圖一所示的薄膜覆晶封裝堆疊結構1,故圖二A至圖二F的標號對照圖一之薄膜覆晶封裝堆疊結構1的標號來進行標 示。 Referring to FIG. 2A to FIG. 2F, FIG. 2A to FIG. 2F are schematic structural diagrams showing steps of a manufacturing method according to an embodiment of the present invention. The thin film flip chip package stack structure 1 as shown in FIG. 1 can be fabricated by using the fabrication method of the embodiment, so the reference numerals of FIG. 2A to FIG. 2F are compared with the labels of the film flip chip package stack structure 1 of FIG. Standard Show.
本具體實施例之薄膜覆晶封裝堆疊結構的製作方法包含下列步驟。首先,如圖二A所示,提供包含第一可撓性基板10、第一導線層12及第一晶片14的第一薄膜覆晶封裝體,其中第一導線層12、第一晶片14係設置在第一可撓性基板10的第一功能面100上;如圖二B所示,提供包含第二可撓性基板20、第二導線層22及第二晶片24的第二薄膜覆晶封裝體,其中第二導線層22、第二晶片24係設置在第二可撓性基板20的第二功能面200上。第一薄膜覆晶封裝體及第二薄膜覆晶封裝體的結構與前述的具體實施例大致上相同,故於此不再贅述。 The manufacturing method of the film flip chip package stack structure of the embodiment includes the following steps. First, as shown in FIG. 2A, a first thin film flip chip package including a first flexible substrate 10, a first wiring layer 12, and a first wafer 14 is provided, wherein the first wiring layer 12 and the first wafer 14 are Provided on the first functional surface 100 of the first flexible substrate 10; as shown in FIG. 2B, a second thin film on-chip including the second flexible substrate 20, the second conductive layer 22, and the second wafer 24 is provided. The package body, wherein the second wire layer 22 and the second wafer 24 are disposed on the second functional surface 200 of the second flexible substrate 20. The structures of the first thin film flip chip package and the second thin film flip chip package are substantially the same as those of the foregoing specific embodiments, and thus will not be described herein.
接著,如圖二C所示,設置黏膠層30於第一可撓性基板10之第一背面102上。具體而言,第一薄膜覆晶封裝體可被翻轉,使第一可撓性基板10的第一背面102朝上,以利設置黏膠層30於第一背面102上。如圖二D所示,佈設多個電磁屏蔽粒子32於黏膠層30上,其中電磁屏蔽粒子32的佈設可利用噴灑的方法將電磁屏蔽粒子32噴灑於黏膠層30上。此外,設置於第一背面102上的黏膠層30可為液態,因此電磁屏蔽粒子32佈設於液態的黏膠層30後,可由液態的黏膠層30表面漸漸滲入內部。由於黏膠層30已被設置於第一背面102上,故噴灑時電磁屏蔽粒子32會先接觸黏膠層30遠離第一背面102之一側,致使噴灑後電磁屏蔽粒子32在黏膠層30遠離第一背面102的一側的濃度較高,且越接近第一背面102濃度越低。 Next, as shown in FIG. 2C, an adhesive layer 30 is disposed on the first back surface 102 of the first flexible substrate 10. Specifically, the first thin film flip chip package can be flipped so that the first back surface 102 of the first flexible substrate 10 faces upward to facilitate the adhesive layer 30 on the first back surface 102. As shown in FIG. 2D, a plurality of electromagnetic shielding particles 32 are disposed on the adhesive layer 30, wherein the electromagnetic shielding particles 32 are disposed by spraying the electromagnetic shielding particles 32 onto the adhesive layer 30 by spraying. In addition, the adhesive layer 30 disposed on the first back surface 102 can be in a liquid state. Therefore, after the electromagnetic shielding particles 32 are disposed on the liquid adhesive layer 30, the surface of the liquid adhesive layer 30 can gradually penetrate into the interior. Since the adhesive layer 30 has been disposed on the first back surface 102, the electromagnetic shielding particles 32 will first contact the adhesive layer 30 away from the side of the first back surface 102 during spraying, so that the electromagnetic shielding particles 32 after spraying are in the adhesive layer 30. The concentration away from the side of the first back side 102 is higher, and the closer to the first back side 102, the lower the concentration.
接著,如圖二E所示,將第一薄膜覆晶封裝體及第二薄膜覆晶封裝體以背對背方式壓合,使黏膠層30連接第一背面102及第二 背面202。經過壓合後,電磁屏蔽粒子32會緊密分佈於黏膠層30遠離第一背面102的一側,亦即,靠近第二背面202的一側,進而形成電磁屏蔽薄膜。於本具體實施例中,電磁屏蔽粒子32可選用銀、鐵、銅、銅/鎳、銅/銀、金、鋁、鎳、黃銅、不鏽鋼、鐵氧體(Ferrite)、石墨、碳黑、奈米碳管、奈米碳球、碳纖維、鍍鎳石墨、鍍鎳碳纖維或鍍銅/鎳碳纖維等具有電磁屏蔽效果的材料。 Next, as shown in FIG. 2E, the first thin film flip chip package and the second thin film flip chip package are pressed back to back, and the adhesive layer 30 is connected to the first back surface 102 and the second surface. Back side 202. After being pressed, the electromagnetic shielding particles 32 are closely distributed on the side of the adhesive layer 30 away from the first back surface 102, that is, on the side close to the second back surface 202, thereby forming an electromagnetic shielding film. In this embodiment, the electromagnetic shielding particles 32 may be selected from the group consisting of silver, iron, copper, copper/nickel, copper/silver, gold, aluminum, nickel, brass, stainless steel, ferrite, graphite, carbon black, Electromagnetic shielding materials such as carbon nanotubes, carbon spheres, carbon fibers, nickel-plated graphite, nickel-plated carbon fibers or copper-plated/nickel carbon fibers.
再者,黏膠層30係用來連接第一薄膜覆晶封裝體與第二薄膜覆晶封裝體,故液態的黏膠層30須經過固化製程轉變為固態,才具有足夠的接合力接合固定兩薄膜覆晶封裝體。如圖二F所示,於壓合後對液態的黏膠層30進行固化製程,使得液態的黏膠層30轉變為半固態再進一步轉變為固態。 Furthermore, the adhesive layer 30 is used to connect the first film flip chip package and the second film flip chip package, so that the liquid adhesive layer 30 has to be converted into a solid state through a curing process to have sufficient bonding force to be fixed. Two thin film flip chip packages. As shown in FIG. 2F, the liquid adhesive layer 30 is subjected to a curing process after pressing, so that the liquid adhesive layer 30 is transformed into a semi-solid state and further converted into a solid state.
上述具體實施例之製作方法為整個薄膜覆晶封裝堆疊結構製作完成後再對液態的黏膠層30進行固化。然而,為了製作方便起見,也可先對液態的黏膠層30進行半固化,使黏膠層30先維持一個特定形狀後再進行後續程序。請參閱圖三A至圖三G,圖三A至圖三G係繪示根據本發明之另一具體實施例之薄膜覆晶封裝堆疊結構之製作方法各步驟的結構示意圖。圖三A至圖三D所說明之步驟與圖二A至圖二D相同,在此不再贅述。本具體實施例與上一具體實施例不同處,在於本具體實施例在如圖三D所示佈設多個電磁屏蔽粒子32於液態之黏膠層30上之後,先對已包含電磁屏蔽粒子32的液態之黏膠層30進行固化製程使液態之黏膠層30由液態轉變為半固態,如圖三E所示。接著,再將第一薄膜覆晶封裝體及第二薄膜覆晶封裝體以背對背方式壓合, 以對半固態的黏膠層30施壓使電磁屏蔽粒子32緊密分佈於半固態之黏膠層30中而形成電磁屏蔽薄膜,如圖三F所示。最後,再對半固態之黏膠層30進行固化製程使其由半固態進一步轉變為固態,如圖三G所示。藉此,轉變成為如圖一所示之固態的黏膠層30,以連接第一薄膜覆晶封裝體與第二薄膜覆晶封裝體而形成薄膜覆晶封裝堆疊結構1,同時黏膠層30中的電磁屏蔽粒子32所形成的電磁屏蔽薄膜提供了良好的電磁屏蔽效果。 The manufacturing method of the above specific embodiment is to cure the liquid adhesive layer 30 after the entire film flip-chip package stack structure is completed. However, for the sake of convenience of production, the liquid adhesive layer 30 may be semi-cured first, so that the adhesive layer 30 is maintained in a specific shape before the subsequent process. Please refer to FIG. 3A to FIG. 3G. FIG. 3A to FIG. 3G are structural diagrams showing steps of a method for fabricating a film flip chip package stack according to another embodiment of the present invention. The steps illustrated in FIG. 3A to FIG. 3D are the same as those in FIG. 2A to FIG. 2D, and are not described herein again. The difference between this embodiment and the previous embodiment is that after the plurality of electromagnetic shielding particles 32 are disposed on the liquid adhesive layer 30 as shown in FIG. 3D, the electromagnetic shielding particles 32 are included. The liquid adhesive layer 30 is subjected to a curing process to convert the liquid adhesive layer 30 from a liquid state to a semi-solid state, as shown in FIG. 3E. Then, the first thin film flip chip package and the second thin film flip chip package are pressed back to back. The electromagnetic shielding film 32 is tightly distributed in the semi-solid adhesive layer 30 by applying pressure to the semi-solid adhesive layer 30 to form an electromagnetic shielding film, as shown in FIG. Finally, the semi-solid adhesive layer 30 is subjected to a curing process to further convert from a semi-solid to a solid state, as shown in FIG. 3G. Thereby, the solid-state adhesive layer 30 as shown in FIG. 1 is connected to form the thin film flip-chip package stack 1 by connecting the first thin film flip chip package and the second thin film flip chip package, and the adhesive layer 30 is simultaneously formed. The electromagnetic shielding film formed by the electromagnetic shielding particles 32 provides a good electromagnetic shielding effect.
綜上所述,本具體實施例之薄膜覆晶封裝堆疊結構及其製作方法,可使LCD驅動IC在單位體積內的晶片數量增加,符合高速積體電路的趨勢,同時具有良好的電磁屏蔽效果,可有效阻隔晶片間的電磁干擾現象。 In summary, the film flip-chip package stack structure and the manufacturing method thereof of the embodiment can increase the number of wafers in the unit volume of the LCD driver IC, conform to the trend of the high-speed integrated circuit, and have a good electromagnetic shielding effect. It can effectively block the electromagnetic interference between the wafers.
藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。 The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.
1‧‧‧薄膜覆晶封裝堆疊結構 1‧‧‧ Film flip chip package stack structure
10‧‧‧第一可撓性基板 10‧‧‧First flexible substrate
20‧‧‧第二可撓性基板 20‧‧‧Second flexible substrate
12‧‧‧第一導線層 12‧‧‧First wire layer
22‧‧‧第二導線層 22‧‧‧Second wire layer
14‧‧‧第一晶片 14‧‧‧First chip
24‧‧‧第二晶片 24‧‧‧second chip
16‧‧‧第一防銲層 16‧‧‧First solder mask
26‧‧‧第二防銲層 26‧‧‧Second solder mask
100‧‧‧第一功能面 100‧‧‧ first function surface
102‧‧‧第一背面 102‧‧‧ first back
200‧‧‧第二功能面 200‧‧‧second function surface
202‧‧‧第二背面 202‧‧‧ second back
30‧‧‧黏膠層 30‧‧‧Adhesive layer
Claims (14)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW104116427A TWI562326B (en) | 2015-05-22 | 2015-05-22 | Stacked chip on film package structure and manufacturing method thereof |
CN201510453927.5A CN106169462B (en) | 2015-05-22 | 2015-07-29 | Thin film flip chip package stack structure and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW104116427A TWI562326B (en) | 2015-05-22 | 2015-05-22 | Stacked chip on film package structure and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201642437A true TW201642437A (en) | 2016-12-01 |
TWI562326B TWI562326B (en) | 2016-12-11 |
Family
ID=57358882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW104116427A TWI562326B (en) | 2015-05-22 | 2015-05-22 | Stacked chip on film package structure and manufacturing method thereof |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN106169462B (en) |
TW (1) | TWI562326B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11189597B2 (en) | 2018-10-29 | 2021-11-30 | Novatek Microelectronics Corp. | Chip on film package |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5641997A (en) * | 1993-09-14 | 1997-06-24 | Kabushiki Kaisha Toshiba | Plastic-encapsulated semiconductor device |
EP0714125B1 (en) * | 1994-11-24 | 1999-12-29 | Dow Corning Toray Silicone Company Limited | Method of fabricating a semiconductor device |
US7503155B2 (en) * | 2002-08-26 | 2009-03-17 | Meyers John G | Method for packaging a tape substrate |
US20070267737A1 (en) * | 2006-05-17 | 2007-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packaged devices and methods for forming packaged devices |
CN101877335B (en) * | 2009-04-30 | 2012-07-25 | 玮锋科技股份有限公司 | Gradient type anisotropic conductive film and manufacturing method thereof |
CN102104033A (en) * | 2009-12-18 | 2011-06-22 | 中国科学院微电子研究所 | Three-dimensional mixed signal chip stack package and preparation method thereof |
TW201208035A (en) * | 2010-08-10 | 2012-02-16 | Powertech Technology Inc | Multi-chip stacked assembly with ground connection of EMI shielding |
JP6245792B2 (en) * | 2012-03-29 | 2017-12-13 | デクセリアルズ株式会社 | Conductive particle, circuit connection material, mounting body, and manufacturing method of mounting body |
US8698288B1 (en) * | 2013-05-23 | 2014-04-15 | Freescale Semiconductor, Inc. | Flexible substrate with crimping interconnection |
TWI509750B (en) * | 2013-09-30 | 2015-11-21 | Chipmos Technologies Inc | Multi-chip tape package structure |
-
2015
- 2015-05-22 TW TW104116427A patent/TWI562326B/en active
- 2015-07-29 CN CN201510453927.5A patent/CN106169462B/en active Active
Also Published As
Publication number | Publication date |
---|---|
TWI562326B (en) | 2016-12-11 |
CN106169462A (en) | 2016-11-30 |
CN106169462B (en) | 2019-02-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3578770B2 (en) | Semiconductor device | |
TWI618205B (en) | Chip on film package and heat dissipation method thereof | |
TWI555166B (en) | Stack package and method of manufacture | |
TWI409924B (en) | Semiconductor package and manufacturing method thereof | |
JP2023165871A (en) | Method for manufacturing electronic component device and electronic component device | |
US10679914B2 (en) | Electronic package and method for manufacturing the same | |
US20110057301A1 (en) | Semiconductor package | |
TWI496258B (en) | Fabrication method of package substrate | |
JP2005535103A (en) | Semiconductor package device and manufacturing and testing method | |
US20070052082A1 (en) | Multi-chip package structure | |
JP2008159718A (en) | Multichip module and its manufacturing method, and mounting structure of multichip module and its manufacturing method | |
TWI770405B (en) | Package device and method of manufacturing the same | |
TWI332275B (en) | Semiconductor package having electromagnetic interference shielding and fabricating method thereof | |
TW201528459A (en) | Chip package and method for forming the same | |
JP2000082722A (en) | Semiconductor device and its manufacture as well as circuit board and electronic apparatus | |
TWI729895B (en) | Semiconductor package | |
JP6802314B2 (en) | Semiconductor package and its manufacturing method | |
TW201620100A (en) | Package substrate, semiconductor package and method of manufacture | |
TW201508877A (en) | Semiconductor package and manufacturing method thereof | |
TWI556383B (en) | Package structure and method of manufacture | |
TW201642437A (en) | Stacked chip on film package structure and manufacturing method thereof | |
TWI645518B (en) | Package structure and the manufacture thereof | |
KR100510518B1 (en) | Semiconductor device and packaging method of the semiconductor device | |
TWI430376B (en) | The Method of Fabrication of Semiconductor Packaging Structure | |
US8410598B2 (en) | Semiconductor package and method of manufacturing the same |