TW201642420A - Low-profile footed power package - Google Patents

Abstract

The power package includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a led. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The head tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with an electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die. The result is a package with a minimal footprint that is suitable for the technique known as "wave soldering" that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed.

Description

Thin foot power package [Reciprocal Reference of Related Applications]

This application is a continuation of U.S. Patent Application Serial No. 14/056,287, filed on Oct. 17, 2013, and filed on March 9, 2013, the U.S. Provisional Application Nos. 61/775,540 and 61/. Priority interest in 775,544. The texts are hereby incorporated by reference into their entirety in their entirety.

The present invention relates to a semiconductor package for a power component and a power integrated circuit.

Semiconductor components and integrated electrical traces (ICs) are typically included in a semiconductor package that includes a protective coating or encapsulating material to prevent damage during handling and assembly, during shipping, and when mounting components onto a printed circuit board. . The packaging material is usually made of plastic for cost reasons. Plastic "molding compound" in liquid state, without cooling and solid Before being turned into a solid plastic, it is injected to a high temperature and it communicates with the surrounding elements in the mold cavity. Such packages are often referred to as "return molding."

The interconnection of the components is performed by a metal leadframe, typically made of copper, that conducts current and heat from the semiconductor component or wafer into and around the printed circuit board. The connection between the wafer and the lead frame generally comprises bonding the wafer to the "wafer pad" of the lead frame with an electrically conductive or insulating epoxy resin, and the metal bonding wire, usually made of gold, copper or aluminum, from the surface of the wafer Connect to the lead frame. Other options, such as solder balls, gold bumps or copper posts, can be used directly on the upper surface of the wafer to be bonded to the lead frame.

While the metal leadframe acts as a conductor of electricity and heat in the finished product, the leadframe will temporarily hold the component until the plastic hardens during the manufacturing process. After the plastic is cured, the packaged wafers are separated or "cut" from the same leadframe into other packages by mechanical cutting. The cut cuts the metal lead frame and, in some cases, also cuts the hardened plastic.

In "foot" semiconductor packages, where metal pins or "pins" protrude into the plastic and end at the foot, then the pins are bent mechanically to become their final shape, the final finished package The tape and reel are prepared as a package to the customer's printed circuit board (PCB).

1A shows an example of a foot package 1, including a semiconductor wafer 5, a plastic 2, bonding wires 6C and 6D, metal pins 3B, 3C, 3D, and a metal wafer pad 3A. The metal pins and leadframes include components that are separated by a single leadframe 3 during manufacture. The metal pins 3B, 3C and 3D are thinner than the wafer pad 3A, present in the molding compound 2 at a height above the bottom surface 8 of the wafer pad 3A (also shown in FIG. 1B), and must be in the curved portions 4B, 4C and 4D. Bend downward so that the non-bent portions of the metal pins 3B, 3C and 3D lie flat or "coplanar" on the PCB of the flat bottom surface 8 of the metal wafer pad 3A. This type of package is sometimes referred to as a "gull-wing" package due to the shape of its curved pins.

Such foot packages are manufactured in a variety of sizes and pin configurations ranging from three pins for packaged transistors and simple ICs such as bipolar junction transistors, power MOSFETs and shunt voltage regulators. Enclose 12 pins of integrated circuits (ICs). To date, billions of products have been manufactured using injection molded foot plastic packages. Common packages include small transistor packages like the SC70 and SOT23 packages, smaller outline packages such as SOP-8, SOP-16 or SOP-24, and quad flats for more pin counts. Package or LQFP. LQFP packages can have 64 or more pins with even numbers on each of its four edges, while SOT and SOP have pins on only two sides of the package.

In order to achieve the pin bending process, the minimum package height of SOP and LQFP is usually over 1.8mm. Includes small transistor packages such as S0T23-3, S0T23-5, SOT23-6, and SOT223, small chip packages such as SC70, TSOP-8 thin outline package, and TSS0P-8 thin ultra-small outline package. Some packages have been designed to be thinner and thinner than 1mm. It is difficult to manufacture any of these packages below 1 mm thickness. Even for larger package heights, pin coplanarity with good pin bending remains a constant concern in mass production of gull-wing packages.

Pin-accurate molding is problematic with strict specifications and error requirements. The customer considers the deformed pin to be a quality defect and requires formal corrective action to respond and promise to improve the plan. In extreme cases, manufacturing that exceeds certain tolerances can result in manufacturing disruptions, which can lead to economic penalties, cancellation of supplier qualifications, and even litigation. The lack of control of pin bending during manufacturing is not the only limitation of these packages. Since the package height is a major consideration in IC packages, the thickness of the leadframe is limited, typically 200 μm or less, and it exhibits relatively poor power due to its inability to efficiently transfer heat from the wafer to the printed circuit board or heat sink. Dissipation ability.

The power package structure is like the DPAK or D ² PAK shown in Figure 1A, using a thicker metal, 2.5 times the package of the integrated circuit, specifically about 500 μm (microns). As a result, ICs have become more "high-tech" over time, and IC packaging and power packaging have gone a part in their manufacturing methods, which require complex manufacturing and are suitable for use only on expensive reflow printed circuit boards (PCBs). ) Assembly line. Conversely, the power package relies on the old "low-tech" factory and method, and the general adhesion method uses the "wave soldering" technology of the traditional PCB factory. For the same PCB area, a wave soldering based plant can significantly reduce manufacturing costs - from one-half to one-quarter of the cost of a reflow assembly plant.

Due to age, the minimum size and error of the power package is often greater than the new IC package. Referring again to Figure 1A, the pin spacing between pins 3C, 3B and 3D is 1.5 mm. Conversely, the center-to-center spacing of today's ICs pins is typically 0.4mm. 1B shows a cross-sectional view of a tangential line taken along and through the lead 3D package 1, including a wafer pad 3A, a semiconductor wafer 5, a conductor bond wire 6D, and a mold injection molding compound 2. The wafer pad 3A includes an upper surface 18 and a bottom surface 8 and is coated on all four sides by a mold injection molding plastic 2. The wafer pad 3A also extends laterally beyond the mold injection molding plastic 2 at a distance 16 and includes an exposed surface that is not covered by the mold injection plastic 2 along the upper surface 18.

The conductor pin 3D is present in the mold injection plastic 2 parallel to the lower surface 8, above the lower surface 8, but below the upper surface of the mold injection plastic 2. The conductor pin 3D is mechanically bent into a bent portion 4D so that the tail end of the conductor pin 3D is seated above and is flush with the lower surface 8 surface. The special metal on the surface of the wafer 5 is referred to as a bond pad, which is soldered to the conductor pins 3D by a conductor bond wire 6D to enable the circuit to be connected from the printed circuit board to the bond pads. The bonding wire 6D may include gold, aluminum or copper. The bond pad can be composed of a specific dedicated metallization region, such as a gate pad, or in the case of a high power device, a large area of array metal can be placed over the active transistor of a large area array.

For example, in a vertical power MOSFET or an insulate gate bipolar transistor (IGBT), typically a large area of the top metal of the wafer 5 is electrically connected to the source of the component, and a smaller bond pad is connected to it. At the gate or input, the back side of the wafer 5 is electrically connected to the drain or the component is directly connected to the wafer pad 3A via a die bond 35 output, a thin layer of solder or a conductive layer of solder. In manufacturing, the bond wire 6D cannot sag and touch the wafer pad 3A or the component will become electrically shorted. In very high current components, bond wire 6D can be replaced with a copper "clip" that turns over a large area of conductor surface and conductor pins 3D on wafer 5. In some package designs, the vertical position of the conductor pins 3D is not coplanar with the upper surface 18 of the wafer pad 3A.

In the manufacturing process, since the bent legs occur after the plastic molding, the curved portion 4D separates the lateral distance 17 from the mold injection molding plastic 2 or permanently damages the molding compound 2, such as cracks, peeling, and conductor pins 3D and mold. Possible results of delamination between plastics 2. This damage is during visual inspection It can result in loss of production and does not capture its damage, which can lead to reliability failure. If the curved portion 4D is bent too much or too little, so that the bottom surface of the conductor pin 3D is not coplanar with the bottom surface 8 of the wafer pad 3A, it may be another source of manufacturing defects.

A similar, but slightly different, cross-sectional view is shown in Figure 1C, which is a cross-sectional view taken along a line cut along and through conductor pin 3B. In this case, the pin 3B is actually and electrically connected to the wafer pad 3A. Like the conductor pin 3C and other conductor pins, the conductor pin 3B cannot be bent with any bent portion 4B which is closer to the mold injection plastic 2 than the lateral distance 17 minimum, otherwise the mold injection plastic 2 may be damaged.

The bottom view of the package 1, that is, the bottom of the package and the bottom surface 8 are coplanar, as shown in FIG. 1D, the exposed bottom three sides of the wafer pad 3A are covered by the mold injection plastic 2 except for the metal portion 16 or "heat sink". Extends beyond plastic. Portions of pins 3C, 3B and 3D that are not coplanar with the bottom surface 8 are shown in dashed lines, including respective bends 4C, 4B and 4D.

Figure 2A shows a first step of fabrication showing wafer pads 3A in two different cross-sectional views, the upper graph representing a cross-section through and along conductor pin 3B, and the lower graph showing the pass and along conductor leads. A cross-sectional view of the foot 3C. The process begins with a solid copper block, and a thin coating of selectively tin-plated for improved solderability, shielded by a protective layer, ie, photomask 30, typically including a pattern A photoresist material or an organic material that is not susceptible to acid. The reticle 30 can be applied uniformly and then selectively removed, for example using optical exposure to define the area to be removed, or alternatively it can be selectively applied by a steel sheet reticle.

After application and patterning, the patterned mask 30 is baked to harden the material. The copper flakes are then etched in an acid solution, for example hydrochloric acid comprising HCL:FeCl ₃ :H ₂ O mixed in a ratio of 4:1:5, nitric acid comprising HNO ₃ :H ₂ O ₂ in a ratio of 1:20, or ammonia comprising NH ₃ :H ₂ O ₂ was mixed in a ratio of 4:1. If the copper is pre-plated with a thin layer of tin (Sn), the tin must first be removed by etching using hydrofluoric acid, including HF:HCL mixed in a ratio of 1:1, HF:HNO ₃ mixed in a ratio of 1:1, Or HF: H ₂ O is mixed in a ratio of 1:1. A more detailed list of common wet process chemical metal etches can be found in semiconductor process textbooks or online at http://www.cleanroom.byu.edu/wet_etch.phtml . Tin and copper can be etched on one side or by immersion in an acid bath. In the case of immersion etching, in order to prevent excessive etching of the lead frame and thinning of the lead frame, another protective layer must be applied on the back side. For the sake of clarity, this backside protective layer is not shown in the figures, but the techniques of these semiconductor packages are well known.

Returning to Figure 2A, after etching, the copper forms an L-shape, the L-shaped thicker portion including the wafer pad 3A and the thinner "diving plate" 3Z of the projection design. In system The patterned reticle 30 is then removed before the process continues. The cross-sectional view in this step shows an illustration that is identical to the two sections described above. In Figure 2B, a patterned mask 31 is employed to repeatedly etch the portion of the diving plate projection 3Z. In the upper illustration, the slab projection 3Z is protected to result in pin 3B, while the slab projection 3Z illustrated in the lower portion separates the wafer pad 3A by etching to create the individual pins 3D and gaps 32. Pin 3D is maintained in position by being connected to a lead frame not shown around. After etching, the mask 31 is removed.

Next, as shown in FIG. 2C, the semiconductor wafer 5 is mounted on the wafer pad 3A using a thin wafer adhesion layer 35 including solder or a conductive epoxy. In the lower cross-sectional view 2D, one or more bonding wires 6D engage the top of the semiconductor wafer 5 and connect it to the leads 3D. In the upper cross-sectional view, it is not necessary to bond the bonding wires because the wafer bonding layer 35 electrically connects the back surface of the wafer 5 to the wafer pad 3A and up to the lead 3B. After the wire bonding, plastic molding using a transfer molding technique is used, as depicted in FIG. 2E, in order to form a mold injection molding plastic 2 package semiconductor wafer 5, bonding wire 6D and other bonding wires (not shown), And a portion of the wafer pad 3A, pins 3B, 3D and other pins (not shown). In the semiconductor field, transfer molding is superior to injection molding because it gives a superior mold that requires less glue to be removed.

In Figure 2F, pins 3B and 3D are bent by a mechanical "molding" tool that produces curved portions 4B and 4D at their respective pins. The bottom of the pin is coplanar with the bottom surface 8 of the leadframe 3A. Finally, the pins are clipped and pins 3B and 3D are disconnected from leadframe 3G. This cutting operation is referred to as "singulation" because a leadframe contains a number of encapsulated grains that have been packaged or cut into "single" pieces. In the bending forming operation, the mechanical forming tool is firmly clamped and supported in the lead space 17 to prevent the mold injection plastic 2 from being broken due to the stress generated by the operation. The length of the pin space 17 is determined by the size set by the manufacturer's mechanically formed tool and cannot be reduced to less than a specified minimum size without risking package damage during manufacture. From Figure 2F, it is apparent that the pin space 17 and the curved portions 4B and 4D represent "wasted" PCB area because they do not contain active semiconductor dies and they do not represent a used PCB area. Due to poor area efficiency, this packaging technology is not compatible with space-sensitive applications such as smartphones and mobile personal electronics.

The top view of FIG. 3A shows that the conductive line below the printed circuit board 100 is used to adhere the foot package 1 to the PCB, which is a PCB pin pad. The pin pad contains four soldered package 1 components to the area on the PCB: conductor line 41C solder pin 3C end, conductor line 41B solder pin 3B end, conductor line 41D solder pin 3D end, and fourth area It is a large lead pad including a conductor line 41A for soldering the bottom of the package wafer pad 3A. In the case of pins 3C, 3B and 3D, solder Applications can use wave soldering from the above. Through surface tension, the solder naturally wets to the pins and PCB conductive lines. By mechanically temporarily fixing the position by glue or tape, the molten solder itself adheres to the leads and the PCB conductive lines are fixed once cooled and solidified.

The wave soldering method using solder is not possible to connect the large pad pad of the conductor line 41A to the wafer pad 3A of the package. (Marked as dashed line "3A" means that wafer pad 3A is positioned). In this case, the flaky solder 45 must be manually placed onto the PCB before the package 1 is placed on the printed circuit board, so the wafer pad 3A must be fused to the position by heating in the oven prior to wave soldering. The wafer pad 3A can lie flat on the solder during the soldering of the wave and move slightly from its target position, causing a slight inaccuracy in the soldering process. In order to prevent short circuits on the PCB, the components cannot be mounted too tightly to each other. The dashed line 44 represents a "reserved" area where no other components can be mounted to avoid short circuits. Depending on the design rules of the printed circuit board manufacturer, this reserved area 44 may substantially increase the area required for the area to mount a component on the PCB and greatly reduce the area fill density of the product.

3B is a cross-sectional view showing the package 1 being adhered to a two-layer PCB 100. As shown, the PCB 100 includes lower conductor layers 43A and 43B, upper conductor layers 41A and 41B, and conductive vias 42 interposed therebetween. Inside the PCB section. As shown, wafer pad 3A is on the package leads It is placed on the PCB 100 conductor line 41B before soldering, and is soldered to the PCB by the intermediate solder layer 45. Solder layer 45 is typically fused prior to wave soldering. After the wave soldering, the solder is electrically connected to the lead 3D to the PCB conductor line 41A. One feature of the wave soldering is that it connects the side of the lead 3D to the PCB conductor line 41A by the solder 34D, but no intermediate solder exists between the lead 3D and the PCB conductor line 41A.

Therefore, in "low-tech" PCB manufacturing lines, wave soldering is used to solder all components except large packages of power pads, which is a replacement for solder or solder paste to be placed or dispensed manually prior to placement of the power components. This method of manually placing the solder is slow and expensive, and therefore, is only cost effective when used for fewer components. As shown, the solder 34A is also gradually increased from the wave soldering process to one side of the wafer pad 3A. While this solder joint can sufficiently carry the rated current of the power component, it does not guarantee a low thermal resistance between the wafer pad 3A and the PCB conductor traces 41B, 42 and 43B. Thus, when the power components are mixed with other ICs, the use of solder paste 45 in the wave soldering manufacturing process is still unavoidable.

An alternative PCB assembly method, known as reflow soldering, involves printing solder paste throughout the printed circuit board prior to mounting the component, although this process is very accurate but slow and therefore expensive, especially because of high cost reflow The furnace is required to melt the solder in a control method to avoid movement of the components lying flat during welding. While on a smartphone, tablet, notes In the manufacture of computer and mobile products, reflowed PCB components are rarely used in larger low-cost consumer electronics such as televisions, automotive electronics, consumer electronics, large appliances, or power modules.

In a common product package, package 1 is shown in FIG. 1A as a vertical power MOSFET comprising three electrode terminals. The drain of the MOSFET is electrically connected from the back side of the semiconductor wafer 5, and the gate input wire bond is connected from above the wafer. The gate pads are connected by a single wire. The source requires that most of the source bond wires be bonded by the top surface of most of the wafer surface covered by a large area of metal. The equivalent circuit of the power MOSFET is mounted in the above package as shown in FIG. 3C, in which the gate of the power MOSFET 47 is connected to the conductor pin 3C, and the source of the power MOSFET 47 is connected to the conductor by the bonding wire 6D. The leg 3D, and the back drain are connected to the wafer pad 3A and the conductor pin 3B. The high current path includes a parasitic inductance 49A size L _S caused by the source connection bonding wire, and a parasitic inductance 49B size L _D generated by the drain connection package lead frame structure.

In operation, the source inductance 49A has several causes that are extremely worrying. First, the conductor pin 3B can be used as a true drain voltage of the MOSFET 47 after monitoring the high current flowing through the wafer pad 3A and its parasitic inductance 49B. The source inductance 49A including the bond wire inductance can be large, even at L _S >L _D . Unlike in the case of a drain connection, with the back of wafer pad 3A and conductor pin 3B as connections, in package 1, a single sense pin measures the true source voltage of MOSFET 47 is not feasible, however in circuit operation The stray source inductance is problematic and worse than the drain inductance.

Especially when the power MOSFET is switched off, any change in the drain current can cause the source voltage of the MOSFET 47 to oscillate. When the source voltage oscillates, the gate-to-source voltage may rise and fail above the threshold voltage of the MOSFET, and multiple switches increase the switching losses accordingly. In high speed switching, it would be advantageous to connect a separate conductor to the true source of power MOSFET 47 and bypass source inductor 49A. Unfortunately, this conductor pin is not possible in today's DPAK and D ² PAK packages because the conductor pin 3B is used for mechanical support during the packaging process and must be tightly connected to the wafer pad 3A. together.

The function of the conductive pin 3B is shown in FIG. 4A, in which the wafer pad 3A is connected to the lead frame strip 38 by the lead 3B. Therefore, when the conductor pins 3C and 3D need not be connected to the wafer pad 3A, the conductor pin 3B must be connected to the wafer pad 3A, otherwise there will be nothing to fix its position during the manufacturing process, that is, during bonding of the wafer, the wire bonding, During the sealing or cutting and forming steps.

The leadframe also shows that each wafer is encapsulated by a separate mold injection of plastic 2, with a plurality of cavities specifically matching the leadframe. A corresponding mold is used to form a molding compound to encapsulate the wafer and its bonding wire as shown in FIG. 4B, including an upper cavity 37B and a lower substrate 37A, when combined Forming a cavity cavity together for injecting plastic 2, each time and any lead frame spacing or package size change requires a new mold for manufacturing, expensive components require a solid mold involving precision machining .

Conventional presses are large, typically weighing up to 200 tons, or 250 tons of stampers and mold bases. Including the cavity fixture, the total cost of such a system is usually $150,000, just for the first package type, and an additional $100,000 for each additional package type. The new generation of molding presses is more expensive, even at twice the price. In addition, as long as the package leadframe and package cavity width or spacing are changed, other equipment such as cutting and forming machines must be modified to add an additional $70,000 or more to accommodate the new package form factor.

Therefore, each cavity is a fixed width for a single specific package and lead frame, such as DPAK and D ² PAK are different. With standard pin pitch, there are only three conductive pins per package that may not require modification of the mold and cavity width. However, since the wafer pads must be connected to the center conductive pins as previously described, these standardized packages can only provide up to three separate electrical connections.

Product utilization is limited to three types of electrical connections that can be broadly classified into three types, namely bipolar elements, three-pole vertical elements, and three-pole transverse elements. Figure 5A shows a simplified cross-sectional view of an example of a bipolar vertical element including an upper metal 23A, a bulk semiconductor material 20 and an overlying epitaxial layer 21, the backside turn-on 22 is situated on a planar surface 18 of a wafer pad (not shown). The bonding pad region defined by one opening of the protective layer 48 is connected to the surface metal layer 23A as the bonding bonding wire 6D. Below the protective layer 48, an oxide or glass layer 25 protects the surface of the component from contamination. In operation, current flows from the surface metal layer 23A vertically through the epitaxial layer 21 and the substrate 20 to the back metal layer 22. The junction is present in the epitaxial layer 21, that is, the structure of the semiconductor element, and the flow of the main current is not important to the understanding and is not shown. While protective devices and voltage clamps are also examples, bipolar components typically include a semiconductor diode and a rectifier.

Figure 5B shows a simplified cross-sectional view of a three-terminal vertical power device including a surface metal layer 23A, a bulk semiconductor material 20 and an epitaxial layer 21, as well as a wafer pad (not shown) on the planar surface 18, as previously described. The back metal 22, as shown, defines an area of the bond pad by an opening in the protective layer 48, wherein the bond wire 6D causes the surface metal layer 23A to be turned on, indicating that the main current of the high current connection element is vertical The surface metal 23 flows to the back metal 22 to be connected.

In the area where the surface metal 23A is removed, the oxide layer 25 protects the surface of the element from contamination. The metal layer 23B sits on a region of the oxide layer 25 that is not covered by the protective layer 48, and includes a second bonding pad that is turned on by bonding the bonding wires 6C. This type of connection is used for the gate or input to the component. Tripolar Examples of vertical power components include power bipolar transistors, vertical power MOSFETs, insulated gate bipolar transistors (IGBTs), and thyristors. The cross-sectional views do not include junctions present in each particular component type structure, except that the flow of the primary current is vertical and the second bond pad is included as a gate input.

Figure 6 shows that the same package can also be used for a three-pole lateral element that is electrically connected to the epitaxial layer 45 and the substrate 44 by bond wires 6B and surface metal 23B and does not constitute a high current path for the element. On the contrary, the main current in the element flows laterally between the bonding pad 23D to which the bonding wire 6D is turned on and the bonding pad 23A to which the bonding wire 6A is turned on. Since the main current flows through only two bonding wires instead of only one bonding wire, as in the case of vertical components, the packaging of the lateral components is inevitably subject to higher parasitic packages, namely wire bonds and resistors. Another difference is that in the case of a transverse element, the main current of the element does not flow vertically, so the connection of the back and back metal of the substrate 44 is not required.

In short, today's high-volume power packages have only seen small advances since the beginning of decades. The factory line of DPAK and D ² PAK packages is too rigid and requires a lot of expense to accommodate multiple package types. The inherent package is limited to a maximum of three electrode terminals, limiting their use to only a few product types. The center conductive pin of the package must be shorted to the wafer pad, further limiting the selectivity to the layout of the semiconductor component. The package is low-area efficacies, requiring large "reserved" areas and long conductive leads that must be bent over the pins without damaging the molded plastic package. Large package sizes and long bond wires create unwanted parasitic resistance and inductance. The inaccuracy of the pin bends makes it difficult to ensure good coplanarity of the pins and the exposed wafer pad bottom and adversely affect PCB assembly yield. All of the above limitations, the possibility of enhancing today's power package design and manufacturing capabilities to accommodate thin or multi-pin packages remains technically and economically problematic.

What is needed for a new generation of power packaging capabilities is the ability to provide thin, low inductance, multi-pin superior coplanarity, flexible, versatile and cost-effective production lines.

The term "power package" as used herein refers to a semiconductor package that is comprised of one or more semiconductor power components and/or one or more power integrated circuits. Power components are semiconductor components with high currents, typically 1A to hundreds of amps. Power components can conduct high currents at low dropouts, including low operating resistance components, with minimal power dissipation. Alternatively, the power component can include components capable of conducting medium to high currents at a large voltage drop, depleting 1 watt to tens of watts of power, and requiring a heat sink to conduct heat away to avoid overheating and damaging the component or its package. Power components can include dipolar transistors; power MOSFETs of various types and configurations; insulated gate bipolar transistors (IGBT); or various types Type and construction of thyristors, including SCR or 矽 controlled rectifiers. The power integrated circuit includes one or more power circuits having gate drivers and generally logic and digital control circuits.

The foot power package of the present invention includes a semiconductor wafer, a wafer pad, a lead and a plastic encapsulant. In many embodiments, the package further includes at least one heat sink for dissipating heat from the packaged wafer to the heat sink of the PCB. To aid in the heat transfer process, the wafer pad can be exposed to the underside of the molding compound. In a vertical profile view, the pin is typically viewed as a Z-shape and includes a vertical column segment, a cantilever portion and a foot. From the cross-sectional view, the cantilever segment protrudes horizontally inward toward the wafer pad at the top of the vertical column segment, and the foot protrudes horizontally outward at the bottom of the vertical column segment. The vertical column section generally forms a right angle and an acute angle with the cantilever section and the foot. The bottom surface of the pin is coplanar with the bottom surface of the molding compound.

In some embodiments, the vertical column segments extend horizontally beyond the sides of the molding gel to form a protruding portion. In other embodiments, the side surface of the molding compound extends outward beyond the vertical column section and covers the upper surface of a portion of the foot. The upper surface of the foot is exposed in whole or in part.

In many embodiments, the heat sink is protruded from the plastic sealant The extension of the wafer pad. The heat sink may have a foot that is similar to the foot of the pin, or the heat sink may have feet on either or both sides. The heat sink can include a hole for bolt mounting. The heat sink can be formed as a series of fingers to increase the length of its peripheral edge relative to its area, thereby improving the wave soldering thermal resistance. In some embodiments, two or three fins extend from either or both sides of the wafer pad.

The unique foot power package of the present invention incorporates a conventional foot package, as shown in Figure 1B, and the characteristics of those leadless packages. Thus, the vertical edges of the vertical column segments form a vertical plane and are either not covered by the molding gel or slightly outside the molding gel. In embodiments where the vertical outer edge of the vertical column section is covered by a molding compound, the foot projects outwardly at the bottom of the side surface of the molding gel. The bottom surface of the foot is at least flat from the side of the adjacent molding gel and the end portion of the foot is flat. These features minimize the horizontal size of the package.

The invention also includes a process for forming a power package. The process includes forming a first mask layer on a first side of the metal sheet, and then partially etching through the metal sheet to form the wafer pad by forming an opening in the first mask layer region, the cantilever segment of the lead and the lead The gap between the foot and the wafer pad is positioned. Alternatively, if the wafer pad is exposed to the bottom of the molding compound, the wafer pad covered by the mask layer is also positioned, and the area is not Will be etched. Local etching does not cut through the entire metal sheet, and the etched area maintains a thin metal layer.

The process further includes forming a second mask layer on the second side of the metal sheet, the second mask layer having first and second openings, the first opening of the second mask layer covering the wafer pad and the The gap between the pins is located in the second opening of the second mask layer covering the pin area of the pin. If a plurality of packages are formed from the metal sheet, the second opening of the second mask layer may also cover an area separating adjacent packages.

The metal sheet is then etched by the first and second openings of the second mask layer. The etch continues until the metal in the interposed gap region between the wafer pad and the leads is completely removed, but only partially removed (and adjacent packages that are divided within the region) in the positioned foot region. The first opening of the first photomask layer and the second opening of the second photomask layer are vertically offset from each other such that portions of the metal sheet remain unaffected during the etching process. This section will form the vertical column segments of the pins.

Alternatively, a metal stamping process can be used in place of the etching process described above. A first metal die is applied to the first side of the metal sheet for squeezing and thinning the metal sheet into a pin cantilever segment and a gap between the wafer pad and the pin (also where the wafer pad is positioned) . A second metal die is applied to the second side of the metal sheet to cut the gap between the wafer pad and the lead on the metal piece and to place the pin for pinching and thinning the pin on the metal piece (also Select the area between adjacent packages).

Whether using an etch or stamp process, the result is typically a leadframe with multiple wafer pads, each wafer pad being connected to multiple pins. If the package is provided with pins on opposite sides of the wafer pad (a "double side" package), the wafer pads are typically held in position in the lead frame by at least one of the tie bars. If the package is provided with pins on all four sides of the wafer pad (a "four-sided" package), the wafer pad typically has at least one side connected to the pins of the interconnect, at least one side of the wafer pad and the etching or stamping process described above. There is no gap between the pins. Either way, the wafer pad remains attached to the leadframe.

The semiconductor wafer is then bonded to the wafer pad and an electrical bond is typically formed between the wafer pad and the leads using bond wire or flip chip technology. Alternatively, the surface of the wafer can be attached to the pins with a solder clip. A portion of the wafer, wafer pad and leads are encapsulated in a plastic mold mixture to be cured to form a plastic encapsulant, the so-called plastic encapsulant leaving at least a portion of the pin uncovered. In some embodiments, the molding compound does not cover the vertical outer surface of the vertical column segment, forming a protrusion at the top of the pin Out.

The leadframe and semiconductor wafer are then divided into individual packages.

A wide variety of foot power packages can be made in accordance with the present invention. Since the pins are coplanar with the bottom of the package and wafer pad, these pins are referred to herein as "foot" and the resulting package is referred to as a "foot package." These include:

The foot power package has a plurality of feet on one side and a heat sink on the opposite side. One or more of the feet can extend directly from the wafer pad. The number of feet in different embodiments differs, for example, three feet, five feet to seven feet.

The foot power package has a plurality of legs on one side and the heat sinks extend from the wafer pads at opposite sides of the wafer.

The foot power package has a plurality of feet on one side and a three side heat sink extending from the remaining side of the package.

The double foot power package has a plurality of legs on both sides and the heat sink extends from opposite sides of the wafer pad to the right angle pins. Some of the feet are electrically and mechanically connected to each other or to the wafer pad.

The foot power package includes two wafer pads, the legs are on opposite sides of the package, and the heat sink extends from the wafer pads on the package to opposite sides of the right angle foot.

● The foot power package has a plurality of legs on three sides and a heat sink on the fourth side. In one embodiment, there are five feet on each of the three sides.

The foot power package has a plurality of pins, at least one of which is connected to the surface of the wafer adhered to the wafer pad by a solder clip.

According to the above object of the present invention, the present invention provides a foot power package comprising: a plastic encapsulant; the first pin portion is wrapped in a plastic encapsulant, the first pin includes a foot, and the foot is in a plastic encapsulant The first side of the bottom protrudes outwardly; the wafer pad is at least partially enclosed in the molding compound; and a first heat sink extends from the wafer pad to a position other than the molding compound.

Preferably, the heat sink comprises a foot.

Preferably, the bottom surface of the foot of the first pin and the bottom surface of the previous heat sink are coplanar.

Preferably, the first pin includes a column segment and a cantilever segment, and an upper surface of the cantilever segment is coplanar with an upper surface of the die pad.

Preferably, a wafer is mounted on the upper surface of the wafer pad, and the wafer is electrically connected to the cantilever segment of the first pin.

Preferably, the wafer is electrically connected to the cantilever section of the first pin by a solder clip.

Preferably, a second pin is extended from the die pad, the second pin portion is enclosed in the molding compound, and the second pin includes a foot, the second pin The foot of the pin protrudes outward on the bottom side of the molding compound.

Preferably, a bottom surface of the wafer is formed in electrical connection with the wafer pad.

Preferably, the method further includes a third pin, the first pin, the second pin and the third pin extending from the first side of the molding compound, the first heat sink from the plastic sealing body The other end extends.

Preferably, the second pin is located between the first pin and the third pin.

Preferably, the first pin extends from the first side of the molding compound, and wherein the first heat sink extends from a second side opposite the first side of the molding compound.

Preferably, the heat sink extends from the second, third and fourth sides of the molding compound.

Preferably, the second heat sink further extends from the second side of the molding compound, and the third heat sink extends from the third side of the molding compound.

Preferably, each of the second and third sides of the molding compound is perpendicular to the first side of the molding compound.

Preferably, the heat sink comprises a bolt mounting hole.

Preferably, wherein the heat sink comprises a series of parallel fingers.

In accordance with the above objects, the present invention provides a method of fabricating a foot power package using a metal sheet, comprising: placing a first mask layer on a first surface of the metal sheet, the first mask layer covering The area is a region where the wafer pad and the heat sink are formed, and a region where the pin of the pin is formed, the area of the first mask layer having a first opening is a region where the pin is formed by a cantilever segment; and etching is performed A metal sheet is in the first opening of the first mask layer.

Preferably, the method further includes: placing a second mask layer on the metal sheet a second opening of the second mask layer is a region of the pin where the foot is formed; and the method includes etching the metal sheet through the first opening of the second mask layer .

Preferably, wherein the area of the second opening of the second mask layer is the area where the foot of the heat sink is formed, the method includes etching the metal sheet through the second opening of the second mask layer .

Preferably, an area extending in the first opening of the first mask layer is a gap region formed between the pin and the wafer pad, and wherein the second opening of the second mask layer The area is the area in which a foot of the heat sink is formed, the method comprising etching the metal sheet through the second opening in the second mask layer.

The invention will be more fully understood by reference to the appended claims appended claims.

1‧‧‧foot package

2‧‧‧Molded plastic

3‧‧‧ lead frame

3A‧‧‧metal wafer pad

3B, 3C, 3D‧‧‧ metal pins

3G‧‧‧ lead frame

3Z‧‧·projection

4B, 4C, 4D‧‧‧ bent parts

5‧‧‧Semiconductor wafer

6A, 6C, 6D‧‧‧ joint wire

8‧‧‧ surface

17‧‧‧Transverse distance/pin space

18‧‧‧ surface

20‧‧‧Main semiconductor materials

21‧‧‧ epitaxial layer

22‧‧‧Back metal

23A‧‧‧Surface metal/joint pad

23B‧‧‧ metal layer

23D‧‧‧Joint pad

25‧‧‧Oxide/glass layer

30‧‧‧Photomask

31‧‧‧Photomask

32‧‧‧ gap

34A, 34D‧‧‧ solder

35‧‧‧ wafer bonding/wafer adhesion layer

37A‧‧‧lower bottom plate

37B‧‧‧Upper cavity

38‧‧‧ lead wire strip

41A, 41B, 41C, 41D‧‧‧ conductor

42‧‧‧through hole

43A, 43B‧‧‧ conductor layer

44‧‧‧Dash/reserved area

45‧‧‧Solder layer/solder paste

47‧‧‧ MOSFET

48‧‧‧Protective layer

49A, 49B‧‧‧Inductance

70‧‧‧foot power package

72‧‧‧Molded plastic

73A‧‧‧ copper wafer pad

73B, 73C, 73D‧‧‧ conductive pins

73E, 73F, 73G‧‧‧ conductive pins

73H‧‧‧ wafer pad

75‧‧‧Semiconductor wafer

76C, 76D‧‧‧ Bonding wire

78‧‧‧ Surface

78C‧‧‧ feet

79A, 79B, 79C, 79D‧‧‧ feet

80X, 80Y‧‧‧ cutting line

81Y‧‧‧Horizontal length

86‧‧‧ Heat sink

87‧‧‧Protruding

88‧‧‧Surface

89‧‧‧etching gap

90‧‧‧ Brazing clamp

91A‧‧‧etched area

91B‧‧‧ Solder or conductive epoxy layer

91Z‧‧‧Photo Mask Features

91Y‧‧‧mask edge

99‧‧‧ Buffer distance

100‧‧‧PCB

101‧‧‧Photomask

101A, 101B‧‧‧ conductive layer

102‧‧‧through hole

103‧‧‧Photomask

104A, 104B, 104C‧‧‧ openings

105‧‧‧Conducting layer

105A‧‧‧etched area

105B‧‧‧Copper

111A, 111H‧‧‧stepped pad extension

115A‧‧‧Metal/Connecting Bar

115C, 115B, 115D‧‧‧ Connecting bars

116A, 116B‧‧‧Connecting bars

120A, 120B‧‧‧ framework

120C, 120D‧‧‧ cross frame

130~139‧‧‧Steps

135‧‧‧ Conductive epoxy/solder layer

In the drawings listed below, generally similar components are given the same reference numerals.

1A is a top view of a typical power package of a prior art DPAK or D ² PAK type structure; FIG. 1B is a cross-sectional view of a prior art DPAK power package along a cutting line passing through and through separate pins; FIG. 1C is a previous Technical DPAK power package is a cut-away line view along and through the connection pins; Figure 1D is a bottom plan view of a prior art DPAK power package; Figure 2A shows a prior art DPAK etched on the back side of a copper lead frame during fabrication Figure 2B shows a cross-sectional view of the same DPAK front side etched; Figure 2C shows a cross-sectional view of the same DPAK wafer after bonding; Figure 2D shows an identical DPAK bonding line FIG. 2E shows a cross-sectional view of the same DPAK after molding; FIG. 2F shows a cross-sectional view of the same DPAK pin after bending; FIG. 3A shows an adhesive prior art DPAK power package. Printed circuit board layout top view; Figure 3B shows a DPAK power package profile attached to a printed circuit board; Figure 3C shows the equivalent of a power MOSFET adhered to a DPAK power package Figure 4A shows a top view of a lead frame of a DPAK power package; Figure 4B shows a cross-sectional view of a die of a DPAK power package; Figure 5A shows a cross-sectional view of a general-purpose bipolar power element; 5B shows a cross-sectional view of a general three-pole vertical power component; FIG. 6 shows a cross-sectional view of a general three-pole lateral power component; FIG. 7A is a top view of a foot power package according to the present invention; A cross-sectional view of a foot power package along a cutting line that is not connected to the wafer pad by the foot; FIG. 7C is a cross-sectional view of a cutting line of the foot power package connected to the wafer pad through the foot; 7D is a top view of the bottom of a foot power package; Figure 7E is a cross-sectional view of the power package of the foot adhered to the PCB; Figure 7F is a perspective view of a foot power package; Figure 7G is another foot power FIG. 8A is a perspective view of a foot power package of an alternative heat sink design according to the present invention. FIG. 8B is a perspective view of another foot power package for replacing the heat sink design. Figure 9A is a cross-sectional view of a copper lead frame of a foot power package, schematically showing portions that are created and removed during the manufacturing process; Figure 9B is a cross-sectional view of the lead frame before back etching; 9C is a cross-sectional view of the lead frame before the front side etching; FIG. 9D is a cross-sectional view of the etched lead frame; FIG. 9E is a cross-sectional view of the lead frame after the die bonding and wire bonding; FIG. 9F is a FIG. 9G is a cross-sectional view of a lead frame of a foot power package instead of a plastic package; FIG. 9H is a manufacturing flow chart of a foot power package according to the present invention; FIG. Figure 10B is a plan view of a lead frame for a single-wafer foot power package according to the present invention; Figure 10B is a plan view of a multi-chip foot power package lead frame having two lead frame frames; Figure 10C is for a single Top view of the multi-chip foot power package lead frame of the lead frame; FIG. 10D is a top view of the multi-chip foot power package lead frame with two lead frame; FIG. 10E is for A top view of the multi-wafer foot power package of the two leadframe frames in place of the version of the lead frame; FIG. 10F is a top view of the multi-wafer foot power package lead frame having two lead frame frames in which the wafer pads are not connected to the pins; Figure 11 is a top view and a cross-sectional view of a lead power package lead frame; Figure 12A is a top view of a foot power package lead frame with an alternative heat sink; Figure 12B is another foot power package lead frame replacement FIG. 13A is a top view of a three-sided heat sink of a foot power package lead frame; FIG. 13B is a top view of a foot power package lead frame having a side heat sink; FIG. 14A is a bilateral foot; The power package lead frame has a top view of the side heat sink; FIG. 14B is a top view of another bilateral foot power package lead frame with a side heat sink; FIG. 14C is a bilateral foot power package lead frame with side heat sink and isolation a top view of the wafer pad; FIG. 14D is a top view of another bilateral foot power package lead frame having a side heat sink; 15A is a top view and a cross-sectional view of a foot power package lead frame having a side heat sink and a dual wafer pad; FIG. 15B is a top view and a cross-sectional view of a foot power package lead frame having a side heat sink and an oversized dual wafer pad Figure 16A is a top view of a 5-pin foot power package lead frame; Figure 16B is a top view of a 7-pin foot power package lead frame; Figure 17 is a 15 pin bottom FIG. 18 is a top view and a cross-sectional view of a foot power package lead frame having a solder clip surface connection; FIG. 19 is a conventional power package and a foot power package according to the present invention; Section comparison chart.

In order to advance today's power packaging technology, some fundamental changes must be made in the manufacturing process, packaging and lead frame design. Hope to improve next-generation power packages, including: ● Ensure that the pins and the exposed wafer pads are coplanar on the back side; ● Solderable, and can be fabricated using wave soldering and reflow soldering PCBs; ● Reasonably low thermal resistance in solderless presets Under the heat sink; ● thin capability; ● reduced inductance, shorter lead and bond wire length; ● good PCB area efficiency, ie large wafer area for a given PCB foot area; Pin output, does not require pins to be connected to the wafer pad; ● flexible number of conductive pins, can be used on one side, two sides or three sides; ● machine that eliminates pin bending (forming); ● minimum of die Costs; using the disclosure of the present invention, such features and advantages are readily available, reorganizing a production line with minimal or no new investment, including production lines for manufacturing high throughput DPAK and D2PAK packages. Disclosed herein as a method for applying integrated circuit packages It is disclosed in U.S. Application Serial No. 14/056,287, which is incorporated herein by reference. Power packages are typically used to package power components or power integrated circuits. Although this power package can be used for non-power applications, the general power package has fewer pins, lower thermal resistance, and higher material cost than IC packages with similar pin counts, so it is usually only used for The power component and the power integrated circuit are packaged.

Power components are semiconductor components that carry large currents typically ranging from 1A to hundreds of amperes. Power components can conduct high currents with low voltage drops, including low operating resistance components, with power dissipation being minimized. Alternative power components include a medium to high current that has a large voltage drop, dissipates 1 watt to tens of watts of power, and requires a heat sink to carry away heat conduction to avoid overheating and damage the component or its package. Power components can include bipolar transistors; power MOSFETs of various types and configurations; insulated gate bipolar transistors (IGBTs); or thyristor transistors of various types and configurations, including SCR or step-controlled rectifiers. The power integrated circuit includes one or more power components having gate drivers and control circuits generally having analog and digital bits.

The foot package design does not rely on the conductor "pin" extending from the center of the semiconductor power package and mechanically bending into an inaccurate position. The present invention includes a "long leg" having a short conductor. The package, or precisely the "foot", is coplanar with the bottom of the heat sink and wafer pad and extends laterally at the bottom of the package to facilitate soldering. FIG. 7A illustrates one embodiment of a foot power package 70 disclosed herein.

The foot power package 70 includes a copper wafer pad 73A coupled to a conductor pin 73B extending beyond the molded plastic 72 as a foot 79B. The two separate conductor pins 73C and 73D inside the package 70 also extend beyond the molded plastic 72 with corresponding feet 79C and 79D. Similarly, but at the opposite edge of the package, a heat sink 86 extends beyond the molded plastic 72 primarily to diffuse heat from the power package to the PCB conductor over a large area. Unlike conventional bent pin power packages, the bottoms of the legs 79C, 79B and 79D and the bottom of the wafer pad 73A and the heat sink 86 along the surface 78 are precisely coplanar in the foot power package because they are A single piece of copper that is manufactured without any bending or mechanical forming steps.

As shown in the side view of FIG. 7B, the top of inner conductive pin 73D coincides with surface 88 plane by a dicing line along and through conductive pin 73D, coplanar with the top of wafer pad 73A. As shown, the semiconductor wafer 75 is adhered to the wafer pad 73A by a solder or conductive epoxy layer 135, a portion of which is joined by a bonding wire 76D comprising gold, aluminum, copper or other conductive metal wires. To the conductive pin 73D. The conductive pin 73D is slightly protruded from the outside of the molded plastic 72 and has a vertical thickness greater than that of the foot 79D. Out of 87. Below the projections 87, the side walls of the conductive pins 73D are likewise exposed, i.e., are not covered or enclosed within the molded plastic 2. The purpose of the lower leg 79D being lower than the wafer pad 73A is to increase solder wetting, i.e., surface tension pulls the molten solder to the copper foot 79D and thereby improves the solderability of the package 70 in the PCB assembly process. The corresponding thickness of the foot 79A of the heat sink 86 similarly improves the solderability of the heat sink 86. Similarly, the advantage of exposing the protrusions 87 to the molded plastic 2 is that the exposed metal on the vertical edges, i.e., the vertical sidewalls of the conductor 73D, increases the surface area available for soldering. However, if desired, the protrusion 87 is not exposed in an alternate embodiment and the vertical sidewalls of the conductor 73D can remain encapsulated within the molded plastic 2 and only the foot 79D protrudes laterally beyond the molded plastic 2.

Moreover, in the illustrated example, the inner end of the inner conductive pin 73D, toward the wafer pad 73A, is not exposed at the bottom surface of the package along the flat surface 78, but instead is vertically upward from the bottom surface of the package by the gap 89. The ground is separated and filled with the same plastic molded mixture of molded plastic 2. The benefit of embedding the plastic in the inner end of the conductive pin 73D instead of the surface 78 is to reduce the risk of electrical shorting between the wafer pad 73A and the pin 73D. The lateral length 81Y of the metal including the foot 79A can be determined by chemical etching, stamping, or cutting at the time of manufacture of the lead frame, or alternatively by cutting, stamping, or laser cutting when cut into a single sheet. The lateral length 80Y of the foot 79D, that is, the length of the foot 79D is cut, stamped, or lasered into a single process It is determined.

Figure 7C shows another cross-sectional view of the foot power package 70 taken along the wafer pad 73A and cut through the conductive pins 73B. As in the case of the conductive pin line 73D and the conductive pin 73C (not shown) previously shown, the surface of the inner conductive pin 73B is planar with the surface 78 and is coplanar and connected to the wafer pad 73A. . The conductive pin 73B slightly protrudes beyond the molded plastic 72 to form a projection 87 having a vertical thickness greater than the foot 79B. The purpose of the foot 79B being less than the wafer pad 73A is to increase solder wetting, i.e., surface tension pulls the molten solder onto the copper foot and thereby improves the solderability of the package 70 in the wave soldering process PCB assembly. As in the case of the conductive pins 73C and 73D, the advantage of the protrusions 87 over the molded plastic 2 is that the exposed metal with exposed metal at the vertical edges, i.e., the vertical sidewalls of the conductor 73B, increases the surface area available for soldering. However, if desired, the protrusion 87 is not exposed in an alternate embodiment and the vertical sidewalls of the conductor 73D can remain encapsulated within the molded plastic 2 and only the foot 79D protrudes laterally beyond the molded plastic 2. As described in connection with Figure 7B, the lateral length 81Y of the metal includes the cutting of the foot 79A by chemical etching, stamping, or lead frame fabrication, or alternatively by cutting, stamping, or laser cutting. Determine when you are in a single order. The lateral length 80Y of the foot 79B, i.e., the length of the foot 79B, is determined by cutting, stamping, or laser cutting into a single period.

Moreover, in the illustrated example, the inner portion of the conductive pin 73D is not exposed at the bottom surface of the package along the flat surface 78, but instead is vertically separated from the bottom surface of the package by the gap 89 and molded. Plastic 2 is filled with the same plastic pressure mixture. The benefit of embedding a conductive pin in plastic without exposing it to the surface of the PCB is to reduce the risk of electrical shorting of the PCB.

The benefit of having a void 89 between pins 73D and 73B is more clearly presented by the disclosed foot power package wafer pad 73A, as shown in the back top view of Figure 7D, wherein the conductive pins 73D, 73B, and The only portion of the 73C that appears on the bottom surface of the package is the corresponding legs 79D, 79B, and 79C that protrude laterally beyond the molded plastic 72. Similarly, a lateral space defined by the width of the molded plastic 72 exposed to the back of the package provides a buffer distance 99 between the legs 79D and 79C, respectively, to avoid electrical exposure of the exposed wafer pad 73A under the foot power package 70. Short circuit, the buffer distance 99 should ideally be as wide as the gap between the metal legs 79C, 79B and 79D. Also shown in the cross-sectional view of Fig. 7D, a cross-sectional view of the entire package is shown, i.e., the dicing plastic 72 completely encapsulates the wafer pad 73A through a dicing line through the side of the package without pins, such that there is no metal sheet or The foot extends through the side of the package.

Although the cross-sectional views shown in the previous FIGS. 7B and 7C respectively show the cut The secant passes through wafer pad 73A to a separate conductive pin 73D, or to a connected conductive pin 73B, it being understood that the cross-sectional view of the conductive pin is similar through any other separate conductive pin or wafer. For example, a cross-sectional view through a separate conductive pin 73C will be similar to FIG. 7B except that foot 79D with conductive pin 79D will be relabeled as foot 79C with conductive pin 79C, and the corresponding bond wire 76D It will be relabeled as the bond wire 76C.

In another embodiment, the upper surfaces of the individual conductive leads 73C and 73D are not coplanar with the upper surface (flat surface 88) of the wafer pad 73A, but instead are positioned at a height above the upper surface of the lead frame 73A.

Referring again to FIG. 7A, semiconductor wafer 75 includes two separate metal regions bonded to wafer pad 73A by a conductive epoxy or solder layer 135. One or more bond wires 76D connect the large area metal regions of the semiconductor wafer 75 to the inner conductor 73D and the foot 79D. In the case of vertical power components, such connections typically include the source of a vertical power MOSFET, the anode being an IGBT, SCR, or thyristor, or the base of a vertical power bipolar transistor. The smaller area metal region of the semiconductor wafer 75 is connected to the inner conductor 73C and the foot 79C by bond wires 76C. In the case of vertical power components, such connections typically include the gate of a vertical power MOSFET or IGBT, or the base of a vertical power bipolar transistor, SCR, or thyristor.

The wafer pad 73A and its associated inner conductor 73B and foot 79B are electrically connected to the back side of the semiconductor wafer 75. Similar to the previous Figure 5B, a typical semiconductor wafer 75 requires a back metal layer to ensure good ohmic turn-on to a semiconductor substrate with low operating resistance. In contrast, the back metal layer is uncommon and undesirable in integrated circuit packages because the substrate wafer does not carry the proper current when used as a vertical power component. In power applications, the wafer pad 73A and its back exposed to the back surface of the flat surface 78 are not intended to simply conduct current and are also thermally conductive.

To improve heat dissipation and reduce thermal resistance of the package, heat sink 86, including foot 79A, is used to increase the total surface area. The greatest thermal conduction on the power package 70 is from the wafer pad 73A and the heat sink 86 to the PCB, and before the power package 70 is adhered to the PCB, solder is required to be manually placed on the PCB. A unique feature of the foot power package 70, the foot 79A can be easily soldered during wave soldering and achieves a good electrical turn-on without the need to solder the bottom surface of the wafer pad 73A to the PCB. As a result, the foot power package 70 can avoid the need for additional soldering operations to apply the solder layer 135 between the package 70 and the wafer pad 73A (see Figure 7B), by using any thermally conductive compound, including a thermally conductive epoxy or thermal paste. Solder layer 135 to achieve low thermal resistance even though the conductivity of the compound is not as good as solder. The low resistance between the semiconductor wafer 75 and the wafer pad 73A is achieved because of the foot of the spacer 86 79A is wave solderable.

As shown, the embodiment shown in Figure 7A is designed to be externally connected, i.e., conductive pins, similar to the DPAK and D ² PAK locations, representing an interchangeable pin-to-pin compatible It replaces today's common surface mount power packages and can easily accommodate existing PCB designs. Although the external placement of the solder pads remains the same, the disclosed components can accommodate a larger wafer over the same PCB area. Alternatively, by eliminating the need to bond wire bonds to save PCB area, a smaller package can be designed to accommodate semiconductor wafers of the same size. Despite the increased PCB area efficiency, the disadvantage of custom packaging is the need for different areas of PCB and solder pads, which are not compatible with the existing PCBs produced by conventional DPAK and D ² PAK packages.

Figure 7E shows the adhesive foot packaged on a PCB, wherein the PCB 100 includes conductive layers 103A and 103B at the bottom, conductive layers 101A and 101B at the surface, and vias 102. As shown, the solder layer 34D is electrically connected to the conductive layer 101A of the PCB by the foot 79D and the conductive pin 73D, and the solder layer 34A is electrically connected to the conductive layer of the PCB by the foot 79A or the heat sink 86 and the wafer pad 73A. 101B. The thermally conductive layer 105 includes a thermally conductive compound or solder that improves the thermal conductivity from the wafer pad 73A and the heat sink 86 to the PCB surface conductive layer 101B, the via 102, and the PCB bottom conductive layer 103B. If the thermal layer 105 is non-conductive, including, for example, an organic thermal compound, and all current from wafer pad 73A must flow through the conductive path represented by solder layer 34A and foot 79A. If the thermally conductive layer 105 includes solder, electrical conduction also occurs directly from the wafer pad 73A into the PCB conductive layer 101B.

As shown, the solder layer 34A is pulled onto the bottom leg 79A to complete the electrical connection between the foot power package and the PCB 100 because of the surface tension. Similarly, the solder layer 34D is pulled onto the bottom leg 79D, even to the conductive lead. The foot 73D is exposed to the vertical side walls. In this way, the wave soldering method used in the foot power package and the conventional foot package is feasible.

A perspective view of the DPAK and D ² PAK compatible foot power package is shown in Figure 7F. The unique function of the foot 79A extending from the heat sink 86 is shown, the bottom of the package including molded plastic 72, wafer pad 73A (not visible), heat sink 86, feet 79A and 79C, and other feet (not shown) All are coplanar with the flat surface 78 and do not rely on any metal bending and mechanical forming. An alternative perspective view, as shown in Figure 7G, illustrates the vertical planes of the feet 79C, 79B, and 79D coplanar and the corresponding exposed pins 73C, 73B, and 73D below the protrusions 87. All feet are precisely coplanar because all of the feet 79A, 79C, 79B and 79D and the wafer pad 73 and the spacers 86 are made from the same copper sheet without any metal bending or mechanical forming.

FIG. 8A shows an alternative heat sink design including a heat sink 86 and a three-sided foot 79A surrounding the heat sink 86 in place of only one side. Figure 8B shows another version of the heat sink that eliminates all bevels. This simple linear design is easier to manufacture in the manufacture of leadframes using stamping tools, and the finer geometry in leadframe fabrication is more suitable for chemical or laser based fabrication.

Foot Package Fabrication The fabrication of the foot package 70 of the present disclosure begins with a solid copper sheet 110, typically 400 microns thick. This thickness can be adjusted to be thicker or thinner depending on the purpose and use of the package. As shown in Figure 9A, through a combination of chemical etching, stamping, cutting, or laser cutting processes, the initial copper sheet will be machined into various portions in a dashed line definition to create a unique foot power package. The indicia defined by the vertical lines 80Y and 81Y illustrate the lateral extension of the fabricated and de-framed packages, i.e., the separately etched individual packages are separated from the adjacent sides of the same lead frame. All subsequent cross-sectional views will be described with respect to the starting diagram. For reference, the bottom of the copper sheet forms the back side of the package and the back side of the copper lead frame is coplanar with the flat surface 78.

In FIG. 9B, a protective coating, i.e., reticle 101, is patterned on the back side of copper sheet 110 with selective openings 102A and 102B to define where copper sheet 110 is etched. While the figure is two dimensional, it will be understood that the opening 102 in the reticle extends to a third dimension not shown in the two dimensional map. Photomask 101 can To include any material, including organic compounds or photoresists, will not be attacked or etched through wet chemical metals such as sulfuric acid, nitric acid, hydrofluoric acid (HF), ammonia, and other corrosive chemicals. The reticle 101 can be uniformly applied and subsequently patterned, or applied in a pattern from the beginning. For example, the application of the organic coating of the reticle 101 can be defined by a screen reticle or printing. Alternatively, the reticle 101 may comprise an organic photoresist, uniformly coated, lightly baked to prevent it from moving, and then optically transmitted to the reticle by exposure of the reticle to the light. After exposure, the photoresist at the locations of openings 102A and 102B is removed with an organic developer leaving only the mask 101 to protect the remaining areas. Region 89 schematically represents the area of copper removed by subsequent etching.

After application and patterning, the patterned mask 101 is then baked to harden the material. The term "hard roast" is sometimes used to define an acid etch that is sufficiently high in baking temperature to cross the carbon bond to become a strong polymer such as a molecule that can withstand extended aging. Compared to soft baking, the organic photoresist retains its photosensitivity, and after hard baking, the sensitivity of the resist is no longer. Although the baking temperature varies depending on the choice of mask chemistry, for example, soft baking can occur at 100 ° C for about 1 to 4 minutes, while hard baking can occur at a higher temperature, such as 130 ° C to 140 ° C. After the photomask layer is hard baked, the copper is then etched in an acid solution, for example using hydrochloric acid including HCL:FeCl ₃ :H ₂ O for mixing in a 4:1:5 ratio, and nitric acid including HNO ₃ :H ₂ O ₂ is mixed in a ratio of 1:20, or ammonia including NH ₃ :H ₂ O ₂ is mixed in a ratio of 4:1.

If copper is pre-plated with a thin layer of tin (Sn) for improved solderability in PCB fabrication, the tin must first be removed using etching. For example, hydrofluoric acid contains HF:HLC in a 1:1 ratio, HF:HNO ₃ with 1:1 mixing, or HF:H ₂ O with 1:1 mixing. A common wet process chemical metal etch can be found in a more detailed list in semiconductor technology textbooks or at http://www.cleanroom.byu.edu/wet_etch.phtml . Tin and copper can be etched on one side or by dipping in an acid bath. In the case of immersion etching, in order to prevent over-etching and the entire thinning of the lead frame, the back side of the metal lead frame must be coated with another protective layer. For the sake of clarity, this backside protective layer is not shown in the figures, but is also well known to those skilled in the art of semiconductor packaging.

In an alternative manufacturing process, wet chemical etching can be replaced by plasma or reactive ion etching, also known as "dry etching", using a non-corrosive gas such as HBr or Cl ₂ /Ar in an RF modulated electric field. Decomposed into reactive components. The radio frequency gas is ionized in the plasma and then the metal copper ions are chemically etched to remove them into a gas. Once the plasma ionization is eliminated, the gas returns to a non-corrosive form. In most cases, dry etching occurs only on one side of the copper, so the other side of the copper sheet does not need to be covered by a protective layer.

As shown, the etched copper sheet 110 is designed to produce an etched region 89 that does not completely penetrate the copper sheet 110 and retains some of the unetched portions of the copper sheet, such as 50% to 90% of the remaining thickness of the copper sheet 110. . For example, a 400 micron thick copper sheet 110 is etched to remove 300 microns, leaving a local thin copper 100 microns thick. This region 89 is etched not only through the opening 102A near the conductive pin but also through the opening 102B that passes through the vertical line 81Y "cutting lane". After etching, the mask 101 is chemically removed or referred to as "ashing" in a special etching machine used to remove organic compounds. The resulting patterned copper sheet 110 is shown in the cross-sectional view of Figure 9C. In the manufacturing view, after backside etching, the etched copper sheet 110 can now be visually identified as a leadframe portion of a semiconductor package fabrication. (Thus, the copper sheet 110 will sometimes be referred to as "lead frame 110"). The leadframe 110 typically includes a plurality of identical units temporarily held by a copper "frame" and a "connecting bar" that hold the actual leadframe copper sheets until the plastic is molded to bond them.

The next step is to use a reticle 103 to mask the back of the previously etched copper leadframe 110, i.e., on the front side. After patterning, the reticle 103 includes openings 104A, 104B and 104C. As shown, the opening 104A defines an etched region 105A that sits above the etched region 89 and is thinned by a prior etch process while the opening 104B is used to etch portions of the leadframe 110 that have not previously been etched. Region 91A, wherein 30% to 80% of the lead frame 110 The copper between them is removed, leaving a thin piece of copper including the etched foot 79D. Above opening 104A, which sits above etched region 89, the region is etched, i.e., region 105 merges with previously etched region 89 to completely remove all of the copper on leadframe 110. The etching is then performed using dry etching or wet chemical etching, which is similar to the previous etching step. The reticle 103 is removed after etching.

Thus, while the specific etching time for backside etching and frontside etching is flexible, one process standard for ensuring proper package fabrication is that the thickness of leadframe 110 may be removed by a combination of backside etching and frontside etching that may exceed the entire copper wafer 110. The starting thickness. For example, if the backside etch (FIG. 9B) removes 60% of the thickness of the copper leadframe 110, the front side etch (FIG. 9C) removes more than 40% of the thickness of the copper leadframe 110. If the backside etch removes 50% of the thickness of the copper leadframe 110, the front side etch removes more than 50% of the thickness of the copper leadframe 110. Since one goal of the package design is to achieve solderability of the package foot, then in the preferred embodiment the foot should not be too thick, i.e., the benefit of front side etching is much greater than back side etching.

For example, if a 100 [mu]m thick foot needs to be front etched by 75% of a 400 [mu]m copper sheet 110, backside etching requires removal of at least 25% copper thickness. If a 150 μm thick foot is required, 71% of the thickness of the copper sheet 110 should be removed by front side etching, and at least 29% of the copper should be removed by backside etching. At least 10% excess as a matter of good manufacturing practices Etching should be performed to ensure that the copper metal in this region is clearly removed completely, such as under the photoresist opening 104A. Therefore, a 100μm thick foot should have a 75% front etch and 35% back etch performed, and the same 150μm foot should have 71% front etch and 39% back etch performed.

The opening 104C includes two regions - within the vertical line 81Y and outside the package "cutting lane" 81Y. In the vertical line 81Y, the lead frame 91B is removed to retain the foot 79A. Outside of the vertical line 81Y, the removed copper portion 105B is completely removed from the package scribe line vertical line 81Y in combination with the previously etched portion 89. In this way, summarized in the table below, four possible regions can be formed in sequence using these two etching processes:

As described above, various combinations of backside etching and frontside etching result in all necessary structures for the fabrication of the foot power package. Any unetched regions create a thickness of leadframe 110 that forms wafer pad 73A, heat sink 86, tabs 87, and vertical conductors that are connected to a corresponding foot, such as a vertical portion of conductive pin 73D that is coupled to foot 79D. The bottom of such a region is electrically connected to the PCB.

The result of only backside etching is a projection with a suspended conductive pin, i.e., an elevated beam, such as 73B, which is formed by etching a plastic stamper under the cavity. This elevated beam area has no exposed conductors at the bottom. Only the front front etch produces a foot for soldering with a conductive surface that is exposed to the PCB. The combination of both the backside and frontside etches completely removes all copper without the exposed conductors on the underside. This combination is useful in packaging the scribe lines and the gaps between the conductive pins and the gap between the individual leads and the wafer pads 73A, such as the gap between the conductive leads 73D and the wafer pads 73D or the gap between the conductive leads 73B and 73D. .

After front side etching, the resulting leadframe is shown in Figure 9D, wherein the leadframe unetched portions can now be identified as wafer pads 73A and spacers 86, which are thinned under the edge-etched regions 91B on the right hand side of the figure. The metal can be identified as the foot 79A, and the metal thinned under the edge etched region 91A on the left-hand side of the figure can be identified as the foot 79D, which is combined with the conductive pin 73D to form a mirror image of the foot package pin. Shape" feature. As shown, the front etched region 105A is combined with the back etched region 89 to completely sever any connections between the individual conductive leads 73D and the wafer pads 73A. Similarly, the package scribe line is beyond the vertical line 81Y and all metal is removed by a combination of a front side etch and a back side etch. In the manufacturing process, the independent conductive pin line 73D is connected to the vertical line 80Y by it. The position of the leadframe frame is fixed (not visible in this two-dimensional section).

It should also be mentioned in Figure 9C that the opening 104A should be excluded from the features of the reticle 103 and the resulting foot conductive pins will not be severed from the wafer pad 73A as shown in Figure 9D, but retain the shape The resulting surface is unchanged from the previous etch step, and thus the resulting pin remains connected to the wafer pad, having a structure including the connected conductive pins 73B as shown in FIG. 7C.

In FIG. 9E, the semiconductor wafer 75 is adhered to the wafer pad 73A by a thermally conductive compound or solder 135, and then wire bonding, and the bonding wire 76D connects a portion of the metal surface of the semiconductor wafer 75 to the independent conductive pin line 73D and the bottom. Foot 79D. In another cross-sectional view (not shown), bond wire 76C connects a portion of the metal surface of semiconductor wafer 75 to separate conductive pins 73C and feet 79C.

Finally, in FIG. 9F, plastic compression molding is performed, typically using a transfer molding technique well known in the art of semiconductor packaging, to form a molded plastic 72 to encapsulate the semiconductor wafer 75, bond wires 76D and others, and to fill the etch regions 89 and 105A. Once the plastic is cured, the feet 79B, 79C and 79D are stamped, cut, or lasered from the lead frame (not shown) along the vertical line 80Y to produce a foot power that is split from the lead frame into a single. Package the finished product Prepare for electrical testing.

As an alternative embodiment, as shown in Fig. 9G, the foot 79A, such as the legs 78C, 79B, and 79D with conductive pins, is also connected to the lead frame by the metal 115A because the back is not performed beyond the vertical line 81Y. Etching. Additional stability during wire bonding is achieved by leaving the foot 79A attached to the leadframe frame. Otherwise, back mechanical support is necessary during wire bonding operations to prevent "warping" such as oscillating effects.

Figure 9H shows a step 130 for the foot power package fabrication sequence beginning with a copper sheet. The copper sheet may be pre-plated with a solderable metal such as tin (Sn) or include pure copper. At step 131 the back side of the copper sheet is masked and partially etched to a final thickness nominally less than 50%, such as 29%. At step 132 the front side of the copper sheet is masked and partially etched to a final thickness nominally greater than 50%, such as 61%. Thereafter, in step 133, the leadframe is finished plated with a solderable metal such as tin. This step can be skipped if the leadframe has been pre-plated. At step 134, wafer bonding is performed using epoxy or solder, followed by wire bonding at step 135, which includes wire bond bonding of the gate input and high current connection of either wire bond or braze bond to the wafer. . Next, in step 136, a plastic molding using a transfer molding is performed, followed by tin plating in an optional step 137. In step 138, the individual packaged wafers are divided into single, that is, separated by leadframes, using cutting, stamping, or laser techniques, followed by Step 139 to do electrical testing.

Leadframe Design The foot power package accommodates a flexible array of leadframe designs. Figure 10A shows a top view of a portion of the leadframe, including exposed wafer tray 73A, heat sink 86, and foot 79A, conductive pins 73C, 73B and 73D as elevated beams in front etched region 89, vertically connecting the projections The lower 87 to the bottom legs 79C, 79B, and 79D are defined by the line 91B as an etched region and extend to the copper frame 120B. The connecting bars 115C, 115B, and 115D connect the legs 79C, 79B, and 79D to the copper frame 120B and are cut into a single process to be cut along the slit line 80Y. Similarly, the foot 79A is defined by the line 91A as an etched area and extends until the copper frame 120A is connected to the copper frame 120A via the connecting bar 115A and is cut along the line 81Y during the division into a single process. The molded plastic 72 can be constructed as a single strip that is cut by the cutting knife along line 80X or by a mold acupoint to define a defined area. Element 90 is repeated multiple times on the same lead frame.

Fig. 10B shows a lead frame showing that two wafer pads 73A are connected to the frame 120A by the foot 79A and the connecting bar 115A and to the frame 120B by the conductive pins 73C, 73B, 73D. The wafer pad 73A is securely held by supporting the wafer pads between the two opposing frames to eliminate vibration like a diving plate when the wire bonds. Cross frames 120C and 120D are added to provide additional mechanical support.

In order to improve the division into a single shape and reduce the cutting wear, the cutting line 81Y is cut by thinning the copper thickness, that is, the same thickness of the foot 79A is defined by the reticle features 91A and 91Z. Similarly, the cutting line 80Y is cut by thinning the copper thickness as defined by the mask edges 91B and 91Y. The vertical cut line 80X, as shown in Fig. 10A, is equally applicable to the design of other lead frames and is excluded from the drawing for clarity of illustration.

The leadframe design is shown in Figure 10C. The lateral extension of wafer pad 73A along line 80Y is determined by etching in the leadframe etch process rather than being split into a single process. However, there is a lack of support at both edges of the wafer pad, and backside support is required during wire bonding. In another embodiment, as shown in FIG. 10D, wafer pad 73A includes heat sinks on three sides, wherein the side heat sinks 73A extend to connecting bars 116A and 116B to frames 120A and 120B. Figure 10E shows another leadframe design that provides mechanical support to each other and is separated along the saw wire 82Y during the split into a single process.

The lead frame design is shown in Fig. 10F, the wafer pad 73A is supported by the frame 120A and the conductive pins 73C, 73B and 73D are supported by the frame rail 120B. Unlike the previously shown embodiment, however, in this embodiment the center pin 73B is not electrically connected to the wafer pad 73A, thereby enabling four different electrical connections in a three-foot package, respectively, via Each conductive pin 73C, Three separate connections, 73B and 73D, and one connection via wafer pad 73A. Cross frames 120C and 120D are added to provide additional mechanical support.

Figure 11 shows a simplified top view and cross-sectional view representing a leadframe design for a foot power package in both front and side views, which is illustrated by the elimination of the leadframe frame and molded plastic 72. Defined by the manufactured mold points rather than the cut. As shown, the metal defined by wafer pad 73A, heat sink 86, foot 79A and portions of conductive pins 73C, 73B and 73D are exposed to the bottom surface of the package except that the diagonal portion indicates that the conductor is located in etched region 89. Filled with plastic. A portion of the conductive pin 73D is wider than the foot 79D as shown. This wider T-shaped portion includes connections to the power component for higher currents as an additional bond wire.

Figure 12A represents a variant package surrounded by three-sided feet 79A of the heat sink 86 and including bolt mounting holes. Figure 12B shows a design of another heat sink 86 in which the peripheral edge increases the area of the heat sink relative to the heat dissipated by forming the heat sink 86 as a series of parallel fingers, one longer side contributing to the foot 79A Improve the thermal resistance of wave soldering.

Figure 13A shows a variation of the foot power package with the heat sink 86 and the three sides of the package surrounded by the foot 79. Figure 13B shows another foot package variant in which the heat sink 86 and foot 79A are only present in the package. side.

Figure 14A shows that the design and technique of the foot package can also accommodate a package comprising a single wafer pad 73A and its heat sink 86, with feet 79A on opposite sides thereof, and feet 79B to 79G in their other The two sides of the side create a six-foot package with five electrical connections. In this version, conductive pins 73B and 73E are all in close contact with wafer pad 73A, providing additional rigidity and mechanical support during packaging. In one variation of this package, as shown in Figure 14B, the conductive pin line 73E is broken by the wafer pad 73A such that the power package becomes a six-foot package with six different electrical connections. Figure 14C shows the same package except that the exposed back side of the wafer pad 73A is removed and the wafer is instead bonded to the unexposed portion of the modified insulated conductive wafer pad 73A, and the etched region 86 under the wafer pad is filled with plastic. However, the sides do include the heat sink 86 and the foot 79A to achieve reasonable power dissipation. Another variation is shown in Figure 14D. The individual conductive pin lines 73C and 73D are shorted together to increase the available space for wire bond bonding, and in a similar manner the individual conductive pins 73F and 73G are also shorted together. .

Figure 15A illustrates how a multi-pin foot power package can be used to support two separate wafer pads 73A and 73H. The individual conductive leads 73C and 73D provide a method for bonding a three-pole element to the wafer pad 73A while the wafer pad connection conductive pin 73B provides a wafer pad 73A during the package process. External mechanical support. Similarly, the second wafer pad 73H provides a separate bond for the individual conductive pins 73G and 73F for bonding a three-pole device to the wafer pad 73H while the wafer pad is connected to the conductive pin 73E during the package process. The 73H provides additional mechanical support. However, since both wafer pad 73A and wafer pad 73H are exposed to the bottom of the package, there is a risk that some of the spacing from one wafer pad to another may be too small resulting in a short on the PCB.

A method for increasing the area of the exposed wafer pad to another without reducing the maximum size of the wafer can be achieved on the wafer pad using the design shown in Figure 15B. A portion of the wafer pad 73A is formed in a stepped shape to the pad extensions 111A and 111H. In this manner the same wafer size can be achieved in the previously shown dual wafer pad foot package, but the exposed wafer spacing can be increased as needed to support any PCB design rule. In all of the described packages, the sides of any unused package can be modified to include a heat sink and a corresponding foot for improved heat transfer to the PCB.

Figure 16A shows that the foot power package can be extended to support five electrical connections on one side of the package, and can be made into a pin-to-pin layout and a 5-pin DPAK if required. . Similarly, Figure 16B shows that the foot power package can be extended to support seven electrical connections on one side of the package, and can be made into a pin-to-pin layout and if desired. The pins are DPAK compatible.

Figure 17 shows a power system in which the foot power package can be adapted to a power integrated circuit or a single wafer pad 73A having heat sink 86 and foot 79A can support a multi-pin power integrated circuit. In the illustrated design, a fifteen-pin power package is shown to include separate conductive pins 73C through 73P and corresponding legs 79C through 79P and the wafer pads are coupled to conductive pins 73B and associated legs 79B.

Figure 18 shows both a top view and a side view of a solder clip used in a foot power package. As shown, a semiconductor wafer 75 is adhered to the exposed wafer pad 73A using a conductive epoxy or solder layer 135. The brazing clip 90 is then adhered to the surface of the semiconductor wafer 75 using a solder or conductive epoxy layer 91B, and the brazing clip 90 is adhered to the conductive pins 73D using a solder or conductive epoxy layer 91A. For power components having three or more electrical connections, the braze clip 90 does not cover the entire semiconductor wafer 75 to allow the bond wires to be driven and signaled with low current gates. For example, as shown, the braze clip 90 does not cover the gate connection pads of the semiconductor wafer 75 to allow the bond wires 76C to connect the gate pads to the conductive pins 73C. The side view shown does not show the presence of bond wire 76C because it takes a cross-sectional cut line along the length of the package through foot 79D and through conductive pin 73D.

Comparison of conventional packages: A comparison of the foot package of the present invention with a conventional surface mount power package, such as the DPAK foot power package, is shown in Figure 19, where the lateral distances y1 through y0 are considered identical for the two packages. As shown in the figure, the lateral dimensions y1 to y5 on the conventional package are quite large, because of the inherently poor manufacturing tolerances, it must be bent by the pin extension 17 clamp pin, the continuous pin bend 4D is The wasted space. The result is a significant improvement in area efficiency of the present invention, particularly in smaller packages where the extra space for additional fixation is more pronounced.

A similar improvement over conventional power packages is evident in the vertical height (X' ₂ -X' _O ) of the foot package. Since the pin bending is not involved, the package height of the foot package is limited by the desired leadframe thickness and the height of the molded plastic 2 required to package the bond wires. One way to solve this problem is to use a brazing clip 90 instead of a wire when the bond wire must be loaded with a high current. Brazing clips 90 are adhered to the metal surface of semiconductor wafer 75 and to conductive pins 73D using solder or conductive epoxy 91B and 91A as shown. Since it is not necessary to accommodate a large diameter wire with a large wire arc height, the thickness of the molded plastic 72 can be greatly reduced. Input signals like gate bias can be connected with a small diameter bond wire 76C without affecting the height of the thin package.

In addition, since the thickness of the foot is determined by etching and the foot and The bottom of the package is precisely coplanar, and there is no need to compensate for increased package height, such as pin bending, with inaccurate mechanical processes. As a result, the foot power package can be manufactured at a package height that is more competitive than the QFN and thin gull-wing IC package.

In summary, the foot power package as disclosed herein ensures that the bottom of the lead and the exposed back of the wafer pad will be coplanar because they are formed from a piece of copper without bending or mechanical forming. The thin foot supports both wave soldering and reflow soldering techniques for PCB assembly. Because the foot is combined with its heat sink to provide a wide range of soldering the package provides low thermal resistance even without solder being placed under the heat sink. Without the need for long bond wires and long lead bends, the foot package exhibits reduced inductance and increased PCB area efficiency, providing a larger die area for a given PCB area than conventional power packages. In addition, the foot power package can provide any number of pin or pin pitches and is distributed over one, two or three sides of the package without the need to bond pins to the wafer pads. By completely removing the need for bent pins, the mechanical cost of the bend bend and subsequent yield loss can be completely eliminated. Finally, with careful design, the flexibility of the foot package supports a wide range of package options for a limited number of molds and custom mold related costs.

According to an embodiment of the present invention, the present invention provides a foot power package comprising: a plastic encapsulant; the first pin portion is wrapped in a plastic In the encapsulant, the first pin includes a foot protruding outwardly from a first side of the bottom of the molding compound; the wafer pad is at least partially wrapped in the molding compound; and a first heat sink is from the wafer The pad extends to a location other than the molding compound.

According to an embodiment of the present invention, there is provided a method of fabricating a foot power package from a metal sheet, comprising: placing a first mask layer on a first surface of the metal sheet, the first mask layer The area covered is the area where the wafer pad and the heat sink are formed, and the area where the foot of the pin is formed. The area of the first mask layer having a first opening is the area formed by the cantilever section of the pin; and etching Passing the metal sheet to the first opening of the first mask layer.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

70‧‧‧foot power package

72‧‧‧Molded plastic

73A‧‧‧ wafer pad

73B, 73C, 73D‧‧‧ pins

75‧‧‧ wafer

76C, 76D‧‧‧ Bonding wire

78‧‧‧cut face

79B, 79C, 79D‧‧‧ feet

86‧‧‧ Heat sink

87‧‧‧Protruding

89‧‧‧etching gap

Claims (20)

A foot power package includes: a plastic encapsulant; the first pin portion is wrapped in a plastic encapsulant, the first pin includes a foot, and the foot protrudes outward on a first side of the bottom of the molding compound; The wafer pad is at least partially wrapped in the molding compound; and a first heat sink extends from the wafer pad to a position other than the molding compound. The foot power package of claim 1, wherein the first heat dissipation pad comprises a foot. The foot power package of claim 2, wherein a bottom surface of the foot of the first pin and a bottom surface of the previous heat dissipation pad are coplanar. The foot power package of claim 3, wherein the first pin comprises a column section and a cantilever section, and an upper surface of the cantilever section is coplanar with an upper surface of the wafer pad. The foot power package of claim 4, further comprising: a wafer mounted on the upper surface of the wafer pad, the chip being electrically connected to the first The cantilever segment of a pin. The foot power package of claim 5, wherein the wafer is electrically connected to the cantilever section of the first pin by a solder clip. The foot power package of claim 5, further comprising: a second pin extending from the die pad, the second pin portion being wrapped in the plastic seal body, The second pin includes a foot, and the foot of the second pin protrudes outward on a bottom side of the molding compound. The foot power package of claim 7, wherein a bottom surface of the wafer is formed in electrical connection with the wafer pad. The foot power package of claim 8, further comprising: a third pin, the first pin, the second pin and the third pin from the first side of the molding compound Extendingly, the first heat dissipation pad extends from the other end of the molding compound. The foot power package of claim 9, wherein the second pin is located between the first pin and the third pin. The foot power package of claim 1, wherein the first pin Extending from the first side of the molding compound, and wherein the first heat dissipating pad extends from a second side opposite the first side of the molding compound. The foot power package of claim 11, wherein the heat dissipation pad extends from the second, third and fourth sides of the molding compound. The foot power package of claim 1, further comprising: a second heat dissipation pad extending from a second side of the plastic sealant, the third heat dissipation pad being from the plastic sealant Three sides extend. The foot power package of claim 13, wherein each of the second and third sides of the molding compound is perpendicular to the first side of the molding compound. The foot power package of claim 1, wherein the heat dissipation pad comprises a bolt mounting hole. The foot power package of claim 1, wherein the heat sink pad comprises a series of parallel fingers. A method for manufacturing a foot power package using a metal sheet, comprising: placing a first mask layer on a first surface of the metal sheet, the area covered by the first mask layer is formed by a wafer pad and a heat dissipation pad Area and the bottom of the pin An area in which the foot is formed, an area of the first mask layer having a first opening is an area formed by the pin-a cantilever section; and the first opening of the first mask layer is etched through the metal sheet. The method of claim 17, further comprising: placing a second mask layer on the second surface of the metal sheet, the first opening of the second mask layer being the foot of the pin a region to be formed; and the method includes etching the metal sheet through the first opening in the second mask layer. The method of claim 18, wherein an area of the second opening of the second mask layer is an area where the foot of the heat dissipation pad is formed, the method comprising etching the metal sheet through the second The second opening of the mask layer. The method of claim 19, wherein an area extending in the first opening of the first mask layer is a gap region formed between the lead and the wafer pad, and wherein the second The area of the second opening of the mask layer is the area where a foot of the heat sink pad is formed, the method comprising etching the metal sheet through the second opening of the second mask layer.