TW201640586A - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TW201640586A
TW201640586A TW104139091A TW104139091A TW201640586A TW 201640586 A TW201640586 A TW 201640586A TW 104139091 A TW104139091 A TW 104139091A TW 104139091 A TW104139091 A TW 104139091A TW 201640586 A TW201640586 A TW 201640586A
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楊玉麟
何嘉政
葉致鍇
彭成毅
李宗霖
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台灣積體電路製造股份有限公司
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Abstract

半導體裝置的形成方法包括形成鰭狀結構於基板上，以及形成第一閘極結構於鰭狀結構的第一部份上。第一氮化物層形成於鰭狀部份的第二部份上。以紫外線曝光第一氮化物層。源極區與汲極區形成於鰭狀結構之第二部份。

Description

半導體裝置與其形成方法
本揭露關於半導體裝置，更特別關於FinFET裝置與其形成方法。
當半導體產業朝向奈米技術的製程節點邁進，以達更高的裝置密度、更高的效能、與更低的成本時，在三維設計如鰭狀場效電晶體(FinFET)面臨製程與設計的問題。FinFET通常包含高高寬比的半導體鰭狀物，且半導體電晶體裝置之通道與源極/汲極區形成其中。閘極係沿著鰭狀結構之側壁延伸至鰭狀結構上(比如包覆鰭狀結構)，可增加通道與源極/汲極區之表面積以製作更快、更可信、與更易控制的半導體電晶體裝置。在某些裝置中，FinFET之源極/汲極(S/D)部份中可採用應力材料如矽鍺(SiGE)、磷化矽(SiP)、或碳化矽(SiC)以增加載子移動率。
本揭露一實施例提供之半導體裝置的形成方法，包括：形成鰭狀結構於基板上；形成第一閘極結構於鰭狀結構的第一部份上；形成第一氮化物層於鰭狀結構的第二部份上；以紫外線曝光第一氮化物層；以及形成源極區與汲極區於鰭狀結構的第二部份。
本揭露一實施例提供之半導體裝置的形成方法，包括：形成第一鰭狀結構與第二鰭狀結構於基板上；形成第一閘極結構於第一鰭狀結構之第一部份上，以及形成第二閘極結構於第二鰭狀結構之第一部份上；形成一壓縮應力膜於第一鰭狀結構之第二部份上；以紫外線曝光壓縮應力膜；形成源極區與汲極區於第一鰭狀結構之第二部份；形成拉伸應力膜於第二鰭狀結構之第二部份上；以及形成源極區與汲極區於第二鰭狀結構之第二部份。
本揭露一實施例提供之半導體裝置，包括：第一鰭狀結構與一第二鰭狀結構；第一閘極結構位於第一鰭狀結構之第一部份上，而第二閘極結構位於第二鰭狀結構之第一部份上；壓縮應力膜位於第一鰭狀結構之第二部份上，以及拉伸應力膜位於第二鰭狀結構之第二部份上；以及源極區與汲極區位於第一鰭狀結構之第二部份與第二鰭狀結構之第二部份。
a-a、A-A‧‧‧剖線
S101、S102、S103、S104、S105、S201、S202、S203、S204、S205、S206、S207‧‧‧步驟
10‧‧‧半導體基板
12‧‧‧鰭狀物
14‧‧‧STI區
16‧‧‧閘極結構
18‧‧‧閘極
20‧‧‧閘極介電物
22‧‧‧側壁間隔物
24‧‧‧第一部份
26‧‧‧第二部份
28‧‧‧氮化物層
32‧‧‧氮化物殘餘物
34‧‧‧源極/汲極區
36‧‧‧合併之源極/汲極區
40、42、50‧‧‧FinFET半導體裝置
44‧‧‧PMOS區
46‧‧‧NMOS區
48‧‧‧蓋層
52‧‧‧壓縮應力膜
54‧‧‧壓縮應力膜之殘餘物
56‧‧‧虛置層
58‧‧‧接點層
60‧‧‧拉伸應力膜
62‧‧‧拉伸應力膜之殘餘物
第1圖係本揭露一實施例中，具有鰭狀結構之半導體FET裝置(FinFET)之形成方法的流程圖。
第2-6、7A-7B、8圖係本揭露一實施例中，半導體FinFET裝置之形成製程的圖式。
第9圖係本揭露另一實施例中，半導體FinFET裝置的圖式。
第10圖係本揭露另一實施例中，具有鰭狀結構之半導體FET裝置之形成方法的流程圖。
第11A至11H圖、第12A至12F圖、與第13A至13H圖係本揭 露另一實施例中，半導體FinFET裝置之形成製程的圖式。
第14圖係本揭露一實施例中，後處理時間對氫減少/應力增加的效應圖。
第15圖係本揭露一實施例中，層狀物厚度對膜應力之效應圖。
第16圖係本揭露一實施例中，硬化溫度對應力之效應圖。
下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，單元尺寸並不限於揭露的範圍或數值，而可依製程條件及/或裝置所需的性質而定。此外，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。為了簡化與清楚說明，可依不同比例任意繪示多種結構。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。此外，用語「之組成為」指的是「包括」或者「由...組成」。
利用本揭露之一或多個實施例之裝置，係半導體裝置。舉例來說，此裝置為FinFET裝置。舉例來說，FinFET裝置可為互補式金氧半(CMOS)裝置，其包含p型金氧半(PMOS) FinFET裝置與n型金氧半(NMOS)FinFET裝置。下述內容包含FinFET以說明本揭露的多種實施例。然而應理解的是除非特別記載於申請專利範圍中，否則本揭露並不限於特定種類的裝置。
本揭露一實施例中，具有鰭狀結構之半導體FET裝置(FinFET)的形成方法如第1圖所示。上述方法之步驟S101形成鰭狀結構於基板上，而步驟S120形成閘極結構於鰭狀結構上。步驟S103形成氮化物層，而步驟S104接著以紫外線曝光氮化物層。步驟S105接著形成源極/汲極區。
在本揭露一實施例中，半導體裝置的形成方法包括形成鰭狀結構(包含一或多個鰭狀物12)於半導體基板10上，如第2圖所示。在一實施例中，半導體基板10為矽基板。在其他實施例中，半導體基板10可包含鍺、矽鍺、砷化鎵、或其他適當的半導體材料。在又一實施例中，半導體基板可包含磊晶層。舉例來說，半導體基板可具有磊晶層位於基體半導體上。此外，半導體基板可具有應力以增加效能。舉例來說，磊晶層之半導體材料可不同於基體半導體，比如矽鍺層位於基體矽上，或矽層位於基體矽鍺上。上述應力基板之形成方法可為選擇性磊晶成長(SEG)。此外，半導體基板可包含絕緣層上半導體(SOI)結構。在又一實施例中，半導體基板可包含埋置介電層如埋置氧化物(BOX)層，或者由佈植氧隔離(SIMOX)技術、晶圓接合、SEG、或其他適當方法所形成者。在其他實施例中，基板可包含IV-IV族半導體化合物如碳化矽或矽鍺、III-V族半導體化合物如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、 AlGaN、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP、或上述之組合。
鰭狀物12位於半導體基板10上，其材料可與半導體基板10相同，並可自半導體基板10連續地延伸。鰭狀物12之形成方法可為選擇性蝕刻半導體基板10。在其他實施例中，鰭狀物12之形成方法可為先磊晶法。在先磊晶法中，形成磊晶層於半導體基板10上，再圖案化磊晶層以形成鰭狀物12。
光微影製程可用以定義鰭狀物12於半導體基板10上。在某些實施例中，形成硬遮罩層於半導體基板10上。硬遮罩層可包含氮化矽與氧化矽之雙層結構。以旋轉塗佈法將光阻層塗佈於半導體基板上。光阻的圖案化方法可為選擇性曝光光阻至光化學射線。一般而言，圖案化步驟可包含塗佈光阻(如旋轉塗佈)、軟烘烤、對準光罩、曝光、曝光後烘烤、顯影光阻、沖洗、乾燥(如硬烘烤)、其他合適製程、或上述之組合。在其他實施例中，光微影曝光製程可置換為其他合適方法如無光罩光微影、電子束直寫、直寫、離子束直寫、及/或奈米壓印。
接著蝕刻硬遮罩層露出的部份，以將光阻層圖案轉移至硬遮罩圖案。硬遮罩層之後可作為蝕刻半導體基板時的遮罩。蝕刻半導體基板的多種方法包含乾蝕刻、濕蝕刻、或乾蝕刻與濕蝕刻之組合。乾蝕刻製程可採用含氟氣體(如CF4、SF6、CH2F2、CHF3、及/或C4F8)、含氯氣體(如Cl2、CHCl3、CCl4、及/或BCl3)、含溴氣體(如HBr及/或CHBr3)、含氧氣體、含碘氣體、其他合適氣體及/或電漿、或上述之組合。蝕刻製程可包 含多重蝕刻步驟以達蝕刻選擇性、製程彈性、與所需的蝕刻形狀。
在此實施例中，半導體裝置包含絕緣材料沿著鰭狀物12之較下部份形成於半導體基板10上。在多個鰭狀物的實施例中，當形成STI(淺溝槽隔離)區14於多個鰭狀物12之間時可沉積絕緣材料。STI區14可包含氧化矽、氮化矽、氮氧化矽、其他合適材料、或上述之組合。STI區14之形成方法可為任何合適製程。在一實施例中，STI區14之形成方法係以化學氣相沉積(CVD)將一或多種介電材料填入鰭狀物之間的區域。在某些實施例中，被填入介電材料的區域可具有多層結構，比如熱氧化襯墊層上填有氮化矽或氧化矽。在形成STI區後，可進行回火製程。回火製程包含快速熱回火(RTA)、雷射回火製程、或其他合適的回火製程。
在某些實施例中，STI區14的形成方法為可流動CVD。在可流動CVD中，沉積可流動的介電材料而非氧化矽。可流動的介電材料如其名，在沉積中可流動以填入高深寬比的間隙或空間。一般而言，多種化學品可添加至含矽前驅物使沉積的膜狀物流動。在某些實施例中，可新增氮氫化物的鍵結。舉例來說，可流動介電前驅物(特別是可流動氧化矽前驅物)包含矽酸鹽、矽氧烷、甲基倍半矽氧烷(MSQ)、氫倍半矽氧烷(HSQ)、MSQ/HSQ、全氫矽氮烷(TCPS)、全氫聚矽氮烷(PSZ)、四乙氧基矽烷(TEOS)、或矽烷基胺如三矽烷基胺(TSA)。這些可流動氧化矽材料之形成方法可為多重步驟製程。在沉積可流動膜後，硬化並回火可流動膜以去除不需要的元素以形成氧化 矽。當移除不需要的元素時，可流動膜會緻密化並收縮。在某些實施例中，將進行多重回火製程，即多次硬化與回火可流動膜，比如在1000℃至1200℃之間回火總計30小時或更久。
化學機械拋光(CMP)步驟可自STI區移除多餘材料，以提供實質上平坦的表面。接著將掺質佈植至鰭狀物以形成n型井與p型井，再回火半導體裝置。接著回蝕刻STI區以移除部份STI區，並露出鰭狀物的較上部份作為後續形成之閘極結構與源極/汲極區所在處。閘極的形成方法可包括額外沉積、圖案化、與蝕刻製程。STI區的移除方法可為合適的蝕刻製程如半等向性蝕刻(如HF+NH3而不使用電漿，或HF+NH3搭配電漿)或等向性蝕刻(如稀HF)。
在此實施例中，閘極結構16係形成於鰭狀結構的第一部份24上，如第3圖所示。閘極結構的形成製程可包含沉積閘極介電物20、沉積閘極18、圖案化閘極、佈植輕掺雜汲極(LDD)、與回火。接著形成側壁間隔物22於閘極結構16上，佈植源極/汲極，與進行回火。第4圖係沿著第3圖之剖線a-a的剖視圖，顯示鰭狀物12與閘極結構16之排列方式。
閘極介電物20可包含氧化矽、氮化矽、氮氧化矽、高介電常數之介電材料、其他合適介電材料、及/或上述之組合。此實施例之閘極18組成為多晶矽，且可包含硬遮罩形成於閘極上。硬遮罩之組成可為合適的硬遮罩材料如SiO2、SiN、或SiCN。閘極結構可包含額外層如界面層、蓋層、擴散阻障層、介電層、導電層、其他合適層、或上述之組合。除了多晶矽以外，閘極18可包含任何其他合適材料如鋁、銅、鈦、鉭、鎢、 鉬、氮化鉭、鎳矽化物、鈷矽化物、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他合適材料、或上述之組合。
在此實施例中，FinFET之製作方法可為閘極優先方法或閘極後製方法。在採用高介電常數介電物與金屬閘極(HK/MG)時，將採用閘極後製方法形成閘極，即先形成虛置閘極，接著在高溫回火步驟後移除虛置閘極，之後再形成高介電常數介電物與金屬閘極(HK/MG)。
在本揭露實施例中，高介電常數之閘極介電物20可包含HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適的高介電常數介電材料、或上述之組合。金屬閘極材料可包含一或多層的Ti、TiN、鈦鋁合金、Al、AlN、Ta、TaN、TaC、TaCN、TaSi、或類似物。
在某些實施例中，採用側壁間隔物22以偏離後續形成之掺雜區如源極/汲極區。側壁間隔物22亦可用以設計或調整源極/汲極區(接面)的形狀。側壁間隔物22之形成方法可為合適的沉積與蝕刻製程，且可包含氮化矽、碳化矽、氮氧化矽、其他合適材料、或上述之組合。
如第5圖所示，沉積氮化物層28於鰭狀物12露出的第二部份26(見第3圖)上，即閘極結構16與側壁間隔物22未形成處。氮化物層28可為氮化矽層。用以沉積氮化物層28的方法可為沉積氮化矽層的任何合適技術如CVD。在此實施例中，氮化物層可為氮化矽、氮氧化矽、掺雜碳的氮化矽、掺雜碳的氮 氧化矽、氮化硼、或氮化硼碳。
接著以紫外線30曝光氮化物層28一段時間(介於約1秒至約2小時之間)，如第6圖所示。紫外線30的曝光時間取決於氮化物層的厚度。在某些實施例中，紫外線30曝光氮化物層28的時間介於約30秒至約1小時之間。在其他實施例中，紫外線30曝光氮化物層28的時間介於約2分鐘至約15分鐘之間。
曝光氮化物層28之紫外線30其波長小於約400nm。在某些實施例中，紫外線30之波長小於200nm。
在此實施例中，以紫外線曝光氮化物層時加熱裝置。加熱裝置的溫度可介於約200℃至約600℃之間。在此實施例中，在紫外線曝光時加熱裝置的溫度介於約300℃至約500℃之間。在其他實施例中，在紫外線曝光時加熱裝置的溫度介於約380℃至約480℃之間。
接著蝕刻氮化物層28覆蓋的鰭狀物之第二部份26，以移除STI區14上的部份鰭狀物，如第7A圖所示。合適的光微影與蝕刻技術可用以移除鰭狀物的第二部份26。在蝕刻步驟後，氮化物殘餘物32保留於STI區14上。保留於STI區14上的氮化物殘餘物32與蝕刻後的鰭狀物12，如第7B圖所示。
在此實施例中，接著形成隆起的源極/汲極區34於鰭狀物12的蝕刻部份上，以提供第8圖所示之FinFET半導體裝置40。隆起的源極/汲極區之形成方法可為一或多道磊晶製程，比如形成結晶態的Si結構、SiC結構、SiGe結構、SiP結構、SiCP結構、磊晶矽上的III-V族半導體材料、或其他合適結構於鰭狀物上。磊晶製程包含CVD沉積技術(如氣相磊晶(VPE)及/ 或超高真空CVD(UHV-CVD))、分子束磊晶、及/或其他合適製程。
在本揭露某些實施例中，形成源極/汲極以接觸個別的源極/汲極區。源極與汲極可為合適的導電材料如銅、鎢、鎳、鈦、或類似物。在某些實施例中，形成金屬矽化物於導電材料及源極(與汲極)之間的介面，以改善界面導電性。在一例中，採用鑲嵌及/或雙鑲嵌製程以形成銅為主的多層內連線結構。在另一實施例中，採用鎢形成鎢插塞。
在本揭露實施例中，亦可進行後續製程以形成多種接點/通孔/線路與多層內連線結構(金屬層與層間介電層)於半導體基板上，以連接FinFET裝置的多種結構。舉例來說，多層內連線包含垂直內連線如習知的通孔或接點，以及水平內連線如金屬線路。
在此實施例中，源極/汲極區的磊晶成長製程持續至個別的源極/汲極區合併在一起，以形成具有合併之源極/汲極區36的FinFET半導體裝置42。
第10圖係本揭露一實施例中，形成具有Fin結構之半導體FET裝置的另一方法。此方法之步驟S201形成第一與第二鰭狀物結構，而步驟S202形成第一與第二閘極結構。步驟S203形成壓縮應力膜於半導體裝置上，而S204接著以紫外線曝光壓縮應力膜。步驟S205形成源極/汲極區於第一鰭狀結構上。步驟S206接著形成拉伸應力膜於半導體裝置上。步驟S207接著形成源極/汲極區於第二鰭狀結構上。
在本揭露某些實施例中，FinFET半導體裝置50包 含PMOS區與NMOS區。如第11A圖所示，PMOS區44與NMOS區46形成於半導體基板10上。PMOS區44與NMOS區46之間隔有STI區14。第11A圖係沿著PMOS與NMOS之閘極結構的x方向之剖視圖。如第11A與11D圖所示，閘極18位於鰭狀物的第一部份24上。在某些實施例中，蓋層48位於閘極18上。蓋層48之組成可為氮化矽。第11B與11C圖係分別沿著PMOS與NMOS之y方向，鰭狀物12的剖視圖。第11B與11C圖對應鰭狀物的第二部份26。
在第11D圖中，壓縮應力膜52形成於半導體裝置50上。在某些實施例中，壓縮應力膜52為氮化物層。在此實施例中，氮化物層52為氮化矽、氮氧化矽、掺雜碳的氮化矽、掺雜碳之氮氧化矽、氮化硼、或氮化硼碳。如第11E與11F圖所示，壓縮應力膜52分別形成於PMOS與NMOS中的鰭狀物12上。壓縮應力膜52可提供拉伸應力於NMOS之通道區中。
如第11G圖所示，自NMOS區46之半導體裝置50移除部份壓縮應力膜52。在此實施例中，移除壓縮應力膜52的方法為蝕刻。在此實施例中，接著蝕刻NMOS區46中鰭狀物之第二部份26，留下壓縮應力膜之殘餘物54與凹陷的鰭狀物12，如第11H圖所示。
源極/汲極區34形成於NMOS區46中移除壓縮應力膜處，而接點層58形成於源極/汲極區34上，如第12A圖所示。第12A圖係沿著PMOS與NMOS其閘極結構的x方向之剖視圖。在此實施例中，源極/汲極區34之組成為SiP。在此實施例中，接點層58之組成為導電材料如矽化物。壓縮應力膜之殘餘物54 可作為應力膜以施加應力於源極/汲極區34上。壓縮應力膜52位於PMOS區中的鰭狀物12上，以及位於NMOS區中的源極/汲極區34上，如第12B與12C圖所示。第12C圖係第12A圖中剖線A-A的剖視圖。
在某些實施例中，壓縮應力膜可為多層沉積物(MLD)如氮化物層(SixNy或SixNy：H)。每一層的厚度可介於約20Å至100Å之間。在氮化物層之沉積總厚度達到300Å至1000Å時，可進行電漿處理以破壞Si-N與N-H鍵以形成壓縮應力膜，其壓縮應力介於約-1至約-2GPa之間。
壓縮應力膜52之形成方法亦可為紫外線輔助的熱處理製程(UVTP)，即以紫外線曝光氮化物層。在UVTP中，先以PECVD或LPCVD沉積約300Å至1000Å的氮化物層，接著以紫外線(波長小於400nm)曝光氮化物層1秒至約2小時。紫外線曝光的時間長度取決於氮化物層的厚度。在某些實施例中，以紫外線曝光壓縮應力膜52約30秒至1小時，以破壞Si-N鍵結與N-H鍵結。在其他實施例中，以紫外線曝光壓縮應力膜52的時間介於約3分鐘至約20分鐘之間。
在某些實施例中，紫外線的波長小於200nm。
在此實施例中，在紫外線曝光時加熱裝置。加熱裝置的溫度可介於約200℃至約600℃之間。在此實施例中，在紫外線曝光時加熱裝置的溫度介於約300℃至約500℃之間。在其他實施例中，紫外線曝光時加熱裝置的溫度介於約380℃至約480℃之間。
如第12D圖所示，在形成源極/汲極區34於NMOS區 46中後，形成虛置層56於NMOS區46上。虛置層56在PMOS區44之後續製程中可保護NMOS區46。自PMOS區44移除壓縮應力膜52，且移除方法可為蝕刻。自PMOS區44中移除壓縮應力膜之鰭狀物12的剖視圖如第12E圖所示，而具有源極/汲極區34與虛置層56於其上之鰭狀物12的剖視圖如第12F圖所示。
如第13A圖所示，在形成虛置層56於NMOS區46上，且自PMOS區44移除壓縮應力膜52後，形成拉伸應力膜60於半導體裝置50上。在此實施例中，拉伸應力膜60可將壓縮應力導入PMOS區44之通道。
為形成拉伸應力膜，在形成氮化物層之CVD製程中添加氣體如氬、氮、氪、氙、或上述之混合物。舉例來說，當氬添加至CVD製程時，其流速介於約100sccm至約500sccm之間，且CVD製程之射頻功率介於約50W至3000W之間，以形成拉伸應力介於約0.7GPa至約2GPa之間的拉伸應力膜。
PMOS區44與NMOS區46之鰭狀物12及其上之拉伸應力膜60分別如第13B與13C圖所示。
接著自PMOS區44移除拉伸應力枚60，保留拉伸應力膜之殘餘物62。拉伸應力膜之殘餘物62可將應力導入後續形成於PMOS區之鰭狀物12上的源極/汲極區34，如第13D圖所示。在這實施例中，PMOS區44中的源極/汲極區34之組成為SiGe。接著形成接點層58於PMOS區44中的源極/汲極區34上。自NMOS區46移除拉伸應力層60與虛置層56，以提供FinFET半導體裝置50。
FinFET半導體裝置50之PMOS區44與NMOS區46之 鰭狀物各自具有源極/汲極區34，其剖視圖分別如第13E與13F圖所示。
第13G與13H圖係由第13B圖之結構形成源極/汲極區34於PMOS區44中(見第13E圖)之中間步驟。在PMOS區44中，自FinFET半導體裝置50移除部份的拉伸應力膜60。在此實施例中，移除拉伸應力膜52之方法為蝕刻。在使實施例中，接著蝕刻PMOS區44中鰭狀物的第二部份26，以保留拉伸應力膜之殘餘物62與凹陷的鰭狀物12，如第13H圖所示。
紫外線曝光的時間長度、層厚、與紫外線曝光時的溫度均會影響壓縮應力膜中產生的應力。舉例來說，如本揭露一實施例所示，紫外線曝光(後處理)的時間增加可增加膜應力並減少氫，如第14圖所示。以紫外線曝光壓縮膜會破壞Si-H鍵結與N-H鍵結。
第15圖係本揭露實施例中，膜厚對膜應力之效應。在第15圖中，紫外線曝光的時間均為20秒。在本揭露一實施例中，硬化時間對膜應力之效應圖如第16圖所示。
將應力導入半導體通道可改善通道之載子移動率，並改善源極/汲極效能。在尺寸縮小的半導體裝置中，能導入應力源的空間有限。然而，藉由應力膜之蝕刻殘餘物，則不需消耗半導體裝置中過多的空間即可在源極與汲極區中產生應力。對NMOS區而言，可採用壓縮應力膜提供拉伸應力至通道。對PMOS區而言，可採用拉伸應力膜提供壓縮應力至通道。在某些實施例中，NMOS中的壓縮應力膜的壓縮應力介於約-1GPa至-2GPa之間，而PMOS中的拉伸應力膜的拉伸應力介 於約0.7GPa至約2GPa之間。
在本揭露一實施例中，半導體裝置的形成方法包括：形成鰭狀結構於基板上，以及形成第一閘極結構於鰭狀結構的第一部份上。形成第一氮化物層於鰭狀結構的第二部份上。以紫外線曝光第一氮化物層。形成源極區與汲極區於鰭狀結構的第二部份。
在本揭露另一實施例中，半導體裝置的形成方法包括：形成第一鰭狀結構與第二鰭狀結構於基板上。形成第一閘極結構於第一鰭狀結構之第一部份上，以及形成第二閘極結構於第二鰭狀結構之第一部份上。形成壓縮應力膜於第一鰭狀結構之第二部份上。形成源極區與汲極區於第一鰭狀結構之第二部份。形成拉伸應力膜於第二鰭狀結構之第二部份上。形成源極區與汲極區於第二鰭狀結構之第二部份。
本揭露一實施例提供之半導體裝置包括第一鰭狀結構與一第二鰭狀結構。第一閘極結構位於第一鰭狀結構之第一部份上，而第二閘極結構位於第二鰭狀結構之第一部份上。壓縮應力膜位於第一鰭狀結構之第二部份上，且拉伸應力膜位於第二鰭狀結構之第二部份上。源極區與汲極區位於第一鰭狀結構之第二部份與第二鰭狀結構之第二部份。
本技術領域中具有通常知識者應理解，其他實施例之方法將上述方法之某些步驟取代為其他步驟，或省略上述方法之某些步驟。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本揭露。本技術領域中具有通常知識者應理解可採 用本揭露作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本揭露之精神與範疇，並可在未脫離本揭露之精神與範疇的前提下進行改變、替換、或更動。
S101、S102、S103、S104、S105‧‧‧步驟

Claims (10)

  1. 一種半導體裝置的形成方法，包括：形成一鰭狀結構於一基板上；形成一第一閘極結構於該鰭狀結構的第一部份上；形成一第一氮化物層於該鰭狀結構的第二部份上；以紫外線曝光該第一氮化物層；以及形成源極區與汲極區於該鰭狀結構的第二部份。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，更包括在以紫外線曝光該第一氮化物層後，以及在形成該源極區與該汲極區之前，移除部份該鰭狀結構的第二部份，以保留該第一氮化物層之殘餘物。
  3. 如申請專利範圍第2項所述之半導體裝置的形成方法，其中移除部份該鰭狀結構的第二部份之步驟包含蝕刻該第一氮化物層。
  4. 如申請專利範圍第1所述之半導體裝置的形成方法，其中形成該源極區與該汲極區之步驟係磊晶製程。
  5. 如申請專利範圍第1所述之半導體裝置的形成方法，其中該第一氮化物層係氮化矽、氮氧化矽、掺雜碳之氮化矽、掺雜碳之氮氧化矽、氮化硼、或氮化硼碳。
  6. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中以紫外線曝光該第一氮化物層之時間介於約30秒至60分鐘之間，且紫外線之波長小於400nm。
  7. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中形成該鰭狀結構之步驟包括形成多個鰭狀物，且更包括形 成隔離絕緣層於該些鰭狀物之間，使該鰭狀結構自該隔離絕緣層凸起。
  8. 如申請專利範圍第7項所述之半導體裝置的形成方法，其中該半導體裝置包括NMOS FinFET與PMOS FinFET，且該NMOS FinFET形成於一第一鰭狀物中，而PMOS FinFET形成於一第二鰭狀物中；其中該NMOS FinFET之形成步驟早於該PMOS FinFET之形成步驟，且該NMOS FinFET之形成步驟包括：形成該第一閘極結構於該第一鰭狀物之第一部份上；形成該第一氮化物層於該第一鰭狀物之第二部份上；以紫外線曝光該第一氮化物層；形成源極區與汲極區於該第一鰭狀物之第二部份；以及形成一虛置層於該NMOS FinFET上；其中該PMOS FinFET之形成步驟包括：形成一第二閘極結構於該第二鰭狀物之第一部份上；形成一第二氮化物層於該第二鰭狀物之第二部份上；以及形成源極區與汲極區於該第二鰭狀物之第二部份。
  9. 一種半導體裝置的形成方法，包括：形成一第一鰭狀結構與一第二鰭狀結構於一基板上；形成一第一閘極結構於該第一鰭狀結構之第一部份上，以及形成一第二閘極結構於該第二鰭狀結構之第一部份上；形成一壓縮應力膜於該第一鰭狀結構之第二部份上；以紫外線曝光該壓縮應力膜；形成源極區與汲極區於該第一鰭狀結構之第二部份； 形成一拉伸應力膜於該第二鰭狀結構之第二部份上；以及形成源極區與汲極區於該第二鰭狀結構之第二部份。
  10. 一種半導體裝置，包括：一第一鰭狀結構與一第二鰭狀結構；一第一閘極結構位於該第一鰭狀結構之第一部份上，而一第二閘極結構位於該第二鰭狀結構之第一部份上；一壓縮應力膜位於該第一鰭狀結構之第二部份上，以及一拉伸應力膜位於該第二鰭狀結構之第二部份上；以及源極區與汲極區位於該第一鰭狀結構之第二部份與該第二鰭狀結構之第二部份。
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KR20160134440A (ko) 2016-11-23
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