TW201639230A - Signal coupler and signal transmission conductive structure included therein - Google Patents
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本案係為一種信號耦合器與其中的信號傳輸導線層結構,尤指可應用於高頻微波電路之信號耦合器與其中的信號傳輸導線層結構。The present invention relates to a signal coupler and a signal transmission wire layer structure thereof, and more particularly to a signal coupler applicable to a high frequency microwave circuit and a signal transmission wire layer structure therein.
隨著通訊時代的演進,高頻微波電路因為用途廣泛而逐漸受到矚目,在電子產業應用上的需求量也是扶搖直上。而產業應用上對於高頻微波電路的設計要求是趨向體型精巧且製造成本要低,於是,若能降低電路尺寸與成本又有良好的電路特性,絕對為現今電路設計者所追求的目標。With the evolution of the communication era, high-frequency microwave circuits have gradually attracted attention because of their wide range of uses, and the demand for applications in the electronics industry has skyrocketed. In industrial applications, the design requirements for high-frequency microwave circuits tend to be compact and the manufacturing cost is low. Therefore, if the circuit size and cost can be reduced and the circuit characteristics are good, it is definitely the goal pursued by today's circuit designers.
高頻微波電路中常見的信號耦合器(Coupler)可使通過的高頻微波訊號有相移效果,並且將通過的訊號分為預設的比例進行傳輸。信號耦合器常與不同電路進行搭配進行設計,例如:功率分配器,功率合成器,功率放大器,巴特勒矩陣,陣列天線等等。信號耦合器主要可利用各種微波線路結構,例如:微帶線、條帶線、共平面波導和導波管等等來實現。A common signal coupler in a high-frequency microwave circuit can have a phase shift effect of the passed high-frequency microwave signal, and the transmitted signal is divided into preset ratios for transmission. Signal couplers are often designed with different circuits, such as power dividers, power combiners, power amplifiers, Butler matrices, array antennas, and more. Signal couplers can be implemented primarily using a variety of microwave line structures, such as microstrip lines, strip lines, coplanar waveguides, and waveguides.
請參見圖1,其係一鼠圈式環形信號耦合器(Rat-race coupler)之習知等效電路示意圖,其中每段傳輸線11係代表具有相移90度(或是四分之一波長)阻抗特性的傳輸線(transmission line),因此在完成具有四個輸出入埠P1、P2、P3及P4的鼠圈式環形信號耦合器(Rat-race coupler)的實際電路時,同常需要以六段阻抗為Z=70.7Ω且相移角度=90˚之傳輸線(Z,)來分別完成三段相移角度90˚及一段阻抗為Z’=70.7Ω且相移角度270度的傳輸線(Z’,’),然而相移角度’=270度阻抗特性之傳輸線的實體長度過長,將大幅增加電路的面積,造成電路不易縮小化而無法符合當今與未來電子產業的需求。Please refer to FIG. 1 , which is a schematic diagram of a conventional equivalent circuit of a rat-ring coupler, wherein each transmission line 11 represents a phase shift of 90 degrees (or a quarter wavelength). The transmission line of the impedance characteristic, so when the actual circuit of the rat-type ring-couple coupler with four outputs 埠P1, P2, P3 and P4 is completed, it is often necessary to have six segments. The impedance is Z=70.7Ω and the phase shift angle =90 ̊ transmission line (Z, ) to complete the three-phase phase shift angle of 90 ̊ and a transmission line with impedance of Z'=70.7Ω and phase shift angle of 270 degrees (Z', '), however the phase shift angle The physical length of the transmission line with '=270 degree impedance characteristics is too long, which will greatly increase the area of the circuit, making the circuit difficult to shrink and failing to meet the needs of today's and tomorrow's electronics industries.
故本案主要是將相移270度之傳輸線利用等效方式來改變設計,藉此減少此段傳輸線所占的電路面積,同時也將三段相移90度之傳輸線進行等效,使整體電路面積大為降低。Therefore, this case mainly uses the equivalent method to change the design of the transmission line with a phase shift of 270 degrees, thereby reducing the circuit area occupied by the transmission line of this section, and also equivalently transforming the three transmission lines with a phase shift of 90 degrees to make the overall circuit area. Greatly reduced.
本發明主要目的在於提供一種信號耦合器,該信號耦合器包含:基板;接地導體層,設置於該基板之一第一表面;以及一信號傳輸導線層,主要設置於該基板之一第二表面,該信號傳輸導線層包含有:第一導線結構、一第二導線結構與一第三導線結構,其中該第一導線結構與該第二導線結構間相連接而形成一第一節點,該第二導線結構與該第三導線結構間相連接而形成一第二節點,該第一導線結構、該第二導線結構與該第三導線結構中至少有一導線結構包含:第一子導線結構、第二子導線結構以及第一開路殘段,其中該第一子導線結構之一第一端、該第二子導線結構之一第一端與該開路殘段皆連接於一第三節點;以及一第四導線結構,其包含有一第一電容、一第二電容與一接地傳輸線,其中該第一電容之一第一端與該第二電容之一第一端係分別連接至該第一導線結構與該第三導線結構而形成一第四節點與一第五節點,而該第一電容之一第二端與該第二電容之一第二端與該接地傳輸線皆連接於一第六節點,且該接地傳輸線電性連接至該接地導體層。A main object of the present invention is to provide a signal coupler comprising: a substrate; a ground conductor layer disposed on a first surface of the substrate; and a signal transmission wire layer disposed on a second surface of the substrate The signal transmission wire layer includes: a first wire structure, a second wire structure and a third wire structure, wherein the first wire structure and the second wire structure are connected to form a first node, the first The second wire structure is connected to the third wire structure to form a second node. The first wire structure, the second wire structure and the third wire structure have at least one wire structure including: a first sub-wire structure, a first sub-wire structure and a first open-circuit stub, wherein the first end of the first sub-wire structure, the first end of the second sub-wire structure and the open stub are connected to a third node; The fourth wire structure includes a first capacitor, a second capacitor and a ground transmission line, wherein the first end of the first capacitor is connected to the first end of the second capacitor Forming a fourth node and a fifth node to the first wire structure and the third wire structure, and connecting the second end of the first capacitor to the second end of the second capacitor and the ground transmission line And a sixth node, and the ground transmission line is electrically connected to the ground conductor layer.
根據上述構想,本案所述之信號耦合器,其中該基板可由介電材料完成,該第一導線結構、該第二導線結構、該第三導線結構與該第四導線結構之等效特性阻抗皆可為70.7Ω,且該第一導線結構、該第二導線結構與該第三導線結構的相位延遲皆可為90度,該第四導線結構的相位延遲可為270度,該第四導線結構而該第一節點可電性連接至一第一信號輸出入端,該第四節點係電性連接至一第二信號輸出入端,該第五節點係電性連接至一第三信號輸出入端,該第二節點係電性連接至一第四信號輸出入端。According to the above concept, the signal coupler of the present invention, wherein the substrate is made of a dielectric material, and the equivalent characteristic impedance of the first wire structure, the second wire structure, the third wire structure and the fourth wire structure are both The phase of the first wire structure, the second wire structure and the third wire structure may each be 90 degrees, and the phase delay of the fourth wire structure may be 270 degrees. The fourth wire structure may be 70.7 Ω. The first node is electrically connected to a first signal input and output end, the fourth node is electrically connected to a second signal input and output end, and the fifth node is electrically connected to a third signal input and output. The second node is electrically connected to a fourth signal input and output end.
根據上述構想,本案所述之信號耦合器,其中該第一導線結構、該第二導線結構與該第三導線結構之等效特性阻抗與相位延遲皆相等,而且各自包含有相對應的該第一子導線結構、該第二子導線結構以及該第一開路殘段。According to the above concept, the signal coupler of the present invention, wherein the first conductor structure, the second conductor structure and the third conductor structure have equal equivalent characteristic impedances and phase delays, and each includes a corresponding one. a sub-wire structure, the second sub-wire structure, and the first open stub.
根據上述構想,本案所述之信號耦合器,其中該第四導線結構之該第一電容與該第二電容具有相同的電容值,該接地傳輸線係經穿過該基板之一透孔而電性連接至該第一表面上的該接地導體層,該接地傳輸線、該第一子導線結構、該第二子導線結構以及該第一開路殘段具有實質上相等之導線寬度。According to the above concept, the signal coupler of the present invention, wherein the first capacitor of the fourth wire structure has the same capacitance value as the second capacitor, and the ground transmission line passes through a through hole of the substrate and is electrically Connected to the ground conductor layer on the first surface, the ground transmission line, the first sub-wire structure, the second sub-wire structure, and the first open stub have substantially equal wire widths.
根據上述構想,本案所述之信號耦合器,其中該接地傳輸線、該第一子導線結構、該第二子導線結構以及該第一開路殘段中至少有一結構具有大於或等於直角的轉折。According to the above concept, the signal coupler of the present invention, wherein at least one of the ground transmission line, the first sub-wire structure, the second sub-wire structure, and the first open stub has a turn greater than or equal to a right angle.
本案之另一方面係為一種信號傳輸導線層結構,其包含:一第一導線結構、一第二導線結構與一第三導線結構,其中該第一導線結構與該第二導線結構間相連接而形成一第一節點,該第二導線結構與該第三導線結構間相連接而形成一第二節點,該第一導線結構、該第二導線結構與該第三導線結構中至少有一導線結構包含:一第一子導線結構、一第二子導線結構以及一第一開路殘段,其中該第一子導線結構之一第一端、該第二子導線結構之一第一端與該開路殘段皆連接於一第三節點;以及一第四導線結構,其包含有一第一電容、一第二電容與一接地傳輸線,其中該第一電容之一第一端與該第二電容之一第一端係分別連接至該第一導線結構與該第三導線結構而形成一第四節點與一第五節點,而該第一電容之一第二端與該第二電容之一第二端與該接地傳輸線皆連接於一第六節點,且該接地傳輸線電性連接至一接地導體層,而該接地導體層透過一介電材料與該等導線結構隔開。Another aspect of the present invention is a signal transmission wire layer structure, comprising: a first wire structure, a second wire structure and a third wire structure, wherein the first wire structure and the second wire structure are connected And forming a first node, the second wire structure is connected with the third wire structure to form a second node, and the first wire structure, the second wire structure and the third wire structure have at least one wire structure The first sub-wire structure, a second sub-wire structure, and a first open-circuit stub, wherein the first end of the first sub-wire structure, the first end of the second sub-wire structure, and the open end Each of the first capacitors is connected to a third node The first end is connected to the first wire structure and the third wire structure respectively to form a fourth node and a fifth node, and the second end of the first capacitor and the second end of the second capacitor And the grounding Lines are connected to a sixth node, and the transmission ground line is electrically connected to a ground conductor layer, and spaced apart from the ground conductor layer through a dielectric material with such conductor structures.
根據上述構想,本案所述之信號傳輸導線層結構,其中該第一導線結構、該第二導線結構、該第三導線結構與該第四導線結構之等效特性阻抗皆為70.7Ω,且該第一導線結構、該第二導線結構與該第三導線結構的相位延遲皆為90度,該第四導線結構的相位延遲為270度,而該第一節點係電性連接至一第一信號輸出入端,該第四節點係電性連接至一第二信號輸出入端,該第五節點係電性連接至一第三信號輸出入端,該第二節點係電性連接至一第四信號輸出入端。According to the above concept, the signal transmission wire layer structure of the present invention, wherein the first wire structure, the second wire structure, the third wire structure and the fourth wire structure have an equivalent characteristic impedance of 70.7 Ω, and The phase difference between the first wire structure, the second wire structure and the third wire structure is 90 degrees, the phase delay of the fourth wire structure is 270 degrees, and the first node is electrically connected to a first signal The fourth node is electrically connected to a second signal input and output end, the fifth node is electrically connected to a third signal input and output end, and the second node is electrically connected to a fourth Signal output terminal.
根據上述構想,本案所述之信號傳輸導線層結構,其中該第一導線結構、該第二導線結構與該第三導線結構之阻抗與相位延遲皆相等,而且各自包含有相對應的該第一子導線結構、該第二子導線結構以及該第一開路殘段。According to the above concept, the signal transmission wire layer structure of the present invention, wherein the impedance of the first wire structure, the second wire structure and the third wire structure are equal to each other, and each of the first wire structure has a corresponding first a sub-wire structure, the second sub-wire structure, and the first open stub.
根據上述構想,本案所述之信號傳輸導線層結構,其中該第四導線結構之該第一電容與該第二電容具有相同的電容值,該接地傳輸線係穿過該介電材料之一透孔而電性連接至該接地導體層,該接地傳輸線、該第一子導線結構、該第二子導線結構以及該第一開路殘段具有實質上相等之導線寬度。According to the above concept, the signal transmission wire layer structure of the present invention, wherein the first capacitance of the fourth wire structure and the second capacitance have the same capacitance value, and the ground transmission line passes through one of the dielectric materials And electrically connected to the ground conductor layer, the ground transmission line, the first sub-wire structure, the second sub-wire structure and the first open stub have substantially equal conductor widths.
根據上述構想,本案所述之信號傳輸導線層結構,其中該接地傳輸線、該第一子導線結構、該第二子導線結構以及該第一開路殘段中至少有一結構具有大於或等於直角的轉折。According to the above concept, the signal transmission wire layer structure of the present invention, wherein at least one of the ground transmission line, the first sub-wire structure, the second sub-wire structure, and the first open stub has a turn greater than or equal to a right angle .
本案之再一方面係為一種信號傳輸導線層結構,其包含:一第一導線結構、一第二導線結構與一第三導線結構,其中該第一導線結構與該第二導線結構間相連接而形成一第一節點,該第二導線結構與該第三導線結構間相連接而形成一第二節點;以及一第四導線結構,其包含有一第一電容、一第二電容與一接地傳輸線,其中該第一電容之一第一端與該第二電容之一第一端係分別連接至該第一導線結構與該第三導線結構而形成一第四節點與一第五節點,而該第一電容之一第二端與該第二電容之一第二端與該接地傳輸線皆連接於一第六節點,且該接地傳輸線電性連接至一接地導體層,而該接地導體層透過一介電材料與該等導線結構隔開,而該第一導線結構、該第二導線結構、該第三導線結構與該第四導線結構之等效特性阻抗皆為相等,且該第一導線結構、該第二導線結構與該第三導線結構的相位延遲皆為90度,該第四導線結構的相位延遲為270度。A further aspect of the present invention is a signal transmission wire layer structure, comprising: a first wire structure, a second wire structure and a third wire structure, wherein the first wire structure and the second wire structure are connected Forming a first node, the second wire structure is connected to the third wire structure to form a second node; and a fourth wire structure including a first capacitor, a second capacitor and a ground transmission line The first end of the first capacitor and the first end of the second capacitor are respectively connected to the first wire structure and the third wire structure to form a fourth node and a fifth node, and the The second end of the first capacitor and the second end of the second capacitor and the ground transmission line are both connected to a sixth node, and the ground transmission line is electrically connected to a ground conductor layer, and the ground conductor layer is transmitted through a The dielectric material is spaced apart from the conductor structures, and the first conductor structure, the second conductor structure, the third conductor structure and the fourth conductor structure have equal equivalent characteristic impedances, and the first conductor structure The phase of the second conductor structure and the third conductor structure are all delayed by 90 degrees, the fourth wire structure phase delay is 270 degrees.
本案之又一方面係為一種信號傳輸導線層結構,其包含:一第一導線結構、一第二導線結構與一第三導線結構,其中該第一導線結構與該第二導線結構間相連接而形成一第一節點,該第二導線結構與該第三導線結構間相連接而形成一第二節點,該第一導線結構、該第二導線結構與該第三導線結構中至少有一導線結構包含:一第一子導線結構、一第二子導線結構以及一第一開路殘段,其中該第一子導線結構之一第一端、該第二子導線結構之一第一端與該開路殘段皆連接於一第三節點;以及一第四導線結構,其與該第一導線結構、該第二導線結構、該第三導線結構之等效特性阻抗皆為相同,且該第一導線結構、該第二導線結構與該第三導線結構的相位延遲皆為90度,該第四導線結構的相位延遲為270度。A further aspect of the present invention is a signal transmission wire layer structure, comprising: a first wire structure, a second wire structure and a third wire structure, wherein the first wire structure and the second wire structure are connected And forming a first node, the second wire structure is connected with the third wire structure to form a second node, and the first wire structure, the second wire structure and the third wire structure have at least one wire structure The first sub-wire structure, a second sub-wire structure, and a first open-circuit stub, wherein the first end of the first sub-wire structure, the first end of the second sub-wire structure, and the open end The stubs are all connected to a third node; and a fourth wire structure is identical to the first wire structure, the second wire structure, and the third wire structure, and the first wire is The phase delay of the structure, the second wire structure and the third wire structure are both 90 degrees, and the phase delay of the fourth wire structure is 270 degrees.
體現本案特徵與優點的一些典型實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的樣態上具有各種的變化,其皆不脫離本案的範圍,且其中的說明及圖式在本質上係當作說明之用,而非用以限制本案。Some exemplary embodiments embodying the features and advantages of the present invention are described in detail in the following description. It is to be understood that the present invention is capable of various modifications in the various aspects of the present invention, and the description and the drawings are in the nature of the description and are not intended to limit the present invention.
請參見圖2,其係本案為改善習知技藝缺失所發展出來關於鼠圈式環形耦合器(Rat-race coupler)的等效電路示意圖。如上所述,耦合器主要可利用各種微波線路結構,例如:微帶線、條帶線、共平面波導和導波管等等來實現。而其中微帶線具有體積小、重量輕及使用頻帶寬廣的優點,故本案採用微帶線來進行實施例說明,當然,本案概念也可以選用其它微波電路結構來完成。Please refer to FIG. 2, which is an equivalent circuit diagram of a rat-ring type coupler developed in order to improve the lack of conventional skills. As noted above, the coupler can be implemented primarily using a variety of microwave line structures, such as microstrip lines, strip lines, coplanar waveguides, and waveguides. Among them, the microstrip line has the advantages of small size, light weight and wide frequency band of use. Therefore, the microstrip line is used in the present embodiment for description. Of course, the concept of the present invention can also be completed by using other microwave circuit structures.
首先,為了要等效出圖1中Z=70.7Ω;=90˚之傳輸線,本案之第一導線結構21與第二導線結構22間相連接而形成第一節點N1,該第二導線結構22與該第三導線結構23間相連接而形成一第二節點N2,本案之第一導線結構21、第二導線結構22與第三導線結構23中之任一導線結構皆可以利用第一子導線結構211、第二子導線結構212以及開路殘段213來完成,其中該第一子導線結構211之第一端2111、該第二子導線結構212之第一端2121與該開路殘段213皆連接於第三節點N3。可以先給定代表每個子導線結構(211,212)相位延遲的值,選擇的要領是最好可以先給定一個小於90˚的,如此可以讓其等效電路中的每個子導線結構(211,212)長度縮短,例如,先給定=35˚,並將=35˚代入式(1)來推出代表每個子導線結構21特性阻抗的值。……………式(1) 而由上述式子運算出當=35˚時,=100.9Ω,接著將與代入式(2),進而求得特性導納。………………………式(2) 而本案是選用開路殘段213的結構來等效特性導納,所以先設定好開路殘段的特性阻抗後再代入下列式(3),而因為微帶線的寬度與特性阻抗相關,因此為能讓線寬一致好製作,於是本例是選定=100Ω來與=100.9Ω對應,當然也可以是選用其它合適的寬度,以滿足設計當時的需求。……………………………式(3) 以本例而言,由選定之與對應出之特性導納再代入式(3)將可求得代表開路殘段相位延遲之電氣長度=35.9˚。於是,圖1中所示之Z=70.7Ω;=90˚的傳統微帶傳輸線將可由兩段(=35˚,=100.9Ω)之微帶傳輸線(第一子導線結構211與該第二子導線結構212)以及一段(=35.9˚,=100Ω)之微帶傳輸線開路殘段213來等效完成。First, in order to be equivalent to Z = 70.7 Ω in Figure 1; The first wire structure 21 and the second wire structure 22 are connected to form a first node N1, and the second wire structure 22 is connected with the third wire structure 23 to form a second The node N2, any one of the first wire structure 21, the second wire structure 22 and the third wire structure 23 of the present invention can utilize the first sub-wire structure 211, the second sub-wire structure 212 and the open stub 213 The first end 2111 of the first sub-wire structure 211, the first end 2121 of the second sub-wire structure 212, and the open stub 213 are all connected to the third node N3. The value representing the phase delay of each sub-wire structure (211, 212) can be given first. The choice of the best is to give a less than 90 先 first So that the length of each sub-wire structure (211, 212) in its equivalent circuit can be shortened, for example, given first =35 ̊, and =35 ̊ Substituting (1) to derive the value representing the characteristic impedance of each sub-wire structure 21 . ...............Formula (1) and by the above formula =35 ̊, =100.9Ω, then will versus Substituting equation (2), and then obtaining characteristic admittance . ........................... (2) In this case, the structure of the open-circuit stub 213 is selected to obtain the equivalent characteristic admittance. , so first set the characteristic impedance of the open stub Substituting the following formula (3), and because the width of the microstrip line is related to the characteristic impedance, it is made to make the line width uniform, so this example is selected. =100Ω to = 100.9Ω corresponds to, of course, other suitable widths can be selected to meet the needs of the design at the time. ................................. (3) In this case, selected by Characteristic admittance Substituting into equation (3) will find the electrical length representing the phase delay of the open stub. =35.9 ̊. Thus, Z = 70.7 Ω shown in Figure 1; The traditional microstrip transmission line of =90 将 will be available in two segments ( =35 ̊, a microstrip transmission line of =100.9 Ω (the first sub-conductor structure 211 and the second sub-conductor structure 212) and a segment ( =35.9 ̊, The microstrip transmission line open block 213 of =100 Ω is equivalently completed.
而由上述設計流程可看出,透過事先給定微帶傳輸線的線寬或線長,便可利用公式推估出相對應的線長或線寬,因此設計者可以視環境需求而來適度調整等效所需微帶傳輸線的線寬與線長,進而能符合應用環境對於布局面積與形狀的需求。As can be seen from the above design flow, by specifying the line width or line length of the microstrip transmission line in advance, the corresponding line length or line width can be estimated by the formula, so the designer can appropriately adjust according to the environmental demand. The line width and line length of the equivalent required microstrip transmission line can meet the requirements of the application environment for layout area and shape.
接著,本案再提出以電容搭配傳輸線接地結構來等效出圖1中所示出之=70.7Ω;=270˚之微帶傳輸線(第四導線結構24),於是將給定之與先代入如下之式(4),求得 …………………………………(4) 再將利用接地傳輸線240來等效替代,首先給定接地傳輸線240之特性阻抗=100Ω,代表與上述佈局的線寬一致,製作較為方便。接著,將=100Ω代入式(5),式(5)如下:………………………………...(5) 如此將可求得接地的傳輸線之電氣長度=35.26˚,接著將無線區域網路的工作頻率f=2.45GHz代入式(6),式(6) 如下:……………………………… (6) 求得等效所需的電容值C=0.918pF。而第四導線結構24中之兩個電容C係分別連接至該第一導線結構21與該第三導線結構23而形成一第四節點N4與一第五節點N5,而兩個電容C之第二端與接地傳輸線240皆連接於一第六節點N6,且該接地傳輸線240電性連接至一接地導體層(本圖未示出),而該接地導體層透過一介電材料(本圖未示出)與該等導線結構21~24隔開。而上述第一節點N1係電性連接至第一信號輸出入端P1,該第四節點N4係電性連接至一第二信號輸出入端P2,該第五節點N5係電性連接至一第三信號輸出入端P3,該第二節點N2係電性連接至一第四信號輸出入端P4。Then, in this case, the capacitor is combined with the transmission line grounding structure to equate the one shown in Figure 1. =70.7Ω; =270 微 microstrip transmission line (fourth wire structure 24), so will be given versus First enter the following formula (4), and obtain .................................(4) Using the ground transmission line 240 for an equivalent replacement, first the characteristic impedance of the ground transmission line 240 is given. =100Ω, which is consistent with the line width of the above layout, and is convenient to manufacture. Next, will =100Ω is substituted into equation (5), and equation (5) is as follows: .................................(5) The electrical length of the transmission line that will be grounded in this way =35.26 ̊, then substituting the operating frequency of the wireless local area network f=2.45GHz into equation (6), the following equation (6): .............................. (6) Find the equivalent capacitance value C = 0.918pF. The two capacitors C of the fourth wire structure 24 are respectively connected to the first wire structure 21 and the third wire structure 23 to form a fourth node N4 and a fifth node N5, and the two capacitors C The two ends and the grounding transmission line 240 are both connected to a sixth node N6, and the grounding transmission line 240 is electrically connected to a grounding conductor layer (not shown in the figure), and the grounding conductor layer is transmitted through a dielectric material (this figure is not Shown) separated from the conductor structures 21-24. The first node N1 is electrically connected to the first signal input/output terminal P1, and the fourth node N4 is electrically connected to a second signal input/output terminal P2. The fifth node N5 is electrically connected to the first node. The third signal is input to the terminal P3, and the second node N2 is electrically connected to a fourth signal input/output terminal P4.
再請參見圖3a,其係本實施例之信號耦合器之剖面示意圖,主要包含有基板30以及接地導體層31,接地導體層31設置於該基板30之第一表面301,而信號傳輸導線層32主要設置於該基板30之一第二表面302。而上述基板30可選用常見的FR-4(通常由玻璃布(Woven glass)及/或環氧樹脂來組成)雙面板(厚度(h)=1.6mm, 相對介電常數(εr)=4.3)來當基礎材料,當然也可以其它的介電材料。Referring to FIG. 3a, it is a cross-sectional view of the signal coupler of the embodiment, which mainly includes a substrate 30 and a ground conductor layer 31. The ground conductor layer 31 is disposed on the first surface 301 of the substrate 30, and the signal transmission wire layer 32 is mainly disposed on one of the second surfaces 302 of the substrate 30. The substrate 30 can be selected from common FR-4 (usually composed of Woven glass and/or epoxy resin) double panel (thickness (h)=1.6 mm, relative dielectric constant (εr)=4.3). As a base material, of course, other dielectric materials are also available.
至於該信號傳輸導線層32之布局實例示意圖則如圖3b之所示,主要包含有第一導線結構321、第二導線結構322與第三導線結構323,其中該第一導線結構321與該第二導線結構322間相連接而形成第一節點N1,該第二導線結構322與該第三導線結構323間相連接而形成第二節點N2,該第一導線結構321、該第二導線結構322與該第三導線結構323中至少有一導線結構包含:第一子導線結構3211、第二子導線結構3212以及第一開路殘段3213,其中該第一子導線結構3211之一端、該第二子導線結構3212之一端與該開路殘段3213皆連接於第三節點N3。至於第四導線結構3214則可包含有第一電容C1、第二電容C2與接地傳輸線32140,其中該第一電容C1之一第一端與該第二電容C2之一第一端係分別連接至該第一導線結構321與該第三導線結構323而形成一第四節點N4與一第五節點N5,而該第一電容C1之一第二端與該第二電容C2之一第二端與該接地傳輸線32140皆連接於一第六節點N6,且該接地傳輸線32140透過接地透孔299電性連接至圖3a所示之接地導體層31。本例主要是在FR-4的雙面電路板(厚度(h)=1.6mm, 相對介電常數(εr)=4.3)上實現電路的布局尺寸示意圖,其設計主要是為了縮小電路面積,所以許多繞線都具有轉折來讓電路面積優化,因此本例中之接地傳輸線32140、第一子導線結構3211、第二子導線結構3212以及第一開路殘段3213中至少有一結構具有大於或等於直角的轉折。其中各個導線結構中的段落長度L1~L11與寬度W分別為:L1=3.15mm;L2=7.82mm;L3=3.78mm;L4=1.72mm;L5=0.78mm;L6=5mm;L7=1.6mm;L8=9.4mm;L9=5.4mm;L10=3.25mm;W=0.71mm;G=0.4mm(G是置放表面黏著技術(SMT)電容位置兩端金屬間的空隙距離);C=0.9pF。As shown in FIG. 3b, the schematic diagram of the layout of the signal transmission wire layer 32 mainly includes a first wire structure 321, a second wire structure 322 and a third wire structure 323, wherein the first wire structure 321 and the first The two wire structures 322 are connected to each other to form a first node N1. The second wire structure 322 is connected to the third wire structure 323 to form a second node N2. The first wire structure 321 and the second wire structure 322 are formed. The at least one wire structure of the third wire structure 323 includes: a first sub-wire structure 3211, a second sub-wire structure 3212, and a first open-circuit stub 3213, wherein the first sub-wire structure 3211 is at one end, the second sub- One end of the wire structure 3212 and the open circuit segment 3213 are both connected to the third node N3. The fourth conductor structure 3214 may include a first capacitor C1, a second capacitor C2, and a ground transmission line 32140, wherein the first end of the first capacitor C1 and the first end of the second capacitor C2 are respectively connected to The first wire structure 321 and the third wire structure 323 form a fourth node N4 and a fifth node N5, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are The grounding transmission line 32140 is connected to a sixth node N6, and the grounding transmission line 32140 is electrically connected to the grounding conductor layer 31 shown in FIG. 3a through the grounding through hole 299. This example is mainly to realize the layout size of the circuit on the FR-4 double-sided circuit board (thickness (h)=1.6mm, relative dielectric constant (εr)=4.3). The design is mainly to reduce the circuit area, so Many windings have a turning point to optimize the circuit area, so at least one of the ground transmission line 32140, the first sub-conductor structure 3211, the second sub-conductor structure 3212, and the first open stub 3213 in this example has a structure greater than or equal to a right angle. The turning point. The lengths of the segments L1~L11 and width W in each wire structure are: L1=3.15mm; L2=7.82mm; L3=3.78mm; L4=1.72mm; L5=0.78mm; L6=5mm; L7=1.6mm ; L8 = 9.4mm; L9 = 5.4mm; L10 = 3.25mm; W = 0.71mm; G = 0.4mm (G is the gap distance between the metal at both ends of the surface mount technology (SMT) capacitor position); C = 0.9 pF.
最後所完成的電路尺寸約占用2.9cm * 1.8cm的面積,其實體示意圖可參見圖4與圖7之所示,由圖可清楚看出,本案可以有效降低電路面積。當然,上述繞線尺寸並非不可變動,而是可以隨著需求而進行調整,但是以本案概念設計完成之電路,其面積都可以得到相當程度的縮減,進而達到改善習用手段缺失的目的。而FR-4的雙面板的選用及其厚度的設定皆是因為材料取得的方便,但實際上不侷限於此種規格與尺寸。The final completed circuit size occupies an area of 2.9cm * 1.8cm. The physical schematic diagram can be seen in Figure 4 and Figure 7. It can be clearly seen from the figure that the case can effectively reduce the circuit area. Of course, the above-mentioned winding size is not immutable, but can be adjusted according to the demand, but the circuit designed by the concept of the present case can be reduced in size to a certain extent, thereby achieving the purpose of improving the lack of conventional means. The selection of the double panel of the FR-4 and the thickness setting are all due to the convenience of the material, but in fact it is not limited to such specifications and dimensions.
至於圖5與圖6則是表示出上述設計以網路分析儀量測其結果與模擬結果,兩者間具有良好的一致性。其中由圖5可看出通帶|S21|及|S41|模擬與實測之S參數,實測大小為-3.48dB及-3.1dB,實測相位∠S21= -166˚;∠S41= -145˚相位差21˚,圖5所示之|S23|及|S43|實測結果為-3.5dB及-3.5dB,相位為∠S23=8.3˚;∠S43= -166˚相位差185˚。至於圖6所示之反射參數|S11|及隔離參數|S31|皆低於-10dB,皆可驗證此設計方式能有效縮小其電路面積,且有良好之電路特性。As for Fig. 5 and Fig. 6, it is shown that the above design is measured by a network analyzer and the simulation results are obtained, and the two have good consistency. From Fig. 5, we can see that the S-parameters of the passbands |S21| and |S41| are measured and measured, the measured sizes are -3.48dB and -3.1dB, and the measured phase ∠S21= -166 ̊; ∠S41= -145 ̊ phase The difference is 21 ̊, the results of |S23| and |S43| shown in Fig. 5 are -3.5dB and -3.5dB, the phase is ∠S23=8.3 ̊; ∠S43= -166 ̊ phase difference 185 ̊. As for the reflection parameter |S11| and the isolation parameter |S31| shown in Fig. 6, all of them are lower than -10 dB, and it can be verified that the design method can effectively reduce the circuit area and have good circuit characteristics.
綜上所述,本文提出之可應用於WiFi頻段之縮小化鼠圈式耦合器設計,其中可將鼠圈式耦合器中3/4波長(相位延遲270度)傳輸線占用較大電路面積的問題改善,也可將各個1/4波長(相位延遲90度)傳輸線縮小。設計方式使用集總元件、開路殘斷與傳輸線下地混合式的T型等效,使電路中傳輸線等阻抗及相近的電器長度,將低阻抗不連續的問題,實例中可縮小整體電路面積77.9%。另外,本案得由熟知此技術之人士任施匠思而為諸般修飾,然皆不脫如附申請專利範圍所欲保護者。In summary, this paper proposes a reduced-sized mouse-ring coupler design that can be applied to the WiFi band, in which the 3/4 wavelength (phase delay 270-degree) transmission line in the mouse-ring coupler can occupy a large circuit area. Improvements can also reduce the transmission line of each 1/4 wavelength (phase delay 90 degrees). The design method uses the T-type equivalent of the lumped element, the open circuit break and the mixed line under the transmission line, so that the impedance of the transmission line in the circuit and the length of the similar electrical device will cause the low impedance discontinuity. In the example, the overall circuit area can be reduced by 77.9%. . In addition, the present invention has been modified by those skilled in the art, and is not intended to be protected by the scope of the patent application.
11‧‧‧傳輸線
P1、P2、P3及P4‧‧‧四個輸出入埠
21‧‧‧第一導線結構
22‧‧‧第二導線結構
N1‧‧‧第一節點
N2‧‧‧第二節點
211‧‧‧第一子導線結構
212‧‧‧第二子導線結構
213‧‧‧開路殘段
211之第一端2111‧‧‧第一子導線結構
212之第一端2121‧‧‧第二子導線結構
N3‧‧‧第三節點
23‧‧‧第三導線結構
240‧‧‧接地傳輸線
jB0‧‧‧特性導納
L1~L11‧‧‧長度
W‧‧‧寬度
C‧‧‧電容
24‧‧‧第四導線結構
N4‧‧‧第四節點
N5‧‧‧第五節點
N6‧‧‧第六節點
30‧‧‧基板
31‧‧‧接地導體層
301‧‧‧第一表面
32‧‧‧信號傳輸導線層
302‧‧‧第二表面
321‧‧‧第一導線結構
322‧‧‧第二導線結構
323‧‧‧第三導線結構
3211‧‧‧第一子導線結構
3212‧‧‧第二子導線結構
3213‧‧‧第一開路殘段
3214‧‧‧第四導線結構
C1‧‧‧第一電容
C2‧‧‧第二電容
299‧‧‧接地透孔
32140‧‧‧接地傳輸線11‧‧‧ transmission line
P1, P2, P3 and P4‧‧‧ four outputs
21‧‧‧First wire structure
22‧‧‧Second wire structure
N1‧‧‧ first node
N2‧‧‧ second node
211‧‧‧First sub-wire structure
212‧‧‧Second sub-wire structure
213‧‧‧Open road segment
The first sub-wire structure of the first end of 211 2111‧‧
The first end of 212 is 2121‧‧‧ the second sub-wire structure
N3‧‧‧ third node
23‧‧‧ Third wire structure
240‧‧‧ Grounding transmission line
jB0‧‧‧Feature Admittance
L1~L11‧‧‧ length
W‧‧‧Width
C‧‧‧ capacitor
24‧‧‧Fourth wire structure
N4‧‧‧ fourth node
N5‧‧‧ fifth node
N6‧‧‧ sixth node
30‧‧‧Substrate
31‧‧‧ Grounding conductor layer
301‧‧‧ first surface
32‧‧‧Signal transmission wire layer
302‧‧‧ second surface
321‧‧‧First wire structure
322‧‧‧Second wire structure
323‧‧‧ Third wire structure
3211‧‧‧First sub-wire structure
3212‧‧‧Second sub-wire structure
3213‧‧‧The first open road segment
3214‧‧‧4th wire structure
C1‧‧‧first capacitor
C2‧‧‧second capacitor
299‧‧‧ Grounding through hole
32140‧‧‧ Grounding transmission line
圖1,其係鼠圈式環形信號耦合器之習知等效電路示意圖。 圖2,其係本案為改善習知技藝缺失所發展出來關於鼠圈式環形耦合器的等效電路示意圖。 圖3a,其係本實施例之信號耦合器之剖面示意圖。 圖3b,其係為在FR-4雙面電路板上實現電路的布局尺寸示意圖。 圖4, 其係本實施例在FR-4雙面電路板上實現電路的實體示意圖。 圖5,其係本實施例以網路分析儀量測其結果與模擬結果的特性比較示意圖。 圖6,其係本實施例以網路分析儀量測其結果與模擬結果的另一特性比較示意圖。 圖7,其係本實施例所完成的實體與傳統技術所完成的實體比較示意圖。FIG. 1 is a schematic diagram of a conventional equivalent circuit of a rat-ring type ring signal coupler. FIG. 2 is an equivalent circuit diagram of the rat ring type ring coupler developed in the present case to improve the lack of conventional skills. Figure 3a is a schematic cross-sectional view of the signal coupler of the present embodiment. Figure 3b is a schematic diagram showing the layout dimensions of the circuit implemented on the FR-4 double-sided circuit board. Figure 4 is a schematic diagram showing the implementation of the circuit on the FR-4 double-sided circuit board in this embodiment. FIG. 5 is a schematic diagram showing the comparison of the results of the simulation results with the network analyzer in the present embodiment. Fig. 6 is a schematic view showing another comparison of the results of the present embodiment and the simulation results by the network analyzer. FIG. 7 is a schematic diagram showing the comparison between the entity completed by the embodiment and the entity completed by the conventional technology.
21‧‧‧第一導線結構 21‧‧‧First wire structure
22‧‧‧第二導線結構 22‧‧‧Second wire structure
N1‧‧‧第一節點 N1‧‧‧ first node
N2‧‧‧第二節點 N2‧‧‧ second node
211‧‧‧第一子導線結構 211‧‧‧First sub-wire structure
212‧‧‧第二子導線結構 212‧‧‧Second sub-wire structure
213‧‧‧開路殘段 213‧‧‧Open road segment
2111‧‧‧第一子導線結構211之第一端 2111‧‧‧ the first end of the first sub-wire structure 211
2121‧‧‧第二子導線結構212之第一端 2121‧‧‧ the first end of the second sub-wire structure 212
N3‧‧‧第三節點 N3‧‧‧ third node
Claims (12)
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Cited By (1)
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TWI678712B (en) * | 2018-09-27 | 2019-12-01 | 創意電子股份有限公司 | Structure of circuit board and structure of conductive transmission line thereof |
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TWI678712B (en) * | 2018-09-27 | 2019-12-01 | 創意電子股份有限公司 | Structure of circuit board and structure of conductive transmission line thereof |
US10736209B2 (en) | 2018-09-27 | 2020-08-04 | Global Unichip Corporation | Circuit board structure and conductive transmission line structure thereof |
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