TW201626568A - Active device and high voltage-semiconductor device with the same - Google Patents

Abstract

A high voltage (HV) semiconductor device is provided, comprising a substrate, a first well having a first conductive type and extending down from a surface of the substrate; a plurality of active devices respectively formed on the substrate, and the adjacent active devices electrically separated from each other by an insulation. One of the active devices comprises a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well, a ring gate formed in the diffusion region, and a light doping region having a second conductive type and extending down from a surface of the diffusion region. The light doping region is offset from an edge of the insulation.

Description

Active component and high voltage semiconductor component using the same 【0001】

The present invention relates to an active component and a high voltage semiconductor component using the active component, and in particular to an active component capable of supporting high voltage operation without a free of STI edge issue and applying the same High voltage semiconductor component of the active device.

【0002】

In the Very-large-scale integration (VLSI) technology, shallow-trench isolation (STI) isolation active elements (such as complementary metal oxide semiconductor transistors) are usually defined. Channel width. However, researchers have found that STI edges can cause many serious problems for application components.

[0003]

Figure 1 illustrates a conventional layout of a semiconductor component. The semiconductor component includes a plurality of active components 10 disposed on a substrate at a distance from one another and both located in a first well 12 having a first conductivity state, such as a P-well of an NMOS component. Furthermore, a light doping region has a second conductive state (eg, N-) and is located in the P-well and surrounds all active components 10 and P-well contacts. Adjacent active components 10 are electrically isolated by STI. Each active device 10 includes a diffusion region DIF having a first conductive state, a first contact region 111 (eg, a drain region) and a second contact region 113 (eg, a source region) respectively located in the diffusion region DIF. And a polysilicon gate PG having a gate contact 115 thereon is formed between the first contact region 111 and the second contact region 113. For conventional semiconductor components, STIs that exist between adjacent active components 10 can cause undesirable STI edge issues.

[0004]

2 is a schematic cross-sectional view showing a polysilicon gate of a conventional semiconductor device and insulators on both sides. A polysilicon gate PG is formed in a gate oxide layer GOX, and a channel 135 is located under the polysilicon gate PG and between the insulators STI. Figure 3A is a typical low-voltage (LV) NMOS transistor of the I _D -V _G characteristic curve, wherein the gate oxide GOX layer having a thickness of 70Å, W / Lg = 0.6μm /0.4μm , and a drain of the plurality of curve The pole bias (V _D ) is measured at 0.1V. Figure 3B is an I _D -V _G characteristic curve of a typical high voltage (HV) NMOS transistor in which the gate oxide layer GOX has a thickness of 370 Å, W/Lg = 10 μm / 1.6 μm, and the curves are in a bungee The bias voltage (V _D ) was measured at 0.1V. Please refer to Figures 1 to 3B. The STI edge is usually the "weakness" of the semiconductor component (as circled in Figure 2), causing an abnormal subthreshold leakage current and an undesired double hump subcritical I _D- V _G characteristic curve (as shown by curve Process-1 in Figures 3A and 3B). In Figs. 3A and 3B, the curve Process-1 represents the I _D -V _G characteristic curve of a typical NMOS transistor having a bimodal leakage current, and the curve Process-2 represents the I _D of a typical NMOS transistor having an improved STI. The V _G characteristic curve, curve Process-3, represents the I _D -V _G characteristic curve of a typical NMOS transistor with improved STI and STI sidewall STI pocket implants.

[0005]

In general, STI edges usually produce several non-ideal conditions, such as: (1) Boron segregation on the STI side wall leads to P-well dosage loss; (2) The STI induced stress affects the stability of the threshold voltage (Vt); and (3) some interface traps or misalignments increase the leakage current. These conditions can cause undesirable subcritical properties and higher leakage current problems. Although it is often the case that a STI pocket implant is often applied to the "weakness" of the structure (as circled in Figure 2) to improve local well doping at the STI sidewall To suppress double-hump leakage (curve Process-3), the structure still has shortcomings, including: (1) it will reduce the junction breakdown of the high-voltage NMOS because of the junction (lightly doped NM) More P-well doping will be seen at the STI edge, and (2) a narrow narrow channel width effect will result when the channel width is reduced. Therefore, STI sidewall pocket doping still affects channel doping and threshold voltage control.

[0006]

The present invention relates to an active component and a high voltage semiconductor component using the same. The active components of the embodiments are designed to well support high voltage operation and avoid STI edge issues encountered with conventional semiconductor components. The high voltage semiconductor component of the active element of the application embodiment is characterized by low leakage current and high breakdown voltage.

【0007】

According to an embodiment, a high voltage semiconductor device is provided, including a substrate, a first well having a first conductive state and extending downward from a surface of the substrate, a plurality of active components being formed on the substrate at a distance from each other, and adjacent The active components are electrically insulated from one another by an insulator. An active component includes a diffusion region (active region) doped with impurities in the first conductive state and extending downward from a surface of the first well, a ring gate formed in the diffusion region, and There is a light doping region of a second conductive state, and the lightly doped region extends downward from one surface of the diffusion region. Among them, the lightly doped region is offset from one edge of the insulator.

[0008]

According to an embodiment, a high voltage semiconductor device is provided, including a substrate, a first well having a first conductive state and extending downward from a surface of the substrate, a plurality of active components being formed on the substrate at a distance from each other, and The adjacent active components are electrically insulated from each other by an insulator. An active component includes a diffusion region (active region) doped with impurities in the first conductive state and extending downward from a surface of the first well, a gate formed in the diffusion region, and a lightly doped one of the second conductive states In the impurity region, the lightly doped region extends downward from one surface of the diffusion region. Wherein, the lightly doped regions are correspondingly located in the diffusion region.

【0009】

According to an embodiment, an active device is provided, including a diffusion region doped with impurities in a first conductive state and formed in a substrate, a ring-shaped gate formed in the diffusion region and having a lightly doped one of the second conductive states The impurity region extends downward from a surface of one of the diffusion regions, and a first contact having a second conductivity state is formed in the lightly doped region and offset from an edge of the lightly doped region, and has a second conductive state A second contact is formed in the diffusion region, and the second contact is located in a first region surrounded by the ring-shaped gate, wherein the second contact is offset from the ring-shaped gate. Wherein, the lightly doped region deviates from one edge of the diffusion region.

[0010]

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.

[0039]

10, 20‧‧‧ active components
12. PW‧‧‧ first well
111‧‧‧First contact area
113‧‧‧Second contact area
115‧‧‧gate contacts
135‧‧‧ channel
21‧‧‧ (ring type) gate
21-a‧‧‧First area
21-b‧‧‧Second area
22‧‧‧Lightly doped areas
24‧‧‧First contact
26‧‧‧second junction
27‧‧‧gate contacts
STI, 30‧‧‧Insulators
301‧‧‧The edge of insulation
Sub‧‧‧Substrate
DIF‧‧‧Diffusion area
PG‧‧‧ polysilicon gate
GOX‧‧‧ gate oxide layer
Lg‧‧‧ channel length
D1‧‧‧Distance of lightly doped areas from the edge of the insulation
D2‧‧‧The distance at which the first junction deviates from the gate
D3‧‧‧The distance at which the first junction deviates from the edge of the lightly doped area
W‧‧‧Width of the first area
W2‧‧‧ Length of the first area
I _corner ‧‧‧ corner current
Ds‧‧‧ Minimum distance of adjacent active components

[0011]

Figure 1 illustrates a conventional layout of a semiconductor component.
2 is a schematic cross-sectional view showing a polysilicon gate of a conventional semiconductor device and insulators on both sides.
Figure 3A is a typical low-voltage (LV) NMOS transistor of the I _D -V _G characteristic curve, wherein the gate oxide GOX layer having a thickness of 70Å, W / Lg = 0.6μm /0.4μm , and a drain of the plurality of curve The pole bias (V _D ) is measured at 0.1V.
Figure 3B is an I _D -V _G characteristic curve of a typical high voltage (HV) NMOS transistor in which the gate oxide layer GOX has a thickness of 370 Å, W/Lg = 10 μm / 1.6 μm, and the curves are in a bungee The bias voltage (V _D ) was measured at 0.1V.
FIG. 4 is a schematic diagram of a semiconductor device layout and an active device according to an embodiment of the present disclosure.
FIG. 5 is a schematic diagram showing a drain current between a source and a drain of an active device according to an embodiment of the present disclosure.
FIG. 6 is a graph showing I _D -V _G characteristics of a ring-type gate transistor and a conventional MOSFET transistor layout according to an embodiment of the present disclosure.
FIG. 7 is an I _D -V _G characteristic curve of a MOSFET transistor layout according to an embodiment of the present disclosure. Figure 7 clearly shows that there is no bimodal leakage current generation, and the experimental values are ideally coincident with the simulation curves of the theoretical model. Furthermore, only a very low leakage current value was observed when Vg was lower than 0.7V.
Figure 8 shows the X-Decoder (XDEC) circuit design of a NAND flash memory.

[0012]

In an embodiment of the disclosure, an active component and a high voltage semiconductor component are used. The design of the active device of the embodiment can be used to adequately support a high operating voltage by forming a light doping region (eg, N-) in an active area (ie, a diffusion region), wherein The lightly doped regions are offset from an edge of an insulator (e.g., STI) used to electrically isolate adjacent active devices. Therefore, the semiconductor element of the application embodiment can avoid electrical deterioration of the active device due to the edge effect of the insulator. Embodiments of the present disclosure are applicable to many different aspects of high voltage (HV) semiconductor components, such as high voltage semiconductor components that can support operating voltages up to about 30V. The disclosure is not limited to an application aspect. The following embodiments are presented in conjunction with the drawings to explain in detail a new arrangement of one of the active components and a high voltage semiconductor component proposed by the present disclosure. However, the disclosure is not limited to this. The descriptions of the embodiments, such as the details of the details, the dimensions of the elements and the choice of materials, etc., are for illustrative purposes only and are not intended to limit the scope of the disclosure.

[0013]

Furthermore, the disclosure does not show all possible embodiments. The structure and process may be modified and modified to meet the needs of the actual application without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

[0014]

FIG. 4 is a schematic diagram of a semiconductor device layout and an active device according to an embodiment of the present disclosure. In one embodiment, a semiconductor component (eg, a high voltage N-type metal oxide semiconductor, HVNMOS) includes a substrate Sub having a first well PW of a first conductive state (eg, P-type) and a plurality of active components 20 spaced apart from each other The ground is formed in the first well PW of the substrate Sub. In an embodiment, two adjacent active devices 20 are electrically insulated from each other by an insulator 20 such as shallow trench isolation (STI). As shown in FIG. 4, one of the active devices 20 includes a diffusion region DIF (also referred to as an active region AA of the active device 20) doped with impurities of the first conductive state (eg, P-type) and from the first well PW. A surface extends downwardly, a gate 21 is formed in the diffusion region DIF, and a light doping region (such as NM) 22 has a second conductive state (for example, N-type), and is lightly doped. The impurity region 22 extends downward from a surface of one of the diffusion regions DIF. According to an embodiment, the lightly doped region 22 is offset from one edge 301 of the insulator 30 by a distance (i.e. D1) to avoid the STI edge issue. In one embodiment, a boundary of the diffusion region DIF corresponds to the edge 301 of the insulator 30.

[0015]

In one embodiment, the gate 21 is, for example, a ring structure and may also be referred to as a ring gate. As shown in FIG. 4, the ring-shaped gate 21 formed in the diffusion region DIF is correspondingly located within the lightly doped region 22 and offset from the lightly doped region 22. According to an embodiment, the ring-shaped gate 21 is made of, for example, polysilicon.

[0016]

Furthermore, the active component 20 further includes a first contact 24 (eg, a source contact) having a second conductive state (eg, an N-type), and the first contact 24 is formed in the lightly doped region 22 The inside is offset from the ring gate 21 by a distance (ie D2). In one embodiment, the first contact 24 is located between the ring gate 21 and the edge of the lightly doped region 22, and the first contact 24 that is offset from the ring gate 21 is also offset from the lightly doped region 22. The edge (ie D3), as shown in Figure 4.

[0017]

In an embodiment, the active device 20 has a first region 21-a surrounded by a ring gate 21 and a second region 21-b outside the ring gate 21. . And the second region 21-b refers to a region between the lightly doped region 22 and the ring-shaped gate 21.

[0018]

In an embodiment, the active component further includes a second contact (eg, a drain contact) 26 having a second conductive state (eg, an N-type), and the second contact 26 is formed in the diffusion region DIF. And the second contact 26 is located in the first region 21-a surrounded by the ring gate 21. According to an embodiment, the second contact 26 in the first region 21-a is offset from the toroidal gate 21.

[0019]

In one embodiment, the active component includes four first contacts 24 having a second conductive state formed in the second region 21-b. As shown in FIG. 4, the four first contacts 24 may be distributed along the sides of the ring gate 21 and offset from the ring gate 21. For example, if the gate 21 is a square ring shape as shown in FIG. 4, each of the first contacts 24 may respectively correspond to one side of the ring-shaped gate 21, and its position is offset from the ring-shaped gate 21 Distance (ie D2).

[0020]

Furthermore, the active component 20 further includes a gate contact 27, which is correspondingly located at the toroidal gate 21. However, the gate contact 27 is not limited to the position shown in FIG. 4, and may be formed at other positions as long as the gate contact 27 can be electrically connected to the gate 21.

[0021]

In the manufacturing process, after the openings corresponding to the first region 21-a and the second region 21-b are formed, light is formed under the gate 21 by doping a small amount of second conductive state (such as N-) impurities. Doped region 22 (lightly doped region 22 ranges as shown in FIG. 4). Next, the first contact 24 and the second contact 26 are defined, for example, spacers (such as oxides) of appropriate size are formed at the openings corresponding to the first regions 21-a to define the second contacts 26. After the positions of the first contact 24, the second contact 26 and the gate contact 27 are determined, a high concentration of the second conductive state impurity (such as N+) is doped in the plug implant manner. Click below. However, the disclosure is not limited to this manufacturing method. The steps as described above are for illustrative purposes only and may be appropriately adjusted or varied as needed for the actual application conditions.

[0022]

According to the active device 20 of the above embodiment, the ring-shaped gate 21 is located in the lightly doped region 22, and the lightly doped region 22 is located in the diffusion region DIF. The lightly doped region 22 of the active device 20 is offset from one edge 301 of the insulator 30 by a distance D1, thus solving the problem of STI edge effects. Moreover, the first contact 24 of the active device 20 located in the lightly doped region 22 is offset from the toroidal gate 21, thereby reducing gate induced drain leakage (GIDL). The collapse effect.

[0023]

The first contact 24 located in the second region 21-b and the second contact 26 located in the first region 21-a are, for example, the source and the drain of the active device 20, respectively. Furthermore, the ring-shaped gate 21 of the active device 20 has a channel length (Lg), and the channel length corresponds to one of the widths of the ring-shaped gate 21. Furthermore, the first contact 24 having the second conductive state is offset from the channel length (Lg) of the toroidal gate 21. In one embodiment, the channel length (Lg) of the ring-shaped gate 21 is, for example, about 1.6 μm. Sufficient channel length (Lg) can support high voltage operation of the semiconductor component, avoiding charge-punch under high voltage operation and damaging the active component 20.

[0024]

In an embodiment, the first region 21-a has a width W along a first direction (eg, the x-direction) and a length W2 along a second direction (eg, the y-direction). The width W and the length W2 may be equal or unequal, and the disclosure is not limited thereto. In one embodiment, the width W is equal to the length W2 and the effective channel width is about 4W. In one embodiment, both the width W and the length W2 are about 1.7 [mu]m and the effective channel width is about 6.8 [mu]m (= 4 W). The active element 20 of the embodiment has sufficient channel width to meet the requirements of the central drain contact and the drain offset distance.

[0025]

FIG. 5 is a schematic diagram showing a drain current between a source and a drain of an active device according to an embodiment of the present disclosure. The same components in the fifth embodiment and the fourth embodiment are denoted by the same reference numerals to clearly illustrate the embodiments. The structural details of the embodiments are as described above, and are not described herein again. Please refer to Figure 4 and Figure 5 at the same time.

[0026]

As shown in FIG. 5, the drain current flows from the first contact 24 (eg, the source contact) toward the second contact 26 (eg, the drain contact). According to the design of the embodiment, there is no STI edge present in the active device 20 (e.g., a transistor), so the components of the embodiment have no problem of STI edge effect and no double-hump leakage problem. _Long corner current of the flow path, I _corner , whose effective channel length is equal to Therefore, the corner current does not cause leakage current. In an embodiment, the lightly doped region 22 (ie, the lightly doped shallow junction) is offset from the edge 301 of the insulator 30 to reduce the impact of the lightly doped region 22 on the STI edge collapse.

[0027]

FIG. 6 is a graph showing I _D -V _G characteristics of a ring-type gate transistor and a conventional MOSFET transistor layout according to an embodiment of the present disclosure. Curve (C) representative of the layout of a conventional MOSFET transistor I _D -V _G characteristic curve (RG) on behalf of embodiments with embodiments of ring gate transistors of the I _D -V _G characteristics curve. Since the lightly doped region 22 in the embodiment is away from the STI edge and away from the "sidewall STI pocket implant" applied at the "weak point" of the STI sidewall, the ring-shaped gate transistor of the embodiment can be effectively improved. Crash voltage.

[0028]

FIG. 7 is an I _D -V _G characteristic curve of a MOSFET transistor layout according to an embodiment of the present disclosure. Figure 7 clearly shows that there is no bimodal leakage current generation, and the experimental values are ideally coincident with the simulation curves of the theoretical model. Furthermore, only a very low leakage current value was observed when Vg was lower than 0.7V.

[0029]

Figure 8 shows the X-Decoder (XDEC) circuit design of a NAND flash memory. In the X-decoder design of NAND flash memory, elements (1) and (2) in Figure 8 are subjected to the strongest junction bias, so the two components are critical to the overall design. . For component (1), this depletion-mode HVNMOS must be able to withstand the Vpp high voltage of the junction. For component (2), this NMOS must be able to withstand the Vdd high voltage of the junction. The active device of the embodiment has the characteristics of reducing the collapse caused by GIDL (gate induced drain leakage) and increasing the component breakdown voltage, so the component design of the embodiment is particularly suitable for application as in the eighth The components (1) and (2) shown in the figure are designed such that the components (1) and (2) have a strong structure without problems and variations caused by STI edges. Although the structures of components (1) and (2) may occupy some space of the X-decoder of the NAND flash memory, only one component (1) is required in the circuit block as shown in FIG. And (2), therefore, the magnitude of the increase in layout area by these two components is within the tolerable range.

[0030]

The following is a design rule for a high voltage NMOS device of a NAND flash memory circuit (which can support a high voltage operation of about 31 V) without STI edge effects. However, the relevant parameter values set forth below are for illustrative purposes only and are not intended to limit the scope of protection. Please also refer to FIG. 4, in which an active component 20 has a ring gate design.

[0031]

In one of the high voltage semiconductor devices of the embodiment, the lightly doped region 22 of the active device is offset from the edge 301 of the insulator 30 by a distance D1, and the distance D1 is in the range of about 0.1 μm to about 0.4 μm. In one embodiment, the lightly doped region 22 of the active device is offset from the edge 301 of the insulator 30 by a distance D1 of about 0.2 μm.

[0032]

In a high voltage semiconductor device of one embodiment, a first contact 24 (eg, N+) is formed in the lightly doped region 22 and offset from the toroidal gate (eg, Poly) by a distance D2, and the distance D2 is A range of about 0.4 μm to about 1.2 μm can reduce the collapse caused by GIDL (gate induced drain leakage). In one embodiment, the first contact 24 of the active component is offset from the annular gate 21 by a distance D2 of about 0.8 μm.

[0033]

In one of the high voltage semiconductor devices of the embodiment, the first contact 24 is offset from the lightly doped region 22 by a distance D3 of about 0.2 μm. Furthermore, in one embodiment, the minimum dimension of the contacts, such as the minimum size of the second contact 26 (ex: drain) and/or the gate contact 27, has a width of about 0.1 μm and an area of, for example, about 0.1 μm. × 0.1 μm.

[0034]

In a high voltage semiconductor device of an embodiment, the channel length (Lg) may be from about 1.2 μm to about 5 μm to support high voltage operation. In an embodiment of a HVNMOS that can support a maximum operating voltage of 31V, the channel length (Lg) is, for example, about 1.6 μm. For depletion-mode HVNMOS (buried channel elements), the channel length (Lg) can be amplified to approximately 4 μm.

[0035]

Further, in the high voltage semiconductor device of one embodiment, the width W of the ring type gate 21 (assuming W = W2) is in the range of about 1.5 μm to about 3 μm. In one embodiment, the ring gate 21 has a width W of about 1.7 [mu]m. In addition, the spatial minimum distance Ds between the two adjacent active elements 20 is greater than about 0.6 μm to achieve field insulation; for example, the minimum distance Ds between the two active regions of the HVNMOS (ie, the two diffusion regions DIF) is about 0.8. Mm. Furthermore, the pitch of the active device 20 is, for example, about 0.8 μm, which is suitable for use in a design of a NAND flash memory having a block length of about 8 μm.

[0036]

Although the first well has a P-type conductive state and the lightly doped region 22 has an N-conductive state in the above embodiment, the disclosure is not limited thereto. For a PMOS process (although it has no problem of collapse), the present disclosure can also be applied as long as the doped conductive state of the well and the junction is reversed. For example, the P-type well of the NMOS device and the N-type lightly doped region 22 may be replaced by an N-type well and a P-type lightly doped region in the PMOS element.

[0037]

In summary, the high voltage semiconductor component of the active device of the embodiment is formed by forming the lightly doped region 22 in the active region (ie, the diffusion region DIF), and the lightly doped region 22 is deviated from the insulator (such as STI). ) is on the edge and can support high voltage operation well. In one embodiment, the gate 21 of the active device can be designed as a ring, and the contacts (such as the first contact 24) formed in the lightly doped region 22 and outside the gate 21 are offset from the gate 21 ( Ring-type gates, thus reducing the collapse caused by GIDL. The high voltage semiconductor component of the active component of the embodiment successfully solves the problem that the conventional semiconductor component encounters an STI edge effect, such as double-hump subthreshold leakage and breakdown voltage drop, and the like. Furthermore, the results of the simulation experiments (as shown in Fig. 7) also demonstrate that the active components of the embodiments applicable to high voltage semiconductor components also have the advantage of extremely low leakage current.

[0038]

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20‧‧‧Active components

21‧‧‧ (ring type) gate

21-a‧‧‧First area

22‧‧‧Lightly doped areas

24‧‧‧First contact

27‧‧‧gate contacts

301‧‧‧The edge of insulation

W2‧‧‧ Length of the first area

D1‧‧‧Distance of lightly doped areas from the edge of the insulation

D2‧‧‧The distance at which the first junction deviates from the gate

D3‧‧‧The distance at which the first junction deviates from the edge of the lightly doped area

Ds‧‧‧ Minimum distance of adjacent active components

PW‧‧‧First Well

Sub‧‧‧Substrate

21-b‧‧‧Second area

DIF‧‧‧Diffusion area

26‧‧‧second junction

30‧‧‧Insulators

Lg‧‧‧ channel length

W‧‧‧Width of the first area

Claims (10)

[Item 1] A high voltage semiconductor component comprising:
a substrate;
a first well has a first conductive state and extends downward from a surface of the substrate;
A plurality of active components are formed on the substrate at a distance from each other, and the adjacent active components are electrically insulated from each other by an insulator, and one of the active components includes:
Diffusion region doping the impurity of the first conductive state and extending downward from a surface of the first well;
a ring gate is formed in the diffusion region; and a light doping region has a second conductive state, the lightly doped region extending downward from a surface of the diffusion region, and The lightly doped region is offset from one of the edges of the insulator. [Item 2] The high voltage semiconductor component of claim 1, wherein the active component further comprises a first contact having the second conductive state, the first contact being formed in the lightly doped Within the impurity region and deviate from the ring gate. [Item 3] The high voltage semiconductor device of claim 2, wherein the first contact is located between the ring gate and one of the lightly doped regions, and the first contact is offset from the ring shape The gate is offset from the edge of the lightly doped region. [Item 4] The high voltage semiconductor device of claim 2, wherein the active device further comprises a second contact having the second conductive state, the second contact being formed in the diffusion region And the second contact is located in a first region surrounded by the ring-shaped gate, wherein the second contact is offset from the ring-shaped gate. [Item 5] The high voltage semiconductor device of claim 1, wherein the lightly doped region and the ring gate define a second region, wherein the active component further comprises the first region Four first contacts of the two conductive states are formed in the second region, and four of the first contacts are distributed along a side of the ring-shaped gate and deviate from the ring-shaped gate. [Item 6] The high voltage semiconductor device of claim 1, wherein the lightly doped region is correspondingly located in the diffusion region, and the ring gate is correspondingly located in the lightly doped region. [Item 7] The high voltage semiconductor device of claim 1, wherein the ring gate of the active device has a channel length (Lg) along a width thereof, and the active component further comprises There is a first contact of the second conductive state, the first contact being offset from the length of the channel of the ring-shaped gate. [Item 8] A high voltage semiconductor component comprising:
a substrate;
a first well has a first conductive state and extends downward from a surface of the substrate;
A plurality of active components are formed on the substrate at a distance from each other, and the adjacent active components are electrically insulated from each other by an insulator, and one of the active components includes:
Diffusion region doping the impurity of the first conductive state and extending downward from a surface of the first well;
a gate formed in the diffusion region; and a light doping region having a second conductive state, the lightly doped region extending downward from a surface of the diffusion region, and the light The doped regions are correspondingly located within the diffusion region. [Item 9] The high voltage semiconductor device of claim 8, wherein the lightly doped region is offset from an edge of the insulator. [Item 10] The high voltage semiconductor device of claim 9, wherein the gate of the active device is a ring gate, and the active device further comprises:
Having a first contact of the second conductive state, the first contact being formed in the lightly doped region and between the annular gate and one of the edges of the lightly doped region, and The first contact is offset from the ring-shaped gate and offset from the edge of the lightly doped region; and has a second contact of the second conductive state, the second contact is formed And a first region surrounded by the ring-shaped gate in the diffusion region, wherein the second contact is offset from the ring-shaped gate.