TW201626464A - Field-effect transistor - Google Patents

Abstract

A field-effect transistor (100) is provided with a channel (30c) formed of a semiconductor nano wire (30). A source region (30s) and a drain region (30d) are formed adjacent to the channel (30c), and a gate electrode (40) is provided above the channel. On the main surface of the semiconductor nano wire (30), a mask layer (50) is provided, said mask layer containing dopant atoms to be a donor or an acceptor. Though the dopant atoms are ion-implanted into the mask layer (50) on a side wall portion of the gate electrode (40) as well, the implanted ions stay at an upper portion, and are not implanted as far as to a portion in contact with the main surface of the semiconductor nano wire (30). Consequently, a mask layer portion formed with a thickness W on the side wall of the gate electrode (40) does not function as a diffusion source of the dopant.

Description

Field effect transistor

The present invention relates to a field effect transistor having a channel formed by a semiconductor material portion such as a semiconductor nanowire, and more specifically, has a variation in suppressing a threshold voltage and can sufficiently obtain an ON current. The field-effect transistor of the source-dippole structure.

When forming a field effect transistor using a semiconductor nanowire-like semiconductor material portion, it is necessary to dope the source region and the drain region, and directly apply the dopant to the gate electrode as a mask. At the time of ion implantation, even if heat treatment is performed, crystal defects caused by ion implantation remain on the transistor body.

When the source region and the drain region are formed by doping by the solid phase diffusion method, the defect remaining as described above can be avoided, but the dopant invades into the channel region due to diffusion, and the threshold voltage of the transistor is present. The problem of offset. Further, when the dopant concentration is lowered to suppress the threshold voltage shift, a sufficient on-current cannot be obtained.

The present inventors have aimed to suppress the threshold deviation of the field effect transistor, and have reviewed a technique of disposing a spacer on the sidewall of the gate electrode to ionize the dopant before ion implantation. Will not be implanted into the semiconductor region directly under the sidewall spacer (Uzun, etc.) : Non-Patent Document 1). As a result, by providing such a sidewall spacer, it is difficult for the dopant to intrude into the channel region, and as a result, it can be confirmed that the variation between the OFF current and the threshold voltage can be remarkably suppressed.

[Previous Technical Literature] [Non-patent literature]

[Non-Patent Document 1] M. Uematsu et al., "Simulation of the Effect of Arsenic Discrete Distribution on Device Characteristics in Silicon Nanowire Transistors" IEDM12-709 (2012)

However, even if a spacer is provided on the sidewall of the gate electrode as disclosed in Non-Patent Document 1, it is not possible to sufficiently suppress the intrusion of the dopant into the channel region due to heat treatment or the like after ion implantation. Moreover, since the self-dopant has an "outflow" of electrons, the influence on the channel is not only the intrusion of the above dopant but also the "outflow length" of the electron. For example, when the semiconductor nanowire is germanium crystal and the dopant is arsenic, the "outflow length" of electrons is about 2 nm.

Furthermore, even if there is such an intrusion of such a dopant and an "outflow" of electrons, it does not become a problem when the gate length is long. However, with the miniaturization of the field effect transistor, when the gate length becomes shorter, the intrusion of the dopant and the "outflow" of the electron greatly affect the channel region, resulting in a deviation of the threshold voltage. Therefore, it is required to further suppress the intrusion of the dopant into the channel region while further suppressing A channel forming technique (source/drain formation technique) that takes into account the "outflow length" of electrons. Further, there is a need to avoid the problem that crystal defects caused by ion implantation remain on the transistor body.

The present invention has been made in view of the above problems, and an object thereof is to provide a source-drain structure capable of suppressing a threshold voltage deviation while sufficiently obtaining an on-current, without causing ion implantation onto a transistor body. The resulting crystal defect is a field effect transistor having a channel formed by a semiconductor material portion of a semiconductor nanowire.

In order to solve the above problems, a field effect transistor according to a first aspect of the present invention is characterized in that it has a channel formed of a semiconductor material portion having a thickness H (nm), a source region formed adjacent to the channel, and a gate-effect region, a field effect transistor disposed in a gate region above the channel, wherein a gate length (L _g ) of the gate region is 4 nm or more and 10 nm or less, and a number of doping atoms in a central region of the channel is 1 the following.

Further, a field effect transistor according to a second aspect of the present invention is characterized in that it has a channel formed of a semiconductor material portion having a thickness H (nm), a source region and a drain region formed adjacent to the channel. a field effect transistor disposed in a gate region above the channel, wherein a mask layer is disposed on the main surface of the semiconductor material portion, and includes a mask of dopant atoms belonging to the donor or the acceptor a layer is a mask layer having a sidewall thickness of W (nm) disposed on a gate electrode of the gate region, the mask layer covering a main portion of the semiconductor material portion in which the source region and the drain region are formed In the surface portion, the gate length (L _g ) of the gate region is 4 nm or more and 10 nm or less, and the thickness W (nm) of the mask layer on the sidewall of the gate electrode is in [3H - 2] / 7 + [10- The range of L _g ]/2≦W≦[3H+19]/7.

In the field effect transistor of the second aspect described above, it is preferable that the number of doping atoms in the central portion of the channel is 1 or less.

In the field effect transistor of the present invention, it is preferable that the dopant concentration in the 2 nm region from the end portion of the channel toward the source region and the drain region side is 5 × 10 ¹⁹ cm ^-3 or more.

The semiconductor material portion includes any of bismuth, antimony, and III-V compound semiconductors.

For example, the semiconductor material portion includes tantalum, and the mask layer is a tantalum oxide film or a vaporized film.

At this time, the dopant is any one of, for example, phosphorus, antimony, arsenic, boron, aluminum, indium, or gallium.

Further, for example, the semiconductor material portion includes tantalum, and the mask layer is a tantalum oxide film or a vaporized film.

At this time, the dopant is also any one of phosphorus, antimony, arsenic, boron, aluminum, indium, and gallium.

Further, for example, the semiconductor material portion includes a III-V compound semiconductor, and the mask layer is a tantalum oxide film.

At this time, the dopant is any one of zinc, bismuth, and antimony.

In some aspects, the semiconductor material portion is any one of a 矽-nano line, a 锗-nano line, and a III-V compound semiconductor nanowire.

The method for producing a field effect transistor of the present invention is characterized in that it is a method for producing a field effect transistor having a channel formed of a semiconductor material portion having a thickness H (nm), which is provided with a gate length (Lg) a step of forming a gate electrode over the channel in a manner of 4 nm or more and 10 nm or less; a step of forming a mask layer covering the gate electrode and forming a source region and a region adjacent to the channel a mask layer on a main surface portion of the semiconductor material portion of the polar region is a mask layer having a sidewall thickness of the gate electrode of W (nm); and implanting a dopant atom belonging to the donor or the acceptor to the mask layer a step of diffusing the dopant atoms implanted into the mask layer to the source region and the drain region; setting the thickness W (nm) of the mask layer on the sidewall of the gate electrode to [3H- 2]/7+[10-L _g ]/2≦W≦[3H+19]/7 range.

According to the present invention, there is provided a field effect transistor which is provided with a mask layer containing a dopant atom and a gate electrode having a thickness W of W on a main surface of a semiconductor nanowire-like semiconductor material portion. The number of doping atoms in the central region of the channel is 1 or less. As a result, the threshold voltage deviation can be suppressed, and the on-current can be sufficiently obtained.

10‧‧‧矽 substrate

20‧‧‧Insulator film

30‧‧‧Semiconductor nanowire

30c‧‧‧ channel

30d‧‧‧Bungee area

30s‧‧‧ source area

40‧‧‧gate electrode

40g‧‧‧ gate area

45‧‧‧Gate oxide film

50‧‧‧ mask layer

100‧‧‧ field effect transistor

H‧‧‧thickness

L _g ‧‧‧ gate length

t _d ‧‧‧Stacked Si oxide film thickness

t _g ‧‧‧gate electrode height

t _ox ‧‧‧ gate oxide film thickness

W‧‧‧thickness

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view conceptually illustrating the construction of a field effect transistor of the present invention.

Fig. 2 is a view showing a simulation result of an appropriate range of the thickness W (nm) of the mask layer for determining the sidewall of the gate electrode in the field effect transistor of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view conceptually illustrating the construction of a field effect transistor of the present invention. In addition, in this figure, in order to simplify the description, a structure having one gate electrode (single gate) is illustrated, but is not limited thereto. In such a form, it may be a transistor of a double gate or a triple gate structure, or a transistor which is constructed as a gate around the channel.

The field effect transistor 100 illustrated in Fig. 1 is provided with a channel 30c formed by a semiconductor nanowire 30. Adjoining this passage 30c, forming a source region 30s and drain region 30d, above the channel, a gate oxide film 45 interposed therebetween, is provided with a gate electrode 40, below the gate electrode to the gate length L _g of Gate region 40g. In this example, the semiconductor material portion is a semiconductor nanowire. However, the semiconductor material portion constituting the semiconductor transistor of the present invention is not limited to such an aspect, as long as it is a semiconductor material capable of forming a channel. You can do it.

The semiconductor nanowire 30 is, for example, a 矽-nano line obtained by processing a semiconductor layer of an SOI substrate, or a tantalum oxide film (SiO formed on a ruthenium substrate 10 including an n-type or p-type conductivity type). ₂ ) The tantalum-nano line provided on the insulator film 20. Further, the semiconductor nanowire is not limited to the 矽-nano line, and may be a III-nano line and a III-V compound semiconductor nanowire such as GaAs.

The semiconductor nanowire 30 is a thin linear crystal having a large ratio of length to width (aspect ratio), and its thickness H (nm) is, for example, about 10 nm. Such a semiconductor nanowire 30 can be formed by processing a semiconductor layer on an insulator, or by a chemical vapor deposition method (CVD method) or a plasma enhanced chemical vapor deposition method (PECVD method). When the semiconductor nanowire 30 is a 矽-nano line, an SOI substrate can be used to form a semiconductor nanowire, or a silane (SiH ₄ ) or a silicon tetrachloride (SiCl ₄ ) gas can be formed as a source gas. Just fine.

On the main surface of the semiconductor nanowire 30, the inclusion is included A mask layer 50 of dopant atoms belonging to a donor or acceptor. The mask layer 50 is, for example, including a tantalum oxide film, and is formed in such a manner that the thickness of the sidewall of the gate electrode 40 provided over the gate region 40g becomes W (nm) while covering the source region 30s and the drain region. The main surface portion of the 30d semiconductor nanowire 30.

The mask layer 50 is, for example, after forming a tantalum oxide film, in the semiconductor nanowire 30, ion-implanted with a dopant atom belonging to a donor or a acceptor.

In the case where the semiconductor nanowire 30 is a 矽-nano line, the mask layer 50 may be a layer including a bismuth film as a doping atom included in the mask layer 50 in addition to the ruthenium oxide film. Phosphorus, antimony, arsenic, boron, aluminum, indium, and gallium are exemplified.

The semiconductor material portion is not limited to ruthenium. In the aspect illustrated in Fig. 1, the semiconductor nanowire 30 may be a 锗-nano line. At this time, the mask layer 50 may be a layer including a tantalum oxide film and a vaporized film, and examples of the dopant atoms contained in the mask layer 50 include phosphorus, germanium, arsenic, boron, aluminum, indium, and gallium.

Further, the semiconductor material portion is not limited to tantalum or niobium, and the semiconductor nanowire 30 may be a III-V compound semiconductor nanowire. At this time, the mask layer 50 can be, for example, a layer including a tantalum oxide film, and examples of the dopant atoms contained in the mask layer 50 include zinc, tantalum, and niobium.

The mask layer 50 functions as a diffusion source for the dopants of the source region 30s and the drain region 30d when the field effect transistor of the present invention is fabricated.

The conventional method uses the following method: for example, for the 矽-nano line When the source region and the drain region are doped, the gate electrode is used as a mask, and the dopant is directly ion-implanted into the 矽-nano line, and then the implanted ion is electrically activated by heat treatment. And become a donor or acceptor. However, in such a method, there is a problem that crystal defects are caused by ion implantation on the bulk of the transistor, and defects are left after the heat treatment to lower the crystal characteristics.

In order to avoid this problem, when the so-called solid phase diffusion method is employed, the dopant still diffuses into the channel region of the transistor, and there is a problem that the threshold voltage of the transistor is shifted. On the other hand, when the dopant concentration is lowered to suppress the threshold voltage, a sufficient on-current cannot be obtained.

Accordingly, in the present invention, the mask layer 50 is formed in a region including the gate electrode before the ion implantation, whereby ion implantation is performed over the mask layer 50. Since the damage at the time of ion implantation can be absorbed by the mask layer 50, damage to the semiconductor nanowire 30 can be avoided, and crystal defects are not caused, so that heat treatment for recovering damage is not required. Further, the mask layer 50 functions as a diffusion source of the dopant, and the degree of doping can be easily controlled by the amount of ion implantation (doping amount).

In the mask layer 50 of the side wall portion of the gate electrode 40, the dopant may be ion-implanted, and the implanted ions may remain in the upper portion. That is, it is not injected into the portion that contacts the main surface of the semiconductor nanowire 30. Therefore, the portion of the mask layer having a thickness W (nm) formed on the sidewall of the gate electrode 40 does not act as a diffusion source of the dopant. As a result, by appropriately designing the thickness W (nm), the intrusion of the dopant toward the channel region 30c can be avoided, the variation in the threshold voltage can be reduced, and a sufficient on-current can be obtained.

Fig. 2 is a view showing a simulation result of an appropriate range for determining the thickness W (nm) of the mask layer 50 on the side wall of the gate electrode 40 in the field effect transistor of the above configuration. The horizontal axis is the thickness H (nm) of the semiconductor nanowire, and the vertical axis is the thickness W (nm) of the mask layer 50 on the sidewall of the gate electrode 40.

The conditions in this simulation are shown in Table 1. Here, the tantalum oxide film is deposited on the entire surface of the gate electrode including the nanowire MOS field effect transistor (10 nm square or less, length 30 nm). After ion implantation of arsenic, the dopant can be diffused by heat treatment at 1000 °C.

Here, the acceleration voltage at the time of ion implantation was set to 0.5 keV in order to inject arsenic into the deposited Si oxide film having a tg of 3 nm. Further, after ion implantation, the time for diffusing the dopant is set to an optimum value in accordance with the thickness H (nm) of the semiconductor nanowire, and is used for doping the SD (source/drain) portion. The shortest time of uniformity is specifically 0.25 seconds, 0.5 seconds, 1 second, 2.5 seconds, and 5 seconds in response to H = 2 nm, 3 nm, 5 nm, 7.5 nm, and 10 nm.

First, as for the upper limit of the thickness W (nm), in the 2 nm from the end of the channel to the source region and the drain region side, when the concentration of the dopant (here, arsenic) is 5 × 10 ¹⁹ cm ^- when the above ^three conditions to evaluate, on a thickness W (nm) value W _u (nm) lines become [3H + 19] / 7. When the thickness is equal to or higher than this, a sufficient on current cannot be obtained.

Further, in the case of 2 nm from the end of the channel, the dopant concentration is set to be 5 × 10 ¹⁹ cm ^-3 or more because a sufficient on-current cannot be obtained at a dopant concentration lower than the concentration. Caused.

On the other hand, in the case where the lower limit of the thickness W (nm) is evaluated under the condition that the dopant (here, arsenic) enters the center of the channel to be 1 or less, the thickness W (nm) is lower than the limit W. ₁ (nm) is [3H-2]/7+[10-L _g ]/2. When the thickness is below this thickness, the deviation of the threshold becomes large.

Therefore, in the present invention, the thickness W (nm) of the mask layer 50 of the sidewall of the gate electrode 40 is set to [3H-2]/7+[10-L _g ]/2≦W≦[3H+19 ] / 7 range. Further, as can be seen from this relation, the upper limit value W _u (nm) does not depend on the gate length L _g , and the lower limit value W ₁ (nm) depends on the gate length L _g .

In the field effect transistor of the present invention, in order to set the number of doping atoms in the central region of the channel to 1 or less, in other words, in order to make the number of doping atoms in the central region of the channel not more than 2, preferably the gate region The gate length L _g is 4 nm or more and 10 nm or less. In addition, the "central region" of the channel herein means an area in which the geometric center position of the channel is regarded as the center of ±1 nm. As described above, for example, when an arsenic atom as a dopant exists in the ruthenium crystal, the "outflow length" of electrons from the dopant is about 2 nm (±1 nm).

As described above, the field effect transistor system of the present invention comprises: a channel formed by a semiconductor nanowire having a thickness H (nm), a source region and a drain region formed adjacent to the channel, and disposed in the channel The upper gate region also has a mask layer disposed on the main surface of the semiconductor nanowire, and a mask layer containing doping atoms belonging to the donor or the acceptor is disposed in the gate region a sidewall of the gate electrode having a thickness of W (nm), the mask layer covering a main surface portion of the semiconductor nanowire formed with the source region and the drain region, the gate region The gate length (L _g ) is 4 nm or more and 10 nm or less, and the number of doping atoms in the central region of the channel is 1 or less.

The mask layer 50 included in the field effect transistor includes, for example, a tantalum oxide film, and is formed such that the thickness of the sidewall of the gate electrode 40 provided over the gate region 40g becomes W (nm) while covering the formed The main surface portion of the semiconductor nanowire 30 of the source region 30s and the drain region 30d may have a diffusion source as a dopant toward the source region 30s and the drain region 30d when the field effect transistor is fabricated. effect.

With respect to the mask layer 50 of the side wall portion of the gate electrode 40, the implanted ions remain in the upper portion and are not injected into the portion contacting the main surface of the semiconductor nanowire 30. Therefore, the portion of the mask layer formed by the thickness W (nm) on the sidewall of the gate electrode 40 does not function as a diffusion source of the dopant. As a result, by appropriately designing the thickness W (nm), the intrusion of the dopant toward the channel region 30c can be avoided, the variation in the threshold voltage can be reduced, and a sufficient on-current can be obtained.

According to the present invention, there is provided a field effect transistor which is provided with a mask layer which is a mask layer containing a dopant atom on a main surface of a semiconductor nanowire-like semiconductor material portion, which is a gate electrode. The sidewall of the electrode has a thickness of W, and the number of doping atoms in the central region of the channel is 1 or less. As a result, the deviation of the threshold voltage can be suppressed, and the on-current can be sufficiently obtained.

[Industrial availability]

The present invention provides a field effect transistor having a source-drain structure capable of suppressing a threshold voltage deviation and sufficiently obtaining an on-current, and having a channel formed by a semiconductor material portion such as a semiconductor nanowire.

10‧‧‧矽 substrate

20‧‧‧Insulator film

30‧‧‧Semiconductor nanowire

30c‧‧‧ channel

30d‧‧‧Bungee area

30s‧‧‧ source area

40‧‧‧gate electrode

40g‧‧‧ gate area

45‧‧‧Gate oxide film

50‧‧‧ mask layer

100‧‧‧ field effect transistor

H‧‧‧thickness

L _g ‧‧‧ gate length

t _d ‧‧‧Stacked Si oxide film thickness

t _g ‧‧‧gate electrode height

t _ox ‧‧‧ gate oxide film thickness

W‧‧‧thickness

Claims (13)

A field effect transistor comprising a channel formed by a semiconductor material portion having a thickness H (nm), a source region and a drain region formed adjacent to the channel, and a gate region disposed above the channel In the field effect transistor, the gate length (L _g ) of the gate region is 4 nm or more and 10 nm or less, and the number of doping atoms in the central region of the channel is 1 or less. A field effect transistor comprising a channel formed by a semiconductor material portion having a thickness H (nm), a source region and a drain region formed adjacent to the channel, and a gate region disposed above the channel a field effect transistor having a mask layer disposed on a main surface of the semiconductor material portion, comprising a mask layer of dopant atoms belonging to a donor or a acceptor, and a gate layer disposed in the gate region a sidewall layer having a sidewall thickness of W (nm), the mask layer covering a main surface portion of the semiconductor material portion in which the source region and the drain region are formed, and a gate length of the gate region (L _g ) is 4 nm or more and 10 nm or less, and the thickness W (nm) of the mask layer of the sidewall of the gate electrode is [3H-2]/7+[10-L _g ]/2≦W≦[3H+ 19] / 7 range. The field effect transistor of claim 2, wherein the number of doping atoms in the central region of the channel is 1 or less. The field effect transistor according to any one of claims 1 to 3, wherein a dopant concentration of the 2 nm region from the end of the channel toward the source region and the drain region side is 5 × 10 ¹⁹ cm ^-3 or more. The field effect transistor of any one of claims 1 to 4, wherein the semiconductor material portion comprises any one of a bismuth, antimony, and III-V compound semiconductor. The field effect transistor of claim 5, wherein the semiconductor material portion comprises germanium, and the mask layer is a tantalum oxide film or a germanide film. The field effect transistor of claim 6, wherein the dopant is any one of phosphorus, germanium, arsenic, boron, aluminum, indium, and gallium. The field effect transistor of claim 5, wherein the semiconductor material portion comprises germanium, and the mask layer is a tantalum oxide film or a germanide film. The field effect transistor of claim 8, wherein the dopant is any one of phosphorus, germanium, arsenic, boron, aluminum, indium, and gallium. The field effect transistor of claim 5, wherein the semiconductor material portion comprises a III-V compound semiconductor, and the mask layer is a tantalum oxide film. The field effect transistor of claim 10, wherein the dopant is any one of zinc, bismuth, and antimony. The field effect transistor according to any one of claims 1 to 4, wherein the semiconductor material portion is any one of a 矽-nano line, a 锗-nano line, and a III-V compound semiconductor nanowire. A method for producing a field effect transistor, comprising a method of manufacturing a field effect transistor having a channel formed by a semiconductor material portion having a thickness H (nm), wherein the gate length (L _g ) is 4 nm or more a step of forming a gate electrode over the channel in a manner of 10 nm or less; a step of forming a mask layer covering the gate electrode and forming a source region and a drain region adjacent to the channel a main surface portion of the semiconductor material portion is a mask layer having a sidewall thickness of the gate electrode of W (nm); a step of implanting dopant atoms belonging to the donor or the acceptor into the mask layer; a step of diffusing the dopant atoms of the mask layer to the source region and the drain region; setting the thickness W (nm) of the mask layer on the sidewall of the gate electrode to [3H-2]/7+[ The range of 10-L _g ]/2≦W≦[3H+19]/7.