JP2017216258A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor capable of suppressing variation in a threshold voltage and also sufficiently taking an ON current, and including a channel formed from a semiconductor nanowire.SOLUTION: A field effect transistor 100 comprises a channel 30c formed from a semiconductor nanowire 30. A source region 30s and a drain region 30d are formed adjacently to the channel 30c, and a gate electrode 40 is provided at an upper side of the channel. On a principal surface of the semiconductor nanowire 30, a mask layer 50 containing a dopant atom that becomes a donor or an acceptor is provided. The dopant atom is also ion-implanted into the mask layer 50 on a sidewall part of the gate electrode 40 but the implanted ion is residual in an upper part and is not implanted to a portion in contact with the principal surface of the semiconductor nanowire 30. Therefore, a mask layer portion formed with thickness W on a sidewall of the gate electrode 40 does not function as a dopant diffusion source.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a field effect transistor having a channel formed of semiconductor nanowires. More specifically, the present invention relates to an electric field having a source / drain structure that can suppress variation in threshold voltage and can sufficiently take on current. The present invention relates to an effect transistor.

  When forming a field effect transistor using semiconductor nanowires, it is necessary to dope the source region and the drain region. However, even if heat treatment is performed by implanting dopant ions directly using the gate electrode as a mask, Ion implantation-induced crystal defects remain.

  When the source region and the drain region are formed by doping by the solid phase diffusion method, the above-described defect residue can be avoided, but the dopant penetrates into the channel region due to the diffusion, and the threshold voltage of the transistor shifts. There is a problem that it ends up. In addition, when the dopant concentration is lowered to suppress the threshold voltage shift, a sufficient on-current cannot be obtained.

  The inventors of the present invention have provided a spacer on the side wall of the gate electrode prior to ion implantation of the dopant for the purpose of suppressing the threshold variation of the field effect transistor, and the dopant is present in the semiconductor region immediately below the side wall spacer. A technique for preventing injection was studied (Uematsu et al .: Non-Patent Document 1). It was confirmed that by providing such a side wall spacer, the dopant hardly enters the channel region, and as a result, fluctuations in off-current and threshold voltage are remarkably suppressed.

M. Uematsu et al., "Simulation of the Effect of Arsenic Discrete Distribution on Device Characteristics in Silicon Nanowire Transistors" IEDM12-709 (2012)

  However, even if a spacer is provided on the side wall of the gate electrode as disclosed in Non-Patent Document 1, it is not possible to sufficiently suppress the penetration of the dopant into the channel region due to the heat treatment after ion implantation. In addition, since there is “leaching” of electrons from the dopant, it is necessary to consider not only the penetration of the dopant but also the “leaching length” of the electrons as an influence on the channel. For example, when the semiconductor nanowire is a silicon crystal and the dopant is arsenic, the “leaching length” of electrons is about 2 nm.

  However, even if such dopant intrusion or electron “seepage” occurs, it does not matter so much when the gate length is long. However, when the gate length is shortened along with the miniaturization of the field effect transistor, the intrusion of the dopant and the “leaching” of the electrons greatly affect the channel region, resulting in a variation in threshold voltage. Accordingly, there is a need for a channel formation technique (source / drain formation technique) that further suppresses the penetration of dopants into the channel region and also considers the “leaching length” of electrons. It is also necessary to avoid the problem that ion implantation-induced crystal defects remain in the transistor body.

  The present invention has been made in view of the above-described problems, and the object of the present invention is to have a source / drain structure that suppresses variations in threshold voltage and can sufficiently take on current. Another object of the present invention is to provide a field effect transistor having a channel formed of semiconductor nanowires, in which crystal defects due to ion implantation are not induced in the transistor body.

  In order to solve the above problems, a field effect transistor according to the present invention includes a channel formed of a semiconductor nanowire having a thickness of H (nm), a source region and a drain region formed adjacent to the channel, A field effect transistor including a gate region provided above a channel, the mask layer including a dopant atom serving as a donor or an acceptor provided on a main surface of the semiconductor nanowire, and provided in the gate region A gate layer having a thickness of W (nm) on the side wall of the gate electrode, and the mask layer covers a main surface portion of the semiconductor nanowire in which the source region and the drain region are formed; The length (Lg) is 4 nm or more and 10 nm or less, and the number of dopant atoms in the central region of the channel is 1 or less. That, characterized in that.

Preferably, a dopant concentration in a region of 2 nm from the end portion of the channel to the source region and the drain region side is 5 × 10 ¹⁹ cm ⁻³ or more.

  Preferably, the thickness W (nm) of the mask layer on the side wall of the gate electrode is in the range of [3H−2] / 7 + [10−Lg] / 2 ≦ W ≦ [3H + 19] / 7.

  More preferably, the semiconductor nanowire is any one of a silicon nanowire, a germanium nanowire, and a III-V compound semiconductor nanowire.

  For example, the semiconductor nanowire is a silicon nanowire, and the mask layer is a silicon oxide film or a silicide film.

  In this case, for example, the dopant is any one of phosphorus, antimony, arsenic, boron, aluminum, indium, and gallium.

  For example, the semiconductor nanowire is a germanium nanowire, and the mask layer is a germanium oxide film or a germanide film.

  In this case, for example, the dopant is any one of phosphorus, antimony, arsenic, boron, aluminum, indium, and gallium.

  For example, the semiconductor nanowire is a III-V compound semiconductor nanowire, and the mask layer is a silicon oxide film.

  In this case, for example, the dopant is any one of zinc, silicon, and beryllium.

  According to the present invention, a field effect transistor having a mask layer containing dopant atoms on the main surface of a semiconductor nanowire, the mask layer having a side wall thickness of the gate electrode of W, and the number of dopant atoms in the central region of the channel being 1 or less. Is provided. As a result, variation in threshold voltage can be suppressed and sufficient on-current can be obtained.

It is sectional drawing for demonstrating notionally the structure of the field effect transistor which concerns on this invention. In the field effect transistor which concerns on this invention, it is a figure which shows the simulation result performed in order to determine the appropriate range of thickness W (nm) of the mask layer of the side wall of a gate electrode.

  FIG. 1 is a cross-sectional view for conceptually explaining the structure of a field effect transistor according to the present invention. In this figure, in order to simplify the explanation, a single gate electrode structure (single gate) is shown, but the present invention is not limited to such a structure, and a double gate or trigate structure is shown. It may be a transistor, or a transistor having a structure in which the entire periphery of the channel is a gate.

  The field effect transistor 100 includes a channel 30 c formed by the semiconductor nanowire 30. A source region 30s and a drain region 30d are formed adjacent to the channel 30c. A gate electrode 40 is provided above the channel via a gate oxide film 45, and a gate electrode 40 is provided below the gate electrode. The gate region 40g has a length Lg.

The semiconductor nanowire 30 is made of, for example, a silicon nanowire obtained by processing a semiconductor layer of an SOI substrate, or a silicon oxide film (SiO ₂ ) formed on an n-type or p-type conductive silicon substrate 10. It is a silicon nanowire provided on the insulator film 20. The semiconductor nanowire is not limited to a silicon nanowire, and may be a group III-V compound semiconductor nanowire such as germanium nanowire or GaAs.

The semiconductor nanowire 30 is a thin line crystal having a large length to width ratio (aspect ratio), and its thickness H (nm) is, for example, about 10 nm. Such a semiconductor nanowire 30 can be formed by processing a semiconductor layer on an insulator, or by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). When the semiconductor nanowire 30 is a silicon nanowire, the semiconductor nanowire may be formed using an SOI substrate, or silane (SiH ₄ ) gas or silicon tetrachloride (SiCl ₄ ) gas may be formed as a source gas. .

  On the main surface of the semiconductor nanowire 30, a mask layer 50 including a dopant atom that becomes a donor or an acceptor is provided. The mask layer 50 is made of, for example, a silicon oxide film, and is formed such that the side wall thickness of the gate electrode 40 provided above the gate region 40g is W (nm), and the source region 30s and the drain region 30d. The main surface portion of the semiconductor nanowire 30 on which is formed is covered.

  The mask layer 50 is formed by, for example, ion-implanting dopant atoms that become donors or acceptors in the semiconductor nanowire 30 after forming a silicon oxide film.

  When the semiconductor nanowire 30 is a silicon nanowire, the mask layer 50 may be a layer made of a silicide film in addition to the silicon oxide film. As dopant atoms contained in the mask layer 50, phosphorus, antimony, arsenic, boron, aluminum, Examples include indium and gallium.

  The semiconductor nanowire 30 may be a germanium nanowire. In this case, the mask layer 50 may be a layer made of a germanium oxide film or a germanide film, and examples of dopant atoms included in the mask layer 50 include phosphorus, antimony, arsenic, boron, aluminum, indium, and gallium.

  The semiconductor nanowire 30 may be a III-V compound semiconductor nanowire. In this case, the mask layer 50 is a layer made of, for example, a silicon oxide film, and zinc, silicon, and beryllium can be exemplified as dopant atoms included in the mask layer 50.

  The mask layer 50 functions as a dopant diffusion source to the source region 30s and the drain region 30d when the field effect transistor according to the present invention is manufactured.

  Conventionally, for example, when doping a source region and a drain region of a silicon nanowire, a dopant is ion-implanted directly into the silicon nanowire using a gate electrode as a mask, and then heat treatment is performed to electrically activate the implanted ions. The technique used as donors and acceptors was adopted. However, such a method has a problem that crystal defects are induced in the transistor body by ion implantation, and the defects remain after the heat treatment to deteriorate the transistor characteristics.

  Even when a so-called solid phase diffusion method is employed in order to avoid this problem, there is a problem that the dopant is diffused to the channel region of the transistor and the threshold voltage of the transistor is shifted. On the other hand, if the dopant concentration is lowered to suppress the threshold voltage shift, a sufficient on-current cannot be obtained.

  Therefore, in the present invention, a mask layer 50 is formed in a region including the gate electrode at a stage before ion implantation, and ions are implanted from above the mask layer 50. Since damage at the time of ion implantation is absorbed by the mask layer 50, damage to the semiconductor nanowire 30 is avoided and crystal defects are not induced, so that heat treatment for recovering damage is not required. The mask layer 50 functions as a dopant diffusion source, but how much doping is performed can be easily controlled by the ion implantation amount (dose amount).

  Although dopant atoms are also ion-implanted into the mask layer 50 in the side wall portion of the gate electrode 40, the implanted ions remain in the upper portion. That is, it is not injected even into the portion in contact with the main surface of the semiconductor nanowire 30. Therefore, the mask layer portion formed with a thickness W (nm) on the side wall of the gate electrode 40 does not function as a dopant diffusion source. As a result, by appropriately designing the thickness W (nm), it is possible to avoid dopant penetration into the channel region 30c, to reduce variation in threshold voltage, and to obtain sufficient on-current. It becomes.

  FIG. 2 is a diagram showing a simulation result performed to determine an appropriate range of the thickness W (nm) of the mask layer 50 on the side wall of the gate electrode 40 in the field effect transistor having the above-described structure. The horizontal axis represents the thickness H (nm) of the semiconductor nanowire, and the vertical axis represents the thickness W (nm) of the mask layer 50 on the side wall of the gate electrode 40.

  Conditions for this simulation are as shown in Table 1. Here, a silicon oxide film is deposited on the entire surface including the gate electrode of the nanowire MOS field effect transistor (10 nm square or less, length 30 nm), and arsenic is ionized from above. After the implantation, the dopant is diffused by performing a heat treatment at 1000 ° C.

  Here, the acceleration voltage at the time of ion implantation is set to 0.5 keV because arsenic is implanted into the deposited Si oxide film having a tg of 3 nm. The time for diffusing the dopant after ion implantation is an optimum value according to the thickness H (nm) of the semiconductor nanowire, and is the minimum time for doping the SD (source / drain) portion almost uniformly. Specifically, for H = 2 nm, 3 nm, 5 nm, 7.5 nm, and 10 nm, 0.25 seconds, 0.5 seconds, 1 second, 2.5 seconds, and 5 seconds, respectively.

First, regarding the upper limit of the thickness W (nm), the evaluation is performed under the condition that the concentration of the dopant (arsenic in this case) is 5 × 10 ¹⁹ cm ⁻³ or more at 2 nm from the channel end to the source region and the drain region. The upper limit value W _u (nm) of the thickness W (nm) is [3H + 19] / 7. When the thickness exceeds this value, sufficient on-current cannot be obtained.

The reason why the dopant concentration is set to 5 × 10 ¹⁹ cm ⁻³ or more at 2 nm from the channel end is that the on-current cannot be obtained when the dopant concentration is lower than this.

On the other hand, regarding the lower limit of the thickness W (nm), the lower limit value W _l (nm) of the thickness W (nm) is, when evaluated under the condition that the penetration of the dopant (arsenic) into the channel center is 1 or less. [3H-2] / 7 + [10-Lg] / 2. When the thickness is less than or equal to this thickness, the variation in threshold value increases.

Therefore, in the present invention, the thickness W (nm) of the mask layer 50 on the side wall of the gate electrode 40 is set in the range of [3H−2] / 7 + [10−Lg] / 2 ≦ W ≦ [3H + 19] / 7. . As can be seen from this relational expression, the upper limit value W _u (nm) does not depend on the gate length Lg, whereas the lower limit value W _l (nm) depends on the gate length Lg.

  In the field effect transistor according to the present invention, the gate length Lg of the gate region is preferably 4 nm or more and 10 nm or less so that the number of dopant atoms in the central region of the channel is 1 or less.

  As described above, the field effect transistor according to the present invention includes a channel formed of a semiconductor nanowire having a thickness of H (nm), a source region and a drain region formed adjacent to the channel, and an upper portion of the channel. A field effect transistor having a gate region provided on the semiconductor nanowire, the mask layer including a dopant atom serving as a donor or an acceptor provided on a main surface of the semiconductor nanowire, the gate provided on the gate region The electrode includes a mask layer having a sidewall thickness of W (nm), the mask layer covering a main surface portion of the semiconductor nanowire in which the source region and the drain region are formed, and a gate length (Lg) of the gate region ) Is 4 nm or more and 10 nm or less, and the number of dopant atoms in the central region of the channel is 1 or less. It is a transistor.

  The mask layer 50 included in the field effect transistor is made of, for example, a silicon oxide film, and is formed such that the thickness of the side wall of the gate electrode 40 provided above the gate region 40g is W (nm) and the source region. The main surface portion of the semiconductor nanowire 30 in which 30s and the drain region 30d are formed is covered, and has a function as a dopant diffusion source to the source region 30s and the drain region 30d when a field effect transistor is manufactured. Yes.

  In the mask layer 50 on the side wall portion of the gate electrode 40, the implanted ions remain in the upper portion and are not implanted into the portion in contact with the main surface of the semiconductor nanowire 30. Therefore, the mask layer portion formed with a thickness W (nm) on the side wall of the gate electrode 40 does not function as a dopant diffusion source. As a result, by appropriately designing the thickness W (nm), it is possible to avoid dopant penetration into the channel region 30c, to reduce variation in threshold voltage, and to obtain sufficient on-current. It becomes.

  Thus, according to the present invention, a mask layer containing dopant atoms on the main surface of the semiconductor nanowire, the mask layer having a side wall thickness of W of the gate electrode is provided, and the number of dopant atoms in the central region of the channel is 1 or less. A field effect transistor is provided. As a result, variation in threshold voltage can be suppressed and sufficient on-current can be obtained.

  The present invention provides a field effect transistor having a channel formed of semiconductor nanowires, which has a source / drain structure that suppresses variations in threshold voltage and can sufficiently take on current.

10 silicon substrate 20 insulator film 30 semiconductor nanowire 30c channel 30s source region 30d drain region 40 gate electrode 40g gate region 45 gate oxide film 50 mask layer 100 field effect transistor

Claims (10)

A field effect transistor comprising a channel formed of a semiconductor nanowire having a thickness of H (nm), a source region and a drain region formed adjacent to the channel, and a gate region provided above the channel. And
A mask layer including a dopant atom serving as a donor or an acceptor provided on a main surface of the semiconductor nanowire, the gate electrode provided on the gate region having a mask layer having a sidewall thickness of W (nm);
The mask layer covers a main surface portion of the semiconductor nanowire in which the source region and the drain region are formed,
The gate length (Lg) of the gate region is 4 nm or more and 10 nm or less,
The number of dopant atoms in the central region of the channel is 1 or less,
Field effect transistor. 2. The field effect transistor according to claim 1, wherein a dopant concentration in a region of 2 nm from the end portion of the channel to the source region and the drain region side is 5 × 10 ¹⁹ cm ⁻³ or more.   3. The thickness W (nm) of the mask layer on the side wall of the gate electrode is in the range of [3H−2] / 7 + [10−Lg] / 2 ≦ W ≦ [3H + 19] / 7. Field effect transistor.   The field effect transistor according to claim 1, wherein the semiconductor nanowire is any one of a silicon nanowire, a germanium nanowire, and a group III-V compound semiconductor nanowire.   The field effect transistor according to claim 4, wherein the semiconductor nanowire is a silicon nanowire, and the mask layer is a silicon oxide film or a silicide film.   The field effect transistor according to claim 5, wherein the dopant is any one of phosphorus, antimony, arsenic, boron, aluminum, indium, and gallium.   The field effect transistor according to claim 4, wherein the semiconductor nanowire is a germanium nanowire, and the mask layer is a germanium oxide film or a germanide film.   The field effect transistor according to claim 7, wherein the dopant is any one of phosphorus, antimony, arsenic, boron, aluminum, indium, and gallium.   The field effect transistor according to claim 4, wherein the semiconductor nanowire is a III-V compound semiconductor nanowire, and the mask layer is a silicon oxide film.   The field effect transistor according to claim 9, wherein the dopant is any one of zinc, silicon, and beryllium.