JP2020057636A - Nitride semiconductor device and method for manufacturing nitride semiconductor device - Google Patents

Abstract

To provide a technique capable of forming a high-quality p-type region in a nitride semiconductor.SOLUTION: A method for manufacturing a nitride semiconductor device comprises the steps of: forming an n-type GaN layer on a GaN substrate by an epitaxial growth method; forming a low-concentration p-type GaN layer on an upper surface of the n-type GaN layer by the epitaxial growth method; forming a high-concentration p-type GaN layer on an upper surface of the low-concentration p-type GaN layer by the epitaxial growth method; and diffusing hydrogen contained in the low-concentration p-type GaN layer into the high-concentration GaN layer by performing annealing in an inert atmosphere (annealing step).SELECTED DRAWING: Figure 2

Description

  The technology disclosed in the present specification relates to a nitride semiconductor device and a method for manufacturing the nitride semiconductor device.

  In GaN, if hydrogen is contained at a high concentration, the acceptor (eg, Mg) may not be activated, and the performance of the p-type region may not be obtained. Patent Document 1 discloses a technique for performing dehydrogenation annealing in a state where the p-type GaN layer is exposed, in order to efficiently release hydrogen from the p-type GaN layer.

JP 2012-84617 A

  Even when the dehydrogenation annealing is performed in a state where the p-type GaN layer is exposed, hydrogen in the p-type GaN layer may not be sufficiently removed, and the effective acceptor concentration may decrease.

  One embodiment of a method for manufacturing a nitride semiconductor device disclosed in this specification includes a step of forming an n-type GaN layer on a GaN substrate by an epitaxial growth method. forming a low concentration p-type GaN layer on the upper surface of the n-type GaN layer by an epitaxial growth method; Forming a high concentration p-type GaN layer on the upper surface of the low concentration p-type GaN layer by an epitaxial growth method; An annealing step of diffusing hydrogen contained in the low concentration p-type GaN layer into the high concentration p-type GaN layer by annealing in an inert atmosphere is provided.

  The annealing can be performed in a state where the high concentration p-type GaN layer is formed on the upper surface of the low concentration p-type GaN layer. Since the hydrogen contained in the low-concentration p-type GaN layer can be diffused into the high-concentration p-type GaN layer, the hydrogen concentration of the low-concentration p-type GaN layer is reduced by setting the high-concentration p-type GaN layer on the upper surface. It can be sufficiently reduced in a short time as compared with the case where there is not. The effective acceptor concentration of low-concentration p-type GaN can be increased.

  After the annealing step, a step of exposing the low-concentration p-type GaN layer by removing the high-concentration p-type GaN layer in the opening region by etching may be provided. A step of forming an n-type GaN region above the low-concentration p-type GaN layer in the opening region by implanting impurities into the opening region may be provided. A step of forming a trench extending from the upper surface of the n-type GaN region to the n-type GaN layer may be provided in a part of the opening region. The method may include a step of forming a gate electrode inside the trench via a gate insulating film.

  After the annealing step, a step of exposing the low-concentration p-type GaN layer by removing the high-concentration p-type GaN layer in the opening region by etching may be provided. By implanting impurities into the source region and the drain region which are arranged apart from each other in the opening region, an n-type GaN source region and an n-type GaN drain region are formed above the low-concentration p-type GaN layer. A step may be provided. A step of forming a gate electrode on the upper surface of the low-concentration p-type GaN layer in a region between the source region and the drain region via a gate insulating film may be provided.

  One embodiment of the nitride semiconductor device disclosed in this specification includes an n-type GaN drift layer. A low concentration p-type GaN body layer is provided in contact with the upper surface of the drift layer. An n-type GaN source region is provided above the body layer. A gate electrode region extending from the upper surface of the source region to the drift layer; A high-concentration p-type GaN body contact layer disposed on an upper surface of the body layer and having an opening region, wherein at least a part of the source region and the gate electrode region are exposed inside the opening region. Prepare. A source electrode is provided in contact with the upper surface of the source region and the upper surface of the body contact layer. Details of the effects will be described in Examples.

  The hydrogen concentration of the body layer may be lower than the hydrogen concentration of the body contact layer. Details of the effects will be described in Examples.

  The body contact layer may be a layer formed by epitaxial growth. The source region may be a region formed by ion implantation. Details of the effects will be described in Examples.

  One embodiment of the nitride semiconductor device disclosed in this specification includes a low-concentration p-type GaN layer. An n-type GaN source region is provided above the low-concentration p-type GaN layer. An n-type GaN drain region is provided above the low-concentration p-type GaN layer and is located away from the source region. A gate electrode disposed in a region between the source region and the drain region, the gate electrode being disposed on a top surface of the low-concentration p-type GaN layer via a gate insulating film. A high-concentration p-type GaN layer disposed on an upper surface of the low-concentration p-type GaN layer and having an opening region, wherein a gate electrode, at least a part of a source region, and at least a part of a drain region are exposed inside the opening region High concentration p-type GaN layer. A source electrode is provided in contact with the upper surface of the source region and the upper surface of the high concentration p-type GaN layer. A drain electrode is provided in contact with the upper surface of the drain region and the upper surface of the high concentration p-type GaN layer. Details of the effects will be described in Examples.

  The hydrogen concentration of the low concentration p-type GaN layer may be lower than the hydrogen concentration of the high concentration p-type GaN layer. Details of the effects will be described in Examples.

  The high concentration p-type GaN layer may be a layer formed by epitaxial growth. The source region and the drain region may be regions formed by ion implantation. Details of the effects will be described in Examples.

1 is a schematic sectional view of a semiconductor device 1 according to a first embodiment. 4 is a flowchart illustrating a method for manufacturing the semiconductor device 1 according to the first embodiment. FIG. 5 is a diagram illustrating a manufacturing process of the semiconductor device 1 according to the first embodiment. FIG. 5 is a diagram illustrating a manufacturing process of the semiconductor device 1 according to the first embodiment. FIG. 5 is a diagram illustrating a manufacturing process of the semiconductor device 1 according to the first embodiment. 5 is a graph of a measurement result of a hydrogen concentration of a low concentration p-type GaN layer. FIG. 7 is a schematic sectional view of a semiconductor device 101 according to a second embodiment. 9 is a flowchart illustrating a method for manufacturing the semiconductor device 101 according to the second embodiment. FIG. 11 is a diagram illustrating a manufacturing process of the semiconductor device 101 according to the second embodiment.

(Configuration of Semiconductor Device 1)
FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 according to the present embodiment. The semiconductor device 1 is a vertical MOSFET provided with a trench gate. The semiconductor device 1 has a semiconductor substrate 10. The semiconductor substrate 10 has a structure in which a drain layer 32, a drift layer 34, a body layer 36, and a body contact layer 46 are stacked.

The drain layer 32 is a high-concentration n-type (n ⁺ -type) GaN substrate. On the back surface of the drain layer 32, a drain electrode 52 is formed. The donor concentration of the drain layer 32 was 2 × 10 ¹⁸ cm ⁻³ . A drift layer 34 is formed on the surface of the drain layer 32. The drift layer 34 is a low-concentration n-type (n ⁻ type) GaN layer epitaxially grown on the surface of the drain layer 32. The donor concentration of the drift layer 34 was set to 8 × 10 ¹⁵ cm ⁻³ . The body layer 36 is a low-concentration p-type (p ⁻ type) GaN layer epitaxially grown on the drift layer 34. The acceptor (Mg) concentration of the body layer 36 was set to 5 × 10 ¹⁷ cm ⁻³ .

The source region 38 is a high-concentration n-type (n ⁺ -type) GaN region formed at a position facing a part of the surface of the body layer 36. The source region 38 is a region formed by ion implantation. In the source region 38, a donor element (eg, silicon, germanium) exists according to a Gaussian distribution. The donor concentration of the source region 38 was 1 × 10 ²⁰ cm ⁻³ .

On the upper surface of body layer 36, body contact layer 46 is arranged. The body contact layer 46 is a high-concentration p-type (p ⁺ -type) GaN layer epitaxially grown on the surface of the body layer 36. The body layer 36 and the body contact layer 46 may be continuously formed in the same device. The acceptor (Mg) concentration of the body contact layer 46 was set to 3 × 10 ¹⁹ cm ⁻³ . The body contact layer 46 has an opening area A1. The opening region A1 is a region where the body contact layer 46 is not disposed on the upper surface of the body layer 36. Part of the source region 38 and the gate electrode region 41 are exposed inside the opening region A1.

The hydrogen concentration of body layer 36 is lower than the hydrogen concentration of body contact layer 46. For example, the hydrogen concentration of body layer 36 may be 1/10 or less of the hydrogen concentration of body contact layer 46. The hydrogen concentration of the body layer 36 was set to 5 × 10 ¹⁶ cm ⁻³ .

  The gate electrode region 41 includes a trench gate electrode 40 and a gate insulating film 42. Trench gate electrode 40 penetrates into drift layer 34 from the surface of source region 38 through source region 38 and body layer 36. The trench gate electrode 40 is an electrode formed in the trench T1 whose side and bottom are covered with the gate insulating film 42. The trench gate electrode 40 extends outside the trench T1 and is in contact with the gate electrode 50. Trench gate electrode 40 is formed of polycrystalline silicon or the like.

  The interlayer insulating film 48 is a layer for ensuring insulation of the gate electrode 50 and the source electrode 44. The source electrode 44 is in contact with the upper surfaces of the body contact layer 46 and the source region 38.

(Manufacturing method of semiconductor device 1)
A method for manufacturing the semiconductor device 1 will be described with reference to FIGS. In step S1 of the flowchart in FIG. 2, a laminated structure forming step is performed. Specifically, as shown in FIG. 3, the semiconductor substrate 10 on which the drain layer 32, the drift layer 34, the body layer 36, and the body contact layer 46 are stacked is formed. The semiconductor substrate 10 may be formed by growing the drift layer 34, the body layer 36, and the body contact layer 46 on the drain layer 32 by an epitaxial growth method (eg, MOVPE method).

In step S2, an annealing step is performed. Specifically, the semiconductor substrate 10 is heated in an inert atmosphere (eg, in an N ₂ atmosphere) at 850 ° C. for 10 minutes. This allows hydrogen contained in the body layer 36 (low-concentration p-type GaN layer) to diffuse into the body contact layer 46 (high-concentration p-type GaN layer).

  In step S3, an opening region forming step is performed. Specifically, a mask having an opening corresponding to the opening region A1 is processed by using a well-known photolithography technique and dry etching. The body layer 36 is exposed by removing the body contact layer 46 in the opening region A1 by dry etching.

  In step S4, a source region forming step is performed. Specifically, as shown in FIG. 4, silicon or germanium is ion-implanted into the body layer 36 through a mask 61 having an opening corresponding to the source region 38. Thereby, the source region 38 can be formed above the body layer 36 in the opening region A1.

  Source region 38 may be formed such that an end of source region 38 overlaps an end of body contact layer 46. Thereby, as shown in FIG. 4, the overlap region D1 can be formed. The layout of the semiconductor device 1 in the lateral direction (X direction) can be shrunk by the presence of the overlap region D1, so that the size of the semiconductor device 1 can be reduced.

  In step S5, a trench forming step is performed. Specifically, a trench T1 that penetrates through the body layer 36 from the upper surface of the source region 38 and reaches the drift layer 34 is formed in a part of the opening region A1. The processing of the trench T1 can be performed by a known photolithography technique and a dry etching processing.

In step S6, a gate electrode region forming step is performed. Specifically, the gate insulating film 42 is formed in the trench T1 and on the surface of the semiconductor substrate 10. The gate insulating film 42 is an insulating film formed by depositing SiO ₂ or Al ₂ O ₃ or the like by an atomic deposition method or the like. Polysilicon doped with impurities such as boron is formed by an LP-CVD method. The trench gate electrode 40 is formed by removing polysilicon around the trench T1 using a known photolithography technique and dry etching. Thereby, the structure shown in FIG. 5 is formed.

  In step S7, a source electrode and gate electrode formation step is performed. Specifically, an interlayer insulating film 48 is formed on the upper surface of the trench gate electrode 40. Then, the interlayer insulating film 48 and the gate insulating film 42 in the region where the source electrode 44 and the gate electrode 50 are formed are removed by using a known photolithography technique and dry etching. A metal layer is formed. The metal layer is processed into the source electrode 44 and the gate electrode 50 by using a known photolithography technique and dry etching.

  In step S8, a drain electrode forming step is performed. Specifically, a drain electrode 52 of a metal layer is formed on the back surface of the drain layer 32. Thus, the semiconductor device 1 shown in FIG. 1 is completed.

(Operation of Semiconductor Device 1)
In the semiconductor device 1 shown in FIG. 1, the drain electrode 52 is connected to a high potential, the source electrode 44 is grounded, and the potential applied to the gate electrode 50 is changed. When a positive potential is applied to the gate electrode 50, the p ⁻ type body layer 36 in the region R1 facing the trench gate electrode 40 via the gate insulating film 42 is inverted to the n type, and the n ⁺ type is inverted by the inversion layer. The source region 38 and the n ⁻ -type drift layer 34 conduct, and a current flows between the source electrode 44 and the drain electrode 52. When the application of the positive potential to the gate electrode 50 is stopped, the inversion layer in the region R1 disappears, the depletion layer extends in the drift layer 34, and the state between the source electrode 44 and the drain electrode 52 becomes high resistance.

(effect)
The body layer 36, which is a low-concentration p-type GaN layer, is a layer on which the inversion layer is formed as described above, and is therefore an important layer that determines the threshold value of the semiconductor device 1. When p-type GaN contains a high concentration of hydrogen, the acceptor (eg, Mg) is not activated, and sufficient p-type characteristics may not be obtained. Therefore, it is necessary to reduce the hydrogen concentration of the low concentration p-type GaN layer. According to the technique described in this specification, annealing is performed in an inert atmosphere in a state where a high-concentration p-type GaN layer (body contact layer 46) is formed on the upper surface of a low-concentration p-type GaN layer (body layer 36). Is performed (step S2). By performing such annealing, the hydrogen concentration of the low-concentration p-type GaN layer can be sufficiently reduced in a short time as compared with the case where the high-concentration p-type GaN layer is not disposed on the upper surface. The inventors have found. This is probably because hydrogen exists as a proton at the interface between the high-concentration p-type GaN layer and the low-concentration p-type GaN layer, and the diffusion of hydrogen toward the high-concentration p-type GaN layer is accelerated by an electric field.

  Thereby, the hydrogen concentration of the low concentration p-type GaN layer (body layer 36) can be sufficiently reduced. Since the effective acceptor concentration as designed can be obtained, the threshold voltage can be precisely controlled.

  The state in which the high-concentration p-type GaN layer is formed on the upper surface of the low-concentration p-type GaN layer is realized on the entire surface of the substrate, and then dehydrogenation annealing can be performed. Thereby, the hydrogen concentration of the low-concentration p-type GaN layer can be reduced with good in-plane uniformity. Therefore, the in-plane uniformity of the threshold voltage of the semiconductor device 1 can be improved.

  After the dehydrogenation annealing (step S2), an opening region A1 is formed in the high-concentration p-type GaN layer (step S3), so that the high-concentration p-type GaN layer used as the cover film for reducing the hydrogen concentration is removed from the body contact. It can be diverted as the layer 46. The body contact layer 46 is a p-type GaN layer formed by epitaxial growth. In general, the quality of p-type GaN formed by epitaxial growth is higher than that of p-type GaN formed by ion implantation. Therefore, the quality of body contact layer 46 can be improved.

  By forming the source ion-implanted region in step S4 in the opening region A1 formed in step S3, the contact resistance of the source electrode 44 can be reduced as compared with a case where no opening region is formed. As a result, the surface of n-type source region 38 is formed at a position deeper than the surface of p-type body contact layer 46 (that is, at a position closer to drift layer 34). With such a manufacturing process and a surface structure, the body contact resistance and the source resistance can be kept low at the same time.

(Results of measurement of hydrogen concentration)
FIG. 6 shows a graph of the measurement result of the hydrogen concentration of the low-concentration p-type GaN layer. FIG. 6 shows a measurement result using the secondary ion mass spectrometry (SIMS). As a typical measurement condition example, Cs ⁺ ions were used as the primary ion species, and 8.0 kV was used as the acceleration voltage. The vertical axis is the normalized hydrogen concentration. The horizontal axis is the annealing time. The annealing temperature was 850 ° C. and the annealing atmosphere was N ₂ . The hydrogen concentration was measured under each of the three conditions of Comparative Example 1, Comparative Example 2, and the present example. In Comparative Example 1, a sample in which a high-concentration n-type GaN layer was formed on the upper surface of a low-concentration p-type GaN layer was used. In Comparative Example 2, a sample in which the low-concentration p-type GaN layer was exposed was used. In this example, a sample in which a high-concentration p-type GaN layer was formed on the upper surface of a low-concentration p-type GaN layer was used. In FIG. 6, the measurement results of Comparative Example 1 are indicated by triangular points, the measurement results of Comparative Example 2 are indicated by round points, and the measurement results of this example are indicated by square points.

  At time t1 when the annealing time is 10 minutes, in Comparative Example 1 (triangle), the hydrogen concentration is almost the same as before the annealing. In Comparative Example 2 (round), the hydrogen concentration decreased only to about 60% before annealing. However, in this embodiment (square), it can be reduced to about 10% before annealing. It can be seen that annealing in a state where the high concentration p-type GaN layer is formed on the upper surface of the low concentration p-type GaN layer can efficiently reduce the hydrogen concentration of the low concentration p-type GaN layer. It can also be seen that this effect can be obtained even when the annealing time is longer than 10 minutes.

(Configuration of Semiconductor Device 101)
FIG. 7 is a schematic cross-sectional view of a semiconductor device 101 according to the second embodiment. The semiconductor device 101 is a lateral MOSFET having a planar gate. The semiconductor device 101 has a semiconductor substrate 110. The semiconductor substrate 110 has a high-concentration n-type (n ⁺ -type) GaN layer 132, a low-concentration n-type (n ⁻ -type) GaN layer 134, a low-concentration p-type (p ⁻ -type) GaN layer 136, and a contact layer 146. It has a structure. The contact layer 146 is a high-concentration p-type (p ⁺ -type) GaN layer. The low concentration n-type GaN layer 134, the low concentration p-type GaN layer 136, and the contact layer 146 are layers formed by epitaxial growth.

  Above the low-concentration p-type GaN layer 136, an n-type GaN source region 138 and an n-type GaN drain region 139 are arranged. Drain region 139 is arranged away from source region 138. The source region 138 and the drain region 139 are regions formed by ion implantation.

  The contact layer 146 has an opening area A101. The opening region A101 is a region where the contact layer 146 is not disposed on the upper surface of the low concentration p-type GaN layer 136. Inside the opening region A101, at least a part of the gate electrode 140, the source region 138, and at least a part of the drain region 139 are exposed. The hydrogen concentration of the low concentration p-type GaN layer 136 is lower than the hydrogen concentration of the contact layer 146.

  In a region between the source region 138 and the drain region 139, a gate insulating film 142 and a gate electrode 140 are arranged. The gate electrode 140 is disposed on the upper surface of the low-concentration p-type GaN layer 136 via the gate insulating film 142.

  Source electrode 144 is in contact with the upper surface of source region 138 and the upper surface of contact layer 146. The drain electrode 145 is in contact with the upper surface of the drain region 139 and the upper surface of the contact layer 146.

The impurity concentrations of the low-concentration p-type GaN layer 136, the contact layer 146, and the source region 138 are the same as those of the body layer 36, the body contact layer 46, and the source region 38 described in the first embodiment. is there. Further, the impurity concentration of the low-concentration n-type GaN layer 134 is higher than the impurity concentration of the drift layer 34 described in the first embodiment, and is set to 1 × 10 ¹⁶ cm ⁻³ . Thus, the thickness of the low-concentration n-type GaN layer 134 can be reduced.

(effect)
In the semiconductor device 101 according to the second embodiment, the same effects as those of the semiconductor device 1 according to the first embodiment can be obtained. In particular, in the semiconductor device 101 which is a lateral MOSFET, an inversion layer is formed in a region R101 on the surface of the low-concentration p-type GaN layer 136. Then, since the entire surface of the region R101 is covered with the high-concentration p-type contact layer 146 and then subjected to dehydrogenation annealing (step S12), the hydrogen concentration in the entire region R101 can be efficiently reduced. The threshold voltage can be controlled more precisely.

(Method of Manufacturing Semiconductor Device 101)
A method for manufacturing the semiconductor device 101 will be described with reference to FIGS. The contents of steps S11 to S13 in FIG. 8 are the same as the contents of steps S1 to S3 in FIG.

  In step S14, a source region and a drain region forming step is performed. Specifically, as shown in FIG. 9, silicon or germanium is ion-implanted into the low-concentration p-type GaN layer 136 through a mask 161 having openings corresponding to the source region 138 and the drain region 139. As a result, a source region 138 and a drain region 139 which are arranged apart from each other are formed above the low-concentration p-type GaN layer 136 in the opening region A101.

  In step S15, a gate electrode region forming step is performed. Specifically, the gate electrode 140 is formed on the upper surface of the low-concentration p-type GaN layer 136 between the source region 138 and the drain region 139 via the gate insulating film 142. The detailed contents are the same as the contents of step S6 in FIG.

  In step S16, a source electrode and drain electrode formation step is performed. Specifically, the source electrode 144 and the drain electrode 145 are formed by using a well-known photolithography technique and dry etching. Thus, the semiconductor device 101 shown in FIG. 7 is completed.

  As described above, specific examples of the present invention have been described in detail, but these are merely examples, and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings can simultaneously achieve a plurality of objects, and has technical utility by achieving one of the objects.

(Modification)
The temperature of the annealing step is not limited to 850 ° C., and may be a temperature of 850 ° C. or less. As the temperature decreases, the rate of decrease in the hydrogen concentration of the low-concentration p-type GaN layer decreases, but it is possible to suppress the deterioration of crystallinity due to annealing.

  The group III nitride semiconductor constituting the semiconductor substrate 10 is not limited to GaN, but may be, for example, AlN (aluminum nitride), InN (indium nitride), or a mixed crystal thereof.

  In the above embodiment, magnesium (Mg) is used as an example of the group II element for forming the p-type region. However, the present invention is not limited to this configuration. The group II element may be, for example, beryllium (Be), calcium (Ca), or the like.

  The drift layer 34 is an example of an n-type GaN layer. The body layer 36 is an example of a low concentration p-type GaN layer. The body contact layer 46 and the contact layer 146 are examples of a high-concentration p-type GaN layer.

  1: semiconductor device, 10: semiconductor substrate, 32: drain layer, 34: drift layer, 36: body layer, 38: source region, 40: trench gate electrode, 42 and 142: gate insulating film, 46: body contact layer, 134: low concentration n-type GaN layer, 136: low concentration p-type GaN layer, 140: gate electrode, 146: contact layer, A1 and A101: open area

Claims (9)

Forming an n-type GaN layer on the GaN substrate by an epitaxial growth method;
Forming a low concentration p-type GaN layer on the upper surface of the n-type GaN layer by an epitaxial growth method;
Forming a high concentration p-type GaN layer on the upper surface of the low concentration p-type GaN layer by an epitaxial growth method;
An annealing step of diffusing hydrogen contained in the low-concentration p-type GaN layer into the high-concentration p-type GaN layer by annealing in an inert atmosphere;
A method for manufacturing a nitride semiconductor device, comprising: After the annealing step, exposing the low-concentration p-type GaN layer by removing the high-concentration p-type GaN layer in the opening region by etching;
Forming an n-type GaN region above the low-concentration p-type GaN layer in the opening region by implanting impurities into the opening region;
Forming a trench in a part of the opening region from the upper surface of the n-type GaN region to the n-type GaN layer;
Forming a gate electrode inside the trench via a gate insulating film;
The method for manufacturing a nitride semiconductor device according to claim 1, comprising: After the annealing step, exposing the low-concentration p-type GaN layer by removing the high-concentration p-type GaN layer in the opening region by etching;
Impurities are implanted into the source region and the drain region which are arranged apart from each other in the opening region, so that the source region of n-type GaN and the drain of n-type GaN are formed on the low concentration p-type GaN layer. Forming a region;
Forming a gate electrode via a gate insulating film on an upper surface of the low-concentration p-type GaN layer in a region between the source region and the drain region;
The method for manufacturing a nitride semiconductor device according to claim 1, comprising: an n-type GaN drift layer;
A low-concentration p-type GaN body layer in contact with the upper surface of the drift layer;
An n-type GaN source region disposed above the body layer;
A gate electrode region reaching the drift layer from the upper surface of the source region;
A high-concentration p-type GaN body contact layer disposed on an upper surface of the body layer and having an opening region, wherein at least a part of the source region and the gate electrode region are exposed inside the opening region The body contact layer;
A source electrode in contact with an upper surface of the source region and an upper surface of the body contact layer;
A nitride semiconductor device comprising:   The nitride semiconductor device according to claim 4, wherein a hydrogen concentration of said body layer is lower than a hydrogen concentration of said body contact layer. The body contact layer is a layer formed by epitaxial growth,
6. The nitride semiconductor device according to claim 4, wherein said source region is a region formed by ion implantation. A low concentration p-type GaN layer;
A source region of n-type GaN disposed on the low-concentration p-type GaN layer;
An n-type GaN drain region disposed above the low-concentration p-type GaN layer and separated from the source region;
A gate electrode disposed in a region between the source region and the drain region, wherein the gate electrode is disposed on a top surface of the low-concentration p-type GaN layer via a gate insulating film;
A high-concentration p-type GaN layer disposed on the upper surface of the low-concentration p-type GaN layer and having an opening region, wherein the gate electrode, at least a part of the source region, and the drain region are formed inside the opening region; Said high-concentration p-type GaN layer at least partially exposed;
A source electrode in contact with an upper surface of the source region and an upper surface of the high-concentration p-type GaN layer;
A drain electrode in contact with an upper surface of the drain region and an upper surface of the high-concentration p-type GaN layer;
A semiconductor device comprising:   The semiconductor device according to claim 7, wherein a hydrogen concentration of the low-concentration p-type GaN layer is lower than a hydrogen concentration of the high-concentration p-type GaN layer. The high-concentration p-type GaN layer is a layer formed by epitaxial growth,
9. The semiconductor device according to claim 7, wherein said source region and said drain region are regions formed by ion implantation.

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