JP6962063B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Conventionally, a semiconductor device having an N + source region and an N + high concentration region selectively provided on the N + semiconductor substrate side of the high concentration P + base region inside the high concentration P + base region is known (for example). , Patent Document 1). Note that Patent Document 1 does not describe in detail how the N + source region and the N + high concentration region are formed.
[Prior art literature]
[Patent Document]
[Patent Document 1] International Publication No. 2014/125586

In order to make the manufacturing process of the semiconductor device cheaper, the regions corresponding to the N + source region and the N + high concentration region can be formed more easily than by ion implantation using different masks. Is desirable.

In the first aspect of the present invention, a semiconductor device having a gallium nitride based semiconductor layer is provided. The gallium nitride based semiconductor layer may include a first conductive type drift region, a second conductive type base region, a first conductive type source region, and a counter region. The base region may be provided between the front surface of the gallium nitride based semiconductor layer and the drift region. The source region may be provided between the front surface of the gallium nitride based semiconductor layer and the base region. The source region may have a higher first conductive type impurity concentration than the drift region. The counter area may be provided between the base area and the drift area. The counter region may have a first conductive impurity concentration higher than the drift region and lower than the source region. The base region may contain a higher concentration of first conductive type impurities than the drift region. The first conductive type impurity concentration distribution in the base region may have a tendency to gradually decrease from the boundary between the base region and the source region to the boundary between the base region and the counter region.

The first conductive type impurity concentration distribution in the counter region may have a tendency to gradually decrease from the boundary between the base region and the counter region to the boundary between the counter region and the drift region.

The first conductive type impurity concentration distribution in the source region may have a tendency to gradually decrease from the front surface of the gallium nitride based semiconductor layer to the boundary between the source region and the base region.

The first conductive type impurity concentration distribution in the source region, the base region and the counter region may be continuous in the depth direction of the gallium nitride based semiconductor layer.

The concentration of impurities of the first conductive type in the base region may be higher than the concentration of impurities of the first conductive type in the counter region.

The concentration of impurities of the second conductive type in the base region may be higher than the concentration of impurities of the first conductive type in the counter region.

The gallium nitride based semiconductor layer may include two base regions and an upper drift region. The two base regions may be provided apart in a direction orthogonal to the depth direction of the gallium nitride based semiconductor layer. The upper drift region may be provided between the two base regions. The counter region may include a side region provided between the base region and the upper drift region. The concentration of impurities of the first conductive type in the side region may be higher than the concentration of impurities of the first conductive type in the upper drift region.

The concentration of impurities of the first conductive type in the counter region may be twice or more the concentration of impurities of the first conductive type in the drift region.

The thickness of the counter region in the depth direction of the gallium nitride based semiconductor layer may be 0.5 μm or more and 2 μm or less.

The thickness of the counter region in the direction orthogonal to the depth direction of the gallium nitride based semiconductor layer may be 0.4 μm or more and 1.6 μm or less.

When the gallium nitride based semiconductor layer is viewed from above, the range in which the source region is provided may correspond to the range in which the counter region is provided in a plane orthogonal to the depth direction of the gallium nitride based semiconductor layer.

A second aspect of the present invention provides a method for manufacturing a semiconductor device having a gallium nitride based semiconductor layer. The method for manufacturing a semiconductor device may include a step of forming a second conductive type base region, a step of injecting a first conductive type impurity into the base region, and a step of heat-treating a gallium nitride based semiconductor layer. The base region may be formed between the front surface of the gallium nitride based semiconductor layer and the drift region. The step of injecting the first conductive type impurities into the base region may be aimed at forming a peak of the first conductive type impurity concentration at a position shallower than the bottom of the base region. After the heat treatment step, the gallium nitride based semiconductor layer may have a base region, a first conductive type source region, and a counter region. The source region may be located between the front surface of the gallium nitride based semiconductor layer and the base region. The source region may have a higher first conductive type impurity concentration than the drift region. The counter area may be located between the base area and the drift area. The counter region may have a first conductive impurity concentration higher than the drift region and lower than the source region. The base region may contain a higher concentration of first conductive type impurities than the drift region. The first conductive type impurity concentration distribution in the base region may have a tendency to gradually decrease from the boundary between the base region and the source region to the boundary between the base region and the counter region.

At the stage of injecting the first conductive type impurities into the base region, the first conductive type is formed into the base region via one mask material layer so that the source region and the counter region are formed by one photolithography process. Impurities may be injected.

After the step of forming the base region, the step of injecting the first conductive type impurities into the base region may be performed. In addition, a heat treatment step may be performed after the step of injecting the first conductive type impurities into the base region.

At the stage of injecting the first conductive type impurities into the base region, peaks of the first conductive type impurity concentration may be formed at a position shallower than the bottom of the base region and a position deeper than the base region.

The outline of the above invention does not list all the necessary features of the present invention. Sub-combinations of these feature groups can also be inventions.

It is sectional drawing of the semiconductor device 100 in 1st Embodiment. It is a figure which shows the impurity concentration distribution corresponding to AA and BB of FIG. It is a figure which shows the invalid region 60-A and the JFET resistance region 62-A in the 1st comparative example. It is a figure which shows the invalid region 60-B and the JFET resistance region 62-B in the 1st Embodiment. (A) to (g) are diagrams showing a manufacturing process of the semiconductor device 100. It is a partially enlarged view when the semiconductor device 100 is viewed from the top. It is a figure which shows the N-type impurity concentration distribution before the heat treatment in the 1st modification. It is sectional drawing of the semiconductor device 200 in 2nd Embodiment. (A) to (g) are diagrams showing a manufacturing process of the semiconductor device 200. It is a figure which shows the invalid region 60-C in the 2nd comparative example. It is a figure which shows the invalid region 60-D in the 2nd Embodiment. It is a partially enlarged view when the semiconductor device 200 is viewed from the top.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the inventions that fall within the scope of the claims. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

FIG. 1 is a cross-sectional view of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 of this example is a semiconductor chip including a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a planar gate structure. In this example, since the base region 24 and the source region 26 are formed by impurity diffusion, the semiconductor device 100 has a DMOS (Double Diffused MOSFET) structure.

FIG. 1 is also a YY cross-sectional view of the semiconductor device 100. In this example, the X-axis direction and the Y-axis direction are orthogonal to each other, and the Z-axis direction is a direction orthogonal to the XY plane. The X, Y and Z axes form a so-called right-handed system. In this example, the positive direction (+ Z direction) of the Z axis may be referred to as "up", and the negative direction of the Z axis (−Z direction) may be referred to as “down”. However, "above" and "below" do not necessarily mean the vertical direction with respect to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. "Upper" and "lower" are merely convenient expressions for specifying relative positional relationships in regions, layers, films, substrates, and the like. In this example, the downward direction may be expressed as the depth direction.

The semiconductor device 100 of this example includes a gallium nitride (hereinafter referred to as GaN) substrate 10, a GaN layer 20, a gate insulating film 32, a gate electrode 30, a source electrode 40, and a drain electrode 50. The GaN substrate 10 is an example of a gallium nitride based semiconductor substrate, and the GaN layer 20 is an example of a gallium nitride based semiconductor layer.

In this example, the GaN-based semiconductor is GaN. However, the GaN-based semiconductor may contain one or more elements of aluminum (Al) and indium (In). The composition formula of the GaN-based semiconductor may be a mixed crystal semiconductor containing a small amount of Al and In, that is, Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1). .. The composition formula of the GaN-based semiconductor of this example is GaN in which x = y = 0 in _{Al x} In _y Ga _{1-xy N.}

The GaN substrate 10 of this example is an N + type substrate. The GaN substrate 10 may be a low dislocation self-supporting substrate. The GaN substrate 10 of this example has a through dislocation density of less than ^{1E + 7 [cm-2].} In addition, E represents the power of 10. For example, 1E + 7 means 1 × 10 ⁷ . By setting the GaN substrate 10 to a low dislocation density, the dislocation density of the GaN layer 20 formed on the GaN substrate 10 can be reduced. In addition, it is possible to prevent the ion-implanted impurities from diffusing deeply along the dislocations during the heat treatment. Further, by using such a low dislocation substrate, the leakage current can be reduced even if a power device having a large area is formed, so that the power device can be manufactured at a high non-defective rate.

In this example, N or P means that the electrons or holes are multiple carriers, respectively. For + or-to the right of N or P, + means higher carrier concentration than the one without it, and-means lower carrier concentration than the one without it. In this example, the N type is the first conductive type, and the P type is the second conductive type. However, in another example, the P type may be the first conductive type, and the N type may be the second conductive type.

The N-type impurity for GaN may be one or more elements of Si (silicon), Ge (germanium) and O (oxygen). In this example, Si is used as the N-type impurity. Further, the P-type impurity for GaN may be one or more kinds of elements such as Mg (magnesium), Ca (calcium), Be (beryllium) and Zn (zinc). In this example, Mg is used as the P-type impurity.

The GaN layer 20 may be provided on the GaN substrate 10. The GaN layer 20 of this example is a layer formed by epitaxial growth on the GaN substrate 10. In this example, the interface between the GaN substrate 10 and the GaN layer 20 is defined as the boundary 12. Further, in this example, the first main surface of the GaN substrate 10 is the boundary 12, and the second main surface of the GaN substrate 10 is the back surface 16 opposite to the boundary 12. Further, in this example, the first main surface of the GaN layer 20 is the front surface 14 opposite to the boundary 12, and the second main surface of the GaN layer 20 is the boundary 12. In this example, the direction from the front surface 14 to the boundary 12 is the depth direction of the GaN layer 20.

The GaN layer 20 of this example has an N-type drift region 22, a P-type base region 24, an N + type source region 26, and an N-type counter region 27. The GaN layer 20 shown in FIG. 1 has two base regions 24-1 and 24-2 and two source regions 26-1 and 26-2, which are provided apart from each other in the Y-axis direction. Have. The base region 24 and the source region 26 may be well regions provided from the front surface 14 to a predetermined depth of the GaN layer 20. The base region 24 of this example is provided between the front surface 14 and the drift region 22 in the depth direction. Further, the source region 26 of this example is provided between the front surface 14 and the base region 24 in the depth direction.

The source region 26 may have the function of providing a low resistance path for electron currents. A portion of the source region 26 may be in contact with the source electrode 40 on the front surface 14. The bottom and sides of the source region 26 may be in contact with the base region 24.

The counter region 27 may be formed at the same time as the source region 26 is formed. The counter region 27 of this example is formed through a step of ion-implanting N-type impurities to form the source region 26 and a step of activating the injected impurities by heat treatment. The counter region 27 of this example is formed by thermally diffusing N-type impurities ion-implanted to form the source region 26 by heat treatment. The counter region 27 may have an N-type impurity concentration higher than the drift region 22 and lower than the source region 26.

The counter region 27 may project more than the base region 24 in the XY plane direction and the Z axis direction. The counter area 27 of this example has a bottom area 29 and a side area 28. The side region 28 of this example is provided between the base region 24 and the upper drift region 23 at least in the Y-axis direction. The side region 28 may be provided between the base region 24 and the upper drift region 23 in the X-axis direction. Further, the bottom region 29 of this example is provided between the base region 24 and the drift region 22 in the Z-axis direction.

The upper drift region 23 may be part of the drift region 22. The upper drift region 23 of this example is a part of the drift region 22 provided between the two base regions 24 at least in the Y-axis direction. The bottom of the upper drift region 23 may coincide with the bottom of the bottom region 29 in the counter region 27. As a result of the N-type impurities being isotropically diffused from the source region 26 to the base region 24 and reaching the drift region 22 beyond the side portion of the base region 24, the upper drift region 23 is the remaining region of the drift region 22. May be formed as. The upper drift region 23 and the side region 28 may be a part of a JFET (Junction Field Effect Transistor) region.

The base region 24 of this example includes a channel forming region 25. The channel formation region 25 is a region in which a charge inversion layer is formed when a predetermined positive voltage is applied to the gate electrode 30 (when the gate is turned on). The channel forming region 25 of this example is a part of the base region 24 located directly below the gate electrode 30 and the gate insulating film 32. The channel forming region 25 of this example is located between the source region 26 and the side region 28 of the counter region 27 at least in the Y-axis direction. In FIG. 1, the length of the channel forming region 25 in the Y-axis direction is shown as the channel length L.

The base region 24 of this example is located on the side opposite to the side region 28 in the Y-axis direction, and has a portion in which N-type impurities thermally diffused from the source region 26 do not exist. In FIG. 1, the boundary between the region where the N-type impurity is present and the region where the N-type impurity is not present in the base region 24 is shown by a broken line. For example, in the base region 24-1 in the −Y direction from the broken line and in the base region 24-2 in the + Y direction from the broken line, there is a region in which N-type impurities thermally diffused from the source region 26 do not exist. The source electrode 40 may come into contact with a part of the base region 24 in which the N-type impurity is present and a part of the base region 24 in which the N-type impurity is not present.

In another example, the GaN layer 20 may have a P + -shaped contact region in contact with the source electrode 40. The contact region may be provided from the front surface 14 to a predetermined depth position shallower than the base region 24. The contact region may be formed via epitaxial growth or ion implantation. The contact region may have a function of reducing the contact resistance between the GaN layer 20 and the source electrode 40 and a function of providing a hole extraction path at the time of gate off.

The gate electrode 30 may be provided on the gate insulating film 32. The gate electrode 30 of this example is located at least above the upper drift region 23, the side region 28, and the channel forming region 25. The gate electrode 30 may be formed of aluminum (Al), or may be formed of impurity-doped polysilicon.

The source electrode 40 may be provided on the front surface 14. The source electrode 40 of this example is in contact with a part of the source region 26 and a part of the base region 24 different from the channel forming region 25. The source electrode 40 may have a titanium (Ti) layer that contacts the front surface 14 and functions as a barrier metal layer, and an Al layer that contacts the Ti layer. The source electrode 40 may be a nickel (Ni) layer instead of the laminated structure of the Ti layer and the Al layer.

The source electrode 40 may be electrically separated from the gate electrode 30 by an interlayer insulating film. In one example, the source electrode 40 may also be provided on the interlayer insulating film provided on the gate electrode 30. The drain electrode 50 may be provided under the back surface 16 in contact with the back surface 16. The drain electrode 50 may also be made of the same material as the source electrode 40.

In FIG. 1, the gate terminal, the source terminal, and the drain terminal are indicated by G, D, and S, respectively. For example, when a potential equal to or higher than the threshold voltage is applied to the gate electrode 30 via the gate terminal, a charge inversion layer is formed in the channel forming region 25. For example, when the drain electrode 50 has a predetermined high potential and the source electrode 40 has a ground potential, and a charge inversion layer is formed in the channel formation region 25, a current flows from the drain terminal to the source terminal. Further, for example, when a potential lower than the threshold voltage is applied to the gate electrode 30, the charge inversion layer disappears and the current is cut off. Thereby, the semiconductor device 100 can control the current between the source terminal and the drain terminal.

FIG. 2 is a diagram showing an impurity concentration distribution corresponding to AA or BB of FIG. AA is a straight line parallel to the Y-axis direction passing through the source region 26, the channel formation region 25, and the side region 28 of the counter region 27. On the other hand, BB is a straight line parallel to the Z-axis direction passing through the source region 26, the base region 24, and the bottom region 29 of the counter region 27. In this example, the impurity concentration of AA was measured, but those skilled in the art can reasonably understand that the impurity concentration of BB is the same as that of AA.

FIG. 2 shows the Mg and Si concentration distributions obtained by SIMS (Secondary Ion Mass Spectrometry) analysis. The Mg and Si concentration distribution when the heat treatment temperature is 1100 ° C. is shown by a solid line, and the Mg and Si concentration distribution when the heat treatment temperature is 1300 ° C. is shown by a broken line. The vertical axis shows the impurity concentration [cm ^-3 ]. The horizontal axis indicates the depth position [nm] when the front surface 14 has a depth of zero.

The Mg concentration distribution has a flat region in the depth range of about zero nm to about 500 nm. The Mg concentration distribution of this example may be formed by injecting Mg so as to have a plurality of impurity concentration peaks at different depth positions and then heat-treating. Since Mg is less likely to be thermally diffused than Si, the impurity concentration may suddenly decrease in the depth direction than Si in the range deeper than about 500 nm in Mg concentration distribution.

In this example, the range in which the Mg concentration is higher than the Si concentration and is 1E + 17 cm ^-3 or more is defined as the base region 24. The boundary between the base region 24 and the counter region 27 is a depth position ^{where the Mg concentration is 1E + 17 cm -3.} Of course, the base region 24 has a P-type impurity concentration equal to or higher than the N-type impurity concentration. In the base region 24 of this example, the Mg concentration is equal to or higher than the Si concentration.

As described above, the Si concentration distribution may be formed by thermal diffusion of N-type impurities in the source region 26. The Si concentration distribution of this example has a concentration peak of E + 20 units near the front surface 14. The Si concentration distribution tends to gradually decrease from the front surface 14, and becomes ^{about 1E + 18 cm -3 at a depth of about 200 nm.} The Si concentration is equal to or less than the Mg concentration at a depth of about 200 nm. That is, the source region 26 is from the front surface 14 to the position at a depth of about 200 nm, and the position at a depth of about 200 nm is the boundary between the source region 26 and the base region 24. In FIG. 2, the range of the source region 26 at 1100 ° C. is shown with double-headed arrows.

The Si concentration distribution may be continuous from the source region 26 to the base region 24. Further, the Si concentration distribution in the base region 24 may have a tendency to decrease more rapidly in the depth direction than the source region 26. In this example, the Si concentration distribution in the base region 24 tends to gradually decrease from the boundary between the base region 24 and the source region 26 to the boundary between the base region 24 and the counter region 27. The Si concentration in the base region 24 is lower than the source region 26, higher than the counter region 27, and higher than the drift region 22. When the heat treatment temperature is 1100 ° C., the Si concentration in the base region 24 is equal to or higher than the Mg concentration at a depth of about 700 nm, and when the heat treatment temperature is 1300 ° C., the Si concentration is higher than the Mg concentration at a depth of about 900 nm. In FIG. 2, a double-headed arrow is added to the range of the base region 24 at 1100 ° C.

In this example, by thermally diffusing the ion-implanted Si to form the source region 26, a Si concentration distribution that gradually decreases continuously in the depth direction in the source region 26, the base region 24, and the counter region 27 is obtained. Form. Therefore, it is not necessary to separately provide the mask material layer for forming the source region 26 and the mask material layer for forming the counter region 27. In this example, since the source region 26 and the counter region 27 can be formed through ion implantation and heat treatment using the mask material layer for forming the source region 26, compared with the case where the mask material layer is individually provided. Therefore, the manufacturing process of the semiconductor device 100 can be reduced, and therefore the cost of the manufacturing process can be reduced.

The Si concentration distribution may be continuous from the base region 24 to the counter region 27. Further, the Si concentration in the counter region 27 may have a tendency to be further reduced than that in the base region 24. In this example, the Si concentration in the counter region 27 is lower than the base region 24 and higher than the drift region 22. In this example, the Si concentration in the drift region 22 is 1E + 16 cm ^-3 . Although not shown in FIG. 2, in this example, the boundary between the counter area 27 and the drift area 22 (that is, the boundary between the side area 28 and the upper drift area 23 and the boundary between the bottom area 29 and the drift area 22) is It is a depth position where the ^{Si concentration becomes 2E + 16 cm -3} only after the Si concentration decreases from the front surface 14.

The Si concentration distribution in the counter region 27 may have a tendency to gradually decrease from the boundary between the base region 24 and the counter region 27 to the boundary between the counter region 27 and the drift region 22. In this example, the Si concentration in the bottom region 29 is higher than the Si concentration in the drift region 22. Similarly, in BB, the Si concentration in the side region 28 is higher than the Si concentration in the upper drift region 23.

The N-type impurity concentration in the counter region 27 may be 2 times or more and 10 times or less the N-type impurity concentration in the drift region 22. The Si concentration in the counter region 27 may be lower than the Mg concentration in the base region 24. By doubling or more the N-type impurity concentration, the JFET resistance in the upper drift region 23 can be reduced. Further, by setting the value to 10 times or less, it is possible to prevent the P-type impurities in the base region 24 from being compensated by the N-type impurities and making it difficult for the P-type to be expressed in the base region 24.

The inventor of the present application has confirmed that the N-type impurities ion-implanted into the source region 26 in the GaN layer 20 have thermally diffused beyond the P-type base region 24 in the GaN layer 20. Generally, in a Si-doped GaN semiconductor formed by epitaxial growth and containing Si as an N-type impurity, the N-type impurity does not diffuse in the GaN semiconductor even if it is heat-treated at 1300 ° C. It is presumed that the diffusion of impurities in the GaN semiconductor is caused by, for example, the thermal diffusion of point defects introduced into the GaN semiconductor by ion implantation. Further, as far as the inventor of the present application knows, it has not been reported so far that the counter region 27 is formed by the N-type impurity ion-implanted into the source region 26 in the GaN semiconductor. In the silicon carbide (SiC) semiconductor, when boron (B) as a P-type impurity is ion-implanted into the SiC semiconductor and the SiC semiconductor is thermally annealed at a high temperature of about 1700 ° C., the thermal diffusion of boron is performed. Was confirmed. However, with respect to N-type impurities for SiC semiconductors and P-type impurities other than boron, it has not been confirmed that the ions implanted by ions are thermally diffused by thermal annealing up to about 1700 ° C.

FIG. 3A is a diagram showing an invalid region 60 and a JFET resistance region 62 in the first comparative example. The semiconductor device 300 in the first comparative example is different from the semiconductor device 100 of the first embodiment in that it does not have a counter region 27.

In FIG. 3A, the current flowing from the drain electrode 50 to the source electrode 40 after the gate is turned on is indicated by an arrow. When the drain electrode 50 has a predetermined high potential and the source electrode 40 has a ground potential, a JFET resistance region 62-A that serves as a resistance to a current is formed in the upper drift region 23. The JFET resistance region 62 is indicated by a broken line square. The JFET resistance region 62 can be generated by narrowing the current passage as a result of the expansion of the depletion layer formed at the PN junction between the upper drift region 23 and the base region 24 by the electric field between the source electrode 40 and the drain electrode 50. ..

Further, in this example, in the drift region 22 located immediately below the base region 24, there is an invalid region 60-A in which no current flows or the current density is relatively low. In FIG. 3A, the invalid region 60-A is shown with diagonal lines. The larger the invalid region 60-A, the higher the spread resistance under the upper drift region 23. The boundary between the region where current flows or the current density is relatively high and the invalid region 60-A is indicated by a broken line.

FIG. 3B is a diagram showing an invalid region 60 and a JFET resistance region 62 in the first embodiment. Also in FIG. 3B, the current flowing from the drain electrode 50 to the source electrode 40 after the gate is turned on is indicated by an arrow. In this example, by providing the side region 28 having an N-type impurity having a higher concentration than the drift region 22, the expansion of the depletion layer is suppressed as compared with the first comparative example. As a result, the JFET resistance can be reduced as compared with the first comparative example. Further, in this example, by providing the bottom region 29, the range in which the invalid region 60-B is formed becomes narrower than the invalid region 60-A in the first comparative example. Therefore, the spread resistance can be reduced as compared with the first comparative example. In FIG. 3B, the invalid region 60-B is shown with diagonal lines.

FIG. 4 is a diagram showing a manufacturing process of the semiconductor device 100. FIG. 4A is a step of epitaxially growing the GaN layer 20 on the GaN substrate 10. The GaN layer 20 may be formed by an organometallic growth method (MOCVD), a halide vapor phase growth method (HVPE), or the like. The Si concentration of the GaN layer 20 ^{may be 1E + 15cm -3} or more and 2E + 16cm ^-3 or less. However, in this example, the Si concentration of the GaN layer 20 is 1E + 16 cm ^-3 . The thickness of the GaN layer 20 (that is, the length from the boundary 12 to the front surface 14) may be changed according to the withstand voltage, but is, for example, 5 μm or more and 20 μm or less.

FIG. 4B is a step of forming a base region 24 between the front surface 14 of the GaN layer 20 and the drift region 22. In this example, after forming the mask material layer 70-1 having a predetermined opening 72-1 in the region corresponding to the base region 24, Mg is ion-implanted through the mask material layer 70-1. The mask material layer 70-1 may be a photoresist layer that can be selectively removed from the GaN layer 20, and may be a silicon dioxide (SiO ₂ ) layer instead. When the mask material layer 70 is a SiO ₂ layer, the thickness of the mask material layer 70 may be relatively thin in the range corresponding to the opening 72 of the photoresist layer, and the range not corresponding to the opening 72 of the photoresist layer is relative. It may be thick.

The acceleration energy of ion implantation may be changed according to the implantation depth. Acceleration energy may be proportional to the acceleration voltage for a given ion valence. The larger the acceleration energy, the deeper the injection depth can be. In this example, the acceleration voltages 20, 40, 70, 110, 150, 200, 250 and 430 (all units are keV) and the dose amount of 1E + 12cm ^-2 or more and 1E + 14cm ^-2 or less are injected into the GaN layer 20 in multiple stages to obtain Mg ions. Inject. As a result, the Mg concentration distribution in the depth direction becomes a box profile. The smaller the acceleration energy, the smaller the dose amount, and the larger the acceleration energy, the larger the dose amount. The injection depth may range from the front surface 14 to a depth of 1.25 μm. It should be noted that it is not always necessary to perform multi-stage injection, and it may be a single injection. After ion implantation, the mask material layer 70-1 is removed.

In this example, the step of forming the base region 24 may be the step of ion-implanting Mg, and it is not necessary that the P-type impurity implanted in the base region 24 is activated as an acceptor. In this example, Mg is activated to function as an acceptor by performing heat treatment after ion-implanting Mg into the drift region 22.

FIG. 4C is a step of injecting an N-type impurity into the base region 24. In this example, after forming the mask material layer 70-2 having a predetermined opening 72-2 in the region corresponding to the source region 26, Si is ion-implanted through the mask material layer 70-2. As a result, a Si concentration peak is formed at a depth position shallower than the bottom of the base region 24.

In this example, Si is ion-implanted into the base region 24 by multi-stage implantation via the mask material layer 70-2. ^{More specifically, the dose amount is 6E + 14 [cm-2} ] at an acceleration voltage of 30 [keV], the dose amount ^{is 8E + 14 [cm-} 2] at an acceleration voltage of 60 [keV], and the dose amount is 1.6E + 15 [keV] at an acceleration voltage of 80 [keV]. cm ^-2] and an acceleration voltage 160 [keV] under the condition that a dose of 3E + 15 ^{[cm -2],} ion implantation of Si to the base region 24. As a result, the Si concentration distribution in the depth direction becomes a box profile.

In this example, Si is injected into the base region 24 via one mask material layer 70-1 in order to form the source region 26 and the counter region 27 in a single photolithography process. In one photolithography process, each step of coating, exposing, developing and etching the photoresist and removing the photoresist may be performed once. In this example, one mask material layer 70 means the mask material layer 70 formed in this one photolithography process. Therefore, in this example, the mask material layer 70 having the pattern of the openings 72 for forming the source region 26 and the mask material layer 70 having the pattern of the openings 72 for forming the counter region 27 are the same. The mask material layer 70.

In this example, one photomask can be used to form the mask material layer 70-1. Therefore, the number of manufacturing steps can be reduced and the cost required for the manufacturing process can be reduced as compared with the case where different patterns of the mask material layer 70 are used in the source region 26 and the counter region 27. Therefore, the semiconductor device 100 can be manufactured at a lower cost.

In addition, since the ion implantation for forming the counter region 27 can be performed in the ion implantation for forming the source region 26, the ion implantation for forming the counter region 27 can be performed in a self-aligned manner. Therefore, it is possible to eliminate the influence of the mask misalignment that may occur when the source region 26 and the counter region 27 are formed by the individual mask material layers 70. Therefore, the source region 26 and the counter region 27 can be further miniaturized because a margin considering the mask position shift is not required.

FIG. 4D is a step of heat-treating the GaN layer 20. Before the GaN layer 20 is heat-treated, a cap layer may be formed on the entire surface of the front surface 14. As a result, it is possible to reduce the release of nitrogen from the GaN layer 20. Considering that it has high heat resistance, good adhesion to the front surface 14, that impurity diffusion does not diffuse from the cap layer to the GaN layer 20, and that it can be selectively removed from the GaN layer 20. The cap layer is preferably an aluminum nitride (AlN) layer. After forming the cap layer, the laminate of the GaN substrate 10, the GaN layer 20, and the cap layer may be placed in the heat treatment apparatus, and the laminate may be heat-treated at a temperature of 1100 ° C. or higher and 1400 ° C. or lower. The cap layer is removed after the heat treatment.

In this example, after the base region 24 is formed, N-type impurities are injected into the base region 24, and then heat treatment is performed. As a result, the N-type impurity is easily implanted into the drift region 22 through the defect formed in the base region 24 when the P-type impurity is ion-implanted, and the N-type impurity is easily thermally diffused into the drift region 22. .. As a result, the counter region 27 is more likely to be formed as compared with the case where the P-type impurity is ion-implanted to form the base region 24 after the N-type impurity is ion-implanted and then the heat treatment is performed.

After the heat treatment step, the activation of impurities in the drift region 22, the base region 24, the source region 26, and the counter region 27 described in the description of FIGS. 1 and 2 is completed. The Mg concentration in the base region 24 after the heat treatment step ^{may be 5E + 16cm -3} or more and 2E + 18cm ^-3 or less. However, in this example, the Mg concentration in the base region 24 is 1E + 17cm ^-3 or more and 2E + 18cm ^-3 or less. Further, the length of the base region 24 in the Z direction after the heat treatment step may be 0.5 μm or more and 2 μm or less. In this example, the length of the base region 24 in the Z direction is about 0.5 μm. The mask material layer 70-1 is removed after ion implantation.

The Si concentration in the source region 26 after the heat treatment step ^{may be 1E + 18cm -3} or more and 2E + 20cm ^-3 or less. Further, the length of the source region 26 in the Z direction after the heat treatment step may be 0.1 μm or more and 0.2 μm or less. The Si concentration in the counter region 27 after the heat treatment step ^{may be 2E + 16cm -3} or more and 1E + 17cm ^-3 or less. Further, the thickness of the source region 26 after the heat treatment step may be 0.1 μm or more and 2 μm or less.

At the stage of injecting N-type impurities into the base region 24, if there is no resist dripping at the end of the mask material layer 70-2 in the XY plane direction and the shape is sharp, the thermal diffusion of N-type impurities is achieved. The degree may be 0.8 in the XY plane direction when the Z-axis direction is 1. That is, in the counter region 27, the thickness of the side region 28 in the XY plane direction and the thickness of the bottom region 29 in the Z-axis direction may be different.

In this example, the thickness of the bottom region 29 in the depth direction is 0.5 μm or more and 2 μm or less, and the thickness of the side region 28 in the XY plane direction is 0.4 μm or more and 1.6 μm or less. .. For example, the bottom region 29 has a thickness of 1 μm, and correspondingly, the side region 28 of this example has a thickness of 0.8 μm. By setting the thickness of the bottom region 29 to 0.5 μm or more and the thickness of the side region 28 to 0.4 μm or more, it is possible to ensure that the JFET resistance and the spread resistance are reduced. Further, by setting the thickness of the bottom region 29 to 2 μm or less and the thickness of the side region 28 to 1.6 μm or less, the P-type impurities in the base region 24 are compensated by the N-type impurities, and P in the base region 24. It is possible to prevent the type from becoming difficult to express.

FIG. 4 (e) is a stage of forming the gate insulating film 32. In this example, the gate insulating film 32 is formed so as to cover the entire front surface 14. For example, PECVD (Plasma-Enhanced Chemical Vapor Deposition) _{forms a SiO 2} film or an aluminum oxide (Al ₂ O ₃ ) film having a diameter of 50 nm or more and 100 nm or less.

FIG. 4F is a stage of forming the gate electrode 30. In this example, the gate electrode 30 is formed by depositing an Al layer or a polysilicon layer and then processing it into a predetermined shape. After forming the gate electrode 30, for example, using the gate electrode 30 as a mask, the gate insulating film 32 formed in FIG. 4 (e) is etched so as to have a predetermined shape. The gate insulating film 32 may be processed into a predetermined shape by using a photolithography step.

FIG. 4 (g) is a stage of forming the source electrode 40 and the drain electrode 50. In this example, the Ti layer and the Al layer are sequentially deposited, and then the source electrode 40 and the drain electrode 50 are formed through photolithography, etching, and the like.

FIG. 5 is a partially enlarged view of the semiconductor device 100 when viewed from above. For the purpose of facilitating understanding, the film and electrodes on the front surface 14 are omitted, and the source region 26 and the counter region 27 are shown with diagonal lines. The cross-sectional view that passes through I-I and is parallel to the Z-axis direction corresponds to the semiconductor device 100 below the front surface 14 in FIG.

In this example, one unit structure 90 includes a hexagonal ring-shaped counter region 27, a base region 24, a source region 26, and a hexagonal base region 24. The hexagonal ring-shaped counter region 27 may be located on the outermost side of the unit structure 90. The hexagonal ring-shaped counter region 27 observed in top view may correspond to the side region 28.

The hexagonal ring-shaped base region 24 may be located between the counter region 27 and the source region 26. The length L connecting the counter region 27 and the source region 26 with a straight line may correspond to the channel length L of the channel formation region 25 in the base region 24. A hexagonal base region 24 may be provided on the innermost side of the unit structure 90. The hexagonal base region 24 may be a part of the base region 24 in which N-type impurities that are thermally diffused from the source region 26 have not reached. The hexagonal base region 24 may be part of the base region 24 located below the source electrode 40 rather than below the gate electrode 30.

In this example, the outer circumference of the counter region 27 corresponds to the boundary between the side region 28 and the upper drift region 23. An upper drift region 23 may be located between two adjacent unit structures 90. The upper drift region 23 may be provided in a honeycomb structure between the unit structures 90 in a top view.

In this example, due to the formation process of the counter region 27, the range in which the source region 26 is provided corresponds to the range in which the counter region 27 is provided in the XY plane. More specifically, the range in which the source area 26 is provided is included in the range in which the counter area 27 is provided. Further, the range in which the source area 26 is provided may be similar to the range in which the counter area 27 is provided.

FIG. 6 is a diagram showing the N-type impurity concentration distribution before the heat treatment in the first modification. The horizontal axis indicates the depth direction. The vertical axis shows the concentration of N-type impurities. In the first modification, at the stage of injecting the N-type impurity into the base region 24, the peak P4 of the N-type impurity concentration is formed at a position shallower than the bottom of the base region 24 and a position deeper than the base region 24. .. Note that FIG. 6 shows the impurity concentration distribution before the stage of heat treatment. However, after the heat treatment step, the peak derived from the peak P4 may remain.

In this example, a Si concentration peak is formed at each of the positions P1, P2, and P3 having different depth ranges corresponding to the source region 26, and at the depth position P4 corresponding to the bottom region 29 of the counter region 27. It forms a peak of Si concentration. In this example, since the concentration of N-type impurities in the bottom region 29 can be increased as compared with the first embodiment, the spreading resistance can be further reduced.

In another modification, the source region 26, the counter region 27, and the base region 24 may be formed by one mask material layer 70. Specifically, in order to form the base region 24, Mg is ion-implanted through the opening 72 of the mask material layer 70, and then the same mask material layer 70 is continuously formed in order to form the source region 26 and the counter region 27. Si may be ion-implanted through the opening 72 of the. As a result, the cost required for the manufacturing process of the semiconductor device can be further reduced. However, as a trade-off, it may be difficult to control the channel length L.

FIG. 7 is a cross-sectional view of the semiconductor device 200 according to the second embodiment. The semiconductor device 200 of this example is a semiconductor chip including a vertical MOSFET having a trench-type gate structure. The trench portion 80 of this example penetrates the base region 24 and reaches the drift region 22. The trench portion 80 has a gate insulating film 32 provided in contact with the inner wall of the trench and a gate electrode 30 provided in contact with the gate insulating film 32 so as to fill the trench. In this example, the base region 24 is formed by epitaxial growth, and the source region 26 is formed by impurity diffusion.

Also in this example, the range in which the thermally diffused N-type impurities are present in the base region 24 is indicated by a broken line. Unlike the first embodiment, the GaN layer 20 of this example does not have an upper drift region 23. Therefore, the counter region 27 of this example does not have a side region 28 but has a bottom region 29. This example is mainly different from the first embodiment in these points. In this example, CC passing through the source region 26, the channel formation region 25, and the bottom region 29 in the counter region 27 and parallel to the Z-axis direction corresponds to AA and BB in FIG. do.

FIG. 8 is a diagram showing a manufacturing process of the semiconductor device 200. FIG. 8A is a stage of forming the base region 24. In this example, the epitaxial layer 21 corresponding to the base region 24 is formed between the front surface 14 of the GaN layer 20 and the drift region 22. In this example, a raw material gas containing trimethylgallium (TMGa), ammonia (NH ₃ ) and biscyclopentadienyl magnesium (Cp ₂ Mg), and a pressing gas containing _{nitrogen (N 2} ) and hydrogen (H _2). Is supplied onto the hot drift region 22. As a result, the P-type epitaxial layer 21 is formed. In addition, _{Mg of Cp 2} Mg can function as a P-type impurity. In this example, the upper surface of the base region 24 corresponds to the front surface 14 of the GaN layer 20.

FIG. 8B is a step of injecting an N-type impurity into the base region 24. Also in this example, Si is injected into the base region 24 through one mask material layer 70-3 having openings 72-3 to form the source region 26 and the counter region 27 in a single photolithography process. ..

FIG. 8C is a step of heat-treating the GaN layer 20. Also in this example, after forming the base region 24, N-type impurities are injected into the base region 24, and then heat treatment is performed. Also in this example, the N-type and P-type impurities are activated so that the impurities injected after the heat treatment step function as donors and acceptors.

FIG. 8D is a step of removing a part of the GaN layer 20 by etching in order to form the trench 82. FIG. 8 (e) is a stage of forming an insulating film. In this example, an insulating film is formed so as to cover the entire front surface 14 and the bottom surface and the side surface of the trench 82. Since the material and the manufacturing method overlap with FIG. 4D, the description thereof will be omitted. FIG. 8 (f) is a stage of forming the gate electrode 30. In this example, the gate electrode 30 is formed by depositing an Al layer or a polysilicon layer and then removing the deposited layer protruding above the insulating film.

FIG. 8 (g) is a step of forming the source electrode 40 and the drain electrode 50. In this example, the insulating film is processed into a predetermined shape to form the gate insulating film 32. After that, the Ti layer and the Al layer may be sequentially deposited, and then the source electrode 40 and the drain electrode 50 may be formed through photolithography, etching, and the like.

FIG. 9A is a diagram showing an invalid region 60-C in the second comparative example. The semiconductor device 400 in the second comparative example is different from the semiconductor device 200 of the second embodiment in that it does not have the counter region 27. In FIG. 9A, the current flowing from the drain electrode 50 to the source electrode 40 after the gate is turned on is indicated by an arrow. An invalid region 60-C exists in the drift region 22 located immediately below the base region 24. The boundary between the region where current flows or the current density is relatively high and the invalid region 60-C is indicated by a broken line.

FIG. 9B is a diagram showing an invalid region 60-D in the first embodiment. Also in FIG. 9B, the current flowing from the drain electrode 50 to the source electrode 40 after the gate is turned on is indicated by an arrow. Also in this example, by providing the bottom region 29 which is a part of the counter region 27, the range in which the invalid region 60-D is formed becomes narrower than the invalid region 60-C in the second comparative example. Therefore, the spread resistance can be reduced as compared with the second comparative example.

FIG. 10 is a partially enlarged view of the semiconductor device 200 when viewed from above. For the purpose of facilitating understanding, the film and electrodes on the front surface 14 are omitted, and the source region 26 and the counter region 27 are shown with diagonal lines. The cross-sectional view that passes through VII-VII and is parallel to the Z-axis direction corresponds to the semiconductor device 200 below the front surface 14 in FIG.

In this example, one unit structure 95 includes a hexagonal ring-shaped source region 26 and a hexagonal base region 24. The outer circumference of the counter region 27 corresponds to the outer circumference of the hexagonal ring-shaped source region 26. The innermost circumference of the counter region 27 is indicated by a broken line in the hexagonal base region 24. The counter area 27 of this example has a hexagonal ring shape. However, the counter area 27 of this example has only the bottom area 29, and the base area 24 and the source area 26 are present on the bottom area 29.

In this example, the hexagonal base region 24 located inside the broken line is a part of the base region 24 in which the N-type impurities that thermally diffuse from the source region 26 do not reach. The hexagonal base region 24 may be part of the base region 24 located below the source electrode 40 rather than below the gate electrode 30.

In this example, the gate insulating film 32 and the gate electrode 30 may be located between the two adjacent unit structures 95. The gate insulating film 32 and the gate electrode 30 may be provided in a honeycomb structure between the unit structures 95 in a top view.

In this example, due to the formation process of the counter region 27, the range in which the source region 26 is provided corresponds to the range in which the counter region 27 is provided in the XY plane. More specifically, in one unit structure 95, the outer circumference of the source region 26 coincides with the outer circumference of the counter region 27, and the inner circumference of the source region 26 is located outside the inner circumference of the counter region 27. Therefore, the range in which the source area 26 is provided is included in the range in which the counter area 27 is provided. Further, the range in which the source area 26 is provided may be similar to the range in which the counter area 27 is provided.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that such modified or improved forms may also be included in the technical scope of the present invention.

The execution order of each process such as operation, procedure, step, and step in the device, system, program, and method shown in the claims, the specification, and the drawing is particularly "before" and "prior to". It should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first", "next", etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.
[Item 1]
A semiconductor device having a gallium nitride based semiconductor layer.
The gallium nitride based semiconductor layer is
The first conductive type drift region and
A second conductive type base region provided between the front surface of the gallium nitride based semiconductor layer and the drift region, and
A first conductive type source region provided between the front surface of the gallium nitride based semiconductor layer and the base region and having a higher concentration of first conductive type impurities than the drift region.
A counter region provided between the base region and the drift region and having a concentration of impurities of the first conductive type higher than the drift region and lower than the source region, and
With
The base region contains a higher concentration of first conductive type impurities than the drift region.
The first conductive type impurity concentration distribution in the base region tends to gradually decrease from the boundary between the base region and the source region to the boundary between the base region and the counter region.
Semiconductor device.
[Item 2]
The semiconductor according to item 1, wherein the first conductive type impurity concentration distribution in the counter region tends to gradually decrease from the boundary between the base region and the counter region to the boundary between the counter region and the drift region. Device.
[Item 3]
Item 1 or 2, wherein the first conductive type impurity concentration distribution in the source region tends to gradually decrease from the front surface of the gallium nitride based semiconductor layer to the boundary between the source region and the base region. The semiconductor device described.
[Item 4]
The semiconductor device according to any one of items 1 to 3, wherein the first conductive type impurity concentration distribution in the source region, the base region, and the counter region is continuous in the depth direction of the gallium nitride based semiconductor layer. ..
[Item 5]
The semiconductor device according to any one of items 1 to 4, wherein the concentration of impurities of the first conductive type in the base region is higher than the concentration of impurities of the first conductive type in the counter region.
[Item 6]
The semiconductor device according to any one of items 1 to 5, wherein the concentration of impurities of the second conductive type in the base region is higher than the concentration of impurities of the first conductive type in the counter region.
[Item 7]
The gallium nitride based semiconductor layer is
Two base regions provided apart from each other in a direction orthogonal to the depth direction of the gallium nitride based semiconductor layer, and
An upper drift area provided between the two base areas and
Including
The counter area includes a side area provided between the base area and the upper drift area.
The concentration of impurities of the first conductive type in the side region is higher than the concentration of impurities of the first conductive type in the upper drift region.
The semiconductor device according to any one of items 1 to 6.
[Item 8]
The semiconductor device according to any one of items 1 to 7, wherein the concentration of impurities of the first conductive type in the counter region is at least twice the concentration of impurities of the first conductive type in the drift region.
[Item 9]
The semiconductor device according to any one of items 1 to 8, wherein the thickness of the counter region in the depth direction of the gallium nitride based semiconductor layer is 0.5 μm or more and 2 μm or less.
[Item 10]
The semiconductor device according to any one of items 1 to 8, wherein the thickness of the counter region in the direction orthogonal to the depth direction of the gallium nitride based semiconductor layer is 0.4 μm or more and 1.6 μm or less.
[Item 11]
When the gallium nitride based semiconductor layer is viewed from above, the range in which the source region is provided corresponds to the range in which the counter region is provided in a plane orthogonal to the depth direction of the gallium nitride based semiconductor layer. 9. The semiconductor device according to any one of 9.
[Item 12]
A method for manufacturing a semiconductor device having a gallium nitride based semiconductor layer.
The stage of forming the second conductive type base region between the front surface of the gallium nitride based semiconductor layer and the drift region, and
A step of injecting the first conductive type impurities into the base region in order to form a peak of the first conductive type impurity concentration at a position shallower than the bottom of the base region, and a step of injecting the first conductive type impurities into the base region.
The stage of heat-treating the gallium nitride based semiconductor layer and
With
After the heat treatment step,
The gallium nitride based semiconductor layer is
With the above base area
A first conductive type source region having a first conductive type impurity concentration higher than the drift region between the front surface of the gallium nitride based semiconductor layer and the base region,
A counter region between the base region and the drift region having a first conductive type impurity concentration higher than the drift region and lower than the source region,
Have,
The base region contains a higher concentration of first conductive type impurities than the drift region.
The first conductive type impurity concentration distribution in the base region tends to gradually decrease from the boundary between the base region and the source region to the boundary between the base region and the counter region.
Manufacturing method of semiconductor devices.
[Item 13]
At the stage of injecting the first conductive type impurities into the base region,
In order to form the source region and the counter region in one photolithography process, the first conductive type impurities are injected into the base region through one mask material layer.
Item 12. The method for manufacturing a semiconductor device according to item 12.
[Item 14]
After the step of forming the base region, the step of injecting the first conductive type impurities into the base region is executed.
After the step of injecting the first conductive type impurities into the base region, the step of heat treatment is performed.
The method for manufacturing a semiconductor device according to item 12 or 13.
[Item 15]
At the stage of injecting the first conductive type impurities into the base region, peaks of the first conductive type impurity concentration are formed at a position shallower than the bottom of the base region and a position deeper than the base region. The method for manufacturing a semiconductor device according to any one of items 12 to 14.

10 ... GaN substrate, 12 ... boundary, 14 ... front surface, 16 ... back surface, 20 ... GaN layer, 21 ... epitaxial layer, 22 ... drift region, 23 ... upper drift region, 24 .. Base region, 25 ... Channel formation region, 26 ... Source region, 27 ... Counter region, 28 ... Side region, 29 ... Bottom region, 30 ... Gate electrode, 32 ... Gate insulating film, 40 ... Source electrode, 50 ... Drain electrode, 60 ... Invalid region, 62 ... JFET resistance region, 70 ... Mask material layer, 72 ... Opening, 80 ... Trench part, 82 ... Trench, 90, 95 ... Unit structure, 100, 200, 300, 400 ... Semiconductor device

Claims (22)

A semiconductor device having a gallium nitride based semiconductor layer.
The gallium nitride based semiconductor layer is
The first conductive type drift region and
The front surface of the gallium nitride based semiconductor layer provided between the drift region, the two second conductivity type spaced apart in the direction perpendicular to the depth direction of the gallium nitride based semiconductor layer Base area and
A first conductive type source region provided between the front surface of the gallium nitride based semiconductor layer and the base region and having a higher concentration of first conductive type impurities than the drift region.
A counter region provided between the base region and the drift region and having a first conductive type impurity concentration higher than the drift region and lower than the source region .
An upper drift region provided between the two base regions in a direction orthogonal to the depth direction of the gallium nitride based semiconductor layer, and an upper drift region.
With
The base region contains a higher concentration of first conductive type impurities than the drift region.
The first conductive type impurity concentration distribution in the base region tends to gradually decrease from the boundary between the base region and the source region to the boundary between the base region and the counter region .
Semiconductor device. The semiconductor device according to claim 1, wherein the counter region includes a side region provided between the base region and the upper drift region. The semiconductor device according to claim 2, wherein the concentration of the first conductive type impurities in the side region is higher than the concentration of the first conductive type impurities in the upper drift region. The semiconductor device according to claim 2 or 3, wherein the side region and the upper drift region are exposed on the front surface of the gallium nitride based semiconductor layer. The semiconductor device according to any one of claims 2 to 4, further comprising a gate electrode arranged above the upper drift region, the side region, and the base region. A semiconductor device having a gallium nitride based semiconductor layer.
The gallium nitride based semiconductor layer is
The first conductive type drift region and
A second conductive type base region provided between the front surface of the gallium nitride based semiconductor layer and the drift region, and
A first conductive type source region provided between the front surface of the gallium nitride based semiconductor layer and the base region and having a higher concentration of first conductive type impurities than the drift region.
A counter region provided between the base region and the drift region and having a first conductive type impurity concentration higher than the drift region and lower than the source region.
With
The counter region includes a side region provided adjacent to the base region in a direction orthogonal to the depth direction of the gallium nitride based semiconductor layer and the base region in the depth direction of the gallium nitride based semiconductor layer. Including the bottom region provided between the drift region and the drift region.
The base region contains a higher concentration of first conductive type impurities than the drift region.
The first conductive type impurity concentration distribution in the base region tends to gradually decrease from the boundary between the base region and the source region to the boundary between the base region and the counter region.
Semiconductor device. At the position of the front surface of the gallium nitride based semiconductor layer in the direction orthogonal to the depth direction of the gallium nitride based semiconductor layer, the source region is sandwiched between the base regions in the orthogonal direction. The semiconductor device according to any one of claims 1 to 6. When the gallium nitride based semiconductor layer is viewed from above, the counter region and the source region have a hexagonal ring shape, and the base region has a hexagonal ring shape and a hexagonal shape.
When the gallium nitride based semiconductor layer is viewed from above, the hexagonal ring-shaped base region is arranged inside the hexagonal ring-shaped counter region, and the hexagonal ring-shaped source region is the hexagonal ring-shaped base region. Inside, the hexagonal base region is located inside the hexagonal ring-shaped source region.
The semiconductor device according to any one of claims 1 to 7. A semiconductor device having a gallium nitride based semiconductor layer.
The gallium nitride based semiconductor layer is
The first conductive type drift region and
A second conductive type base region provided between the front surface of the gallium nitride based semiconductor layer and the drift region, and
A first conductive type source region provided between the front surface of the gallium nitride based semiconductor layer and the base region and having a higher concentration of first conductive type impurities than the drift region.
A counter region provided between the base region and the drift region and having a first conductive type impurity concentration higher than the drift region and lower than the source region.
With the gate electrode
With
In the gallium nitride based semiconductor layer, a trench portion that penetrates the base region and reaches the drift region is formed.
The gate electrode is provided so as to fill the trench portion.
The bottom surface of the gate electrode is arranged below the top surface of the drift region.
The base region contains a higher concentration of first conductive type impurities than the drift region.
The first conductive type impurity concentration distribution in the base region tends to gradually decrease from the boundary between the base region and the source region to the boundary between the base region and the counter region.
Semiconductor device. When the gallium nitride based semiconductor layer is viewed from above, the source region has a hexagonal ring shape, the base region has a hexagonal shape, and the hexagonal base region is arranged inside the hexagonal ring-shaped source region. The semiconductor device according to claim 8. A semiconductor device having a gallium nitride based semiconductor layer.
The gallium nitride based semiconductor layer is
The first conductive type drift region and
A second conductive type base region provided between the front surface of the gallium nitride based semiconductor layer and the drift region, and
A first conductive type source region provided between the front surface of the gallium nitride based semiconductor layer and the base region and having a higher concentration of first conductive type impurities than the drift region.
A counter region provided between the base region and the drift region and having a first conductive type impurity concentration higher than the drift region and lower than the source region.
With
The base region contains a higher concentration of first conductive type impurities than the drift region.
The first conductive type impurity concentration distribution in the base region tends to gradually decrease from the boundary between the base region and the source region to the boundary between the base region and the counter region.
The thickness of the counter region in the depth direction of the gallium nitride based semiconductor layer is 0.5 μm or more and 2 μm or less.
Semiconductor device. A semiconductor device having a gallium nitride based semiconductor layer.
The gallium nitride based semiconductor layer is
The first conductive type drift region and
A second conductive type base region provided between the front surface of the gallium nitride based semiconductor layer and the drift region, and
A first conductive type source region provided between the front surface of the gallium nitride based semiconductor layer and the base region and having a higher concentration of first conductive type impurities than the drift region.
A counter region provided between the base region and the drift region and having a first conductive type impurity concentration higher than the drift region and lower than the source region.
With
The base region contains a higher concentration of first conductive type impurities than the drift region.
The first conductive type impurity concentration distribution in the base region tends to gradually decrease from the boundary between the base region and the source region to the boundary between the base region and the counter region.
The thickness of the counter region in the direction orthogonal to the depth direction of the gallium nitride based semiconductor layer is 0.4 μm or more and 1.6 μm or less.
Semiconductor device. The first conductive type impurity concentration distribution in the counter region tends to gradually decrease from the boundary between the base region and the counter region to the boundary between the counter region and the drift region , according to claims 1 to 12. The semiconductor device according to any one item. The first conductive type impurity concentration distribution in the source region tends to gradually decrease from the front surface of the gallium nitride based semiconductor layer to the boundary between the source region and the base region , claims 1 to 13. The semiconductor device according to any one of the above. Said source region, said base region and said impurity concentration of the first conductivity type in the counter area distribution, the continuous in the depth direction of the gallium nitride based semiconductor layer, a semiconductor according to any one of claims 1 to 14 Device. The impurity concentration of the first conductivity type in the base region, the higher than the impurity concentration of the first conductivity type in the counter area, the semiconductor device according to any one of claims 1 to 15. The impurity concentration of the second conductivity type in the base region, the higher than the impurity concentration of the first conductivity type in the counter area, the semiconductor device according to any one of claims 1 to 16. The impurity concentration of the first conductivity type in the counter area, the at least twice the impurity concentration of the first conductivity type in the drift region, the semiconductor device according to any one of claims 1 to 17. When the gallium nitride based semiconductor layer is viewed from above, the range in which the source region is provided corresponds to the range in which the counter region is provided in a plane orthogonal to the depth direction of the gallium nitride based semiconductor layer. The semiconductor device according to any one of 1 to 18. A method for manufacturing a semiconductor device having a gallium nitride based semiconductor layer.
A step of forming a second conductive type base region between the front surface of the gallium nitride based semiconductor layer and the drift region, and
A step of injecting the first conductive type impurity into the base region in order to form a peak of the first conductive type impurity concentration at a position shallower than the bottom of the base region, and a step of injecting the first conductive type impurity into the base region.
A step of annealing the GaN-based semiconductor layer,
With
After the heat treatment step,
The gallium nitride based semiconductor layer is
With the base area
A first conductive type source region having a first conductive type impurity concentration higher than the drift region between the front surface of the gallium nitride based semiconductor layer and the base region,
A counter region between the base region and the drift region having a first conductive type impurity concentration higher than the drift region and lower than the source region .
Have,
The base region contains a higher concentration of first conductive type impurities than the drift region.
The impurity concentration distribution of the first conductivity type in the base region, have a tendency to gradually decrease in to a boundary between the base region and the source region and the base region and the counter area from the boundary,
At the stage of injecting the first conductive type impurities into the base region, peaks of the first conductive type impurity concentration are formed at a position shallower than the bottom of the base region and a position deeper than the base region.
Manufacturing method of semiconductor devices. At the stage of injecting the first conductive type impurities into the base region,
A first conductive type impurity is injected into the base region through one mask material layer in order to form the source region and the counter region in one photolithography process .
The method for manufacturing a semiconductor device according to claim 20. After the step of forming the base region, a step of injecting a first conductive type impurity into the base region is performed.
After the step of implanting an impurity of the first conductivity type in said base region, performing said step of heat treating said gallium nitride based semiconductor layer,
The method for manufacturing a semiconductor device according to claim 20 or 21.

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