JP7024761B2 - Nitride semiconductor device and manufacturing method of nitride semiconductor device - Google Patents

Description

The techniques disclosed herein relate to nitride semiconductor devices and methods of manufacturing nitride semiconductor devices.

In GaN, if hydrogen is contained in a high concentration, the acceptor (eg, Mg) may not be activated and the performance in the p-type region may not be obtained. Patent Document 1 discloses a technique for performing dehydrogenation annealing in a state where the p-type GaN layer is exposed in order to efficiently remove hydrogen from the p-type GaN layer.

JP-A-2015-115430

Even when dehydrogenation annealing is performed with the p-type GaN layer exposed, the hydrogen in the p-type GaN layer may not be sufficiently removed and the effective acceptor concentration may decrease.

One embodiment of the nitride semiconductor device disclosed herein comprises a drain electrode. It includes a first n-type GaN layer arranged above the drain electrode. A low-concentration p-type GaN layer arranged on the upper surface of the first n-type GaN layer is provided. A second n-type GaN layer arranged on the upper surface of the low-concentration p-type GaN layer is provided. It includes a trench reaching from the upper surface of the second n-type GaN layer to the low-concentration p-type GaN layer. It is a contact region arranged in a trench and includes a contact region formed of high-concentration p-type GaN having a higher p-type impurity concentration than a low-concentration p-type GaN layer. It is provided with a source electrode in contact with at least a part of the contact area.

Further, one embodiment of the nitride semiconductor device disclosed in the present specification includes a drain electrode. It includes a first n-type GaN layer arranged above the drain electrode. A low-concentration p-type GaN layer arranged on the upper surface of the first n-type GaN layer is provided. It is a high-concentration p-type GaN layer having a higher p-type impurity concentration than the low-concentration p-type GaN layer, and includes a high-concentration p-type GaN layer arranged on the upper surface of the low-concentration p-type GaN layer. It is provided with a trench reaching from the upper surface of the high-concentration p-type GaN layer to the low-concentration p-type GaN layer. It includes an n-type GaN source region arranged in a trench. It includes a gate electrode region that penetrates the low-concentration p-type GaN layer from the upper surface of the source region and reaches the first n-type GaN layer. A source electrode is provided in contact with at least a part of the upper surface of the source region and at least a part of the upper surface of the high-concentration p-type GaN layer.

Annealing can be performed in a state where the high-concentration p-type GaN layer is formed on a part of the upper surface of the low-concentration p-type GaN layer. Since the hydrogen contained in the low-concentration p-type GaN layer can be diffused into the high-concentration p-type GaN layer, the hydrogen concentration of the low-concentration p-type GaN layer is arranged on the upper surface of the high-concentration p-type GaN layer. It can be lowered sufficiently in a short time as compared with the case without it. The effective acceptor concentration of low-concentration p-type GaN can be increased.

A gate electrode region may be further provided from the upper surface of the second n-type GaN layer to the first n-type GaN layer through the low-concentration p-type GaN layer.

The ratio of the hydrogen concentration of the low-concentration p-type GaN layer in the vicinity of the gate electrode region to the hydrogen concentration of the low-concentration p-type GaN layer near the interface between the low-concentration p-type GaN layer and the contact region was within twice. May be good. Details of the effect will be described in Examples.

The low-concentration p-type GaN layer may have an opening. The nitride semiconductor device is an opening semiconductor layer which is n-type GaN arranged in the opening, the lower surface of which is in the same plane as the lower surface of the low-concentration p-type GaN layer, and the upper surface of which is low-concentration p-type GaN. Further, an opening semiconductor layer that is in the same plane as the upper surface of the layer may be provided. A gate electrode arranged above the second n-type GaN layer and the opening, wherein the region where the gate electrode is arranged includes the opening when the gate electrode is viewed from above. May be further provided.

Even if the ratio of the hydrogen concentration of the low-concentration p-type GaN layer in the vicinity of the opening to the hydrogen concentration of the low-concentration p-type GaN layer near the interface between the low-concentration p-type GaN layer and the contact region is within twice. good. Details of the effect will be described in Examples.

The contact region may be a region formed by an epitaxial growth method or a sputtering method.

One embodiment of the method for manufacturing a nitride semiconductor device disclosed in the present specification includes a step of forming a first n-type GaN layer on a GaN substrate by an epitaxial growth method. A step of forming a low-concentration p-type GaN layer on the upper surface of the first n-type GaN layer by an epitaxial growth method is provided. A step of forming a second n-type GaN layer on the upper surface of the low-concentration p-type GaN layer by an epitaxial growth method is provided. A step of forming a trench reaching from the upper surface of the second n-type GaN layer to the low-concentration p-type GaN layer is provided. A step of forming a contact region formed of a high-concentration p-type GaN having a higher p-type impurity concentration than a low-concentration p-type GaN layer in a trench is provided. It is provided with an annealing step of diffusing hydrogen contained in the low-concentration p-type GaN layer into the contact region by annealing in an inert atmosphere. A step of forming a source electrode in contact with at least a part of the contact region is provided.

The step of forming the contact region may be performed by an epitaxial growth method or a sputtering method.

Further, one embodiment of the method for manufacturing a nitride semiconductor device disclosed in the present specification includes a step of forming a first n-type GaN layer on a GaN substrate by an epitaxial growth method. A step of forming a low-concentration p-type GaN layer on the upper surface of the first n-type GaN layer by an epitaxial growth method is provided. A step of forming a high-concentration p-type GaN layer having a higher p-type impurity concentration than the low-concentration p-type GaN layer by an epitaxial growth method is provided on the upper surface of the low-concentration p-type GaN layer. It is provided with an annealing step of diffusing hydrogen contained in the low-concentration p-type GaN layer into the high-concentration p-type GaN layer by annealing in an inert atmosphere. A step of forming a first trench reaching from the upper surface of the high-concentration p-type GaN layer to the low-concentration p-type GaN layer is provided. A step of forming a source region of n-type GaN in the first trench is provided. A step of forming a second trench that penetrates the low-concentration p-type GaN layer from the upper surface of the source region and reaches the first n-type GaN layer is provided. A step of forming a gate electrode in the second trench via a gate insulating film and forming a source electrode in contact with at least a part of the upper surface of the source region and at least a part of the upper surface of the high-concentration p-type GaN layer is provided.

The step of forming the source region may be performed by an epitaxial growth method or a sputtering method.

It is sectional drawing of the semiconductor device 1 which concerns on Example 1. FIG. It is a flowchart which shows the manufacturing method of the semiconductor device 1 which concerns on Example 1. FIG. It is a figure which shows the manufacturing process of the semiconductor device 1 which concerns on Example 1. FIG. It is a figure which shows the manufacturing process of the semiconductor device 1 which concerns on Example 1. FIG. It is a graph of the measurement result of the hydrogen concentration of the low-concentration p-type GaN layer. It is sectional drawing of the semiconductor device 101 which concerns on Example 2. FIG. It is a flowchart which shows the manufacturing method of the semiconductor device 101 which concerns on Example 2. FIG. It is a figure which shows the manufacturing process of the semiconductor device 101 which concerns on Example 2. FIG. It is a figure which shows the manufacturing process of the semiconductor device 101 which concerns on Example 2. FIG. It is sectional drawing of the semiconductor device 201 which concerns on Example 3. FIG. It is a flowchart which shows the manufacturing method of the semiconductor device 201 which concerns on Example 3. FIG. It is a figure which shows the manufacturing process of the semiconductor device 201 which concerns on Example 3. FIG.

(Structure of semiconductor device 1)
FIG. 1 shows a schematic cross-sectional view of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 is a vertical MOSFET provided with a trench gate. The semiconductor device 1 includes a semiconductor substrate 10. The semiconductor substrate 10 has a structure in which a drain layer 32, a drift layer 34, a body layer 36, and a source region 38 are laminated.

The drain layer 32 is a high-concentration n-type (n ⁺ type) GaN substrate. A drain electrode 52 is formed on the back surface of the drain layer 32. The donor concentration of the drain layer 32 was 2 × 10 ¹⁸ cm ^-3 . A drift layer 34 is formed on the surface of the drain layer 32. The drift layer 34 is a low-concentration n-type (n ^- type) GaN layer epitaxially grown on the surface of the drain layer 32. The donor concentration of the drift layer 34 was 8 × 10 ¹⁵ cm ^-3 . The body layer 36 is a low-concentration p-type (p ^- type) GaN layer epitaxially grown on the drift layer 34. The acceptor (Mg) concentration of the body layer 36 was 5 × 10 ¹⁷ cm ^-3 . The source region 38 is a high-concentration n-type (n ⁺ type) GaN region epitaxially grown on the body layer 36. The donor concentration in the source region 38 was 1 × 10 ¹⁸ cm ^-3 .

A contact trench T2 is formed that reaches from the upper surface of the source region 38 to the body layer 36. A body contact region 46 is arranged in the contact trench T2. The body contact region 46 is a high-concentration p-type (p ⁺ -type) GaN layer epitaxially grown in the contact trench T2. The body contact region 46 has a higher p-type impurity concentration than the body layer 36. The acceptor (Mg) concentration in the body contact area 46 was 3 × 10 ¹⁹ cm ^-3 . The body contact region 46 includes an opening region A1. The opening region A1 is a region in which the body contact region 46 is not arranged on the upper surface of the body layer 36. A part of the source region 38 and the gate electrode region 41 are arranged inside the opening region A1.

The hydrogen concentration of the body layer 36 is lower than the hydrogen concentration of the body contact region 46. For example, the hydrogen concentration of the body layer 36 may be 1/10 or less of the hydrogen concentration of the body contact region 46. The hydrogen concentration of the body layer 36 was 5 × 10 ¹⁶ cm ^-3 .

As shown in FIG. 1, a region in the body layer 36 near the gate electrode region 41 and facing the trench gate electrode 40 via the gate insulating film 42 is referred to as a region R1. Further, in the body layer 36, a region near the interface between the body layer 36 and the body contact region 46 is referred to as a region R2. The ratio of the hydrogen concentration of the region R1 to the hydrogen concentration of the region R2 is within 2 times.

The gate electrode region 41 includes a trench gate electrode 40 and a gate insulating film 42. The trench gate electrode 40 penetrates the drift layer 34 from the surface of the source region 38 through the source region 38 and the body layer 36. The trench gate electrode 40 is an electrode formed in the gate trench T1 whose side surface and bottom surface are covered with the gate insulating film 42. The trench gate electrode 40 extends outside the gate trench T1 and is in contact with the gate electrode 50. The trench gate electrode 40 is made of polycrystalline silicon or the like.

The interlayer insulating film 48 is a layer for ensuring insulation between the trench gate electrode 40 and the gate electrode 50 and the source electrode 44. The source electrode 44 is in contact with a part of the upper surface of the body contact region 46 and a part of the upper surface of the source region 38.

(Manufacturing method of semiconductor device 1)
A method for manufacturing the semiconductor device 1 will be described with reference to FIGS. 2 to 4. In step S1 of the flowchart of FIG. 2, the laminated structure forming step is performed. Specifically, the semiconductor substrate 10 in which the drain layer 32, the drift layer 34, the body layer 36, and the source region 38 are laminated is formed. The semiconductor substrate 10 may be formed by growing a drift layer 34, a body layer 36, and a source region 38 on a drain layer 32 by an epitaxial growth method (eg, MOVPE method).

In step S2, a contact trench forming step is performed. Specifically, the contact trench T2 that penetrates the source region 38 from the upper surface of the source region 38 and reaches the body layer 36 is processed. The processing of the contact trench T2 can be performed by a well-known photolithography technique and dry etching processing. As a result, the structure shown in FIG. 3 is formed.

In step S3, the body contact region forming step is performed. Specifically, a high-concentration p-type GaN layer is grown on the source region 38 by an epitaxial growth method (eg, MOVPE method). As a result, a high-concentration p-type GaN layer is formed inside the contact trench T2 and on the upper surface of the source region 38. Next, a mask having an opening corresponding to the opening region A1 is processed using a well-known photolithography technique and dry etching processing. The source region 38 is exposed by removing the high-concentration p-type GaN layer in the opening region A1 by dry etching. As a result, the body contact region 46 is formed as shown in FIG.

In step S4, the annealing step is performed. Specifically, the semiconductor substrate 10 is heated in an inert atmosphere (eg, in an _N2 atmosphere) at 900 ° C. for 10 minutes. As a result, hydrogen contained in the body layer 36 (low-concentration p-type GaN layer) can be diffused into the body contact region 46 (high-concentration p-type GaN layer). In other words, as shown by the arrow Y1 in FIG. 4, hydrogen in the body layer 36 can be sucked out to the body contact region 46 side. As a result, the hydrogen concentration of the body layer 36 can be reduced to about 5 × 10 ¹⁶ cm ^-3 . The annealing temperature is preferably 900 ° C. or lower. This is because if the annealing temperature is higher than 900 ° C., GaN is thermally decomposed.

In step S5, a gate trench forming step is performed. Specifically, a gate trench T1 that penetrates the body layer 36 from the upper surface of the source region 38 and reaches the drift layer 34 is machined in a part of the opening region A1. In step S6, the gate electrode region forming step is performed. Specifically, the gate insulating film 42 is formed in the gate trench T1 and on the surface of the semiconductor substrate 10. The gate insulating film 42 is an insulating film formed by depositing SiO ₂ or Al ₂ O ₃ or the like by an atomic layer deposition method or the like. Polysilicon doped with impurities such as boron is formed into a film by the LP-CVD method. The trench gate electrode 40 is formed by removing the polysilicon around the gate trench T1 using a well-known photolithography technique and dry etching process.

In step S7, a source electrode and gate electrode forming step is performed. Specifically, an interlayer insulating film 48 is formed on the upper surface of the trench gate electrode 40. Then, using a well-known photolithography technique and dry etching processing, the interlayer insulating film 48 and the gate insulating film 42 in the region forming the source electrode 44 and the gate electrode 50 are removed. A metal layer is formed. The metal layer is machined into the source electrode 44 and the gate electrode 50 using well-known photolithography techniques and dry etching processes.

In step S8, the drain electrode forming step is performed. Specifically, a metal layer drain electrode 52 is formed on the back surface of the drain layer 32. As a result, the semiconductor device 1 shown in FIG. 1 is completed.

(Operation of semiconductor device 1)
In the semiconductor device 1 shown in FIG. 1, the drain electrode 52 is connected to a high potential, the source electrode 44 is grounded, and the potential applied to the gate electrode 50 is changed. When a positive potential is applied to the gate electrode 50, the p ^- type body layer 36 of the region R1 facing the trench gate electrode 40 via the gate insulating film 42 is inverted to n-type, and the n ⁺ -type body layer is inverted by the inversion layer. The source region 38 and the n ^- type drift layer 34 are conducted, and a current flows between the source electrode 44 and the drain electrode 52. When the application of the positive potential to the gate electrode 50 is stopped, the inversion layer of the region R1 disappears, the depletion layer extends to the drift layer 34, and a high resistance state is established between the source electrode 44 and the drain electrode 52.

(Effect of Example 1)
Since the body layer 36, which is a low-concentration p-type GaN layer, is a layer on which an inversion layer is formed as described above, it is an important layer for determining the threshold value of the semiconductor device 1. Further, in p-type GaN, if hydrogen is contained in a high concentration, the acceptor (eg, Mg) may not be activated and sufficient p-type characteristics may not be obtained. Therefore, it is necessary to reduce the hydrogen concentration of the body layer 36. In the technique described herein, an inert atmosphere is provided in a state where the high-concentration p-type GaN layer (body contact region 46) is in contact with a part of the upper surface of the low-concentration p-type GaN layer (body layer 36). Can be annealed with (step S4). By performing such annealing, the hydrogen concentration of the low-concentration p-type GaN layer can be sufficiently lowered in a short time as compared with the case where the high-concentration p-type GaN layer is not arranged on the upper surface. The inventors have found. It is considered that this is because hydrogen exists as a proton at the interface between the high-concentration p-type GaN layer and the low-concentration p-type GaN layer, and the diffusion of hydrogen toward the high-concentration p-type GaN layer is accelerated by the electric field. As a result, the hydrogen concentration of the low-concentration p-type GaN layer (body layer 36) can be sufficiently reduced. Since the effective acceptor concentration as designed can be obtained, the threshold voltage can be precisely controlled. As a result, dehydrogenation of the low-concentration p-type GaN layer (body layer 36) can be realized by short-time annealing (eg, 10 minutes or less). It is possible to suppress the situation where new defects are introduced into the low-concentration p-type GaN layer (body layer 36) due to long-term annealing.

The semiconductor device 1 described in the present specification includes a structure in which a high-concentration p-type GaN layer (body contact region 46) is arranged in a contact trench T2 that penetrates the source region 38 and reaches the body layer 36. There is. This makes it possible to divert the body contact region 46 as a region for sucking hydrogen from the body layer 36 by dehydrogenation annealing (step S4).

When a source region (high-concentration n-type GaN layer) is formed on the upper part of the body layer by the ion implantation method as in the conventional case, the channel characteristics are deteriorated due to the damage introduced by the ion implantation. In the semiconductor device 1 described in the present specification, the source region 38 can be formed by epitaxial growth (step S1). As a result, damage is not introduced into the source region 38, so that deterioration of channel characteristics can be suppressed.

By sucking hydrogen from the body layer 36 using the body contact region 46, as shown in FIG. 1, the ratio of the hydrogen concentration of the region R12 to the hydrogen concentration of the region R11 can be made within twice. As a result, the in-plane uniformity is good and the hydrogen concentration of the body layer 36 can be reduced. That is, the activation rate of the body layer 36 can be kept uniform. Therefore, the in-plane uniformity of the threshold voltage of the semiconductor device 1 can be improved. It is possible to precisely control the threshold voltage of the semiconductor device 1 and secure the device withstand voltage.

(Measurement result of hydrogen concentration)
FIG. 5 shows a graph of the measurement result of the hydrogen concentration of the low concentration p-type GaN layer. FIG. 5 shows the measurement results using the secondary ion mass spectrometry (SIMS) method. As a typical example of measurement conditions, Cs ⁺ ion was used as the primary ion species, and 8.0 kV was used as the acceleration voltage. The vertical axis is the normalized hydrogen concentration. The horizontal axis is the annealing time. The annealing temperature was 850 ° C., and the annealing atmosphere was N ₂ . The hydrogen concentration was measured for each of the three conditions of Comparative Example 1, Comparative Example 2, and this Example. In Comparative Example 1, a sample in which a high-concentration n-type GaN layer was formed on the upper surface of the low-concentration p-type GaN layer was used. In Comparative Example 2, a sample in which the low-concentration p-type GaN layer was exposed was used. In this example, a sample in which a high-concentration p-type GaN layer is formed on the upper surface of the low-concentration p-type GaN layer was used. In FIG. 5, the measurement result of Comparative Example 1 is shown by a triangular point, the measurement result of Comparative Example 2 is shown by a round point, and the measurement result of this Example is shown by a quadrangular point.

At time t1 when the annealing time is 10 minutes, the hydrogen concentration in Comparative Example 1 (triangle) is almost the same as that before annealing. Further, in Comparative Example 2 (round shape), the hydrogen concentration was reduced only to about 60% before annealing. However, in this embodiment (square), it can be reduced to about 10% before annealing. It can be seen that the hydrogen concentration of the low-concentration p-type GaN layer can be efficiently reduced by annealing in a state where the high-concentration p-type GaN layer is formed on the upper surface of the low-concentration p-type GaN layer. It can also be seen that this effect can be obtained even when the annealing time is longer than 10 minutes.

(Structure of semiconductor device 101)
FIG. 6 shows a schematic cross-sectional view of the semiconductor device 101 according to the second embodiment. The semiconductor device 101 is a vertical MOSFET provided with a trench gate. A portion different from the semiconductor device 1 (FIG. 1) of the first embodiment and the semiconductor device 101 (FIG. 6) of the second embodiment is distinguished by adding "a" at the end of the reference numeral. The same reference numerals are given to the parts common to the semiconductor devices 1 and 101, and the description thereof will be omitted. The semiconductor device 1 of Example 1 had a structure in which a high-concentration p-type GaN layer (body contact region 46) was formed in the contact trench T2. On the other hand, the semiconductor device 101 of the second embodiment has a structure for forming a high-concentration n-type GaN layer (source region 38a) in the trench T3a. This will be described below.

The semiconductor substrate 10a has a structure in which a drain layer 32, a drift layer 34, a body layer 36, and a body contact region 46a are laminated. The body contact region 46a is a high-concentration p-type (p ⁺ -type) GaN region epitaxially grown on the body layer 36. The body contact region 46a has a higher p-type impurity concentration than the body layer 36.
The acceptor (Mg) concentration was assumed to be 3 × 10 ¹⁹ cm ^-3 for the body contact region 46a and 5 × 10 ¹⁷ cm ^-3 for the body layer 36.

A trench T3a reaching from the upper surface of the body contact region 46a to the body layer 36 is formed. A source region 38a is arranged in the trench T3a. The source region 38a is a high-concentration n-type (n ⁺ type) GaN layer epitaxially grown in the trench T3a. The donor concentration in the source region 38a was 1 × 10 ¹⁸ cm ^-3 .

The hydrogen concentration of the body layer 36 is lower than the hydrogen concentration of the body contact region 46a. Further, as shown in FIG. 6, in the body layer 36, a region near the interface between the body layer 36 and the body contact region 46a is defined as a region R2a. The ratio of the hydrogen concentration of the region R1 to the hydrogen concentration of the region R2a is within 2 times.

(Manufacturing method of semiconductor device 101)
A method of manufacturing the semiconductor device 101 will be described with reference to FIGS. 7 to 9. A portion different from the manufacturing flowchart (FIG. 2) of the semiconductor device 1 of the first embodiment and the manufacturing flowchart (FIG. 7) of the semiconductor device 101 of the second embodiment is designated by adding "a" to the end of the reference numeral. Separated. The common steps are designated by the same reference numerals, and the description thereof will be omitted.

In step S1a of the flowchart of FIG. 7, a laminated structure forming step is performed. Specifically, as shown in FIG. 8, a semiconductor substrate 10a in which the drain layer 32, the drift layer 34, the body layer 36, and the body contact region 46a are laminated is formed.

In step S2a, the annealing step is performed. Specifically, the semiconductor substrate 10a is heated at 900 ° C. for 10 minutes in an inert atmosphere. As a result, hydrogen contained in the body layer 36 (low-concentration p-type GaN layer) can be diffused into the body contact region 46a (high-concentration p-type GaN layer) (FIG. 8, arrow Y2). As a result, the hydrogen concentration of the body layer 36 can be reduced to about 5 × 10 ¹⁶ cm ^-3 .

In step S3a, a trench forming step is performed. Specifically, the trench T3a that reaches the body layer 36 from the upper surface of the body contact region 46a is processed.

In step S4a, the source region forming step is performed. Specifically, a high-concentration n-type GaN layer is formed inside the trench T3a by a sputtering method. Next, the high-concentration n-type GaN layer grown on the upper surface of the body contact region 46a is removed by using a well-known photolithography technique and dry etching processing. As a result, as shown in FIG. 9, the source region 38a is formed in the trench T3a.

Since the contents of steps S5 to S8 are the same as the contents of the flowchart (FIG. 2) of the first embodiment, the description thereof will be omitted. As a result, the semiconductor device 101 shown in FIG. 6 is completed.

(Effect of Example 2)
In the technique described in Example 2, annealing can be performed in a state where the high-concentration p-type GaN layer (body contact region 46a) is in contact with the upper surface of the low-concentration p-type GaN layer (body layer 36). (Step S2a). As a result, the hydrogen concentration of the low-concentration p-type GaN layer (body layer 36) can be sufficiently reduced by annealing in a short time. Further, since the annealing can be performed in a state where the body contact region 46a is arranged on the entire upper surface of the body layer 36, the in-plane uniformity is good and the hydrogen concentration of the body layer 36 can be reduced.

In the semiconductor device 101 described in the second embodiment, the source region 38a can be formed by a sputtering method (step S4a). As a result, it is possible to suppress the damage introduced into the source region as compared with the case where the source region is formed by ion implantation, so that it is possible to suppress the deterioration of the channel characteristics. Further, since the sputtering method does not contain hydrogen in the atmosphere, it is possible to prevent the introduction of new hydrogen into the body layer in step S4a.

(Structure of Semiconductor Device 201)
FIG. 10 shows a schematic cross-sectional view of the semiconductor device 201 according to the third embodiment. The semiconductor device 201 is a normal-off type vertical HEMT (High Electron Mobility Transistor). The semiconductor device 201 includes a drain electrode 210, a drain layer 211, a drift layer 212, a current constriction layer 213, an opening 213a, an opening semiconductor layer 214, a channel layer 215, an AlGaN layer 216, a P-type layer 220, a gate electrode 221 and insulation. A layer 222, a contact region 223, and a source electrode 224 are provided.

The drain layer 211 is a high-concentration n-type GaN (donor concentration = 2 × 10 ¹⁸ cm ^-3 ). The drift layer 212 is a low-concentration n-type GaN (donor concentration = 8 × 10 ¹⁵ cm ^-3 ). The current constriction layer 213 is in contact with the upper surface of the drift layer 212. The current constriction layer 213 is a low-concentration p-type GaN (acceptor (Mg) concentration = 1 × 10 ¹⁹ cm ^-3 ). The current constriction layer 213 includes an opening 213a. A channel layer 215, which is a low-concentration n-type GaN, is in contact with the upper surface of the current constriction layer 213. Inside the opening 213a, an opening semiconductor layer 214 which is a low-concentration n-type GaN is arranged. The opening semiconductor layer 214 functions as a longitudinal current path. Therefore, a so-called aperture structure is formed. The AlGaN layer 216 is heterojunctioned to the upper surface of the channel layer 215 and the upper surface of the opening semiconductor layer 214. A P-type layer 220 (acceptor (Mg) concentration = 2 × 10 ¹⁹ cm ^-3 ), which is a high-concentration p-type GaN, is in contact with the upper surface of the AlGaN layer 216. The gate electrode 221 is in contact with the upper surface of the P-type layer 220. When the gate electrode 221 is viewed from above (the z-axis positive direction), the opening 213a is included in the region where the gate electrode 221 is arranged.

A contact trench T4 is formed from the upper surface of the AlGaN layer 216 through the channel layer 215 and reaching the current constriction layer 213. A contact region 223 is arranged in the contact trench T4. The contact region 223 is a high-concentration p-type GaN (acceptor (Mg) concentration = 5 × 10 ¹⁹ cm ^-3 ) epitaxially grown in the contact trench T4. The contact region 223 has a higher p-type impurity concentration than the current constriction layer 213. The insulating layer 222 is a layer for ensuring insulation between the P-shaped layer 220 and the source electrode 224. The source electrode 224 is in contact with a part of the upper surface of the AlGaN layer 216 and the upper surface of the contact region 223.

As shown in FIG. 10, a region in the vicinity of the opening semiconductor layer 214 in the current constriction layer 213 is referred to as a region R21. Further, in the current constriction layer 213, the region near the interface between the current constriction layer 213 and the contact region 223 is referred to as a region R22. The ratio of the hydrogen concentration in the region R21 to the hydrogen concentration in the region R22 is within twice.

(Manufacturing method of semiconductor device 201)
A method of manufacturing the semiconductor device 201 will be described with reference to FIGS. 11 and 12. In step S101 of the flowchart of FIG. 11, the laminated structure forming step is performed. Specifically, the drift layer 212 and the current constriction layer 213 are grown on the drain layer 211 by an epitaxial growth method (eg, MOVPE method). In step S102, the opening forming step is performed. Specifically, a well-known photolithography technique and dry etching processing are used to remove the portion corresponding to the opening 213a to form a trench. Then, the opening semiconductor layer 214 and the channel layer 215, which are low-concentration n-type GaN, are formed by the embedded regrowth method. In step S103, a gate structure forming step is performed. Specifically, the AlGaN layer 216 and the high-concentration p-type GaN layer are laminated. Then, the high-concentration p-type GaN layer is processed into the P-type layer 220.

In step S104, a contact trench forming step is performed. Specifically, the contact trench T4 that reaches the current constriction layer 213 from the upper surface of the AlGaN layer 216 is machined. Then, a high-concentration p-type GaN layer is formed in the contact trench T4 by the embedded regrowth method. By dry etching, unnecessary high-concentration p-type GaN layers on the surface of the AlGaN layer 216 and the surface of the P-type layer 220 are removed. As a result, the contact region 223 is formed as shown in FIG.

In step S105, the annealing step is performed. Specifically, the structure shown in FIG. 12 is heated in an inert atmosphere (eg, in an _N2 atmosphere) at 900 ° C. for 10 minutes. As a result, as shown by the arrow Y3, the hydrogen in the current constriction layer 213 can be sucked out to the contact region 223 side. As a result, the hydrogen concentration in the current constriction layer 213 can be reduced to about 5 × 10 ¹⁶ cm ^-3 .

In step S106, the gate electrode 221, the source electrode 224, and the drain electrode 210 are formed. As a result, the semiconductor device 201 shown in FIG. 10 is completed.

(Effect of Example 3)
In the technique described in Example 3, annealing can be performed in a state where the high-concentration p-type GaN layer (contact region 223) is in contact with the upper surface of the low-concentration p-type GaN layer (current constriction layer 213). (Step S105). As a result, the hydrogen concentration in the current constriction layer 213 can be sufficiently reduced by annealing in a short time.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples exemplified above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in the present specification or the drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

(Modification example)
The method for forming the body contact region 46 and the contact region 223 in the trench is not limited to the epitaxial growth method, and various methods can be used. For example, it may be a sputtering method. Further, the method for forming the source region 38a may be an epitaxial growth method (eg, a molecular beam epitaxy method) that does not contain hydrogen gas.

The timing of dehydrogenation annealing in this embodiment is an example, and various timings can be used. For example, in the flowchart of Example 2 (FIG. 7), the annealing step may be performed after the trench forming step (step S4a) or after the gate electrode region forming step (step S6).

The temperature of the annealing step is not limited to 850 ° C., and may be a temperature of 850 ° C. or lower. As the temperature is lowered, the rate of decrease in the hydrogen concentration of the low-concentration p-type GaN layer decreases, but it is possible to suppress the deterioration of crystallinity due to annealing.

The group III nitride semiconductor constituting the semiconductor substrate 10 is not limited to GaN, and may be, for example, AlN (aluminum nitride), InN (indium nitride), or a mixed crystal thereof.

In the above embodiment, magnesium (Mg) is used as an example of the group II element for forming the p-type region, but the configuration is not limited to this. The group II element may be, for example, beryllium (Be), calcium (Ca), or the like.

The impurity concentrations described in this example are all examples. It is possible to use various combinations of concentrations.

The drift layer 34 is an example of a first n-type GaN layer. The body layer 36 is an example of a low-concentration p-type GaN layer. The source region 38 is an example of a second n-type GaN layer.
The body contact area 46 is an example of a contact area.

1: Semiconductor device 10: Semiconductor substrate 32: Drain layer 34: Drift layer 36: Body layer 38: Source region 41: Gate electrode region 44: Source electrode 46: Body contact region T2: Contact trench

Claims (6)

With the drain electrode
The first n-type GaN layer arranged above the drain electrode and
A low-concentration p-type GaN layer arranged on the upper surface of the first n-type GaN layer and having an opening ,
A second n-type GaN layer arranged on the upper surface of the low-concentration p-type GaN layer, and
An opening semiconductor layer which is an n-type GaN arranged in the opening, and the opening semiconductor layer connecting the first n-type GaN layer and the second n-type GaN layer. ,
The gate electrode arranged above the second n-type GaN layer and the opening semiconductor layer, and the region where the gate electrode is arranged when the gate electrode is viewed from above is the opening. Containing the gate electrode and
The trench reaching from the upper surface of the second n-type GaN layer to the low-concentration p-type GaN layer , and is formed outside the region where the opening is arranged when viewed from above. Trench and
The contact region arranged in the trench and formed of high-concentration p-type GaN having a higher p-type impurity concentration than the low-concentration p-type GaN layer.
A source electrode in contact with at least a part of the contact area and
Nitride semiconductor device. An AlGaN layer arranged on the upper surface of the second n-type GaN layer and the opening semiconductor layer and further arranged below the gate electrode is further provided.
The nitride semiconductor device according to claim 1, wherein the trench reaches from the upper surface of the AlGaN layer to the low-concentration p-type GaN layer. The ratio of the hydrogen concentration of the low-concentration p-type GaN layer in the vicinity of the opening to the hydrogen concentration of the low-concentration p-type GaN layer in the vicinity of the interface between the low-concentration p-type GaN layer and the contact region is doubled. The nitride semiconductor device according to claim 1 or 2 , which is within the range. The nitride semiconductor device according to any one of claims 1 to 3 , wherein the contact region is a region formed by an epitaxial growth method or a sputtering method. A step of forming a first n-type GaN layer on a GaN substrate by an epitaxial growth method,
A step of forming a low-concentration p-type GaN layer on the upper surface of the first n-type GaN layer by an epitaxial growth method,
A step of forming an opening reaching from the upper surface of the low-concentration p-type GaN layer to the first n-type GaN layer, and
A step of forming a second n-type GaN layer inside the opening and on the upper surface of the low-concentration p-type GaN layer by an epitaxial growth method.
This is a step of forming a trench reaching from the upper surface of the second n-type GaN layer to the low-concentration p-type GaN layer, and is said to be outside the region where the opening is arranged when viewed from above. The process of forming a trench and
A step of forming a contact region formed of high-concentration p-type GaN having a higher p-type impurity concentration than the low-concentration p-type GaN layer in the trench.
An annealing step of diffusing hydrogen contained in the low-concentration p-type GaN layer into the contact region by annealing in an inert atmosphere.
A step of forming a source electrode in contact with at least a part of the contact region, and
A method for manufacturing a nitride semiconductor device. The method for manufacturing a nitride semiconductor device according to claim 5 , wherein the step of forming the contact region is performed by an epitaxial growth method or a sputtering method.

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