TW201624713A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region, wherein a bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure.

Description

Semiconductor device and method of manufacturing same

The present invention relates to an integrated circuit device, and more particularly to a semiconductor device and a method of fabricating the same.

In recent years, due to the rapid development of communication devices such as mobile communication devices and personal communication devices, wireless communication products such as mobile phones and base stations have shown significant growth. Among wireless communication products, high voltage components of laterally diffused metal oxide semiconductor (LDMOS) devices are often used as components of radio frequency (900 MHz-2.4 GHz) circuits.

The laterally diffused MOS device not only has a high operating bandwidth, but also has a high output power because it can withstand a high breakdown voltage, and is therefore suitable for use as a power amplifier for wireless communication products. In addition, since the laterally diffused metal oxide semiconductor (LDMOS) device can be formed by a conventional complementary metal oxide semiconductor (CMOS) process technology, its fabrication technology is relatively mature and can be made by using a cheaper tantalum substrate.

According to an embodiment, the present invention provides a semiconductor device comprising: a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer adjacent to the first well region; a first isolation An element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed between the first isolation element and the second isolation element a first doped region disposed in the first well region; and a second doped region disposed in the second well region, wherein the semiconductor substrate, the semiconductor layer, and the second well region have a first conductivity type, wherein the first well region, the first doped region and the second doped region have a second conductivity type opposite to the first conductivity type, and one of the gate structures Above, below or substantially horizontal to one of the bottom surfaces of the first spacer element.

According to still another embodiment, the present invention provides a method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a semiconductor layer on the semiconductor substrate; forming a first well region in the semiconductor layer and the semiconductor substrate; Forming a second well region in the semiconductor layer adjacent to the first well region; forming a first isolation element in the first well region and a second isolation member in the second well region; forming a gate Structured in the semiconductor layer between the first isolation element and the second isolation element; and forming a first doped region in the first well region and a second doped region in the second well region The semiconductor substrate, the semiconductor layer, and the second well region have a first conductivity type, and the first well region, the first doped region, and the second doped region have opposite to the first conductivity type One of the second conductivity types, and one of the bottom surfaces of the gate structure, is above, below or substantially horizontal to one of the bottom surfaces of the first isolation element.

The above described objects, features and advantages of the present invention will become more apparent and understood.

10‧‧‧Semiconductor device

12‧‧‧Semiconductor substrate

14‧‧‧Semiconductor layer

16‧‧‧First Well Area

18‧‧‧Second well area

20‧‧‧First isolation element

22‧‧‧Second isolation element

26‧‧‧Brake insulation

28‧‧‧ Conductive layer

30‧‧‧Doped area

32‧‧‧Doped area

34‧‧‧ Path

36‧‧‧ corner

100, 200, 300, 400, 500, 600, 700, 800‧‧‧ semiconductor devices

102‧‧‧Semiconductor substrate

104‧‧‧Semiconductor layer

106‧‧‧ Well Area

108‧‧‧ Well Area

110, 110', 112‧‧‧ isolation components

114, 114’‧‧‧ notches

116‧‧‧ brake insulation

118‧‧‧ Conductive layer

120‧‧‧Doped area

122‧‧‧Doped area

130‧‧‧ Path

132‧‧‧ corner

G‧‧‧ gate structure

D1‧‧‧ distance

D2‧‧‧ distance

D3‧‧‧Deep difference

D4‧‧‧Deep difference

1 is a cross-sectional view showing a semiconductor device in accordance with an embodiment of the present invention; and FIGS. 2-5 are a series of cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention; 8 is a series of cross-sectional views showing a method of fabricating a semiconductor device in accordance with another embodiment of the present invention; and FIG. 9 is a cross-sectional view showing a semiconductor device in accordance with still another embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 11 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention; FIG. 11 is a cross-sectional view showing a semiconductor device according to still another embodiment of the present invention; A semiconductor device according to another embodiment of the present invention; FIG. 13 is a cross-sectional view showing a semiconductor device according to still another embodiment of the present invention; and FIG. 14 is a cross-sectional view showing another embodiment according to the present invention. A semiconductor device according to an embodiment; and FIG. 15 is a schematic cross-sectional view showing another embodiment of the present invention Semiconductor device.

Referring to FIG. 1, a cross-sectional view of a semiconductor device 10 in accordance with an embodiment of the present invention is shown. Here, the semiconductor device 10 is The semiconductor device of the present invention is known as a comparative example and is shown as a laterally diffused metal oxide semiconductor (LDMOS) device to illustrate the current crowding effect of the semiconductor device 10 discovered by the inventors of the present invention. Problems such as a breakdown voltage. However, the implementation of the semiconductor device 10 shown in FIG. 1 is not intended to limit the scope of the invention.

As shown in FIG. 1, the semiconductor device 10 includes: a semiconductor substrate 12; a semiconductor layer 14 disposed on the semiconductor substrate 12; a first well region 16 disposed in the semiconductor layer 14 and the semiconductor substrate 12; The well region 18 is disposed in the semiconductor layer 14 and adjacent to the first well region 16; a first isolation element 20 is disposed in the first well region 16; a second isolation member 22 is disposed in the second well region 18; a gate structure G is disposed on the semiconductor layer 16 between the first isolation element 20 and the second isolation element 22 and partially covers the first isolation element 20; a first doped region 32 is disposed in the first well region 16; and a second doped region 30 disposed in the second well region 18.

As shown in FIG. 1, the semiconductor substrate 12 is, for example, a germanium substrate, and the semiconductor layer 14 is an epitaxial semiconductor layer formed on the semiconductor substrate 12 by, for example, an epitaxial method, for example, an epitaxial layer. The semiconductor substrate 12, the semiconductor layer 14 and the second well region 18 may have a first conductivity type such as an N-type or a P-type, and the first well region 16, the first doping region 30 and the second doping region 32 have For example, the P type or the N type is opposite to the second conductivity type of the first conductivity type. Here, the gate structure G is shown as a planar gate structure including a gate insulating layer 26 and a conductive layer 28 sequentially disposed on the semiconductor layer 14, and the first isolation element 20 and The second isolation element 22 is shown as a shallow trench isolation (STI) element having a bottom surface having a semiconductor layer The top surface of 14 is about a distance D1 of 0.1-2 microns.

Thus, the semiconductor device 10 shown in FIG. 1 can be used as a high voltage component such as a laterally diffused metal oxide semiconductor (LDMOS) device. Here, the first well region 16 can be used as a drift region, and the second doping region 32 is disposed in the semiconductor layer 14 between the second isolation element 22 and the gate structure G and is located in the second One portion of the well region 18 is used as a source region, and the first doping region 30 is disposed in the semiconductor layer 14 of the first isolation device 20 not adjacent to one side of the gate structure G and Located in one of the first well regions 16 for use as a drain region. When the semiconductor device 10 is operated, an appropriate bias voltage (not shown) may be applied to the gate structure G and the first doped region 30 doped region and the second doped region 32, thus, such as electron or hole carriers (not Displayed) can flow from the second doped region 32 along a path 34 to the first doped region 30. However, during the flow along the path 34, the carrier is susceptible to a current crowding effect at the corner 36 due to the large angle transition of the path 34 near the corner 36 of the first spacer element 20. The reliability of the semiconductor device 10 is affected. In addition, when the semiconductor device 10 is operated, it can also be found that the associated power line distribution (not shown) also creates an electric field crowding effect at the corner 36 of the first isolation element 20, thereby reducing the breakdown voltage performance of the semiconductor device 10.

Accordingly, the present invention provides a semiconductor device and a method of fabricating the same to provide a semiconductor device that can be used as a high voltage component such as a laterally diffused metal oxide semiconductor (LDMOS) device, with a view to reducing or avoiding the aforementioned undesirable current crowding effect. And the generation of a breakdown voltage, and providing a semiconductor device with more reliable and better electrical performance.

Referring to Figures 2-5, one embodiment of the present invention is shown. A series of cross-sectional schematic views of a method of fabricating a semiconductor device 100.

Referring to FIG. 2, first, a semiconductor substrate 102 such as a germanium substrate is provided. In one embodiment, the semiconductor substrate 102 has a first conductivity type such as a p-type and a resistivity between 0.001 and 1000 ohm-cm (Ω-cm). Then, a semiconductor layer 104 such as a silicon layer is formed on the semiconductor substrate 102 by a method such as epitaxial growth. The semiconductor layer 104 may be doped with a dopant of a first conductivity type such as a P-type, and has a resistivity of about 0.001 to 1000 ohm-cm (Ω-cm). In one embodiment, the resistivity of the semiconductor layer 104 is greater than the resistivity of the semiconductor substrate 102. Next, a well region 106 is formed in one of the semiconductor layer 104 and the semiconductor substrate 102 by the use of a patterned mask layer and the implementation of an ion implantation process (all not shown). The well region 106 is doped with a dopant of a second conductivity type opposite to the first conductivity type of the semiconductor layer 104 and the semiconductor substrate 102, such as an N-type dopant, and has a thickness of about 0.01 to 100 ohm-cm (Ω). -cm) Resistivity.

Referring to FIG. 3, after the patterned mask layer for forming the well region 106 is removed, the use of another patterned mask layer and the execution of another ion implantation process (all not shown) are performed. A well region 108 is formed in one of the semiconductor layers 104 of the adjacent well region 106. The well region 108 is doped with a dopant of the first conductivity type similar to the semiconductor layer 104 and the semiconductor substrate 102, such as a P-type dopant, and has a resistivity of about 0.01 to 100 ohm-cm (Ω-cm). (resistivity). Next, an isolation element 110 is formed in one of the well regions 106 and an isolation element 112 is formed in one of the well regions 108. The isolation elements 110 and 112 are shown here as shallow trench isolation (STI). An element, which may be formed by a process of a conventional shallow trench isolation element, includes an insulating material such as hafnium oxide, and the bottom surfaces of the isolation elements 110 and 112 are separated from the top surface of the semiconductor layer 104 by a distance of about 0.1 to 2 microns. .

Referring to FIG. 4, after removing the patterned mask layer for forming the well region 108, the use of another patterned mask layer and the execution of another etching process (neither shown) are adjacent. A recess 114 is formed in one of the semiconductor layers 104 of the well regions 106 and 108. During the formation of the recess 114, one of the spacer elements 110 in the well region 106 can be selectively removed, thereby forming a recess 114 having a U-like shape. It should be noted that the bottom surface of the recess 114 is substantially horizontal to the bottom surfaces of the spacer elements 110 and 112, so that there is substantially no depth difference between the bottom surface of the recess 114 and the bottom surfaces of the spacer elements 110 and 112. A patterned gate structure G is then formed on the surface of the semiconductor layer 104 and the isolation member 110 exposed by the recess 114 and on the surface of the semiconductor layer 104 adjacent to the recess 114. Here, the patterned gate structure G is adjacent to the isolation element 110 and partially covers the top surface of the isolation element 110. The patterned gate structure G may include a gate insulating layer 116 and a conductive layer 118 disposed in sequence. For the purpose of simplification, the patterned gate structure G can be formed by a conventional gate process, and the inner gate insulating layer 116 and the conductive layer 118 can include a conventional gate structure material, so the implementation thereof will not be described in detail herein. Situation and related production situation. Here, the bottom surface of the portion of the gate structure G patterned in the recess 114 in the semiconductor layer 104 is substantially horizontal to the bottom surfaces of the isolation elements 110 and 112 without a depth difference therebetween.

Referring to FIG. 5, after removing the patterned mask layer for forming the recess 114, the patterning layer is used and the ion implantation process is followed. Execution (neither shown) forms a doped region 120 in a portion of the well region 106 adjacent the isolation element 110 that does not contact the gate structure G, and one of the well regions 108 between the isolation element 112 and the gate structure G A doped region 122 is formed in the portion. The doped regions 120 and 122 are doped with a dopant of a second conductivity type opposite to the first conductivity type of the semiconductor layer 104, the semiconductor substrate 102 and the well region 108, for example, an N-type dopant, and have an approximate Resistivity of 0.1 to 10 ohm-cm (Ω-cm).

At this point, the fabrication of the semiconductor device 100 is substantially completed. The semiconductor device 100 as shown in Fig. 5 can be used as a high voltage component such as a laterally diffused metal oxide semiconductor (LDMOS) device. The well region 106 can be used as a drift region, and the doping region 122 can be used as a source region, and the doping region 120 can be used as a drain region. Use. Appropriate bias voltage (not shown) may be applied to the gate structure G and the doped regions 120 and 122 when the semiconductor device 100 is operated, so that carriers such as electrons or holes (not shown) may be self-doped at the region 122. Flows along a path 130 to the doped region 120. Here, during the flow of the carrier along the path 130, since one portion of the gate structure G is disposed in the semiconductor layer 104 and the bottom surface thereof is substantially horizontal to the bottom surface of the adjacent isolation member 110, The semiconductor device 10 does not have a current crowding effect at the corner 132 due to the angular transition of the path 130 at the corner 132 of the isolation element 130 as in the semiconductor device 10 shown in FIG. Reliability. In addition, by the arrangement as shown in FIG. 5, when the semiconductor device 100 is operated, it can also be found that the relevant power line distribution (not shown) does not cause an electric field crowding effect at the corner 132 of the isolation element 110. Further, the breakdown voltage performance of the semiconductor device 100 is not lowered.

Therefore, with the manufacturing method shown in FIGS. 2-5, it is possible to provide a semiconductor device 100 having a reduced or no aforementioned current crowding effect and a collapse voltage drop situation, which is suitable for, for example, lateral diffusion gold. For high voltage components of oxygen semiconductor (LDMOS) devices.

Referring to FIGS. 6-8, a series of cross-sectional views showing a method of fabricating a semiconductor device in accordance with another embodiment of the present invention are shown. Here, the manufacturing method of the semiconductor device shown in FIGS. 6-8 is obtained by modifying the manufacturing method of the semiconductor device shown in FIGS. 2-5, and therefore only the explanations and FIGS. 6-8 and FIG. 2-5 shows the difference between the manufacturing methods of the semiconductor device shown in the drawings, and the same reference numerals in the drawings represent the same elements.

Referring to Fig. 6, a structure similar to that of Fig. 3 is provided by a manufacturing method similar to that shown in Fig. 2-3. However, in Fig. 6, the formed spacer element 110' includes, in addition to the portion of the spacer element 110 as shown in Fig. 2, which further includes a portion extending toward the well region 108 and disposed in the well region 108.

Referring to Figure 7, a notch 114' is formed in one of the semiconductor layers 104 of adjacent well regions 106 and 108 by the use of a patterned mask layer and the application of an etching process (all not shown). During the formation of the recess 114', one of the spacer elements 110' spanning the well regions 108 and 106 can be selectively removed to form a recess 114' having a U-like shape. It should be noted that the bottom surface of the recess 114' is generally horizontal to the bottom surfaces of the spacer members 110 and 112, so that the bottom surface of the recess 114' does not have a depth difference from the bottom surfaces of the spacer members 110 and 112.

Please refer to FIG. 8 , and then form a gate structure G as a notch. The surface of the exposed semiconductor layer 104 and the spacer member 110' of 114' and the surface of the semiconductor layer 104 and the spacer member 110' adjacent to the recess 114'. Here, the gate structure G of the pattern is adjacent to the spacer element 110' and partially covers the top surface of the spacer element 110. The patterned gate structure G may include a gate insulating layer 116 and a conductive layer 118 disposed in sequence. For the purpose of simplification, the patterned gate structure G can be formed by a conventional gate process, and the inner gate insulating layer 116 and the conductive layer 118 can include a conventional gate structure material, so the implementation thereof will not be described in detail herein. Situation and related production situation. Here, the bottom surface of the portion of the gate structure G patterned in the recess 114' disposed in the semiconductor layer 104 is substantially horizontal to the bottom surfaces of the spacer elements 110 and 112 with substantially no depth difference therebetween.

Referring to FIG. 8, the fabrication of the semiconductor device 100 is substantially completed by the same operation as the process shown in FIG. The semiconductor device 100 shown in FIG. 8 is the same as the semiconductor device 100 shown in FIG. 5, and is also applicable to applications such as a high voltage component of a laterally diffused metal oxide semiconductor (LDMOS) device, and has the same The semiconductor device 100 shown in FIG. 5 has reduced or no technical effects such as an undesired current crowding effect and a collapse voltage drop.

The implementation of the semiconductor device of the present invention is not limited to the implementation of the semiconductor device 100 shown in FIGS. 5 and 8, and may include a semiconductor device as shown in FIGS. 9-15. Here, the semiconductor device shown in FIGS. 9-15 is obtained by modifying the semiconductor device 100 shown in FIGS. 5 and 8, and the same reference numerals in the drawings of FIGS. 9-15 represent the same elements. For the purpose of simplification, only the differences from the semiconductor device 100 shown in FIGS. 5 and 8 are illustrated in FIGS. 9-15.

Referring to FIG. 9, a cross-sectional view of a semiconductor device 200 in accordance with another embodiment of the present invention is shown. Here, unlike the implementation of the semiconductor device 100 shown in FIGS. 5 and 8, in the semiconductor device 200 shown in FIG. 9, the bottom surface of the portion of the gate structure G provided in the semiconductor layer 104 is lower than The bottom surfaces of the isolation members 110 and 112, and the bottom surface of the portion of the gate structure G and the bottom surface of the spacer members 110 and 112 have a depth difference D3 of less than 0.1 μm. In one embodiment, this depth difference D3 is preferably less than 0.05 microns. As such, the semiconductor device 200 can provide an electrical performance situation with or without the aforementioned undesirable current crowding effects and collapse voltage reduction.

Referring to FIG. 10, a cross-sectional view of a semiconductor device 300 in accordance with still another embodiment of the present invention is shown. Here, unlike the implementation of the semiconductor device 100 shown in FIGS. 5 and 8, in the semiconductor device 300 shown in FIG. 10, the bottom surface of the portion of the gate structure G provided in the semiconductor layer 104 is higher than The bottom surfaces of the spacer elements 110 and 112, and the bottom surface of the portion of the gate structure G and the bottom surface of the spacer elements 110 and 112 have a depth difference D4 of less than 0.1 μm. In one embodiment, this depth difference D4 is preferably less than 0.05 microns. As such, the semiconductor device 300 can provide an electrical performance situation with or without the aforementioned undesirable current crowding effects and reduced breakdown voltage.

Referring to FIG. 11, a cross-sectional view of a semiconductor device 400 in accordance with another embodiment of the present invention is shown. Here, unlike the implementation of the semiconductor device 100 shown in FIGS. 5 and 8, in the semiconductor device 400 shown in FIG. 11, the gate structure G is disposed only in the semiconductor layer 104 of the well region 106 and covered. A portion of the top surface of the isolation element 100 adjacent thereto is disposed, and the doped region 122 is disposed adjacent to one of the semiconductor layers 104 of the well region 108 adjacent the well region 106. Within.

Referring to FIG. 12, a cross-sectional view of a semiconductor device 500 in accordance with still another embodiment of the present invention is shown. Here, unlike the implementation of the semiconductor device 100 shown in FIGS. 5 and 8, in the semiconductor device 500 shown in FIG. 12, the spacer member 110 is extended and disposed in a portion of the well region 108, and the gate is The pole structure G is disposed only within the semiconductor layer 104 within the well region 108 and covers a portion of the top surface of the spacer element 110 adjacent thereto.

Referring to FIG. 13, a cross-sectional view of a semiconductor device 600 in accordance with another embodiment of the present invention is shown. Here, unlike the implementation of the semiconductor device 100 shown in FIGS. 5 and 8, in the semiconductor device 600 shown in FIG. 13, the spacer member 110 is extended and disposed in the well region 106 adjacent to the well region 108. In one portion, the gate structure G is disposed only within the semiconductor layer 104 within the well region 108 and adjacent to the isolation element 110 but does not cover the top surface of the isolation element 110.

Referring to FIG. 14, a cross-sectional view of a semiconductor device 700 in accordance with still another embodiment of the present invention is shown. Here, unlike the implementation of the semiconductor device 100 shown in FIGS. 5 and 8, in the semiconductor device 700 shown in FIG. 14, the gate structure G is disposed only in the semiconductor layer 104 in the well region 106 and A portion of the top surface of the isolation element 110 adjacent thereto is covered, and the doped region 122 is disposed within a portion of the well region 108 adjacent the well region 106. Here, the gate structure G has a zig-zag-like shape profile, instead of a U-like shape profile as shown in Figs.

Referring to FIG. 15, a cross-sectional view of a semiconductor device 800 in accordance with another embodiment of the present invention is shown. Here, unlike the 5th and 8th In the semiconductor device 100 shown in FIG. 15, the gate structure G has a zig-zag-like shape profile and covers only the well region. The top surface of the semiconductor layer 104 within 106 does not cover the top surface of the spacer element 110 adjacent thereto, and the doped region 122 is disposed in a portion of the well region 108 adjacent the well region 106.

The semiconductor device shown in Figures 9-15 can also be formed by the manufacturing method as shown in Figures 2-5, 6-8, etc., which is only required in Figures 2-5, 6-8, etc. In the manufacturing method shown, the arrangement position of the relevant member and the pattern of the patterned mask layer for forming the relevant member are adjusted, and thus the related production will not be described in detail herein. In addition, the bottom surface of the gate structure G in the semiconductor devices 400, 500, 600, 700, and 800 shown in FIGS. 11-15 is shown as being substantially horizontal to the bottom surface of the isolation elements 110, 112. However, in other embodiments, the bottom surface of the gate structure G in the semiconductor devices 400, 500, 600, 700, 800 shown in FIGS. 9-15 may also be as shown in FIG. 9-10. It may be higher or lower than the bottom surface of the isolation elements 110, 112 and have a depth difference of less than 0.1 microns from the bottom surfaces of the isolation elements 110, 112. In one embodiment, this difference in depth is preferably less than 0.05 microns. Thus, the semiconductor devices 400, 500, 600, 700, 800 as shown in Figures 9-15 can provide electrical performance with or without the aforementioned undesirable current crowding effects and collapse voltage reduction.

Similar to the semiconductor device 100 shown in FIGS. 5 and 8, the semiconductor devices 400, 500, 600, 700, and 800 shown in FIGS. 9-15 are also applicable to a high voltage such as a laterally diffused metal oxide semiconductor (LDMOS) device. Application of the component, and having the same or less than the semiconductor device 100 shown in FIGS. 5 and 8 Technical effects such as expected current crowding effects and collapse voltage reduction scenarios.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100‧‧‧Semiconductor device

102‧‧‧Semiconductor substrate

104‧‧‧Semiconductor layer

106‧‧‧ Well Area

108‧‧‧ Well Area

110‧‧‧Isolation components

112‧‧‧Isolation components

116‧‧‧ brake insulation

118‧‧‧ Conductive layer

120‧‧‧Doped area

122‧‧‧Doped area

130‧‧‧ Path

132‧‧‧ corner

G‧‧‧ gate structure

Claims (24)

A semiconductor device comprising: a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate; a first well region disposed in the semiconductor layer and the semiconductor substrate; and a second well region disposed in the semiconductor layer And adjacent to the first well region; a first isolation element disposed in the first well region; a second isolation component disposed in the second well region; and a gate structure disposed on the first isolation component a semiconductor layer disposed between the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region, wherein the semiconductor The substrate, the semiconductor layer, the second well region have a first conductivity type, and the first well region, the first doped region and the second doped region have a second opposite to the first conductivity type The conductivity type, and one of the bottom surfaces of the gate structure, is higher, lower or horizontal to one of the bottom surfaces of the first isolation element. The semiconductor device of claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. The semiconductor device of claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type. The semiconductor device of claim 1, wherein the bottom surface of the gate structure is higher or lower than the bottom surface of the first isolation element and has a depth difference of less than 0.1 micron. The semiconductor device of claim 1, wherein the gate junction The bottom surface is horizontal to the bottom surface of the first isolation element, and there is no depth difference between the bottom surface of the gate structure and the bottom surface of the first isolation element. The semiconductor device of claim 1, wherein the first isolation element and the second isolation element are shallow trench spacers. The semiconductor device of claim 1, wherein the gate structure is disposed between the first isolation element and the second isolation element in the first well region and the second well region Inside, and has a U-like shape. The semiconductor device of claim 1, wherein the gate structure is disposed in the semiconductor layer between the first isolation element and the second isolation element in the first well region, and has a class U One of the shapes. The semiconductor device of claim 1, wherein the gate structure is disposed in the semiconductor layer of the second well region between the first isolation element and the second isolation element, and has a class U One shape. The semiconductor device of claim 1, wherein the first isolation element is disposed in the second well region, and the gate structure is disposed between the first isolation element and the second isolation element. The second well region has a shape of a U-like shape in the semiconductor layer. The semiconductor device of claim 1, wherein the gate structure is disposed between the first isolation element and the second isolation element in the first well region and the second well region Inside, and has a shape like a zigzag. A method of fabricating a semiconductor device, comprising: Providing a semiconductor substrate; forming a semiconductor layer on the semiconductor substrate; forming a first well region in the semiconductor layer and the semiconductor substrate; forming a second well region in the semiconductor layer adjacent to the first well region; Forming a first isolation element in the first well region and a second isolation component in the second well region; forming a gate structure between the first isolation element and the second isolation element And forming a first doped region in the first well region and a second doped region in the second well region, wherein the semiconductor substrate, the semiconductor layer, and the second well region have a first Conductive type, and the first well region, the first doped region and the second doped region have a second conductivity type opposite to the first conductivity type, and one of the gate structures is higher than the bottom surface Below or horizontal to one of the bottom surfaces of the first isolation element. The method of fabricating a semiconductor device according to claim 12, wherein the first conductivity type is a P type and the second conductivity type is an N type. The method of fabricating a semiconductor device according to claim 12, wherein the first conductivity type is an N type and the second conductivity type is a P type. The method of fabricating a semiconductor device according to claim 12, wherein the bottom surface of the gate structure is higher or lower than the bottom surface of the first isolation element and has a depth difference of less than 0.1 μm. The method of manufacturing the semiconductor device of claim 12, wherein the bottom surface of the gate structure is substantially horizontal to a bottom surface of the first isolation element, and the bottom surface of the gate structure and the first isolation element The bottom surface There is no depth difference between them. The method of fabricating a semiconductor device according to claim 12, wherein the first isolation element and the second isolation element are shallow trench spacers. The method of manufacturing a semiconductor device according to claim 12, wherein the gate structure is formed between the first well region and the second well region between the first isolation member and the second isolation member The semiconductor layer has a U-like shape. The method of fabricating a semiconductor device according to claim 18, wherein the forming the gate structure in the semiconductor layer between the first isolation element and the second isolation element comprises: forming a notch in the phase Adjacent to the first well region and one of the semiconductor layers in the second well region, wherein the recess is adjacent to the first isolation element and has a U-like shape; and the gate structure is formed And on the semiconductor layer between an isolation element and the second isolation element and on the recess, wherein the gate structure has a U-like shape. The method of fabricating a semiconductor device according to claim 18, wherein the first isolation element is formed in one of the second well regions, and the gate structure is formed in the first isolation element and the second isolation The semiconductor layer between the components includes: forming a recess in the adjacent one of the first well region and the second well region, wherein the recess is adjacent to the first isolation component and Having a shape of a U-like shape, and forming the notch removes the first isolation element formed in the portion of the second well region and located in the first well region One of the first isolation elements; and the gate structure is formed on and on the semiconductor layer between the first isolation element and the second isolation element, wherein the gate structure has a U-like shape The shape. The method of fabricating a semiconductor device according to claim 12, wherein the gate structure is formed in the semiconductor layer between the first isolation element and the second isolation element in the first well region, and Has one of the U-shaped shapes. The method of fabricating a semiconductor device according to claim 12, wherein the gate structure is formed in the semiconductor layer between the first isolation element and the second isolation element in the second well region, and Has a U-like shape. The method of fabricating a semiconductor device according to claim 12, wherein the first isolation element is further formed in the second well region, and the gate structure is disposed on the first isolation element and the second isolation element Between the semiconductor layers of the second well region, and having a U-like shape. The method of manufacturing a semiconductor device according to claim 12, wherein the gate structure is formed between the first well region and the second well region between the first isolation member and the second isolation member The semiconductor layer has a shape of a zigzag-like shape.