TWI623103B - Lateral diffused metal oxide semiconductor transistor and manufacturing method thereof - Google Patents
Lateral diffused metal oxide semiconductor transistor and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 53
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
一種橫向擴散金屬氧化物半導體電晶體及其製作方法。橫向擴散金屬氧化物半導體電晶體包括基底、深井區、井區、隔離結構、閘極、閘介電層、第一摻雜區、第二摻雜區以及導電結構。深井區配置於基底中。隔離結構配置於基底中，以定義出第一主動區與第二主動區。井區配置於第一主動區中的深井區中。閘極配置於第一主動區中的基底上。閘介電層配置於閘極與基底之間。第一摻雜區配置於第一主動區中的井區中且位於閘極的一側。第二摻雜區配置於第二主動區中的深井區中。導電結構配置於隔離結構上、圍繞第二摻雜區，且與閘極連接。A laterally diffused metal oxide semiconductor transistor and a method of fabricating the same. The laterally diffused metal oxide semiconductor transistor includes a substrate, a deep well region, a well region, an isolation structure, a gate, a gate dielectric layer, a first doped region, a second doped region, and a conductive structure. The deep well area is disposed in the substrate. The isolation structure is disposed in the substrate to define the first active area and the second active area. The well zone is disposed in the deep well zone in the first active zone. The gate is disposed on the substrate in the first active region. The gate dielectric layer is disposed between the gate and the substrate. The first doped region is disposed in the well region in the first active region and on one side of the gate. The second doped region is disposed in the deep well region in the second active region. The conductive structure is disposed on the isolation structure, surrounds the second doped region, and is connected to the gate.
Description
本發明是有關於一種半導體元件及其製作方法，且特別是有關於一種橫向擴散金屬氧化物半導體（lateral diffused metal oxide semiconductor，LDMOS）電晶體及其製作方法。The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a lateral diffused metal oxide semiconductor (LDMOS) transistor and a method of fabricating the same.
在目前的半導體元件中，橫向擴散金屬氧化物半導體電晶體由於其高功率、高電壓、高能量以及高頻率等特性而已被廣泛地採用。當LDMOS電晶體應用於高電壓元件時，因為需要有高的崩潰電壓，其必須避免元件產生累增崩潰（avalanche breakdown）現象。Among the current semiconductor elements, laterally diffused metal oxide semiconductor transistors have been widely used due to their high power, high voltage, high energy, and high frequency characteristics. When an LDMOS transistor is applied to a high voltage component, it must avoid avalanche breakdown of the component because of the high breakdown voltage required.
然而，當元件的尺寸持續縮小時，LDMOS電晶體的鄰近汲極的區域容易因為接面崩潰電壓（junction breakdown voltage）過低而導致接面累增崩潰現象的產生。因此，如何有效地提高元件的崩潰電壓已得到業界的高度關注。However, when the size of the element continues to shrink, the area adjacent to the drain of the LDMOS transistor is liable to cause a junction collapse phenomenon due to a junction breakdown voltage that is too low. Therefore, how to effectively increase the breakdown voltage of components has been highly concerned by the industry.
本發明提供一種橫向擴散金屬氧化物半導體電晶體，其中導電結構配置於鄰近汲極的隔離結構上。The present invention provides a laterally diffused metal oxide semiconductor transistor in which a conductive structure is disposed on an isolation structure adjacent to a drain.
本發明提供一種橫向擴散金屬氧化物半導體電晶體的製作方法，其將導電結構形成於鄰近汲極的隔離結構上。The present invention provides a method of fabricating a laterally diffused metal oxide semiconductor transistor that forms a conductive structure on an isolation structure adjacent to a drain.
本發明的橫向擴散金屬氧化物半導體電晶體包括基底、隔離結構、深井區、井區、閘極、閘介電層、第一摻雜區、第二摻雜區以及導電結構。所述隔離結構配置於所述基底中，以定義出第一主動區與第二主動區。所述深井區配置於所述基底中。所述井區配置於所述第一主動區中的所述深井區中。所述閘極配置於所述第一主動區中的所述基底上。所述閘介電層配置於所述閘極與所述基底之間。所述第一摻雜區配置於所述第一主動區中的所述井區中且位於所述閘極的一側。所述第二摻雜區配置於所述第二主動區中的所述深井區中。所述導電結構配置於所述隔離結構上、圍繞所述第二摻雜區，且與所述閘極連接。The laterally diffused metal oxide semiconductor transistor of the present invention includes a substrate, an isolation structure, a deep well region, a well region, a gate, a gate dielectric layer, a first doped region, a second doped region, and a conductive structure. The isolation structure is disposed in the substrate to define a first active area and a second active area. The deep well region is disposed in the substrate. The well zone is disposed in the deep well zone in the first active zone. The gate is disposed on the substrate in the first active region. The gate dielectric layer is disposed between the gate and the substrate. The first doped region is disposed in the well region in the first active region and on one side of the gate. The second doped region is disposed in the deep well region in the second active region. The conductive structure is disposed on the isolation structure, surrounds the second doped region, and is connected to the gate.
在本發明的橫向擴散金屬氧化物半導體電晶體的一實施例中，上述導電結構的材料例如與所述閘極的材料相同。In an embodiment of the laterally diffused metal oxide semiconductor transistor of the present invention, the material of the conductive structure is, for example, the same as the material of the gate.
在本發明的橫向擴散金屬氧化物半導體電晶體的一實施例中，上述導電結構的材料例如為多晶矽。In an embodiment of the laterally diffused metal oxide semiconductor transistor of the present invention, the material of the above conductive structure is, for example, polysilicon.
在本發明的橫向擴散金屬氧化物半導體電晶體的一實施例中，上述導電結構例如與所述閘極連成一體。In an embodiment of the laterally diffused metal oxide semiconductor transistor of the present invention, the conductive structure is integrated, for example, with the gate.
在本發明的橫向擴散金屬氧化物半導體電晶體的一實施例中，上述導電結構與所述第二摻雜區之間的距離例如介於0.5微米至3微米之間。In an embodiment of the laterally diffused metal oxide semiconductor transistor of the present invention, the distance between the conductive structure and the second doped region is, for example, between 0.5 micrometers and 3 micrometers.
在本發明的橫向擴散金屬氧化物半導體電晶體的一實施例中，上述閘極例如延伸至所述閘極與所述第二摻雜區之間的所述隔離結構上。In an embodiment of the laterally diffused metal oxide semiconductor transistor of the present invention, the gate extends, for example, to the isolation structure between the gate and the second doped region.
在本發明的橫向擴散金屬氧化物半導體電晶體的一實施例中，上述隔離結構例如為矽局部氧化（local oxidation of silicon，LOCOS）結構或淺溝渠隔離（shallow trench isolation，STI）結構。In an embodiment of the laterally diffused metal oxide semiconductor transistor of the present invention, the isolation structure is, for example, a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure.
在本發明的橫向擴散金屬氧化物半導體電晶體的一實施例中，上述第一摻雜區作為源極，且所述第二摻雜區作為汲極。In an embodiment of the laterally diffused metal oxide semiconductor transistor of the present invention, the first doped region serves as a source and the second doped region serves as a drain.
在本發明的橫向擴散金屬氧化物半導體電晶體的一實施例中，上述深井區的導電類型例如與所述基底的導電類型不同。In an embodiment of the laterally diffused metal oxide semiconductor transistor of the present invention, the conductivity type of the deep well region is different, for example, from the conductivity type of the substrate.
本發明的橫向擴散金屬氧化物半導體電晶體的製作方法包括以下步驟：於基底中形成深井區；於基底中形成隔離結構，以定義出第一主動區與第二主動區；於所述第一主動區中的所述深井區中形成井區；於所述第一主動區中的所述基底上形成閘極；於所述閘極與所述基底之間形成閘介電層；於所述第一主動區中於所述閘極的一側的所述井區中形成第一摻雜區；於所述第二主動區中的所述深井區中形成第二摻雜區；於所述隔離結構上形成圍繞所述第二摻雜區的導電結構，且所述導電結構與所述閘極連接。The method for fabricating a laterally diffused metal oxide semiconductor transistor of the present invention comprises the steps of: forming a deep well region in a substrate; forming an isolation structure in the substrate to define a first active region and a second active region; Forming a well region in the deep well region in the active region; forming a gate on the substrate in the first active region; forming a gate dielectric layer between the gate and the substrate; Forming a first doped region in the well region of one side of the gate in a first active region; forming a second doped region in the deep well region in the second active region; A conductive structure surrounding the second doped region is formed on the isolation structure, and the conductive structure is connected to the gate.
在本發明的橫向擴散金屬氧化物半導體電晶體的製作方法的一實施例中，上述導電結構的材料例如與所述閘極的材料相同。In an embodiment of the method of fabricating the laterally diffused metal oxide semiconductor transistor of the present invention, the material of the conductive structure is, for example, the same as the material of the gate.
在本發明的橫向擴散金屬氧化物半導體電晶體的製作方法的一實施例中，上述導電結構的材料例如為多晶矽。In an embodiment of the method of fabricating the laterally diffused metal oxide semiconductor transistor of the present invention, the material of the conductive structure is, for example, polysilicon.
在本發明的橫向擴散金屬氧化物半導體電晶體的製作方法的一實施例中，上述導電結構與所述閘極例如在同一個步驟中形成。In an embodiment of the method of fabricating a laterally diffused metal oxide semiconductor transistor of the present invention, the conductive structure and the gate are formed, for example, in the same step.
在本發明的橫向擴散金屬氧化物半導體電晶體的製作方法的一實施例中，上述導電結構與所述第二摻雜區之間的距離例如介於0.5微米至3微米之間。In an embodiment of the method of fabricating the laterally diffused metal oxide semiconductor transistor of the present invention, the distance between the conductive structure and the second doped region is, for example, between 0.5 micrometers and 3 micrometers.
在本發明的橫向擴散金屬氧化物半導體電晶體的製作方法的一實施例中，上述閘極例如延伸至所述閘極與所述第二摻雜區之間的所述隔離結構上。In an embodiment of the method of fabricating a laterally diffused metal oxide semiconductor transistor of the present invention, the gate extends, for example, to the isolation structure between the gate and the second doped region.
在本發明的橫向擴散金屬氧化物半導體電晶體的製作方法的一實施例中，上述隔離結構例如為矽局部氧化結構或淺溝渠隔離結構。In an embodiment of the method for fabricating a laterally diffused metal oxide semiconductor transistor of the present invention, the isolation structure is, for example, a tantalum partial oxidation structure or a shallow trench isolation structure.
在本發明的橫向擴散金屬氧化物半導體電晶體的製作方法的一實施例中，上述第一摻雜區作為源極，且所述第二摻雜區作為汲極。In an embodiment of the method of fabricating a laterally diffused metal oxide semiconductor transistor of the present invention, the first doped region serves as a source and the second doped region serves as a drain.
在本發明的橫向擴散金屬氧化物半導體電晶體的製作方法的一實施例中，上述深井區的導電類型例如與所述基底的導電類型不同。In an embodiment of the method of fabricating a laterally diffused metal oxide semiconductor transistor of the present invention, the conductivity type of the deep well region is different from, for example, the conductivity type of the substrate.
基於上述，在本發明中，導電結構配置於隔離結構上且圍繞元件的汲極。以此方式，在元件的操作過程中，導電結構可以有效地提高深井區與鄰近的基底之間的接面累增崩潰電壓。此外，由於導電結構與閘極是在同一個步驟中形成，因此，不需要額外的生產成本與製程步驟。Based on the above, in the present invention, the conductive structure is disposed on the isolation structure and surrounds the drain of the element. In this manner, the conductive structure can effectively increase the junctional collapse voltage between the deep well region and the adjacent substrate during operation of the component. In addition, since the conductive structure and the gate are formed in the same step, no additional production cost and process steps are required.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A至圖1B為依據本發明實施例所繪示的橫向擴散金屬氧化物半導體電晶體的製作流程的上視示意圖。圖2A至圖2B為依據圖1A至圖1B中的I-I剖線所繪示的橫向擴散金屬氧化物半導體電晶體的製作流程剖面示意圖。在本實施例中，元件的導電類型僅為示例性的，並非用以限定本發明。舉例來說，在本實施例中，某一個元件的導電類型為p型，但在其他實施例中，此元件的導電類型可為n型。1A-1B are top schematic views showing a fabrication process of a laterally diffused metal oxide semiconductor transistor according to an embodiment of the invention. 2A to 2B are schematic cross-sectional views showing a manufacturing process of a laterally diffused metal oxide semiconductor transistor according to the I-I line in FIG. 1A to FIG. 1B. In the present embodiment, the conductivity type of the element is merely exemplary and is not intended to limit the invention. For example, in the present embodiment, the conductivity type of a certain element is p-type, but in other embodiments, the conductivity type of the element may be n-type.
首先，請同時參照圖1A與圖2A，於基底100中形成深井區102。基底100例如是p型矽基底，深井區102例如是n型深井區。深井區102的形成方法例如是對基底100進行離子植入製程，將n型摻質（例如，磷或砷）植入基底100中。然後，於基底100中形成隔離結構104。在本實施例中，隔離結構104例如是矽局部氧化結構，但本發明不限於此。在其他實施例中，隔離結構104也可以是淺溝渠隔離結構。在本實施例中，隔離結構104於基底100中定義出主動區100a與主動區100b。隔離結構104圍繞主動區100a與主動區100b。之後，於主動區100a中的深井區102中形成井區106。井區106例如是p型井區。井區106的形成方法例如是將p型摻質（例如，硼）植入深井區102中。此外，井區106的深度小於深井區102的深度。First, please refer to FIG. 1A and FIG. 2A simultaneously to form a deep well region 102 in the substrate 100. The substrate 100 is, for example, a p-type germanium substrate, and the deep well region 102 is, for example, an n-type deep well region. The deep well region 102 is formed by, for example, performing an ion implantation process on the substrate 100 to implant an n-type dopant (eg, phosphorus or arsenic) into the substrate 100. Then, an isolation structure 104 is formed in the substrate 100. In the present embodiment, the isolation structure 104 is, for example, a tantalum partial oxidation structure, but the invention is not limited thereto. In other embodiments, the isolation structure 104 can also be a shallow trench isolation structure. In the present embodiment, the isolation structure 104 defines the active region 100a and the active region 100b in the substrate 100. The isolation structure 104 surrounds the active area 100a and the active area 100b. Thereafter, well region 106 is formed in deep well region 102 in active region 100a. Well zone 106 is, for example, a p-type well zone. The well region 106 is formed by, for example, implanting a p-type dopant (e.g., boron) into the deep well region 102. Moreover, the depth of the well region 106 is less than the depth of the deep well region 102.
接著，請同時參照圖1B與圖2B，於主動區100a中的基底100上依序形成閘介電層108以及閘極110。此外，在形成閘極110時，同時於主動區100b的周圍的隔離結構104上形成與閘極110連接的導電結構112。閘介電層108、閘極110與導電結構112的形成方法描述如下。首先，進行氧化製程，以於主動區100a中的基底100上形成氧化層。然後，進行沉積製程，以於主動區100a與主動區100b中的基底100上形成導電層，且導電層覆蓋隔離結構104。在本實施例中，導電層例如為多晶矽層。之後，進行圖案化製程，移除部分的氧化層與導電層。Next, referring to FIG. 1B and FIG. 2B simultaneously, the gate dielectric layer 108 and the gate 110 are sequentially formed on the substrate 100 in the active region 100a. In addition, when the gate 110 is formed, the conductive structure 112 connected to the gate 110 is formed on the isolation structure 104 around the active region 100b. A method of forming the gate dielectric layer 108, the gate 110, and the conductive structure 112 is described below. First, an oxidation process is performed to form an oxide layer on the substrate 100 in the active region 100a. Then, a deposition process is performed to form a conductive layer on the substrate 100 in the active region 100a and the active region 100b, and the conductive layer covers the isolation structure 104. In this embodiment, the conductive layer is, for example, a polysilicon layer. Thereafter, a patterning process is performed to remove portions of the oxide layer and the conductive layer.
在本實施例中，在進行上述的圖案化製程之後，所形成的閘極110除了位於主動區100a中的基底100上之外，還延伸至鄰近的隔離結構104上，但本發明不限於此。在其他實施例中，閘極110可以是僅形成於主動區100a中的基底100上。此外，由於閘極110與導電結構112是藉由對導電層進行圖案化製程所定義出來的，因此閘極110與導電結構112具有相同的材料與相同的厚度。換句話說，在本實施例中，不需額外增加製程步驟即可於主動區100b的周圍的隔離結構104上形成與閘極110連接的導電結構112。更具體地說，用單一個光罩（photomask）即可同時定義閘極110與導電結構112。因此，不需要額外的生產成本與複雜的製程步驟。In the present embodiment, after performing the above-described patterning process, the formed gate 110 extends on the substrate 100 in the active region 100a and extends to the adjacent isolation structure 104, but the invention is not limited thereto. . In other embodiments, the gate 110 can be formed on the substrate 100 only in the active region 100a. In addition, since the gate 110 and the conductive structure 112 are defined by a patterning process for the conductive layer, the gate 110 and the conductive structure 112 have the same material and the same thickness. In other words, in the present embodiment, the conductive structure 112 connected to the gate 110 can be formed on the isolation structure 104 around the active region 100b without additional process steps. More specifically, the gate 110 and the conductive structure 112 can be simultaneously defined by a single photomask. Therefore, no additional production costs and complicated process steps are required.
之後，在主動區100a中於閘極110旁的基底100中形成摻雜區114a，以及於主動區100b中形成摻雜區114b，以完成本實施例的橫向擴散金屬氧化物半導體電晶體10的製作。在本實施例中，摻雜區114a與摻雜區114b為n型摻雜區，其摻雜濃度大於深井區102的摻雜濃度，且其深度小於井區106的深度。摻雜區114a與摻雜區114b的形成方法例如是以閘極110與隔離結構104作為罩幕，進行離子植入製程，將n型摻質（例如，磷或砷）植入基底100中。摻雜區114a與摻雜區114b可分別作為橫向擴散金屬氧化物半導體電晶體10的源極與汲極。Thereafter, a doping region 114a is formed in the active region 100a in the substrate 100 beside the gate 110, and a doping region 114b is formed in the active region 100b to complete the laterally diffused metal oxide semiconductor transistor 10 of the present embodiment. Production. In the present embodiment, the doping region 114a and the doping region 114b are n-type doping regions, the doping concentration thereof is greater than the doping concentration of the deep well region 102, and the depth thereof is smaller than the depth of the well region 106. The doping region 114a and the doping region 114b are formed by, for example, using the gate 110 and the isolation structure 104 as a mask to perform an ion implantation process to implant an n-type dopant (for example, phosphorus or arsenic) into the substrate 100. The doped region 114a and the doped region 114b may serve as the source and drain of the laterally diffused metal oxide semiconductor transistor 10, respectively.
在橫向擴散金屬氧化物半導體電晶體10中，導電結構112形成於隔離結構104上且圍繞摻雜區114b（例如，汲極），因此在橫向擴散金屬氧化物半導體電晶體10的操作過程中，導電結構112可以有效地提高深井區102與鄰近的基底100之間的接面崩潰電壓。另一方面，當元件的尺寸持續縮小時，藉由配置本發明導電結構112的方式可有效地將深井區102與鄰近的基底100之間的接面崩潰電壓維持在所需的位準。In the laterally diffused metal oxide semiconductor transistor 10, the conductive structure 112 is formed on the isolation structure 104 and surrounds the doped region 114b (eg, a drain), thus during the lateral diffusion of the metal oxide semiconductor transistor 10, The conductive structure 112 can effectively increase the junction collapse voltage between the deep well region 102 and the adjacent substrate 100. On the other hand, when the size of the element continues to shrink, the junction collapse voltage between the deep well region 102 and the adjacent substrate 100 can be effectively maintained at a desired level by configuring the conductive structure 112 of the present invention.
在本實施例中，導電結構112與摻雜區114b之間的距離D例如介於0.5微米至3微米之間，如圖1B與圖2B所示。在一實施例中，摻雜區114b可為（例如但不限於）長方形摻雜區，且長方形摻雜區的長邊或短邊至導電結構112的邊緣的距離均相同，如圖1B所示，但本發明並不以此為限。在另一實施例中，依設計需求，長方形摻雜區的長邊或短邊至導電結構112的邊緣的距離可不相同。In the present embodiment, the distance D between the conductive structure 112 and the doped region 114b is, for example, between 0.5 micrometers and 3 micrometers, as shown in FIGS. 1B and 2B. In an embodiment, the doping region 114b may be, for example, but not limited to, a rectangular doped region, and the distance from the long side or the short side of the rectangular doping region to the edge of the conductive structure 112 is the same, as shown in FIG. 1B. However, the invention is not limited thereto. In another embodiment, the distance from the long side or the short side of the rectangular doped region to the edge of the conductive structure 112 may be different according to design requirements.
在一實施例中，導電結構112與摻雜區114b之間的距離D可為（例如但不限於）約0.5微米、1.0微米、1.5微米、2.0微米、2.5微米、3.0微米，包括任意兩個前述數值之間的任何範圍。當導電結構112與摻雜區114b之間的距離D大於3微米時，將無法有效地提高元件的接面崩潰電壓。當導電結構112與摻雜區114b之間的距離D小於0.5微米時，導電結構112則無法有效地提高深井區102與鄰近的基底100之間的接面崩潰電壓。特別一提的是，上述導電結構112與摻雜區114b之間的距離D的數值會隨元件的尺寸、操作變壓、深井區的尺寸等而改變，並非用以限定本發明。In one embodiment, the distance D between the conductive structure 112 and the doped region 114b can be, for example, but not limited to, about 0.5 micron, 1.0 micron, 1.5 micron, 2.0 micron, 2.5 micron, 3.0 micron, including any two. Any range between the aforementioned values. When the distance D between the conductive structure 112 and the doped region 114b is greater than 3 micrometers, the junction breakdown voltage of the device cannot be effectively improved. When the distance D between the conductive structure 112 and the doped region 114b is less than 0.5 micrometers, the conductive structure 112 cannot effectively increase the junction collapse voltage between the deep well region 102 and the adjacent substrate 100. In particular, the value of the distance D between the conductive structure 112 and the doped region 114b varies depending on the size of the component, the operational pressure, the size of the deep well region, etc., and is not intended to limit the present invention.
在上述實施例中，是以將導電結構112形成於隔離結構104上且圍繞橫向擴散金屬氧化物半導體電晶體10的摻雜區114b（例如，汲極）為例來說明之，但並不用以限定本發明。本領域具有通常知識者應了解，本發明的觀念可應用於橫向擴散金屬氧化物半導體電晶體10之外的各種金屬氧化物半導體電晶體結構。更具體地說，只要是提供在隔離結構上且電性耦合至閘極以提高崩潰電壓的導電結構，均落入本發明的範疇內。In the above embodiment, the conductive structure 112 is formed on the isolation structure 104 and surrounds the doped region 114b (eg, the drain) of the lateral diffusion metal oxide semiconductor transistor 10 as an example, but is not used. The invention is defined. Those of ordinary skill in the art will appreciate that the concepts of the present invention are applicable to various metal oxide semiconductor transistor structures other than laterally diffused metal oxide semiconductor transistors 10. More specifically, it is within the scope of the present invention to provide a conductive structure that is provided on the isolation structure and electrically coupled to the gate to increase the breakdown voltage.
此外，在本實施例中，導電結構112與閘極110具有相同的材料且彼此連成一體，但本發明不限於此。在其他實施例中，視實際需求，導電結構112與閘極110也可以是具有不同材料，或是在不同製程步驟中形成。Further, in the present embodiment, the conductive structure 112 and the gate 110 have the same material and are integrally connected to each other, but the present invention is not limited thereto. In other embodiments, the conductive structure 112 and the gate 110 may also have different materials or be formed in different process steps depending on actual needs.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10‧‧‧橫向擴散金屬氧化物半導體電晶體10‧‧‧Transversely diffused metal oxide semiconductor transistor
100‧‧‧基底100‧‧‧Base
100a、100b‧‧‧主動區100a, 100b‧‧‧ active area
102‧‧‧深井區102‧‧‧Shenjing District
104‧‧‧隔離結構104‧‧‧Isolation structure
106‧‧‧井區106‧‧‧ Well Area
108‧‧‧閘介電層108‧‧‧gate dielectric layer
110‧‧‧閘極110‧‧‧ gate
112‧‧‧導電結構112‧‧‧Electrical structure
114a、114b‧‧‧摻雜區114a, 114b‧‧‧ doped area
D‧‧‧距離D‧‧‧Distance
圖1A至圖1B為依據本發明實施例所繪示的橫向擴散金屬氧化物半導體電晶體的製作流程的上視示意圖。 圖2A至圖2B為依據圖1A至圖1B中的I-I剖線所繪示的橫向擴散金屬氧化物半導體電晶體的製作流程剖面示意圖。1A-1B are top schematic views showing a fabrication process of a laterally diffused metal oxide semiconductor transistor according to an embodiment of the invention. 2A to 2B are schematic cross-sectional views showing a manufacturing process of a laterally diffused metal oxide semiconductor transistor according to the I-I line in FIG. 1A to FIG. 1B.
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