TW201438108A - Bipolar junction transistor and operating and manufacturing method for the same - Google Patents

Bipolar junction transistor and operating and manufacturing method for the same Download PDF

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TW201438108A
TW201438108A TW102109971A TW102109971A TW201438108A TW 201438108 A TW201438108 A TW 201438108A TW 102109971 A TW102109971 A TW 102109971A TW 102109971 A TW102109971 A TW 102109971A TW 201438108 A TW201438108 A TW 201438108A
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region
doped region
conductivity type
well regions
bipolar junction
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TW102109971A
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TWI532101B (en
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li-fan Chen
Wing-Chor Chan
Jeng Gong
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Macronix Int Co Ltd
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Abstract

A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions.

Description

雙極性接面電晶體及其操作方法與製造方法Bipolar junction transistor, operation method and manufacturing method thereof

本揭露是有關於半導體裝置及其操作方法與製造方法,特別是有關於雙極性接面電晶體及其操作方法與製造方法。
The present disclosure relates to a semiconductor device, a method of operating the same, and a method of fabricating the same, and more particularly to a bipolar junction transistor, an operating method thereof, and a method of fabricating the same.

半導體雙極性接面電晶體(bipolar junction transistor;BJT)裝置能藉由控制施加至基極端與集極端之電壓而操作成順向主動模式(forward-active mode)。舉例來說,NPN型雙極接面電晶體裝置具有P型基極區及N型集極區與射極區,於操作時,可分別於基極端與集極端施加正電壓V BE 與比V BE 更高之正電壓V CE。射極-基極接面可因而為順向偏壓,基極-集極接面可因而為逆向偏壓,並可降低基極電流I B 與集極電流I C,集極電流I C係定義為基極電流I B之β倍。因此雙極接面電晶體裝置可作為具有電流增益或β增益(beta gain)β之電流放大器。
A semiconductor bipolar junction transistor (BJT) device can operate in a forward-active mode by controlling the voltage applied to the base and collector terminals. For example, the NPN-type bipolar junction transistor device has a P-type base region and an N-type collector region and an emitter region. During operation, a positive voltage V BE and a ratio V can be applied to the base terminal and the collector terminal, respectively. BE Higher positive voltage V CE. The emitter-base junction can thus be forward biased, the base-collector junction can thus be reverse biased, and the base current IB and collector current IC can be reduced. The collector current IC is defined as the base. The current of the pole current IB is β times. Therefore, the bipolar junction transistor device can be used as a current amplifier with current gain or beta gain β.

實施例是有關於雙極性接面電晶體及其操作方法與製造方法,其具有良好的裝置特性。Embodiments are related to bipolar junction transistors and methods of operation and methods of manufacture thereof that have good device characteristics.


 根據一實施例,提供一種雙極性接面電晶體,包括一第一摻雜區、一第二摻雜區與一第三摻雜區。第一摻雜區具有一第一導電型。第二摻雜區包括形成於第一摻雜區中的數個井區。井區具有相反於第一導電型的一第二導電型。井區藉由第一摻雜區互相分開。第三摻雜區具有第一導電型。第三摻雜區形成在井區中,或形成在井區之間的第一摻雜區中。

According to an embodiment, a bipolar junction transistor is provided, including a first doped region, a second doped region, and a third doped region. The first doped region has a first conductivity type. The second doped region includes a plurality of well regions formed in the first doped region. The well region has a second conductivity type opposite to the first conductivity type. The well regions are separated from one another by a first doped region. The third doped region has a first conductivity type. The third doped region is formed in the well region or formed in the first doped region between the well regions.


根據一實施例,提供一種雙極性接面電晶體的操作方法。雙極性接面電晶體包括一第一摻雜區、一第二摻雜區與一第三摻雜區。第一摻雜區具有一第一導電型。第二摻雜區包括形成於第一摻雜區中的數個井區。井區具有相反於第一導電型的一第二導電型。井區藉由第一摻雜區互相分開。第三摻雜區具有第一導電型。第三摻雜區形成在井區中,或形成在井區之間的第一摻雜區中。操作方法包括以下步驟。提供一集極電壓至第一摻雜區。提供一基極電壓至第二摻雜區。提供一射極電壓至第三摻雜區。

According to an embodiment, a method of operating a bipolar junction transistor is provided. The bipolar junction transistor includes a first doped region, a second doped region, and a third doped region. The first doped region has a first conductivity type. The second doped region includes a plurality of well regions formed in the first doped region. The well region has a second conductivity type opposite to the first conductivity type. The well regions are separated from one another by a first doped region. The third doped region has a first conductivity type. The third doped region is formed in the well region or formed in the first doped region between the well regions. The method of operation includes the following steps. A collector voltage is provided to the first doped region. A base voltage is provided to the second doped region. An emitter voltage is provided to the third doped region.


 根據一實施例,提供一種雙極性接面電晶體的製造方法,包括以下步驟。於一第一摻雜區中形成一第二摻雜區的數個井區。第一摻雜區具有一第一導電型。井區具有相反於第一導電型的一第二導電型。井區藉由第一摻雜區互相分開。於井區中或於井區之間的第一摻雜區中形成一第三摻雜區。第三摻雜區具有第一導電型。

According to an embodiment, a method of fabricating a bipolar junction transistor is provided, comprising the following steps. A plurality of well regions of a second doped region are formed in a first doped region. The first doped region has a first conductivity type. The well region has a second conductivity type opposite to the first conductivity type. The well regions are separated from one another by a first doped region. A third doped region is formed in the well region or in the first doped region between the well regions. The third doped region has a first conductivity type.


為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

第1A圖繪示根據一實施例之雙極性接面電晶體的上視圖。
第1B圖為第1A圖之雙極性接面電晶體沿BB線的剖面圖。
第1C圖為第1A圖之雙極性接面電晶體沿CC線的剖面圖。
第2A圖繪示根據一實施例之雙極性接面電晶體的上視圖。
第2B圖為第2A圖之雙極性接面電晶體沿BB線的剖面圖。
第2C圖為第2A圖之雙極性接面電晶體沿CC線的剖面圖。
第3A圖繪示根據一實施例之雙極性接面電晶體的上視圖。
第3B圖為第3A圖之雙極性接面電晶體沿BB線的剖面圖。
第3C圖為第3A圖之雙極性接面電晶體沿CC線的剖面圖。
第4A圖繪示根據一實施例之雙極性接面電晶體的上視圖。
第4B圖為第4A圖之雙極性接面電晶體沿BB線的剖面圖。
第4C圖為第4A圖之雙極性接面電晶體沿CC線的剖面圖。
第5A圖繪示根據一實施例之雙極性接面電晶體的上視圖。
第5B圖為第5A圖之雙極性接面電晶體沿BB線的剖面圖。
第5C圖為第5A圖之雙極性接面電晶體沿CC線的剖面圖。
第6A圖繪示根據一實施例之雙極性接面電晶體的剖面圖。
第6B圖繪示根據一實施例之雙極性接面電晶體的剖面圖。
第7圖為根據一實施例之雙極性接面電晶體的電性曲線。
第8圖為根據一實施例之雙極性接面電晶體的電性曲線。
FIG. 1A is a top view of a bipolar junction transistor in accordance with an embodiment.
Fig. 1B is a cross-sectional view of the bipolar junction transistor of Fig. 1A taken along line BB.
Figure 1C is a cross-sectional view of the bipolar junction transistor of Figure 1A taken along line CC.
2A is a top view of a bipolar junction transistor in accordance with an embodiment.
Figure 2B is a cross-sectional view of the bipolar junction transistor of Figure 2A taken along line BB.
Figure 2C is a cross-sectional view of the bipolar junction transistor of Figure 2A taken along line CC.
3A is a top view of a bipolar junction transistor in accordance with an embodiment.
Figure 3B is a cross-sectional view of the bipolar junction transistor of Figure 3A taken along line BB.
Figure 3C is a cross-sectional view of the bipolar junction transistor of Figure 3A taken along line CC.
4A is a top view of a bipolar junction transistor in accordance with an embodiment.
Figure 4B is a cross-sectional view of the bipolar junction transistor of Figure 4A taken along line BB.
Figure 4C is a cross-sectional view of the bipolar junction transistor of Figure 4A taken along line CC.
FIG. 5A is a top view of a bipolar junction transistor in accordance with an embodiment.
Figure 5B is a cross-sectional view of the bipolar junction transistor of Figure 5A taken along line BB.
Figure 5C is a cross-sectional view of the bipolar junction transistor of Figure 5A taken along line CC.
6A is a cross-sectional view of a bipolar junction transistor in accordance with an embodiment.
6B is a cross-sectional view of a bipolar junction transistor in accordance with an embodiment.
Figure 7 is an electrical diagram of a bipolar junction transistor in accordance with an embodiment.
Figure 8 is an electrical diagram of a bipolar junction transistor in accordance with an embodiment.

第1A圖繪示根據一實施例之雙極性接面電晶體的上視圖。第1B圖為雙極性接面電晶體沿BB線的剖面圖。第1C圖為雙極性接面電晶體沿CC線的剖面圖。FIG. 1A is a top view of a bipolar junction transistor in accordance with an embodiment. Figure 1B is a cross-sectional view of the bipolar junction transistor along line BB. Figure 1C is a cross-sectional view of the bipolar junction transistor along line CC.

請參照第1B圖,第一摻雜區102包括井區104與接觸區106。井區104與接觸區106具有第一導電型例如N導電型。井區104位在基底108上。基底108具有相反於第一導電型的第二導電型例如P導電型。於一實施例中,井區104可藉由摻雜基底108的方式形成。於其他實施例中,井區104可以成長或沉積等的方式形成在基底108上。井區104可為高壓(HV)井區。井區104與基底108可包括半導體材料例如矽,或其他合適的材料。基底108可包括絕緣層上覆矽(SOI)。接觸區106可以摻雜井區104的方式形成。於實施例中,接觸區106是為重摻雜的。Referring to FIG. 1B, the first doped region 102 includes a well region 104 and a contact region 106. The well region 104 and the contact region 106 have a first conductivity type such as an N conductivity type. The well zone 104 is on the substrate 108. The substrate 108 has a second conductivity type, such as a P conductivity type, opposite to the first conductivity type. In one embodiment, the well region 104 can be formed by doping the substrate 108. In other embodiments, well region 104 may be formed on substrate 108 in a manner that is grown or deposited. Well zone 104 can be a high pressure (HV) well zone. Well region 104 and substrate 108 may comprise a semiconductor material such as germanium, or other suitable material. Substrate 108 may include an insulating layer overlying germanium (SOI). Contact region 106 can be formed in a manner that is doped with well region 104. In an embodiment, contact region 106 is heavily doped.

請參照第1B圖,第二摻雜區110包括數個井區112、114、116。井區112、114、116具有第二導電型例如P導電型。井區112、114、116可藉由摻雜第一摻雜區102的井區104形成。井區112、114、116可以磊晶的方式形成。第二摻雜區110的井區112、114、116可藉由第一摻雜區102的井區104互相分開。第二摻雜區110包括接觸區118,具有第二導電型例如P導電型。接觸區118可以摻雜井區112的方式形成,並可為重摻雜的。Referring to FIG. 1B, the second doped region 110 includes a plurality of well regions 112, 114, 116. The well regions 112, 114, 116 have a second conductivity type, such as a P conductivity type. The well regions 112, 114, 116 may be formed by doping the well region 104 of the first doped region 102. The well regions 112, 114, 116 can be formed in an epitaxial manner. The well regions 112, 114, 116 of the second doped region 110 may be separated from one another by the well region 104 of the first doped region 102. The second doped region 110 includes a contact region 118 having a second conductivity type such as a P conductivity type. Contact region 118 may be formed in a manner that is doped with well region 112 and may be heavily doped.

請參照第1B圖,第三摻雜區120包括接觸區122。接觸區122具有第一導電型例如N導電型。接觸區122的形成方法可包括摻雜第二摻雜區110的井區114、116,並摻雜井區114與井區116之間的第一摻雜區102的井區104。接觸區122可為重摻雜的。Referring to FIG. 1B , the third doping region 120 includes a contact region 122 . The contact region 122 has a first conductivity type such as an N conductivity type. The method of forming the contact region 122 can include doping the well regions 114, 116 of the second doped region 110 and doping the well region 104 of the first doped region 102 between the well region 114 and the well region 116. Contact region 122 can be heavily doped.

請參照第1B圖,具有第二導電型的第一頂摻雜層124位於具有第一導電型的第一摻雜區102的井區104上。第一頂摻雜層124可藉由摻雜井區104形成。具有第一導電型的第二頂摻雜層126位於第一頂摻雜層124上。第二頂摻雜層126可藉由摻雜第一頂摻雜層124形成。介電結構128形成於第二頂摻雜層126上。介電結構128並不限於如第1B圖與第1C圖所示的場氧化物,而可包括其他合適的介電結構,例如淺溝槽隔離等。導電結構130形成於介電結構128上。於一實施例中,導電結構130包括多晶矽,例如以單一多晶矽(single poly)或雙多晶矽(double poly)製程形成。Referring to FIG. 1B, a first top doped layer 124 having a second conductivity type is located on the well region 104 having the first doped region 102 of the first conductivity type. The first top doped layer 124 can be formed by doping the well region 104. A second top doped layer 126 having a first conductivity type is located on the first top doped layer 124. The second top doped layer 126 can be formed by doping the first top doped layer 124. A dielectric structure 128 is formed on the second top doped layer 126. The dielectric structure 128 is not limited to the field oxides as shown in FIGS. 1B and 1C, but may include other suitable dielectric structures such as shallow trench isolation and the like. Conductive structure 130 is formed on dielectric structure 128. In one embodiment, the conductive structure 130 includes polysilicon, for example, formed by a single poly or double poly process.

第1C圖與第1B圖所示的雙極性接面電晶體的剖面圖差異在於,第1C圖省略了第1B圖中的第一頂摻雜層124與第二頂摻雜層126。第1A圖僅繪示雙極性接面電晶體部分元件的上視圖,包括第一摻雜區102的接觸區106;第二摻雜區110的井區112、114、116與接觸區118;第三摻雜區120的接觸區122;以及第二頂摻雜層126。雙極性接面電晶體並不限於如第1A圖的圓形(circle)配置,而也能設計成正方形(square)、長方形(rectangle)、六邊形(hexagonal)、八邊形(octagonal),或其他形狀的結構。The difference in cross-sectional view of the bipolar junction transistor shown in FIG. 1C and FIG. 1B is that the first top doping layer 124 and the second top doping layer 126 in FIG. 1B are omitted in FIG. 1C. 1A is a top view of only a portion of a bipolar junction transistor, including a contact region 106 of the first doped region 102; a well region 112, 114, 116 and a contact region 118 of the second doped region 110; a contact region 122 of the three doped region 120; and a second top doped layer 126. The bipolar junction transistor is not limited to the circular configuration as in FIG. 1A, but can also be designed as a square, a rectangle, a hexagonal, an octagonal, or an octagonal. Or other shape structure.

第2A圖至第2C圖分別繪示第1A圖至第1C圖之雙極性接面電晶體,其第二摻雜區110的井區112、114、116在被擴散之後的示意圖。此擴散井區112、114、116的步驟是用以形成第二摻雜區110的連接區132。位在第三摻雜區120之接觸區122下方的連接區132是鄰接在井區114與井區116之間,並具有第二導電型。井區114、116的底表面是低於連接區132的底表面。擴散第二摻雜區110的井區112、114、116的方法可包括進行退火步驟。此退火步驟可在任意適當的時機進行,例如在形成第二摻雜區110的接觸區118與形成第三摻雜區120的接觸區122之前或之後進行。2A to 2C are schematic views showing the bipolar junction transistors of FIGS. 1A to 1C, respectively, after the well regions 112, 114, 116 of the second doping region 110 are diffused. The step of diffusing the well regions 112, 114, 116 is to form the connection region 132 of the second doped region 110. The connection region 132 located below the contact region 122 of the third doping region 120 is adjacent between the well region 114 and the well region 116 and has a second conductivity type. The bottom surface of the well regions 114, 116 is lower than the bottom surface of the connection region 132. The method of diffusing the well regions 112, 114, 116 of the second doped region 110 can include performing an annealing step. This annealing step can be performed at any suitable timing, for example, before or after forming the contact region 118 of the second doping region 110 and the contact region 122 forming the third doping region 120.

請參照第2B圖,於一實施例中,舉例來說,雙極性接面電晶體的第一摻雜區102可藉由接觸區106電性連接至集極電壓134。第二摻雜區110可藉由接觸區118電性連接至基極電壓136。第三摻雜區120可藉由接觸區122電性連接至射極電壓138。換句話說,第一摻雜區102(包括第一導電型例如N導電型的井區104與接觸區106)是用作集極。第二摻雜區110(包括第二導電型例如P導電型的井區112、114、116、連接區132與接觸區118)是用作基極。第三摻雜區120(包括第一導電型例如N導電型的接觸區122)是用作射極。導電結構130可電性連接至結構電壓。於一實施例中,結構電壓是耦接於基極電壓136。Referring to FIG. 2B , in an embodiment, for example, the first doping region 102 of the bipolar junction transistor can be electrically connected to the collector voltage 134 by the contact region 106 . The second doped region 110 can be electrically connected to the base voltage 136 by the contact region 118. The third doped region 120 can be electrically connected to the emitter voltage 138 by the contact region 122. In other words, the first doped region 102 (including the first conductivity type, such as the N-conducting well region 104 and the contact region 106) is used as a collector. The second doped region 110 (including the second conductivity type, such as the P conductivity type well regions 112, 114, 116, the connection region 132, and the contact region 118) is used as a base. The third doping region 120 (including the first conductive type such as the N conductive type contact region 122) is used as an emitter. The conductive structure 130 can be electrically connected to the structure voltage. In one embodiment, the structure voltage is coupled to the base voltage 136.

請參照第2B圖,於實施例中,擴散之後的井區112、114、116與形成的連接區132具有比擴散之前的井區112、114、116更小的摻雜濃度,因此能提高雙極性接面電晶體的β增益。形成的連接區132可具有微小的尺寸(例如深度淺或寬度窄),此能提高基極電阻並提高β增益。因此,換句話說,實施例可藉由調整第二摻雜區110的井區112、114、116(例如井區112、114、116之間的間隔),或調整擴散井區112、114、116(例如退火)的製程參數,來控制形成的連接區132,進而控制雙極性接面電晶體的β增益。Referring to FIG. 2B, in the embodiment, the well regions 112, 114, 116 after diffusion and the formed connection region 132 have a smaller doping concentration than the well regions 112, 114, 116 before diffusion, thereby improving the double The beta gain of the polar junction transistor. The formed connection region 132 can have a small size (e.g., shallow depth or narrow width) which can increase the base resistance and increase the beta gain. Thus, in other words, embodiments may be by adjusting the well regions 112, 114, 116 of the second doped region 110 (eg, the spacing between the well regions 112, 114, 116), or adjusting the diffusion well regions 112, 114, A process parameter of 116 (e.g., annealing) is used to control the formed junction region 132 to control the beta gain of the bipolar junction transistor.

再者,形成在介電結構128下方之井區104 (漂移區)中的第一頂摻雜層124與第二頂摻雜層126,是應用縮減表面場(reduced surface field; RESURF)的概念,其能幫助提高高壓雙極性接面電晶體(HVBJT)的崩潰電壓。配置在(集極)接觸區106與(基極)接觸區118之間的介電結構128上的導電結構130可幫助提升雙極性接面電晶體的接面崩潰電壓(junction breakdown voltage)。於一實施例中,高壓雙極性接面電晶體可藉由縮減(井區104中)漂移區域的尺寸來縮小裝置的尺寸並降低操作電壓。於實施例中,可最佳化(射極)接觸區122與(集極)接觸區106之間的距離,以避免雙極性接面電晶體發生橫向貫穿(lateral punch through),此概念亦可應用至高壓裝置中。Furthermore, the first top doped layer 124 and the second top doped layer 126 formed in the well region 104 (drift region) below the dielectric structure 128 are the concept of applying a reduced surface field (RESURF). It can help increase the breakdown voltage of high voltage bipolar junction transistors (HVBJT). The conductive structure 130 disposed on the dielectric structure 128 between the (collector) contact region 106 and the (base) contact region 118 can help to increase the junction breakdown voltage of the bipolar junction transistor. In one embodiment, the high voltage bipolar junction transistor can reduce the size of the device and reduce the operating voltage by reducing the size of the drift region (in the well region 104). In an embodiment, the distance between the (emitter) contact region 122 and the (collector) contact region 106 can be optimized to avoid lateral punch through of the bipolar junction transistor. Applied to high pressure devices.

於實施例中,雙極性接面電晶體可利用標準的高壓製程來形成,因此不需要額外的製程、光罩,或改變製程程式。In an embodiment, the bipolar junction transistor can be formed using a standard high voltage process, thus eliminating the need for additional processes, masks, or changing process recipes.

第3A圖繪示根據一實施例之雙極性接面電晶體的上視圖。第3B圖為雙極性接面電晶體沿BB線的剖面圖。第3C圖為雙極性接面電晶體沿CC線的剖面圖。3A is a top view of a bipolar junction transistor in accordance with an embodiment. Figure 3B is a cross-sectional view of the bipolar junction transistor along line BB. Figure 3C is a cross-sectional view of the bipolar junction transistor along line CC.

第3A圖至第3B圖的雙極性接面電晶體與第1A圖至第1B圖的雙極性接面電晶體的差異在於,第三摻雜區220的接觸區222A、222B是形成在第二摻雜區110的井區114、116中。第3B圖與第3C圖之剖面圖的差異在於,第3C圖省略了第二摻雜區110的井區114、116與第三摻雜區220的接觸區222A、222B。第二摻雜區110的井區114、116與第三摻雜區220的接觸區222A、222B並不限於如第3A圖的長方形(rectangle)配置,而也能設計成正方形(square)、六邊形(hexagonal)、八邊形(octagonal)、圓形(circle),或其他形狀的結構。The difference between the bipolar junction transistors of FIGS. 3A to 3B and the bipolar junction transistors of FIGS. 1A to 1B is that the contact regions 222A, 222B of the third doping region 220 are formed in the second Doped region 110 is in well region 114, 116. The difference between the 3B and 3C cross-sectional views is that the 3C diagram omits the contact regions 222A, 222B of the well regions 114, 116 and the third doping region 220 of the second doped region 110. The contact regions 222A, 222B of the well regions 114, 116 and the third doping region 220 of the second doping region 110 are not limited to the rectangular configuration as shown in FIG. 3A, but can also be designed as squares, six. A structure of hexagonal, octagonal, circular, or other shape.

第4A圖至第4C圖分別繪示一實施例中第3A圖至第3C圖之雙極性接面電晶體,其第二摻雜區110的井區112、114、116在被擴散之後的示意圖。此擴散井區112、114、116的步驟是用以形成第二摻雜區110的連接區132。連接區132是鄰接在井區112、114、116之間,並具有第二導電型。井區112、114、116的底表面是低於連接區132的底表面。擴散第二摻雜區110的井區112、114、116的方法可包括進行退火步驟。此退火步驟可在任意適當的時機進行,例如於一實施例中,退火步驟是在形成第三摻雜區220的接觸區222A、222B之前進行。4A to 4C are diagrams respectively showing the bipolar junction transistors of FIGS. 3A to 3C in an embodiment, after the well regions 112, 114, 116 of the second doping region 110 are diffused. . The step of diffusing the well regions 112, 114, 116 is to form the connection region 132 of the second doped region 110. The connection region 132 is adjacent between the well regions 112, 114, 116 and has a second conductivity type. The bottom surface of the well regions 112, 114, 116 is lower than the bottom surface of the connection region 132. The method of diffusing the well regions 112, 114, 116 of the second doped region 110 can include performing an annealing step. This annealing step can be performed at any suitable timing. For example, in one embodiment, the annealing step is performed prior to forming the contact regions 222A, 222B of the third doping region 220.

請參照第4B圖與第4C圖,於一實施例中,舉例來說,雙極性接面電晶體的第一摻雜區102可藉由接觸區106電性連接至集極電壓134。第二摻雜區110可藉由接觸區118電性連接至基極電壓136。第三摻雜區220可藉由接觸區222A、222B電性連接至射極電壓138。換句話說,第一摻雜區102(包括第一導電型例如N導電型的井區104與接觸區106是用作集極。第二摻雜區110(包括第二導電型例如P導電型的井區112、114、116、連接區132與接觸區118是用作基極。第三摻雜區220(包括第一導電型例如N導電型的接觸區222A、222B)是用作射極。導電結構130可電性連接至結構電壓。於一實施例中,結構電壓是耦接於基極電壓136。Referring to FIG. 4B and FIG. 4C , in one embodiment, for example, the first doping region 102 of the bipolar junction transistor can be electrically connected to the collector voltage 134 by the contact region 106 . The second doped region 110 can be electrically connected to the base voltage 136 by the contact region 118. The third doped region 220 can be electrically connected to the emitter voltage 138 by the contact regions 222A, 222B. In other words, the first doping region 102 (including the first conductivity type such as the N conductivity type well region 104 and the contact region 106 is used as a collector. The second doping region 110 (including the second conductivity type such as P conductivity type) The well regions 112, 114, 116, the connection region 132 and the contact region 118 serve as a base. The third doping region 220 (including the first conductivity type, such as the N conductivity type contact regions 222A, 222B) is used as an emitter. The conductive structure 130 can be electrically connected to the structure voltage. In an embodiment, the structure voltage is coupled to the base voltage 136.

於實施例中,擴散之後的井區112、114、116與形成的連接區132具有比擴散之前的井區112、114、116更小的摻雜濃度,此能提高雙極性接面電晶體的β增益。形成的連接區132可具有微小的尺寸,此能提高基極電阻並提高β增益。因此,換句話說,實施例可藉由調整第二摻雜區110的井區112、114、116,或調整擴散井區112、114、116(例如退火)的製程參數,來控制形成的連接區132,進而控制雙極性接面電晶體的β增益。In an embodiment, the well regions 112, 114, 116 after diffusion and the formed junction regions 132 have a smaller doping concentration than the well regions 112, 114, 116 prior to diffusion, which can increase the bipolar junction transistor β gain. The formed connection region 132 can have a small size, which can increase the base resistance and increase the beta gain. Thus, in other words, embodiments can control the resulting connections by adjusting well regions 112, 114, 116 of second doped region 110, or by adjusting process parameters of diffusion well regions 112, 114, 116 (eg, annealing). Region 132, in turn, controls the beta gain of the bipolar junction transistor.

第5A圖至第5C圖分別繪示另一實施例中第3A圖至第3C圖之雙極性接面電晶體,其第二摻雜區110的井區112、114、116與第三摻雜區220的接觸區222A、222B在被擴散之後的示意圖。井區112、114、116擴散之後是形成第二摻雜區110的連接區132。連接區132鄰接在井區112、114、116之間,並具有第二導電型。井區112、114、116的底表面是低於連接區132的底表面。接觸區222A、222B擴散之後是形成第三摻雜區220的連接區240。連接區240鄰接在接觸區222A、222B之間,並具有第一導電型。第三摻雜區220的連接區240是位在第二摻雜區110的連接區132上。擴散第二摻雜區110的井區112、114、116與第三摻雜區220的接觸區222A、222B的方法可包括進行退火步驟。此退火步驟可在任意適當的時機進行,例如於一實施例中,退火步驟是在形成第三摻雜區220的接觸區222A、222B之後進行。5A to 5C are respectively diagrams showing the bipolar junction transistors of FIGS. 3A to 3C in another embodiment, the well regions 112, 114, 116 of the second doping region 110 and the third doping. A schematic of the contact regions 222A, 222B of region 220 after being diffused. After the well regions 112, 114, 116 are diffused, the junction regions 132 forming the second doped regions 110 are formed. Connection zone 132 abuts between well zones 112, 114, 116 and has a second conductivity type. The bottom surface of the well regions 112, 114, 116 is lower than the bottom surface of the connection region 132. After the contact regions 222A, 222B are diffused, the connection regions 240 forming the third doping regions 220 are formed. The connection region 240 is adjacent between the contact regions 222A, 222B and has a first conductivity type. The connection region 240 of the third doping region 220 is located on the connection region 132 of the second doping region 110. The method of diffusing the contact regions 222A, 222B of the well regions 112, 114, 116 of the second doped region 110 and the third doped region 220 may include performing an annealing step. This annealing step can be performed at any suitable timing. For example, in one embodiment, the annealing step is performed after forming the contact regions 222A, 222B of the third doping region 220.

請參照第5B圖與第5C圖,雙極性接面電晶體的第一摻雜區102可藉由接觸區106電性連接至集極電壓134。第二摻雜區110可藉由接觸區118電性連接至基極電壓136。第三摻雜區220可藉由接觸區222A、222B電性連接至射極電壓138。換句話說,第一摻雜區102(包括第一導電型例如N導電型的井區104與接觸區106)是用作集極。第二摻雜區110(包括第二導電型例如P導電型的井區112、114、116、連接區132與接觸區118)是用作基極。第三摻雜區220(包括第一導電型例如N導電型的接觸區222A、222B與連接區240)是用作射極。導電結構130可電性連接至結構電壓。於一實施例中,結構電壓是耦接於基極電壓136。Referring to FIGS. 5B and 5C , the first doping region 102 of the bipolar junction transistor can be electrically connected to the collector voltage 134 by the contact region 106 . The second doped region 110 can be electrically connected to the base voltage 136 by the contact region 118. The third doped region 220 can be electrically connected to the emitter voltage 138 by the contact regions 222A, 222B. In other words, the first doped region 102 (including the first conductivity type, such as the N-conducting well region 104 and the contact region 106) is used as a collector. The second doped region 110 (including the second conductivity type, such as the P conductivity type well regions 112, 114, 116, the connection region 132, and the contact region 118) is used as a base. The third doping region 220 (including the first conductive type such as the N conductive type contact regions 222A, 222B and the connection region 240) functions as an emitter. The conductive structure 130 can be electrically connected to the structure voltage. In one embodiment, the structure voltage is coupled to the base voltage 136.

於實施例中,擴散之後的井區112、114、116與形成的連接區132具有比擴散之前的井區112、114、116更小的摻雜濃度,此能提高雙極性接面電晶體的β增益。形成的連接區132可具有微小的尺寸,此能提高基極電阻並提高β增益。因此,換句話說,實施例可藉由調整第二摻雜區110的井區112、114、116,或調整擴散井區112、114、116(例如退火)的製程參數,來控制形成的連接區132,進而控制雙極性接面電晶體的β增益。In an embodiment, the well regions 112, 114, 116 after diffusion and the formed junction regions 132 have a smaller doping concentration than the well regions 112, 114, 116 prior to diffusion, which can increase the bipolar junction transistor β gain. The formed connection region 132 can have a small size, which can increase the base resistance and increase the beta gain. Thus, in other words, embodiments can control the resulting connections by adjusting well regions 112, 114, 116 of second doped region 110, or by adjusting process parameters of diffusion well regions 112, 114, 116 (eg, annealing). Region 132, in turn, controls the beta gain of the bipolar junction transistor.

第6A圖繪示根據一實施例之雙極性接面電晶體的剖面圖。閘結構142配置在井區112、114、116之間第一摻雜區102的井區104上。閘結構142包括閘介電層與配置在閘介電層上的閘電極層。閘介電層可包括氧化物、氮化物,例如氧化矽、氮化矽、氮氧化矽,或其他合適的材料。閘電極層可包括多晶矽、金屬、金屬矽化物,或其他合適的材料。多晶矽可例如以單一多晶矽(single poly)或雙多晶矽(double poly)製程形成。6A is a cross-sectional view of a bipolar junction transistor in accordance with an embodiment. The gate structure 142 is disposed on the well region 104 of the first doped region 102 between the well regions 112, 114, 116. The gate structure 142 includes a gate dielectric layer and a gate electrode layer disposed on the gate dielectric layer. The gate dielectric layer can include oxides, nitrides such as hafnium oxide, tantalum nitride, hafnium oxynitride, or other suitable materials. The gate electrode layer may comprise polysilicon, metal, metal halide, or other suitable material. The polycrystalline germanium can be formed, for example, in a single poly poly or double poly process.

第6B圖繪示第6A圖之雙極性接面電晶體的操作方法。提供一閘極電壓至閘結構142,以在閘結構142下方之第一摻雜區102的井區104(第一導電型例如N導電型)中形成連接區232(第二導電型例如P導電型)。連接區232鄰接在井區112、114、116之間。於一實施例中,閘極電壓是耦接於基極電壓136。再者,第一摻雜區102可藉由接觸區106電性連接至集極電壓134。第二摻雜區110可藉由接觸區118電性連接至基極電壓136。第三摻雜區220可藉由接觸區222A、222B電性連接至射極電壓138。換句話說,第一摻雜區102(包括第一導電型例如N導電型的井區104與接觸區106)是用作集極。第二摻雜區110(包括第二導電型例如P導電型的井區112、114、116、連接區232與接觸區118是用作基極。第三摻雜區220(包括第一導電型例如N導電型的接觸區222A、222B)是用作射極。導電結構130可電性連接至結構電壓。於一實施例中,結構電壓是耦接於基極電壓136。FIG. 6B is a diagram showing the operation method of the bipolar junction transistor of FIG. 6A. A gate voltage is provided to the gate structure 142 to form a connection region 232 in the well region 104 (first conductivity type, such as N conductivity type) of the first doping region 102 below the gate structure 142 (second conductivity type such as P conductive type). Connection zone 232 abuts between well zones 112, 114, 116. In one embodiment, the gate voltage is coupled to the base voltage 136. Moreover, the first doping region 102 can be electrically connected to the collector voltage 134 by the contact region 106. The second doped region 110 can be electrically connected to the base voltage 136 by the contact region 118. The third doped region 220 can be electrically connected to the emitter voltage 138 by the contact regions 222A, 222B. In other words, the first doped region 102 (including the first conductivity type, such as the N-conducting well region 104 and the contact region 106) is used as a collector. The second doping region 110 (including the second conductivity type such as the P conductivity type well regions 112, 114, 116, the connection region 232 and the contact region 118 is used as the base. The third doping region 220 (including the first conductivity type) For example, the N-conductor contact regions 222A, 222B) are used as emitters. The conductive structure 130 can be electrically connected to the structure voltage. In one embodiment, the structure voltage is coupled to the base voltage 136.

於實施例中,可調變提供至閘結構142的閘極電壓,來控制形成在井區104中的連接區232的輪廓與載子濃度,以得到期望的裝置特性。舉例來說,連接區232可控制成具有低的載子濃度,藉此提高雙極性接面電晶體的β增益。再者,連接區232可輕易地控制成具有微小的尺寸,藉此提高β增益。In an embodiment, the varistor voltage is provided to the gate structure 142 to control the profile and carrier concentration of the connection region 232 formed in the well region 104 to achieve desired device characteristics. For example, the connection region 232 can be controlled to have a low carrier concentration, thereby increasing the beta gain of the bipolar junction transistor. Furthermore, the connection area 232 can be easily controlled to have a small size, thereby increasing the beta gain.

第7圖與第8圖顯示實施例中雙極性接面電晶體的電性曲線。從第7圖發現,雙極性接面電晶體的電流放大可達至約3900倍。再者,從第8圖發現,雙極性接面電晶體的爾利效應並不嚴重。Figures 7 and 8 show the electrical curves of the bipolar junction transistors in the examples. From Figure 7, it is found that the current amplification of the bipolar junction transistor can reach about 3900 times. Furthermore, it is found from Fig. 8 that the Erleigh effect of the bipolar junction transistor is not serious.

雖然實施例中第一導電型為N導電型,且第二導電型為P導電型。然本揭露並不限於此,於其他實施例中,第一導電型可為P導電型,且第二導電型可為N導電型。Although the first conductivity type is an N conductivity type in the embodiment, and the second conductivity type is a P conductivity type. However, the disclosure is not limited thereto. In other embodiments, the first conductive type may be a P conductive type, and the second conductive type may be an N conductive type.

綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102...第一摻雜區102. . . First doped region

104、112、114、116...井區104, 112, 114, 116. . . Well area

106、118、122、222A、222B...接觸區106, 118, 122, 222A, 222B. . . Contact area

108...基底108. . . Base

110...第二摻雜區110. . . Second doped region

120、220...第三摻雜區120, 220. . . Third doped region

124...第一頂摻雜層124. . . First top doped layer

126...第二頂摻雜層126. . . Second top doped layer

128...介電結構128. . . Dielectric structure

130...導電結構130. . . Conductive structure

132、232、240...連接區132, 232, 240. . . Connection area

134...集極電壓134. . . Collector voltage

136...基極電壓136. . . Base voltage

138...射極電壓138. . . Emitter voltage

102...第一摻雜區102. . . First doped region

104、112、114、116...井區104, 112, 114, 116. . . Well area

106、118、122...接觸區106, 118, 122. . . Contact area

108...基底108. . . Base

110...第二摻雜區110. . . Second doped region

120...第三摻雜區120. . . Third doped region

128...介電結構128. . . Dielectric structure

130...導電結構130. . . Conductive structure

134...集極電壓134. . . Collector voltage

136...基極電壓136. . . Base voltage

138...射極電壓138. . . Emitter voltage

Claims (10)

一種雙極性接面電晶體,包括:
一第一摻雜區,具有一第一導電型;
一第二摻雜區,包括形成於該第一摻雜區中的數個井區,其中該些井區具有相反於該第一導電型的一第二導電型,該些井區藉由該第一摻雜區互相分開;以及
一第三摻雜區,具有該第一導電型,其中該第三摻雜區形成在該些井區中,或形成在該些井區之間的該第一摻雜區中。
A bipolar junction transistor comprising:
a first doped region having a first conductivity type;
a second doped region includes a plurality of well regions formed in the first doped region, wherein the well regions have a second conductivity type opposite to the first conductivity type, and the well regions are The first doped regions are separated from each other; and a third doped region having the first conductivity type, wherein the third doped region is formed in the well regions or formed between the well regions In a doped region.
如申請專利範圍第1項所述之雙極性接面電晶體,其中該第二摻雜區更包括一連接區,鄰接在該些井區之間,並具有該第二導電型,該些井區的底表面是低於該連接區的底表面。The bipolar junction transistor according to claim 1, wherein the second doping region further comprises a connection region adjacent to the well regions and having the second conductivity type, the wells The bottom surface of the zone is below the bottom surface of the joint zone. 如申請專利範圍第2項所述之雙極性接面電晶體,其中該第三摻雜區包括一接觸區,具有該第一導電型,並位於該些井區與該連接區之間,該接觸區位於該連接區上。The bipolar junction transistor according to claim 2, wherein the third doping region comprises a contact region having the first conductivity type and located between the well region and the connection region, The contact area is located on the connection area. 如申請專利範圍第1項所述之雙極性接面電晶體,其中該第三摻雜區包括一接觸區,具有該第一導電型,並形成在該第二摻雜區中。The bipolar junction transistor of claim 1, wherein the third doped region comprises a contact region having the first conductivity type and formed in the second doped region. 一種雙極性接面電晶體的操作方法,其中該雙極性接面電晶體包括:
一第一摻雜區,具有一第一導電型;
一第二摻雜區,包括形成於該第一摻雜區中的數個井區,其中該些井區具有相反於該第一導電型的一第二導電型,該些井區藉由該第一摻雜區互相分開;以及
一第三摻雜區,具有該第一導電型,其中該第三摻雜區形成在該些井區中,或形成在該些井區之間的該第一摻雜區中,
該操作方法包括:
提供一集極電壓至該第一摻雜區;
提供一基極電壓至該第二摻雜區;以及
提供一射極電壓至該第三摻雜區。
A method of operating a bipolar junction transistor, wherein the bipolar junction transistor comprises:
a first doped region having a first conductivity type;
a second doped region includes a plurality of well regions formed in the first doped region, wherein the well regions have a second conductivity type opposite to the first conductivity type, and the well regions are The first doped regions are separated from each other; and a third doped region having the first conductivity type, wherein the third doped region is formed in the well regions or formed between the well regions In a doped region,
The method of operation includes:
Providing a collector voltage to the first doped region;
Providing a base voltage to the second doped region; and providing an emitter voltage to the third doped region.
如申請專利範圍第5項所述之雙極性接面電晶體的操作方法,其中該第二摻雜區更包括一連接區,鄰接在該些井區之間,並具有該第二導電型,該些井區的底表面是低於該連接區的底表面,該第三摻雜區包括一接觸區,具有該第一導電型,並位於該些井區與該連接區之間,該接觸區位於該連接區上。The method for operating a bipolar junction transistor according to claim 5, wherein the second doping region further comprises a connection region adjacent to the well regions and having the second conductivity type. The bottom surface of the well regions is lower than the bottom surface of the connection region, and the third doped region includes a contact region having the first conductivity type and located between the well regions and the connection region, the contact The zone is located on the connection zone. 如申請專利範圍第5項所述之雙極性接面電晶體的操作方法,其中該雙極性接面電晶體更包括一閘結構,配置在該些井區之間的該第一摻雜區上,該操作方法更包括提供一閘極電壓至該閘結構,以在該閘結構下方的該第一摻雜區中形成一連接區,該連接區具有該第二導電型,並鄰接在該些井區之間。The method for operating a bipolar junction transistor according to claim 5, wherein the bipolar junction transistor further comprises a gate structure disposed on the first doped region between the well regions The method further includes providing a gate voltage to the gate structure to form a connection region in the first doped region under the gate structure, the connection region having the second conductivity type and adjoining the Between well areas. 如申請專利範圍第5項所述之雙極性接面電晶體的操作方法,其中該雙極性接面電晶體更包括:
一介電結構,位於該第一摻雜區上;以及
一導電結構,位於該介電結構上,
該方法更包括提供一結構電壓至該導電結構。
The method for operating a bipolar junction transistor according to claim 5, wherein the bipolar junction transistor further comprises:
a dielectric structure on the first doped region; and a conductive structure on the dielectric structure
The method further includes providing a structural voltage to the electrically conductive structure.
一種雙極性接面電晶體的製造方法,包括:
於一第一摻雜區中形成一第二摻雜區的數個井區,其中該第一摻雜區具有一第一導電型,該些井區具有相反於該第一導電型的一第二導電型,該些井區藉由該第一摻雜區互相分開;以及
於該些井區中或於該些井區之間的該第一摻雜區中形成一第三摻雜區,其中該第三摻雜區具有該第一導電型。
A method for manufacturing a bipolar junction transistor, comprising:
Forming a plurality of well regions of a second doped region in a first doped region, wherein the first doped region has a first conductivity type, and the well regions have a first opposite to the first conductivity type a second conductivity type, wherein the well regions are separated from each other by the first doping region; and a third doping region is formed in the well regions or in the first doping region between the well regions, Wherein the third doping region has the first conductivity type.
如申請專利範圍第9項所述之雙極性接面電晶體的製造方法,更包括進行一退火步驟以擴散該些井區,以形成該第二摻雜區的一連接區鄰接在該些井區之間,其中該連接區具有該第二導電型,該些井區的底表面是低於該連接區的底表面。The method for manufacturing a bipolar junction transistor according to claim 9, further comprising performing an annealing step to diffuse the well regions to form a connection region of the second doping region adjacent to the wells Between the zones, wherein the junction zone has the second conductivity type, and the bottom surfaces of the well zones are lower than the bottom surface of the connection zone.
TW102109971A 2013-03-21 2013-03-21 Bipolar junction transistor and operating and manufacturing method for the same TWI532101B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543452B1 (en) 2015-07-01 2017-01-10 Macronix International Co., Ltd. High voltage junction field effect transistor
TWI569442B (en) * 2015-06-24 2017-02-01 旺宏電子股份有限公司 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI569442B (en) * 2015-06-24 2017-02-01 旺宏電子股份有限公司 Semiconductor device
US9543452B1 (en) 2015-07-01 2017-01-10 Macronix International Co., Ltd. High voltage junction field effect transistor

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