TW201624568A - Semiconductor device and method of manufacturing thereof - Google Patents

Abstract

A semiconductor device and a method of manufacturing thereof is provided. The method of manufacturing the semiconductor device includes the following steps. A substrate is provided, wherein a plurality of trenches are formed in the substrate and an oxide layer, a silicon-based layer and a mask layer are sequentially disposed on the substrate between the trenches. A dielectric layer is formed to fill the trenches and cover the mask layer, the silicon-based layer, the oxide layer and the substrate. An annealing process is performed on the substrate, wherein a silicon-hydrogen bond is formed between the hydrogen in the mask layer and the silicon in the silicon-based layer.

Description

Semiconductor component and manufacturing method thereof

The present invention relates to an element and a method of fabricating the same, and more particularly to a semiconductor element and a method of fabricating the same.

With the development of integrated circuits, the feature size of memory is shrinking, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Time-dependent Injection (HCI). The problem of component reliability such as TDDB (Time Dependence Dielectric Breakdown) also arises. Among them, the NBTI effect refers to the electrical drift of the component under the temperature stress condition that the component applies a negative bias to the gate, and the offset of the gate initial voltage Vth is the most serious, that is, with the temperature stress. As the conditions increase, the amount of offset increases.

In general, hydrogen is believed to have a certain effect on NBTI, and its main argument focuses on the diffusion and bonding of hydrogen in the process. For example, in an interface trap between yttrium oxide and ytterbium, when a weaker 矽-hydrogen bond is interrupted under stress conditions, the vacant interface trap captures a hole. Causing the start of the gate The pressure Vth drifts.

It can be seen that under the current trend of miniaturization of components, how to balance the integration of components and component reliability in a limited space will be one of the focuses of research.

The present invention provides a semiconductor device and a method of fabricating the same that can improve negative bias temperature instability.

The method of fabricating the semiconductor device of the present invention includes the following steps. A substrate is provided, and a plurality of trenches are formed in the substrate, wherein an oxide layer, a germanium-based material layer and a mask layer are sequentially disposed on the substrate between the trenches. A dielectric layer is formed to fill the trench and cover the mask layer, the germanium-based material layer, the oxide layer, and the substrate. An annealing process is performed on the substrate, wherein hydrogen from the mask layer forms a 矽-hydrogen bond with the ruthenium in the ruthenium-based material layer.

In an embodiment of the invention, a ruthenium oxide layer is further formed between the ruthenium-based material layer and the mask layer.

In an embodiment of the invention, the method for forming the ruthenium oxide layer includes performing an oxidation process on the ruthenium-based material layer prior to forming the mask layer.

In an embodiment of the invention, the oxidation process includes a rapid thermal oxidation (RTO).

In an embodiment of the invention, the method for forming the ruthenium oxide layer includes a low pressure chemical vapor deposition process.

In an embodiment of the invention, the annealing process has a temperature of 700 °C to 1000 °C.

In an embodiment of the invention, the groove has an aspect ratio greater than 4:1.

In an embodiment of the invention, the germanium-based material layer comprises an amorphous germanium layer or a poly germanium layer.

In an embodiment of the invention, the mask layer is a tantalum nitride layer.

In an embodiment of the invention, the temperature at which the bismuth-based material layer is formed is lower than the temperature of the annealing process.

In an embodiment of the invention, after performing the annealing process, the method further includes removing a portion of the dielectric layer to form a plurality of isolation structures in the trench.

In an embodiment of the invention, the method for removing a portion of the dielectric layer includes performing a planarization process on the dielectric layer with the mask layer as a termination layer.

In an embodiment of the invention, after the annealing process is performed, the mask layer and the germanium-based material layer are further removed.

In an embodiment of the invention, the method of removing the mask layer includes using a wet etching process.

In an embodiment of the invention, the method of removing the layer of germanium-based material includes using a wet etching process.

The semiconductor device of the present invention comprises a substrate, an oxide layer, a germanium-based material layer, a mask layer, and a dielectric layer. A plurality of grooves have been formed in the substrate. The oxide layer is disposed on the substrate between the trenches. The ruthenium-based material layer is disposed on the oxide layer. The mask layer is disposed on the layer of germanium-based material, wherein hydrogen from the mask layer forms a helium-hydrogen bond with the germanium in the layer of germanium-based material. The dielectric layer fills the trench and covers the mask layer, the germanium-based material layer, the oxide layer, and the substrate.

In an embodiment of the invention, a ruthenium oxide layer is further disposed between the ruthenium-based material layer and the mask layer.

In an embodiment of the invention, the yttria layer has a thickness of between 10 Å and 50 Å.

In an embodiment of the invention, the 矽-hydrogen bond concentration between the bismuth-based material layer and the yttrium oxide layer interface is higher than the 矽-hydrogen bond concentration between the substrate and the oxide layer interface.

In an embodiment of the invention, the 矽-hydrogen bond concentration between the ruthenium-based material layer and the mask layer interface is higher than the 矽-hydrogen bond concentration between the substrate and the oxide layer interface.

In an embodiment of the invention, the germanium-based material layer comprises an amorphous germanium layer or a poly germanium layer.

In an embodiment of the invention, the mask layer comprises a tantalum nitride layer.

In an embodiment of the invention, the oxide layer has a thickness of between 1000 Å and 1500 Å.

In an embodiment of the invention, the 矽-hydrogen bond concentration between the bismuth-based material layer and the yttrium oxide layer interface is higher than the 矽-hydrogen bond concentration between the substrate and the oxide layer interface.

In an embodiment of the invention, the 矽-hydrogen bond concentration between the ruthenium-based material layer and the mask layer interface is higher than the 矽-hydrogen bond concentration between the substrate and the oxide layer interface.

In an embodiment of the invention, the mask layer has a thickness of between 500 Å and 1000 Å.

In an embodiment of the invention, a pad oxide layer is further disposed between the trench and the dielectric layer.

Based on the above, the present invention forms a gap between the substrate and the mask layer containing hydrogen. The ruthenium-based material layer, which is capable of capturing hydrogen driven by the mask layer to the substrate due to the high temperature process. In this way, hydrogen can be prevented from being trapped in the interface interface between the oxide layer and the substrate, thereby improving the negative bias temperature instability.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Base

102‧‧‧First District

104‧‧‧Second District

110‧‧‧Oxide layer

120‧‧‧矽 base material layer

122‧‧‧Oxide layer

130‧‧‧ Cover layer

140‧‧‧ trench

142‧‧‧Sheath oxide layer

150‧‧‧ dielectric layer

160‧‧‧Isolation structure

AP‧‧‧ Annealing Process

1A-1C are schematic diagrams showing a manufacturing process of a non-volatile memory according to an embodiment of the invention.

1A-1C are schematic diagrams showing a manufacturing process of a semiconductor device according to an embodiment of the invention. First, referring to FIG. 1A, a substrate 100 is provided. A plurality of trenches 140 are formed in the substrate. The substrate 100 between the trenches 140 is sequentially provided with an oxide layer 110, a germanium-based material layer 120, and a mask layer. 130. The substrate 100 is, for example, a crucible substrate. The substrate 100 includes, for example, a first region 102 and a second region 104. The first region 102 is, for example, a high voltage circuit region, the second region 104 is, for example, a low voltage circuit region, and the combination of the high voltage circuit region and the low voltage circuit region is a peripheral circuit region. The substrate 100 includes, for example, a memory cell region, but is not shown.

In the present embodiment, the oxide layer 110 located in the first region 102 is, for example, a high-voltage gate oxide layer having a thickness of, for example, 1000 Å to 1500 Å, which is located in the second region 104. Layer 110 is, for example, a pad oxide layer having a thickness of, for example, between 100 Å and 150 Å. In the present embodiment, the material of the oxide layer 110 is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation method.

The germanium-based material layer 120 is, for example, a polysilicon layer or an amorphous germanium layer, and has a thickness of, for example, 100 Å to 300 Å. The method for forming the germanium-based material layer 120 is, for example, a low-pressure chemical vapor deposition process using germanium methane as a gas source, and the deposition temperature thereof is, for example, between 500 ° C and 550 ° C. In this embodiment, a ruthenium oxide layer 122 is further formed between the ruthenium-based material layer 120 and the mask layer 130. The ruthenium oxide layer 122 may be formed by performing an oxidation process on the surface of the ruthenium-based material layer 120 or depositing a ruthenium oxide layer on the ruthenium-based material layer 120 to form a ruthenium dioxide/polysilicon interface. The oxidation process may be rapid thermal oxidation (RTO), such as a temperature between 500 ° C and 800 ° C, a gas such as oxygen, and a gas flow rate of, for example, between 1 slm and 30 slm. The deposition method may be a low pressure chemical vapor deposition process, for example, a deposition temperature of from 500 ° C to 550 ° C, a gas such as oxygen, and a gas flow rate of, for example, from 1 slm to 30 slm. Wherein, the ruthenium-based material layer 120 and the ruthenium oxide layer 122 may be performed in the same deposition chamber, that is, the ruthenium-based material layer 120 and the ruthenium oxide layer 122 are sequentially formed in an in-situ manner, wherein the ruthenium-based material layer 120 is oxidized. The deposition temperature of the germanium layer 122 is, for example, the same. The thickness of the yttrium oxide layer 122 is, for example, between 10 Å and 50 Å.

The mask layer 130 is, for example, a tantalum nitride layer having a thickness of, for example, 500 Å to 1000 Å. The method of forming the mask layer 130 is, for example, a deposition process using a hydrogen-containing gas as a gas source, such as dichloroethane and ammonia. The deposition process may be a low pressure chemical vapor deposition process, and the deposition temperature is, for example, between 700 ° C and 800 ° C. Special attention Yes, in the deposition process, the gas source usually has a phenomenon of incomplete reaction, so the deposited film layer will include the gas in the unreacted gas source, that is, the mask layer 130 contains hydrogen.

In the present embodiment, the trench 140 has, for example, a high aspect ratio, such as greater than 4:1. The trench 140 is formed by, for example, masking the mask layer 130, removing a portion of the hafnium oxide layer 122, the germanium-based material layer 120, the oxide layer 110, and the substrate 100 to form a plurality of trenches 140. The method of removing the partial yttrium oxide layer 122, the ruthenium-based material layer 120, the oxide layer 110, and the substrate 100 is, for example, a dry etching process or a wet etching process. The trench 140 is, for example, located between the first region 102 and the second region 104, and in particular, a portion of the trench 104 is located in the first region 102 and another portion of the trench 104 is located in the second region 104.

Referring to FIG. 1B , in the embodiment, after the trench 140 is formed, the pad oxide layer 142 is further formed in the trench 140 . The material of the pad oxide layer 142 is, for example, ruthenium oxide, and the formation method thereof is, for example, thermal oxidation, on-site vapor generation (ISSG) oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD) or furnace tube oxidation. law. The thickness of the pad oxide layer 142 is, for example, between 100 Å and 150 Å.

Then, a dielectric layer 150 is formed to fill the trench 140 and cover the mask layer 130, the germanium-based material layer 120, the oxide layer 110, and the substrate 100. Dielectric layer 150 is, for example, a material that is adapted to fill a high aspect ratio trench.

Then, the substrate 100 is subjected to an annealing process AP. The annealing process AP is, for example, an atmospheric pressure furnace tube whose temperature is, for example, between 700 ° C and 1000 ° C. In the present embodiment, the annealing process AP is used, for example, to densify the fill material filled in the trenches 140, that is, to allow the dielectric layer 150 to be completely filled into the trenches 140. Of course, in other embodiments, The fire process AP may also be a high temperature process used in the fabrication of other components, and the invention is not limited thereto. It is particularly noted that hydrogen is generated in the mask layer 130 during the annealing process AP, or is driven into the substrate 100 to be trapped by the interface of the germanium-based material layer 120 or the substrate 100, thereby forming a bond. A weak 矽-hydrogen bond. In the present embodiment, since the germanium-based material layer 120 is formed between the substrate 100 and the mask layer 130, hydrogen driven by the mask layer 130 to the substrate 100 preferentially drives the germanium-based material layer 120 and the mask layer. The interface of 130 is trapped by the interface trap, and only a small amount of hydrogen is further driven into the interface of the substrate 100 and the oxide layer 110. That is, the 矽-hydrogen bond concentration between the ruthenium-based material layer 120 and the interface of the mask layer 130 is higher than the 矽-hydrogen bond concentration between the interface of the substrate 100 and the oxide layer 110. In addition, since the ruthenium oxide layer 122 is further formed between the ruthenium-based material layer 120 and the mask layer 130, hydrogen driven by the mask layer 130 to the substrate 100 is more easily captured by the ruthenium-based material layer 120 and oxidized. Interface traps between layers 122. Therefore, in the present embodiment, the 矽-hydrogen bond concentration between the interface of the ruthenium-based material layer 120 and the ruthenium oxide layer 122 is higher than the 矽-hydrogen bond concentration between the interface of the substrate 100 and the oxide layer 110.

In the present embodiment, the semiconductor device includes a substrate 100, an oxide layer 110, a germanium-based material layer 120, a mask layer 130, and a dielectric layer 150. A plurality of trenches 140 have been formed in the substrate 100. The oxide layer 110 is disposed on the substrate 100 between the trenches 140. The germanium-based material layer 120 is disposed on the oxide layer 110. The mask layer 130 is disposed on the ruthenium-based material layer 120, wherein hydrogen from the mask layer 130 forms a 矽-hydrogen bond with ruthenium in the ruthenium-based material layer 120. The dielectric layer 150 fills the trench 140 and covers the mask layer 130, the germanium-based material layer 120, the oxide layer 110, and the substrate 100. In this embodiment, the ruthenium oxide layer 122 and the pad oxide layer 142 are further included. The yttrium oxide layer 122 is disposed, for example, on the ruthenium-based material layer 120 and the mask layer 130. between. The pad oxide layer 142 is disposed between the trench 140 and the dielectric layer 150.

The subsequent process will be further described next. Referring to FIG. 1C , after the annealing process AP is performed, a portion of the dielectric layer 150 is removed to form a plurality of isolation structures 160 in the trenches 140 . In the present embodiment, the method of removing a portion of the dielectric layer 150 includes performing a planarization process on the dielectric layer 150 with the mask layer 130 as a termination layer.

Then, the mask layer 130 and the germanium-based material layer 120 are removed. The method of removing the mask layer 130 is, for example, a wet etching process, such as using hot phosphoric acid. The method of removing the ruthenium-based material layer 120 is, for example, a wet etching process such as the use of diluted hydrofluoric acid (DHF) and diluted aqueous ammonia mixture (DAPM). In this embodiment, the method further includes removing the ruthenium oxide layer 122 by a wet etching process such as using a mixed solution of diluted aqueous ammonia and hydrogen peroxide (DAPM). Subsequent re-viewing of component requirements to perform generally familiar process steps, such as high voltage gate fabrication, etc., are well known in the art and will not be further described herein.

In general, since the filled material has a certain process limit for the trench having a high aspect ratio, after the filling material is filled into the trench, a high temperature annealing process is performed to densify the filled material. However, this high temperature annealing process may cause hydrogen evolution in the mask layer, or drive into the interface of the substrate and the gate oxide layer and be trapped by the interface trap, thereby forming a 矽-hydrogen bond with weak bonding strength. This weak 矽-hydrogen bond will break under the pressure test, which will cause the gate start voltage Vth to drift. In this embodiment, a germanium-based material layer 120 is formed between the substrate 100 and the hydrogen-containing mask layer 130, so that the interface trap of the germanium-based material layer 120 can preferentially capture the mask due to a high-temperature process such as an annealing process. The curtain layer 130 drives the hydrogen into the substrate 100. Therefore, it is possible to prevent hydrogen from being trapped in the interface interface between the oxide layer 110 and the substrate 100, thereby improving the negative bias temperature instability. In addition, in the present embodiment, the yttrium oxide layer 122 is further formed on the surface of the ruthenium-based material layer 120 such that the interface of the ruthenium-based material layer 120/the yttrium oxide layer 122 preferentially captures the original drive to the substrate 100/oxide layer 110. The hydrogen of the interface can greatly reduce the 矽-hydrogen bonds of the weak bonds present at the interface of the substrate 100/oxide layer 110. In addition, after the annealing process, the germanium-based material layer 120 and the hafnium oxide layer 122 are removed, that is, the germanium-based material layer 120 and the hafnium oxide layer 122 are not used as a subsequent gate material, thereby avoiding trapped hydrogen. Escape again. As a result, the offset generated by the gate start voltage Vth under the stress test can be greatly improved. Therefore, the semiconductor element of the present embodiment has an improved high-voltage gate negative bias temperature instability, so that it has better yield and element characteristics.

In summary, an embodiment of the present invention forms a germanium-based material layer or a germanium-based material layer and a tantalum oxide layer between the substrate and the hydrogen-containing mask layer, such that the germanium-based material layer or the germanium-based material layer The interface of the yttrium oxide layer preferentially captures hydrogen that is driven into the substrate by the mask layer due to the annealing process. In this way, hydrogen can be prevented from driving into the interface between the oxide layer and the substrate to greatly reduce the interface trap of hydrogen trapped between the oxide layer and the substrate. That is, the concentration of the 矽-hydrogen bond between the interface of the ruthenium-based material layer and the ruthenium oxide layer is much higher than the 矽-hydrogen bond concentration between the interface of the substrate and the oxide layer. In addition, after the annealing process, the germanium-based material layer and the hafnium oxide layer are removed, instead of being used as a material for subsequently forming the gate, so that the trapped hydrogen can be prevented from re-escape and affect the characteristics of the gate. . As a result, the offset generated by the gate start voltage Vth under the stress test can be greatly improved. Therefore, the semiconductor device of the present embodiment has an improved high voltage gate negative bias temperature instability Sex, so it has better yield and component characteristics.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102‧‧‧First District

104‧‧‧Second District

110‧‧‧Oxide layer

120‧‧‧矽 base material layer

122‧‧‧Oxide layer

130‧‧‧ Cover layer

140‧‧‧ trench

142‧‧‧Sheath oxide layer

150‧‧‧ dielectric layer

AP‧‧‧ Annealing Process

Claims (25)

A method of fabricating a semiconductor device, comprising: providing a substrate having a plurality of trenches formed therein, wherein an oxide layer, a germanium-based material layer, and a mask are sequentially disposed on the substrate between the trenches a mask layer; forming a dielectric layer to fill the trenches and covering the mask layer, the germanium-based material layer, the oxide layer, and the substrate; and performing an annealing process on the substrate, wherein the mask is from the mask The hydrogen of the curtain layer forms a 矽-hydrogen bond with the ruthenium in the ruthenium-based material layer. The method for fabricating a semiconductor device according to claim 1, further comprising forming a hafnium oxide layer between the germanium-based material layer and the mask layer. The method of fabricating a semiconductor device according to claim 2, wherein the method for forming the ruthenium oxide layer comprises performing an oxidation process on the ruthenium-based material layer before forming the mask layer. The method of fabricating a semiconductor device according to claim 3, wherein the oxidation process comprises a rapid thermal oxidation (RTO). The method of fabricating a semiconductor device according to claim 2, wherein the method for forming the ruthenium oxide layer comprises a low pressure chemical vapor deposition process. The method for fabricating a semiconductor device according to claim 1, wherein the annealing process has a temperature of from 700 ° C to 1000 ° C. The method of fabricating the semiconductor device of claim 1, wherein the trenches have an aspect ratio greater than 4:1. The method of fabricating a semiconductor device according to claim 1, wherein the germanium-based material layer comprises an amorphous germanium layer or a poly germanium layer. The method of fabricating a semiconductor device according to claim 1, wherein the mask layer is a tantalum nitride layer. The method of fabricating a semiconductor device according to claim 1, wherein a temperature at which the bismuth-based material layer is formed is lower than a temperature of the annealing process. The method for fabricating a semiconductor device according to claim 1, after the annealing process, further comprising removing a portion of the dielectric layer to form a plurality of isolation structures in the trenches. The method of fabricating a semiconductor device according to claim 11, wherein the method of removing a portion of the dielectric layer comprises performing a planarization process on the dielectric layer by using the mask layer as a termination layer. The method for fabricating a semiconductor device according to claim 1, after the annealing process, further comprising removing the mask layer and the germanium-based material layer. The method of fabricating a semiconductor device according to claim 13, wherein the method of removing the mask layer comprises using a wet etching process. The method of fabricating a semiconductor device according to claim 13, wherein the method of removing the germanium-based material layer comprises using a wet etching process. A semiconductor device comprising: a substrate having a plurality of trenches formed therein; an oxide layer disposed on the substrate between the trenches; a germanium-based material layer disposed on the oxide layer; a mask layer disposed on the germanium-based material layer, wherein hydrogen from the mask layer forms a germanium-hydrogen bond with germanium in the germanium-based material layer; and a dielectric layer fills the trenches And covering the mask layer, the germanium-based material layer, and the oxygen Layer and the substrate. The semiconductor device of claim 16, further comprising a ruthenium oxide layer disposed between the ruthenium-based material layer and the mask layer. The semiconductor device of claim 17, wherein the yttrium oxide layer has a thickness of from 10 Å to 50 Å. The semiconductor device according to claim 17, wherein a 矽-hydrogen bond concentration between the ruthenium-based material layer and the interface of the ruthenium oxide layer is higher than 矽-hydrogen between the substrate and the interface of the oxide layer. Key concentration. The semiconductor device of claim 16, wherein a concentration of a 矽-hydrogen bond between the layer of the ruthenium-based material and the interface of the mask layer is higher than that of the interface between the substrate and the interface of the oxide layer. Key concentration. The semiconductor device of claim 16, wherein the germanium-based material layer comprises an amorphous germanium layer or a poly germanium layer. The semiconductor device according to claim 16, wherein the mask layer is a tantalum nitride layer formed using a gas source containing methane. The semiconductor device of claim 16, wherein the oxide layer has a thickness of from 1000 Å to 1500 Å. The semiconductor component of claim 16, wherein the mask layer has a thickness of between 500 Å and 1000 Å. The semiconductor device of claim 16, further comprising a pad oxide layer disposed between the trenches and the dielectric layer.