TW201624550A - 半導體晶圓之接合結構的形成方法 - Google Patents

半導體晶圓之接合結構的形成方法 Download PDF

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TW201624550A
TW201624550A TW104137571A TW104137571A TW201624550A TW 201624550 A TW201624550 A TW 201624550A TW 104137571 A TW104137571 A TW 104137571A TW 104137571 A TW104137571 A TW 104137571A TW 201624550 A TW201624550 A TW 201624550A
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joint
connectors
bonding
portions
forming
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TW104137571A
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TWI569316B (zh
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余振華
陳明發
蔡文景
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台灣積體電路製造股份有限公司
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Abstract

本發明提供接合結構及其製造方法。導電層係形成於接合結構的第一表面，接合結構包括接合至第二基材的第一基材，接合結構的第一表面為第一基材之被暴露出的表面。具有複數個第一開口和複數個第二開口的圖案化罩幕係形成於導電層上，第一開口和第二開口暴露出導電層的複數個部分。複數個第一接合連接件的複數個第一部分係形成於第一開口中，而複數個第二接合連接件的複數個第一部分係形成於第二開口中。導電層係被圖案化以形成第一接合連接件的第二部分和第二接合連接件的第二部分。，接合接合結構係利用第一接合連接件和第二接合連接件被接合至第三基材。

Description

半導體晶圓之接合結構的形成方法
本發明是有關於一種半導體晶圓的接合結構的形成方法，且特別是有關於一種晶圓對晶圓(Wafer to Wafer)之接合結構的形成方法。
面對如摩爾定律所述之持續的挑戰，半導體製造商不斷地努力以持續縮小特徵尺寸(如主動元件和半動元件之尺寸)、內連線的寬度和厚度、功率消耗，並增加元件密度、線路的密度和操作頻率。在一些應用中，這些較小的電子元件亦需要較小的封裝，這些封裝所使用的面積小於過去的封裝。
三維積體電路(3DICs)為半導體封裝上的最近發展，其中多個半導體芯片(Die)係相互堆疊，如層疊封裝(Package-on-Package；PoP)及系統級封裝(System-in-Package；SiP)技術。形成三維積體電路的一些方法包括接合二個或更多的半導體晶圓，而如邏輯、記憶體、處理器電路或其類似物的主動電路係位於不同的半導體晶圓上。一般使用的接合技術包括直接接合(Direct Bonding)、化學活化接合(Chemically Activated Bonding)、電漿活化接合(Plasma Activated Bonding)、陰極接合(Anodic Bonding)、共晶接合(Eutectic Bonding)、玻璃粉末接合(Glass Frit Bonding)、黏著接合(Adhesive Bonding)、熱壓縮接合(Thermo-Compressive Bonding)、反應性接合(Reactive Bonding)及/或其類似接合方式。一旦二個半導體晶圓接合在一起，二個半導體晶圓間的界面可提供堆疊半導體晶圓間的導電路徑。
堆疊半導體元件的優點之一係藉由使用堆疊半導體元件，可達到更高的密度。再者，堆疊半導體元件也可達到更小的形狀因子(Form Factor)、低成本、增加的性能以及較低的功率消耗。
因此，本發明之一態樣是在提供一種半導體晶圓之接合結構的形成方法，其係利用第一接合連接件和第二接合連接件，以接合接合結構與第三基材。
本發明之另一態樣是在提供一種半導體晶圓之接合結構的形成方法，其係形成第一突出特徵和第二突出特徵，並將第一接合連接件的第一部分和第二接合連接件的第一部分形成於其上，再形成第一接合連接件的第二部分和第二接合連接件的第二部分於各自的第一部分上。藉由上述方法形成第一接合連接件和第二接合連接件，並使其用以接合 第二基材和第一基材。
本發明之又一態樣是在提供一種半導體晶圓之接合結構的形成方法，其係圖案化第一基材，以形成第一突出特徵和第二突出特徵。先於第一突出特徵和第二突出特徵上，形成第一接合連接件的第二部分和第二接合連接件的第二部分，再將第一接合連接件的第一部分和第二接合連接件的第一部分分別形成於各自的第二部分上。藉由上述方法形成第一接合連接件和第二接合連接件，並使其用以接合第二基材和第一基材。
根據本發明上述態樣，提出一種半導體晶圓之接合結構的形成方法。在一實施例中，上述形成方法包含形成導電層於接合結構的第一表面上，接合結構包含與第二基材接合的第一基材，接合結構的第一表面為第一基材被暴露出的表面。圖案化罩幕係形成於導電層上，圖案化罩幕包含複數個第一開口和複數個第二開口，第一開口和第二開口暴露出導電層的複數個部分。複數個第一接合連接件的複數個第一部分係形成於第一開口中，複數個第二接合連接件的複數個第一部分係形成於第二開口中。圖案化導電層，以形成第一接合連接件的複數個第二部分和第二接合連接件的複數個第二部分，其中第一接合連接件的第一部分和第二接合連接件的第一部分係做為罩幕。利用第一接合連接件和第二接合連接件，以接合接合結構至第三基材，其中第一接合連接件和第二接合連接件係延伸貫穿複數個第三開口，並接觸第三開口所暴露出的導電特徵，第三開口係形成於第三基材 的正面。
依據本發明之一實施例，上述之第一基材為微機電系統(MEMS)晶圓，上述之第二基材為蓋晶圓(Cap Wafer)，上述之第三基材為互補式金氧半導體晶圓。
依據本發明之一實施例，第一接合連接件可形成接合環，第二接合連接件可被上述接合環所包圍，第一接合連接件可具有與第二接合連接件實質相同的厚度。
依據本發明之一實施例，在上述接合接合結構至第三基材的步驟後，第一接合連接件之第一部分係分別沿第一接合連接件的第二部分之側壁延伸。
根據本發明之另一態樣，提出一種半導體晶圓之接合結構的形成方法。在一實施例中，上述形成方法包括形成複數個第一突出特徵和複數個第二突出特徵於第一基材的背面。第一導電材料係形成於第一突出特徵和第二突出特徵上。複數個第一接合連接件的複數個第一部分係形成於第一突出特徵上。複數個第二接合連接件的複數個第一部分係形成於第二突出特徵上。第一導電材料係被圖案化，以形成第一接合連接件的複數個第二部分和第二接合連接件的複數個第二部分，其中第一接合連接件的第一部分和第二接合連接件的第一部分係做為罩幕。利用第一接合連接件和第二接合連接件，以接合第二基材至第一基材。
依據本發明之一實施例，上述形成第一接合連接件之第一部分的步驟包含形成第一圖案化罩幕於第一導電材料上，其中第一圖案化罩幕具有複數個第一開口，第一 開口暴露出設置於第一突出特徵上的第一導電材料之複數個部分；形成第二導電材料於第一開口中；以及，移除第一圖案化罩幕。上述之第二導電材料與第一導電材料不同。此外，形成第二接合連接件之第一部分的步驟包含形成第二圖案化罩幕於第一導電材料上，其中第二圖案化罩幕具有複數個第二開口，第二開口暴露出設置於第二突出特徵上的第一導電材料之一部分；形成第二導電材料於第二開口中；以及，移除第二圖案化罩幕。
依據本發明之一實施例，第一接合連接件形成接合環，第二接合連接件可被接合環所包圍。
依據本發明之一實施例，上述之形成方法更包還在接合第二基材至第一基材的步驟前，形成複數個第三開口和複數個第四開口於第二基材的前表面上，其中第三開口暴露出複數個第一導電元件，第四開口暴露出複數個第二導電元件，第一接合連接見延伸入第三開口中並接觸第一導電元件，第二接合連接件延伸入第四開口中並接觸第二導電元件。
根據本發明之又一態樣，提出一種半導體晶圓之接合結構的形成方法。在一實施例中，上述形成方法包括圖案化第一基材的背表面，以形成複數個第一突出特徵和複數個第二突出特徵。複數個第一接合連接件的複數個第二部分係形成於第一突出特徵上，且複數個第二接合連接件的複數個第二部分係形成於第二突出特徵上。第一接合連接件的複數個第一部分係形成於第一接合連接件的第二部分上，且 第二接合連接件的複數個第一部分係形成於第二接合連接件的第二部分上。利用第一接合連接件和第二接合連接件，以接合第二基材至第一基材。
依據本發明之一實施例，上述形成第一接合連接件之第二部分以及第二接合連接件之第二部分的步驟包含濺鍍第一導電材料於第一突出特徵以及第二突出特徵上，以及圖案化第一導電材料。此外，形成第一接合連接件之第一部分以及第二接合連接件之第一部分的步驟包含藉由無電電鍍法，形成一第二導電材料於該第一導電材料上，其中第二導電材料與第一導電材料不同。再者，第一接合連接件之厚度實質與些第二接合連接件之厚度相同，第一接合連接件形成接合環，第二接合連接件為複數個接合墊，且接合墊係被接合環所包圍。
100、500、800‧‧‧第一接合結構
101‧‧‧第一晶圓/微機電系統晶圓
103‧‧‧第二晶圓/蓋晶圓
105‧‧‧腔
101A、103A‧‧‧第一表面
101B‧‧‧第二表面
107‧‧‧導電層
109、803‧‧‧圖案化罩幕
111、209、509‧‧‧第一開口
113、211、515‧‧‧第二開口
115A/115B、511A/511B、805A/805B‧‧‧第一接合連接件/接合環
115A、117A、511A、517A、805A、807A‧‧‧第一部分
115B、117B、511B、517B、805B、807B‧‧‧第二部分
117A/117B、517A/517B、807A/807B‧‧‧第二接合連接件/接合墊
200‧‧‧第三晶圓/互補式金氧半導體晶圓
201‧‧‧金屬化層
203‧‧‧重分佈層
205‧‧‧介電層
207‧‧‧導電特徵
213、505、801‧‧‧種晶層/凸塊下金屬化層
400、700、1000‧‧‧方法
401、403、405、407、409、411、701、703、705、707、709、711、713、715、717、1001、1003、1005、1007、1009、1011‧‧‧步驟
501‧‧‧第一突出特徵
503‧‧‧第二突出特徵
507‧‧‧第一圖案化罩幕
513‧‧‧第二圖案化罩幕
301、303、601、603、901、903‧‧‧第二接合結構
W1、W2、W3、W4、W5、W6、W7、W8‧‧‧寬度
H1、H2、H3、H4、H5、H6、H7、H8‧‧‧高度
T1、T2、T3‧‧‧厚度
藉由以下詳細說明並配合圖式閱讀，可更容易理解本發明。在此強調的是，按照產業界的標準做法，各種特徵並未按比例繪製，僅為說明之用。事實上，為了清楚的討論，各種特徵的尺寸可任意放大或縮小。
[圖1A]至[圖1E]、[圖2A]至[圖2C]以及[圖3A]至[圖3B]係繪示根據一些實施例所述之製造接合結構的各個製程階段的剖面圖；[圖4]係繪示根據一些實施例所述之接合結構的形成方法之流程圖； [圖5A]至[圖5G]、[圖6A]至[圖6B]係繪示根據一些實施例所述之製造接合結構的各個製程階段的剖面圖；[圖7]係繪示根據一些實施例所述之接合結構的形成方法之流程圖；[圖8A]至[圖8E]、[圖9A]至[圖9B]係繪示根據一些實施例所述之製造接合結構的各個製程階段的剖面圖；以及[圖10]係繪示根據一些實施例所述之接合結構的形成方法之流程圖。
下面的揭露提供了許多不同的實施例或例示，用於實現本發明的不同特徵。部件和安排的具體實例描述如下，以簡化本發明之揭露。當然，這些是僅僅是例示並且不意在進行限制。例如，在接著的說明中敘述在第二特徵上方或上形成第一特徵可以包括在第一和第二特徵形成直接接觸的實施例，並且還可以包括一附加特徵可以形成第一特徵的形成第一和第二特徵之間的實施例，從而使得第一和第二特徵可以不直接接觸。此外，本公開可以在各種例示重複元件符號和/或字母。這種重複是為了簡化和清楚的目的，並不在本身決定所討論的各種實施例和/或配置之間的關係。
此外，空間相對術語，如“之下”、“下方”、“低於”、“上方”、“高於”等，在本文中可以用於簡單說明如圖中所示元件或特徵對另一元件(多個)或特徵(多個特徵)的關係。除了在圖式中描述的位向，空間相對術語 意欲包含元件使用或步驟時的不同位向。元件可以其他方式定位(旋轉90度或者在其它方位)，並且本文中所使用的相對的空間描述，同樣可以相應地進行解釋。
下述內文將描述實施例，也就是藉由接合二或多個晶圓，而形成接合結構。在一些實施例中，晶圓可為微機電系統(Microelectromechanical Systems；MEMS)晶圓、互補式金氧半導體(CMOS)晶圓及/或其類似物。
圖1A至圖1E、圖2A至圖2C以及圖3A至圖3B係繪示根據一些實施例所述之製造接合結構之各個製程階段的剖面圖。特別是，圖1A至圖1E係繪示製造第一接合結構100的各個製程階段的剖面圖，其中第一接合結構100包含第一晶圓101，第一晶圓101係在後續接合製程中，接合至第二晶圓103。圖2A至圖2C係繪示為後續製程而製造的第三晶圓200之各個製程階段的剖面圖。圖3A至圖3B係分別繪示第二接合結構301和第二接合結構303之剖面圖，其中根據一些實施例，第二接合結構301和第二接合結構303包含接合至第三晶圓200的第一接合結構100。
首先請參照圖1A。在一些實施例中，第一接合結構100包含第一晶圓101，其中第一晶圓101係接合至第二晶圓103。在所示的實施例中，第一晶圓101可使用微機電系統製程(MEMS Process)形成，且可稱作微機電系統晶圓(MEMS Wafer)101。第二晶圓103可扮演微機電系統晶圓101的蓋層，且可稱作蓋晶圓(Cap Wafer)103。
在一些實施例中，微機電系統晶圓101可包含 基材以及設置於基材上的各種元件。因上述元件並非了解後述各個實施例所必要的，故其未明確地繪示於圖1A中。基材可由矽形成，然而也可使用如矽、鍺、鎵、砷及上述之組合的其他第三族、第四族及/或第五族元素來形成。上述基材也可為絕緣層上覆矽(SOI)的形式。絕緣層上覆矽可包含半導體材料層(如矽、鍺及/或其類似物)，其係形成於絕緣層(如埋藏氧化物(Buried Oxide)及/或其類似物)上，且上述絕緣層上覆矽基材可形成於矽基材上。此外，也可使用包括多層基材、梯度基材、混合位向基材、上述之任意組合及/或其類似物之其他基材。
上述之各種元件可包含微機電系統元件，其包括腔、共振器、懸臂式元件(Cantilevered Element)、壓力感測器、加速度感應器、動作感測器、陀螺儀及/或其類似物，且可使用習知的微機電系統技術來形成上述之各種元件。上述之各種元件可更包含各種主動和被動互補式金氧半導體元件，包括電晶體、電容、電阻、二極體、光二極體、保險絲及/或其類似物。
在一些實施例中，蓋晶圓103可或可不為互補式金氧半導體晶圓，且其可或可不具有電路(未繪示)。特別是，蓋晶圓103可包含基材和各種主動以及被動互補式金氧半導體元件，其包括電晶體、電容、電阻、二極體、光二極體、保險絲及/或其類似物。在一些實施例中，蓋晶圓103也可包括為電子佈線所設置的介電層、導線以及介層窗(Via)。蓋晶圓103的基材可類似於微機電系統晶圓101的基 材，故此處不另贅述。選擇性地，蓋晶圓103可由其他適合的材料形成，其中上述其他適合的材料包括陶瓷材料、石英或其類似物。
在一些實施例中，如腔105之腔係形成於蓋晶圓103中。在蓋晶圓103接合至微機電系統晶圓101後，腔105可做為各種微機電系統元件中的密封腔。在一些實施例中，腔105可使用適合的微影和蝕刻製程來形成。在圖1A中，僅繪示單一個腔105，以進行說明。腔的數量可依照微機電系統晶圓101的設計需求而變化。
請再參照圖1A，在一些實施例中，蓋晶圓103的第一表面103A係接合至微機電系統晶圓101的第一表面101A，以形成第一接合結構100。蓋晶圓103的腔105可與微機電系統晶圓101的微機電系統元件對齊。可使用任何適合的技術，將微機電系統晶圓101接合至蓋晶圓103。上述適合的技術可如熔化接合(Fusion Bonding；如氧化物-氧化物接合、金屬-金屬接合、混合接合等)、陰極接合、共晶接合、其類似物或上述之組合。在一些實施例中，微機電系統晶圓101可熔化接合至蓋晶圓103，在上述接合的步驟中，使用由多晶矽或其他適合的材料所形成之薄層(未繪示)作為接合界面。在一些實施例中，因上述製程可於低壓下進行，故形成第一接合結構100後，密封腔105可具有低壓(高真空)。在另一些實施例中，密封腔105可具有任何適合的壓力，其係依照微機電系統晶圓101的設計需求而決定。
在一些實施例中，薄化微機電系統晶圓101的 步驟可於形成第一接合結構100前或後進行，使得一或多個導電特徵(未繪示)可暴露於微機電系統晶圓101的第二表面101B上。在一些實施例中，薄化製程可包括研磨製程、化學機械研磨(CMP)製程或其類似製程。以下將對形成於微機電系統晶圓101之第二表面101B的複數個接合連接件進行更詳細的描述。在一些實施例中，複數個接合連接件可不與微機電系統晶圓101之第二表面101B上的一或多個其他導電特徵耦合，且複數個接合連接件可用於將第一接合結構100機械地接合和電性地耦合至其他晶圓。在其他實施例中，複數個接合連接件可耦合至微機電系統晶圓101之第二表面101B上的一或多個導電特徵，且複數個接合連接件可用於將第一接合結構100機械地接合和電性地耦合至其他晶圓。
請參照圖1B，導電層107係形成於微機電系統晶圓101之第二表面101B上。如以下之詳細描述，後續製程係圖案化導電層107，以形成複數個接合連接件(如圖1E所示之第一接合連接件115A/115B以及第二接合連接件117A/117B)於微機電系統晶圓101之第二表面101B(相對於第一表面101A)上，以製備後續接合製程所需之微機電系統晶圓101。在一些實施例中，複數個接合連接件可用以將微機電系統晶圓101接合至第三晶圓200(請參照如圖3A和圖3B)。導電層107可包含一或多層銅、鈦、鎳、金、鎂、其類似物或上述之組合，且導電層107可藉由原子層沉積(ALD)、物理氣相沉積(PVD)、蒸鍍、濺鍍、其類似製程 或上述之組合來形成。在一些實施例中，導電層107可具有約2μm至約4μm之厚度T1。在一些實施例中，導電層107包含銅層，其具有約1.95μm至約3.9μm之厚度。上述銅層係形成於鈦層上，且鈦層具有約500Å至約1000Å之厚度。
請參照圖1C，圖案化罩幕109係形成於導電層107暴露出的表面上。在一些實施例中，圖案化罩幕109包含光阻材料或任何光可圖案化之材料。在一些實施例中，圖案化罩幕109的材料係沉積、照射(曝光)以及顯影，以移除部分的材料，進而形成複數個第一開口111和複數個第二開口113，藉此形成圖案化罩幕109。如所示的實施例，第一開口111和第二開口113暴露出導電層107的複數個部分，並定義後續形成的複數個接合連接件的圖案(如圖1E所示的第一接合連接件115A/115B和第二接合連接件117A/117B)。以下將詳細地描述接合環(或稱第一接合連接件115A/115B)的第一部分將形成於第一開口111中，且接合墊(或稱第二接合連接件117A/117B)的第一部分將形成於第二開口113中的步驟。在繪示的實施例中，圖案化罩幕109設置有二個第一開口111。然而，在一些實施例中，以俯視角來看，上述之二個第一開口111可為單一個連續開口的一部分，並可具有圓環形、方環(Annular Rectangular)形或其類似形狀。在一些實施例中，第二開口113的俯視形狀可為圓形、橢圓形、如三角形、長方形、六角形或其類似形狀之多角形。在繪示的實施例中，第一開口111和第二開口113的數量僅為說明而繪示。在其他實施 例中，第一開口111和第三開口113的數量可根據微機電系統晶圓101和第三晶圓200的設計需求而變化。
請參照圖1D，在一些實施例中，複數個第一接合連接件115A/115B的複數個第一部分115A和複數個第二接合連接件117A/117B的複數個第一部分117A係分別形成於複數個第一開口111和複數個第二開口113中。在一些實施例中，第一接合連接件115A/115B的第一部分115A和第二接合連接件117A/117B的第一部分117A包含適當的導電材料，如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似物或上述之組合，且上述第一部分115A或第一部分117A可使用如電化學電鍍製程、無電式電鍍製程或其類似製程來形成。在一些實施例中，第一接合連接件115A/115B的第一部分115A和第二接合連接件117A/117B的第一部分117A可具有約0.5μm至約1μm之高度H1。在一些實施例中，第一接合連接件115A/115B的第一部分115A可具有約30μm至約70μm之寬度W1，且第二接合連接件117A/117B的第一部分117A可具有約10μm至約50μm之寬度W2。接著，移除圖案化罩幕109，以暴露出第一接合連接件115A/115B的第一部分115A的側壁和第二接合連接件117A/117B的第一部分117A的側壁。在一些實施例中，其中圖案化罩幕109係以光阻材料形成，且移除圖案化罩幕109的步驟可使用如灰化製程，並伴隨濕式清洗製程。
請參照圖1E，圖案化導電層107，以形成複數個第一接合連接件115A/115B的複數個第二部分115B和 複數個第二接合連接件117A/117B的複數個第二部分117B。在一些實施例中，可使用一或多個蝕刻製程，以圖案化導電層107，其中以第一接合連接件115A/115B的第一部分115A和第二接合連接件117A/117B的第一部分117A做為蝕刻罩幕。因此，在繪示的實施例中，第一接合連接件115A/115B的第二部分115B具有寬度W1，而第二接合連接件117A/117B的第二部分117B具有寬度W2。再者，第一接合連接件115A/115B的第二部分115B和第二接合連接件117A/117B的第二部分117B具有高度H2，其係與導電層之厚度T1相等。在一些實施例中，其中導電層107包含銅層，且銅層係形成於鈦層上。可使用如三氯化鐵(FeCl3)、氯化氫(HCl)及水(為蝕刻銅)之混合物，以及過氧化氫、氟化氫和水(為蝕刻鈦)之混合物，以蝕刻導電層107。
請再參照圖1E，第一接合連接件115A/115B和第二接合連接件117A/117B的俯視形狀係分別與第一開口111和第二開口113的俯視圖之形狀相似，故此處不另贅述。接下來，複數個第一接合連接件115A/115B也可被視為接合環115A/115B，而複數個第二接合連接件117A/117B也可被視為複數個接合墊117A/117B。以下將對第一接合連接件115A/115B和第二接合連接件117A/117B進行詳細的說明。第一接合連接件115A/115B和第二接合連接件117A/117B可用於將第一接合結構100接合及電性耦合至第三晶圓200(例如請參照圖3A和圖3B)。如前述之圖1A至圖1E所示，形成第一接合連接件 115A/115B和第二接合連接件117A/117B的步驟，並未圖案化微機電系統晶圓101的第二表面101B，其利於以較低的成本形成具有高厚度均勻性的接合連接件。
圖2A至圖2C係繪示製備後續接合製程所需之第三晶圓200的各個製程階段的剖面圖。首先請參照圖2A，其係繪示第三晶圓200的一部分。在一些實施例中，第三晶圓200可使用互補式金氧半導體製程形成，且第三晶圓200可視為互補式金氧半導體晶圓200。在一些實施例中，互補式金氧半導體晶圓200包括基材、設於基材上之各種主動及被動元件，以及設於基材上方之各種金屬化層，金屬化層係以圖2A之層201一併繪示。在一些實施例中，互補式金氧半導體200的基材可類似於微機電系統晶圓101的基材，故此處不另贅述。
在一些實施例中，各種主動和被動元件可包括各種n型金屬-氧化物半導體(NMOS)元件及/或p型金屬-氧化物半導體(PMOS)元件，如電晶體、電容、電阻、二極體、光二極體、保險絲及/或其類似物。
金屬化層可包括形成於基材上的層間介電層(ILD)/介金屬介電層(IMD)。舉例來說，層間介電層/介金屬介電層可由低介電常數材料所形成，且上述之低介電常數材料係如磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟矽玻璃(FSG)、碳氧化矽(SiOxCy)、旋塗式玻璃(Spin-On-Glass)、旋塗式高分子(Spin-On-Polymer)、碳化矽材料、化合物、組合物、上述之組合或其類似物。上述 之低介電常數材料可使用任何適合的習知方法形成，例如：旋轉塗佈、化學氣相沉積、電漿加強化學氣相沉積或其類似製程。
在一些實施例中，內連結構可形成於層間介電層/介金屬介電層中，形成內連結構的步驟可例如使用金屬鑲嵌製程(Damascene Process)、雙重金屬鑲嵌製程(Dual Damascene Process)或其類似製程。圖案化層間介電層/介金屬介電層的步驟可使用微影技術，以形成溝渠和介層窗(Via)。內連結構可藉由沉積適當的導電材料於層間介電層/介金屬介電層的溝渠和介層窗中，以形成內連結構。上述沉積適當材料的步驟可使用各種沉積和電鍍方法或其類似方法。此外，內連結構可包括一或多個阻障層(Barrier Layer)/黏著層，以保護層間介電層/介金屬介電層，使其不會擴散並不受金屬毒害(Metallic Poisoning)。一或多個阻障層/黏著層可包含鈦、氮化鈦、鉭、氮化鉭或其他替代物。可使用如物理氣相沉積、原子層沉積、濺鍍或其類似製程，以形成阻障層。內連結構的導電材料可包含銅、銅合金、銀、金、鎢、鉭、鋁及其類似物。在一實施例中，形成內連結構的步驟可包括毯覆式地形成一或多個阻障層/黏著層、沉積導電材料的薄種晶(Thin Seed)層，以及將導電材料填入層間介電層/介金屬介電層中溝渠和介層窗，其中上述步驟可例如藉由電鍍進行。然後，進行化學機械研磨(CMP)以移除內連結構超出的部分。在一些實施例中，內連結構可提供形成於基材上的各種被動元件和主動元件之間的電性連接。
在一些實施例中，接觸墊(未繪示)可形成於金屬化層上。形成接觸墊的步驟可包括毯覆式地沉積導電層，並圖案化導電層以形成接觸墊。接觸墊可包含如銅、鎢、鋁、銀、金、其類似物、上述之合金或上述之組合的導電材料。鈍化層(未繪示)可形成於接觸墊上，並圖案化鈍化層以暴露出部分的接觸墊。在一些實施例中，鈍化層可包含如氮化矽、碳化矽、氧化矽、氮氧化矽、其類似物或其組合之介電材料，且可使用化學氣相沉積、物理氣相沉積、原子層沉積、其類似製程或上述製程之組合，以形成上述之鈍化層(Passivation Layer)。在其他實施例中，鈍化層可包含聚合物，其包括但不限於聚亞醯胺(Polyimide；PI)、苯并環丁烯(Benzocyclobutene；BCB)、聚苯并噁唑(Poylbenzoxazole；PBO)、其類似物或上述之組合，且可使用如旋轉塗布法或其類似方法形成鈍化層。圖案化鈍化層的步驟可使用適合的微影和蝕刻方法進行。
請再參照圖2A，一或多個重分佈層(Redistribution Layer；RDL)203係形成於接觸墊上。在一些實施例中，重分佈層203可包含一或多個介電層205以及一或多個導電特徵207(例如：導電的線和介層窗)，導電特徵207可形成於一或多個介電層205中。在一些實施例中，一或多個介電層205可包含聚合物，所述聚合物包括但不限於聚亞醯胺、苯并環丁烯、聚苯并噁唑、其類似物或上述之組合的聚合物，且可使用如旋轉塗布法或其類似方法形成介電層。一或多個導電特徵207可包含種晶層(未繪示)以 及形成於種晶層上的導電材料。種晶層可包括銅、鈦、鎳、金、鎂、其類似物或其組合，且可利用原子層沉積、物理氣相沉積、濺鍍、其類似製程或其組合來形成種晶層。導電材料包括銅、鎢、鋁、銀、金、其類似物或其組合，且可利用電化學電鍍、無電式電鍍、原子層沉積、物理氣相沉積、其類似製程或其組合來形成導電材料。
在一些實施例中，圖案化一或多個介電層205之最上層介電層(未個別繪示)，以形成複數個第一開口209和複數個第二開口211。在一些實施例中，可使用適合的微影方法圖案化一或多個介電層205之最上層介電層。第一開口209和第二開口211暴露出一或多個導電特徵207的複數個部分。以下詳細描述接合微機電系統晶圓101以及互補式金氧半導體晶圓200的步驟。藉由將複數個第一接合連接件115A/115B以及複數個第二接合連接件117A/117B分別插設至複數個第一開口209和複數個第二開口211中，並接觸暴露出的一或多個導電特徵207，以將微機電系統晶圓101接合至互補式金氧半導體晶圓200。因此，第一開口209和第二開口211所設計的尺寸和形狀係為容納第一接合連接件115A/115B以及第二接合連接件117A/117B。在一些實施例中，第一開口209的寬和第二開口211的寬係分別大於第一接合連接件115A/115B的寬W1和第二接合連接件117A/117B的寬W2。在一些實施例中，第一開口209的高和第二開口211的高係小於第一接合連接件115A/115B以及第二接合連接件117A/117B之高H1和高H2的和(即 H1+H2)。在其他實施例中，第一開口209的高和第二開口211的高係小於第一接合連接件115A/115B之第二部分115B以及第二接合連接件117A/117B之第二部分117B的高H2。
請參照圖2B，種晶層213係毯覆式地形成於重分佈層203上以及第一開口209和第二開口211中。在一些實施例中，種晶層213可包括與導電層107類似的材料，且可使用類似於形成導電層107的方法，以形成種晶層213，上述材料和方法請參照圖1B之說明，此處不另贅述。在一些實施例中，種晶層213可包含銅層，銅層具有約0.5μm至約2μm的厚度，且銅層係形成於厚度為約200Å至約500Å之鈦層上。
請參照圖2C，設於重分佈層203之最上層表面的種晶層213的一部分係被移除，以保留第一開口209和第二開口211中的種晶層213，而形成複數個第一接合連接件115A/115B和複數個第二接合連接件117A/117B的複數個凸塊下金屬化(Under-Bump Metallization；UBM)層。在一些實施例中，移除設於重分佈層203的最上層表面之種晶層213的一部分的步驟，可使用如研磨、化學機械研磨或其類似製程來進行。
圖3A係繪示根據一些實施例所述之第二接合結構301，其中第二接合結構301包含如圖2A所示之第一接合結構100，其係接合至互補式金氧半導體晶圓200。在所示的實施例中，接合第一接合結構100至互補式金氧半導體 晶圓200的步驟，未形成凸塊下金屬化層213於第一開口209和第二開口211中。在一些實施例中，第一接合結構100的第一接合連接件115A/115B和第二接合連接件117A/117B係分別相對對齊至互補式金氧半導體晶圓200的第一開口209和第二開口211。之後，第一接合結構100與互補式金氧半導體晶圓200係相互接觸，使得複數個第一接合連接件115A/115B和複數個第二接合連接件117A/117B分別延伸入第一開口209和第二開口211，並接觸重分佈層203所暴露出之各個導電特徵207。
在一些實施例中，其中第一接合連接件115A/115B的第一部分115A和第二接合連接件117A/117B的第一部分117A係由如錫之焊料形成，且可進行回焊製程(Reflow Process)以調整焊料的形狀至連接件預定的形狀。在所示的實施例中，在回焊製程後，將第一接合連接件115A/115B的第一部分115A填充至第一開口209中，並沿著各第一接合連接件115A/115B的第二部分115B之側壁延伸。類似地，將第二接合連接件117A/117B的第一部分117A填充至第二開口211中，並沿著各第二接合連接件117A/117B的第二部分117B之側壁延伸。在所示的實施例中，第一接合連接件115A/115B的第二部分115B和第二接合連接件117A/117B的第二部分117B係直接接觸相對應的重分佈層203之導電特徵207。在其他實施例中，第一接合連接件115A/115B的第一部分115A的材料可介於個別的第一接合連接件115A/115B的第二部分115B和個 別的重分佈層203之導電特徵207之間。同樣地，第二接合連接件117A/117B的第一部分117A的材料可介於個別的第二接合連接件117A/117B的第二部分117B和個別的重分佈層203之導電特徵207之間。
請再參照圖3A，在一些實施例中，複數個第一接合連接件115A/115B和複數個第二接合連接件117A/117B係將第一接合結構100機械地及電性地耦合至互補式金氧半導體晶圓200。在一些實施例中，其中第一接合連接件115A/115B形成接合環，第一接合連接件115A/115B僅可提供機械性接合且為電性惰性。在上述實施例中，第一接合連接件115A/115B(或稱接合環)可密封微機電系統晶圓101的微機電系統元件，而與外在環境隔絕。在其他實施例中，第一接合連接件115A/115B(或稱接合環)可電性地耦合至微機電系統晶圓101的微機電系統元件，且與互補式金氧半導體晶圓200的各種主動元件和被動元件電性地耦合。
圖3B係繪示根據一些實施例所述之第二接合結構303，其包含如圖2C所示之第一接合結構100，其係接合至互補式金氧半導體晶圓200。在所示的實施例中，在形成凸塊下金屬化層213於第一開口209和第二開口211中後(如圖2B和圖2C所示)，互補式金氧半導體晶圓200係接合至第一接合結構100。在一些實施例中，可使用類似於形成第二接合結構301的方法，以形成第二接合結構303，此處不另贅述。在所示的實施例中，凸塊下金屬化層213係介於 第一接合連接件115A/115B和重分佈層203個別的導電特徵207中，以及介於第二接合連接件117A/117B和重分佈層203個別的導電特徵207中。
圖4係繪示根據一些實施例所述之接合結構(如第二接合結構301或第二接合結構303)的形成方法之流程圖。方法400由步驟401開始，其中第一晶圓(如微機電系統晶圓101)係接合至第二晶圓(如蓋晶圓103)，以形成第一接合結構(如第一接合結構100)，如前述圖1A所說明。在步驟403中，導電層(如導電層107)係形成於第一晶圓所暴露出的表面上，其悉如前述圖1B所說明。在步驟405中，具有複數個第一開口(如第一開口111)和複數個第二開口(如第二開口113)之圖案化罩幕(如圖案化罩幕109)係形成於導電層暴露出的表面上，其悉如前述圖1C所說明。在步驟407中，複數個第一接合連接件的複數個第一部分和複數個第二接合連接件的複數個第一部分(如第一接合連接件115A/115B的第一部分115A和第二接合連接件117A/117B的第一部分117A)係分別形成於第一開口和第二開口中，其悉如前述圖1D所說明。在步驟409中，圖案化導電層以形成複數個第一接合連接件的複數個第二部分和複數個第二接合連接件的複數個第二部分(如第一接合連接件115A/115B的第二部分115B和第二接合連接件117A/117B的第二部分117B)，其悉如前述圖1E所說明。在一些實施例中，第一接合連接件的第一部分和第二接合連接件的第一部分可做為導電層的蝕刻罩幕。在步驟411中， 使用第一接合連接件和第二接合連接件，將第一接合結構接合至第三晶圓(如互補式金氧半導體晶圓200)，藉以形成第二接合結構(如第二接合結構301或第二接合結構303)，其悉如前述圖3A和圖3B所說明。
圖5A至圖5G、圖6A和圖6B係繪示根據一些實施例所述之製造接合結構的各個製程階段的剖面圖。特別是，圖5A至圖5G係繪示製備續接合製程所需的第一接合結構500的中間製程之剖面圖，其中第一接合結構500包含第一晶圓101，第一晶圓101係接合至第二晶圓103。圖6A和圖6B係分別繪示根據一些實施例所述之第二接合結構601和第二接合結構603的剖面圖，其中第二接合結構601和第二接合結構603包含第一接合結構500，其係接合至互補式金氧半導體晶圓200。
請參照圖5A，根據一些實施例，第一接合結構500包含第一晶圓101，且第一晶圓101係接合至第二晶圓103。在一些實施例中，第一接合結構500係類似於如圖1A所述之第一接合結構100，並使用相似的元件符號標示，故此處不另贅述。
請參照圖5B，微機電系統晶圓101的第二表面101B係被圖案化，以形成第一突出特徵501和第二突出特徵503。在一些實施例中，可使用適合的微影和蝕刻方法，以圖案化微機電系統晶圓101的第二表面101B。在一些實施例中，第一突出特徵501和第二突出特徵503可具有約1.5μm至約2.5μm的高度H3。在所示的實施例中係繪示二個 第一突出特徵501。然而，在一些實施例中，以俯視角來看，二個第一突出特徵501可為單一個連續突出特徵的一部分，且可具有圓環形、方環形或其類似形狀。在一些實施例中，第二突出特徵503的俯視形狀可為圓形、橢圓形、如三角形、四角形、六角形或其類似形狀的多角形。在所示的實施例中，第一突出特徵501和第二突出特徵503的數量僅為說明而繪示。在其他實施例中，第一突出特徵501和第二突出特徵503的數量可根據微機電系統晶圓101的設計需求而改變。以下將詳細說明形成第一接合連接件511A/511B以及第二接合連接件517A/517B的步驟。第一接合連接件511A/511B以及第二接合連接件517A/517B將分別形成於第一突出特徵501和第二突出特徵503上(如圖5G所示)，且用於將第一接合結構100接合至互補式金氧半導體晶圓200。
請參照圖5C，種晶層505係共形形成(Conformally Formed)於微機電系統晶圓101之圖案化的第二表面101B上。在一些實施例中，種晶層505可使用類似於導電層107之材料以及形成方法來形成，導電層107的材料與形成方法已於前述圖1B詳述，故此處不另贅述。在一些實施例中，可使用電化學電鍍製程或其類似製程，以形成種晶層505。在一些實施例中，種晶層505可具有約2200A至3500Å的厚度T2。在一些實施例中，種晶層505包含具有厚度為約2000Å至3000Å的銅層，且銅層係形成於具有約200Å至500Å之厚度的鈦層上。
請再參照圖5C，第一圖案化罩幕507具有複數個第一開口509，第一開口509形成於種晶層505暴露出的表面上。在一些實施例中，可使用與圖案化罩幕109類似的材料和形成方法，以形成第一圖案化罩幕507，圖案化罩幕109的材料和形成方法已於前述圖1C中說明，故此處不另贅述。在所示的實施例中，第一開口509暴露出種晶層505的複數個部分，其中種晶層505係設於第一突出特徵501上。在一些實施例中，第一開口509的俯視形狀可類似於如圖5B所述之第一突出特徵501的俯視形狀，此處不另贅述。
請參照圖5D，複數個第一接合連接件511A/511B的複數個第一部分511A(如圖5G所示)係形成於複數個第一開口509中。在一些實施例中，可使用類似於第一接合連接件115A/115B的第一部分115A之材料和形成方法，以形成第一接合連接件511A/511B的第一部分511A，上述材料和形成方法悉如圖1D所述，故此處不另贅述。在所示的實施例中，可使用電化學電鍍或其類似製程，以形成第一接合連接件511A/511B的第一部分511A。之後，移除第一圖案化罩幕507，以暴露出第一接合連接件511A/511B的第一部分511A的側壁。移除第一圖案化罩幕507的步驟可使用類似於移除如圖1D所示之圖案化罩幕109的方法，故此處不另贅述。在一些實施例中，第一接合連接件511A/511B的第一部分511A可具有約0.2μm至約1μm的高度H4和約30μm至約70μm的寬度W4。
請參照圖5E，第二圖案化罩幕513係形成於種 晶層505暴露出的表面和第一接合連接件511A/511B的第一部分511A上，且第二圖案化罩幕513具有複數個第二開口515。在一些實施例中，可使用類似於如圖1C所示之圖案化罩幕109的材料和形成方法，以形成第二圖案化罩幕513，故此處不另贅述。在所示的實施例中，第二開口515暴露出設於第二突出特徵503上之種晶層505的複數個部分。在一些實施例中，第二開口515的俯視形狀可類似於如圖5B所述之第二突出特徵503之俯視形狀，此處不另贅述。
請參照圖5F，複數個第二接合連接件517A/517B的複數個第一部分517A(如圖5G)係形成於第二開口515。在一些實施例中，可使用類似於第一接合連接件115A/115B的第一部分115A之材料和形成方法，以形成第二接合連接件517A/517B的第一部分517A，上述材料和形成方法悉如圖1D所述，故此處不另贅述。在所示的實施例中，可使用電化學電鍍或其類似製程，以形成第一接合連接件517A/517B的第一部分517A。之後，移除第二圖案化罩幕513，以暴露出第一接合連接件511A/511B的第一部分511A和第二接合連接件517A/517B的第一部分517A。在一些實施例中，移除第二圖案化罩幕513的步驟可使用類似於移除如圖1D所示之圖案化罩幕109的方法，故此處不另贅述。在一些實施例中，第二接合連接件517A/517B的第一部分517A可具有約0.2μm至約1μm的高度H5和約10μm至約50μm的寬度W5。在所示的實施例中，第二接合連接件517A/517B的第一部分517A之高度H5係實質與第一接 合連接件511A/511B的第一部分511A的高度H4相等。在其他實施例中，第二接合連接件517A/517B的第一部分517A之高度H5係不同於第一接合連接件511A/511B的第一部分511A的高度H4。
請再參照圖5G，圖案化種晶層505以形成複數個第一接合連接件511A/511B的複數個第二部分511B和複數個第二接合連接件517A/517B的複數個第二部分517B。在一些實施例中，圖案化種晶層505的步驟可使用類似於如圖1E所示之導電層107的方法，此處不另贅述。因此，在所示的實施例中，第一接合連接件511A/511B的第二部分511B具有寬度W4，且第二接合連接件517A/517B的第二部分517B具有寬度W5。再者，第一接合連接件511A/511B的第二部分511B和第二接合連接件517A/517B的第二部分517B具有高度H6，其係與種晶層505的厚度T2相等。
請再參照圖5G，第一接合連接件511A/511B和第二接合連接件517A/517B的俯視形狀係分別相似於第一開口509和第二開口515的俯視形狀，此處不另贅述。接下來，複數個第一接合連接件511A/511B也可被視為接合環511A/511B，且複數個第二接合連接件517A/517B也可被視為複數個接合墊517A/517B。以下將對第一接合連接件511A/511B和第二接合連接件517A/517B的功用進行詳細描述。第一接合連接件511A/511B和第二接合連接件517A/517B將用以使第一接合結構500接合並電性耦合至 第三晶圓200(如圖6A和圖6B所示)。如圖5A至圖5G所示，第一接合連接件511A/511B和第二接合連接件517A/517B係分別使用第一圖案化罩幕507和第二圖案化罩幕513，並於分開的製程步驟中形成。上述製程有利於形成具有高厚度均勻性的接合連接件，因為具有相似形狀和尺寸的開口(如第一開口509或第二開口515)係於每一製程步驟中被填充。
圖6A係根據一些實施例繪示第二接合結構601的剖面圖，其中第二接合結構601包含如圖2A所示之第一接合結構500，其係與互補式金氧半導體晶圓200接合。在所示的實施例中，並未於第一開口209和第二開口211中形成凸塊下金屬化層213，以將互補式金氧半導體晶圓200接合至第一接合結構500。在一些實施例中，第一接合結構500的第一接合連接件511A/511B和第二接合連接件517A/517B係分別相對對齊互補式金氧半導體晶圓200之第一開口209和第二開口211(如圖2A所示)。然後，第一接合結構500和互補式金氧半導體晶圓200係相互接觸，使得第一接合連接件511A/511B和第二接合連接件517A/517B分別延伸入第一開口209和第二開口211中，並接觸重分佈層203上暴露出的個別導電特徵207。
在一些實施例中，其中第一接合連接件511A/511B的第一部分511A和第二接合連接件517A/517B的第一部分517A係由如錫之焊料所形成，且可於低於焊料回焊溫度的溫度下進行接合製程。在上述實施例 中，第一接合連接件511A/511B的第一部分511A和第二接合連接件517A/517B的第一部分517A不改變形狀，且可使用如擴散焊接法(Diffusion Soldering Method)，將第一接合連接件511A/511B的第一部分511A和第二接合連接件517A/517B的第一部分517A接合至重分佈層203之個別的導電特徵207。在其他實施例中，可使用如圖3A所示之回焊製程，將第一接合連接件511A/511B的第一部分511A和第二接合連接件517A/517B的第一部分517A接合至重分佈層203之個別的導電特徵207，此處不另贅述。在一些實施例中，第一接合連接件511A/511B和第二接合連接件517A/517B係機械地及電性地耦合第一接合結構500至互補式金氧半導體晶圓200。在一些實施例中，複數個第一接合連接件511A/511B形成接合環，第一接合連接件511A/511B僅可提供機械性接合且為電性惰性。在上述實施例中，第一接合連接件511A/511B(或稱接合環)可密封微機電系統晶圓101的微機電系統元件，而與外在環境隔絕。在其他實施例中，第一接合連接件511A/511B(或稱接合環)可接地。在另一些實施例中，第一接合連接件511A/511B(或稱接合環)可電性地耦合至微機電系統晶圓101的微機電系統元件，並電性地耦合至互補式金氧半導體晶圓200的各種主動元件和被動元件。
圖6B係根據一些實施例繪示第二接合結構603的剖面圖，其中第二接合結構603包含如圖2C所示之第一接合結構500，其係與互補式金氧半導體晶圓200接合。在所 示的實施例中，在形成凸塊下金屬化層213於第一開口209和第二開口211中後(如圖2C所示)，將互補式金氧半導體晶圓200接合至第一接合結構500。在一些實施中，可使用類似於如圖6A之第二接合結構601的形成方法，以形成第二接合結構603，此處不另贅述。在所示的實施例中，凸塊下金屬化層213係介於第一接合連接件511A/511B和重分佈層203之個別的導電特徵207中，且介於第二接合連接件517A/517B和重分佈層203之個別的導電特徵207中。
圖7係繪示根據一些實施例所述之接合結構(如第二接合結構601或第二接合結構603)的形成方法700之流程圖。方法700由步驟701開始，其中第一晶圓(如微機電系統晶圓101)係接合至第二晶圓(如蓋晶圓103)，以形成第一接合結構(如第一接合結構500)，如前述圖5A所說明。在步驟703中，圖案化第一晶圓之暴露出的表面，以形成複數個第一突出特徵和複數個第二突出特徵(如第一突出特徵501和第二突出特徵503)，其悉如前述圖5B所說明。在步驟705中，導電層(如種晶層505)係形成於第一晶圓之圖案化的表面上，其悉如前述圖5C所說明。在步驟707中，具有複數個第一開口(如第一開口509)之第一圖案化罩幕(如第一圖案化罩幕507)係形成於導電層暴露出的表面上，其悉如前述圖5C所說明。在步驟709中，複數個第一接合連接件的複數個第一部分(如第一接合連接件511A/511B的第一部分511A)係形成於複數個第一開口中，其悉如前述圖5D所說明。在步驟711中，具有複數個第二開口(如第二開口 515)的第二圖案化罩幕(如第二圖案化罩幕513)係形成於導電層暴露出的表面上和第一接合連接件之第一部分上，其悉如前述圖5E所說明。在步驟713中，複數個第二接合連接件的複數個第一部分(如第二接合連接件517A/517B的第一部分517A)係形成於複數個第二開口中，其悉如前述圖5F所說明。在步驟715中，圖案化導電層，以形成複數個第一接合連接件的複數個第二部分和複數個第二接合連接件的複數個第二部分(如第一接合連接件511A/511B的第二部分511B和第二接合連接件517A/517B的第二部分517B)，其悉如前述圖5G所說明。在一些實施例中，第一接合連接件的第一部分和第二接合連接件的第一部分係做為導電層的蝕刻罩幕。在步驟717中，利用第一接合連接件和第二接合連接件，將第一接合結構接合至第三晶圓(如互補式金氧半導體晶圓200)，藉以形成第二接合結構(如第二接合結構601或第二接合結構603)，其悉如前述圖6A和圖6B所說明。
圖8A至圖8E和圖9A至圖9B係繪示根據一些實施例所述之製造接合結構的各個製程階段的剖面圖。特別是，圖8A至圖8E繪示製備第一接合結構800的各個製程階段的剖面圖，其中第一接合結構800包含在後續製程中接合至第二晶圓103的第一晶圓101。圖9A至圖9B分別繪示根據一些實施例所述之第二接合結構901和第二接合結構903的剖面圖，其中第二接合結構901和第二接合結構903包含第一接合結構800，其係接合至互補式金氧半導體晶圓200。
首先參照圖8A，其係根據一些實施例繪示第一接合結構800，第一接合結構800包含第一晶圓101，第一晶圓101係接合至第二晶圓103。在一些實施例中，第一接合結構800係類似於如前述圖1A所說明的第一接合結構100，並以相似的元件符號標示，故此處不另贅述。
圖8B繪示圖案化微機電晶圓101的第二表面101B後，以形成複數個第一突出特徵501和複數個第二突出特徵503的第一接合結構800。在一些實施例中，如圖8B所示的第一接合結構800係類似於如前述圖5B所說明之第一接合結構500，並以類似的元件符號標示，故此處不另贅述。以下將詳細說明，分別於複數個第一突出特徵501和複數個第二突出特徵503上，形成複數個第一接合連接件805A/805B和複數個第二接合連接件807A/807B(如圖8E所示)，且第一接合連接件805A/805B和第二接合連接件807A/807B將用以接合第一接合結構800至互補式金氧半導體200。
請參照圖8C，種晶層801係共形地形成於微機電系統晶圓101的圖案化第二表面101B上。在所示的實施例中，可使用濺鍍或其他類似製程，以形成種晶層801。在其他實施例中，可使用與圖1B之導電層107相似的形成方法和材料，以形成種晶層801，故此處不另贅述。在一些實施例中，種晶層801可具有約2200Å至約3500Å的厚度T3。在一些實施例中，種晶層801包含具有約2000Å至約3000Å之銅層，其中銅層係形成於具有約200Å至500Å之厚度的鈦 層上。
請再參照圖8C，圖案化罩幕803係形成於種晶層801暴露出的表面上。在一些實施例中，可使用與圖1C之圖案化罩幕109相似的形成方法和材料，以形成圖案化罩幕803，故此處不另贅述。在所示的實施例中，圖案化罩幕803保護種晶層801之一部分，上述之種晶層801的一部分係設於第一突出特徵501和第二突出特徵503上。
請參照圖8D，種晶層801暴露出的部分係被移除，以形成第一突出特徵501上的第一接合連接件805A/805B的第二部分805B以及第二突出特徵503上的第二接合連接件807A/807B的第二部分807B。在一些實施例中，可使用相似於圖1E所述之導電層107的圖案化方法，以圖案化種晶層801，故此處不另贅述。因此，在所示的實施例中，第二部分805B和第二部分807B具有高度H7，其係與種晶層801的厚度T3相等。在一些實施例中，第二部分805B可具有約30μm至約50μm的寬度W7，且第二部分807B可具有約10μm至約50μm之寬度W8。
請參照圖8E，第一部分805A係形成於第二部分805B上，以形成第一接合連接件805A/805B，且第一部分807A係形成於第二部分807B上，以形成第二接合連接件807A/807B。在所示的實施例中，可使用無電電鍍製程或其類似製程，以形成第一部分805A和第一部分807A。因此，第一部分805A具有寬度W7且第一部分807A具有寬度W8。在一些實施例中，第一部分805A和第一部分807A具 有約0.2μm至約1μm的高度H8。
請參照圖8E，第一接合連接件805A/805B的俯視形狀和第二接合連接件807A/807B的俯視形狀係分別與圖5B所述之第一突出特徵501和第二突出特徵503之俯視圖的形狀相似，此處不另贅述。接下來，複數個第一接合連接件805A/805B也可被視為接合環805A/805B，而複數個第二接合連接件807A/807B也可被視為複數個接合墊807A/807B。以下將針對第一接合連接件805A/805B和第二接合連接件807A/807B的功用進行詳細描述。第一接合連接件805A/805B和第二接合連接件807A/807B將用以使第一接合結構800接合並電性地耦合至第三晶圓200(如圖9A和圖9B所示)。如圖8A至圖8E所述，種晶層801係以濺鍍的方式形成，然而第一部分805A和第一部分807A係以無電電鍍製程形成，上述之製程方式有利於形成具有高厚度均勻性的接合連接件。
圖9A係繪示根據一些實施例所述之第二接合結構901的剖面圖，其中第二接合結構901包含第一接合結構800，其係接合至如圖2A所示之互補式金氧半導體晶圓200。在一些實施例中，可使用與圖6A所述之第二接合結構601相似的形成方法，以形成第二接合結構901，此處不另贅述。
圖9B係繪示根據一些實施例所述之第二接合結構901的剖面圖，其中第二接合結構903包含第一接合結構800，其係接合至如圖2C所示之互補式金氧半導體晶圓 200。在所示的實施例中，形成凸塊底層金屬化層213於第一開口209和第二開口211中後(如圖2B和圖2C所示)，互補式金氧半導體晶圓200係接合至第一接合結構800。在一些實施例中，可使用與如圖6B所述之第二接合結構603相似的方法，以形成第二接合結構903，此處不另贅述。
圖10係繪示根據一些實施例所述之形成接合結構(如第二接合結構901或第二接合結構903)的方法1000。方法1000由步驟1001開始，其中第一晶圓(如微機電系統晶圓101)係接合至第二晶圓(如蓋晶圓103)，以形成第一接合結構(如第一接合結構800)，如前述之圖8A所說明。在步驟1003中，圖案化第一晶圓暴露出的表面，以形成複數個第一突出特徵和複數個第二突出特徵(如第一突出特徵501和第二突出特徵503)，如前述之圖8B所說明。在步驟1005中，形成導電層(如種晶層801)於第一晶圓圖案化的表面上，如前述之圖8C所說明。在步驟1007中，圖案化導電層，以形成複數個第一接合連接件的複數個第二部分和複數個第二接合連接件的複數個第二部分(如第一接合連接件805A/805B的第二部分805B和第二接合連接件807A/807B的第二部分807B)，如前述之圖8C和圖8D所說明。在步驟1009中，複數個第一接合連接件的複數個第一部分(如第一接合連接件805A/805B的第一部分805A)係分別形成於上述第一接合連接件的第二部分上，且複數個第二接合連接件的複數個第一部分(如第二接合連接件807A/807B的第一部分807A)係分別形成於上述的第二接 合連接件的第二部分上，如前述之圖8E所說明。在步驟1011中，利用第一接合連接件和第二接合連接件，以將第一接合結構接合至第三晶圓(如互補式金氧半導體晶圓200)，藉以形成第二接合結構(如第二接合結構901或第二接合結構903)，如前述之圖9A和圖9B所說明。
本發明的實施例提供各種優點，如接合連接件的高黏度(Tackiness)均勻性以及成本之降低。在一些實施例中，形成接合連接件的過程係避免圖案化晶圓，其係利於以較低的成本，形成具有高厚度均勻性的接合連接件。在一些實施例中，二罩幕法可分開接合環的製程階段和接合墊的製程階段，其有利於形成具有高厚度均勻性的接合連接件。在一些實施例中，如濺鍍、無電電鍍之沉積製程係於形成接合連接件的步驟中使用，其有利於形成具有高厚度均勻性的接合連接件。
根據一實施例，本發明之方法包括形成導電層於接合結構的第一表面上，接合結構包含接合至第二基材的第一基材，接合結構的第一表面為第一基材暴露出的表面。圖案化罩幕係形成於導電層上，圖案化罩幕包含複數個第一開口和複數個第二開口，複數個第一開口和複數個第二開口暴露出導電層的複數個部分。複數個第一接合連接件的複數個第一部分係形成於複數個第一開口中，且複數個第二接合連接件的複數個第一部分係形成於複數個第二開口中。圖案化導電層以形成複數個第一接合連接件的複數個第二部分和複數個第二接合連接件的複數個第二部分，其中第一接合 連接件的第一部分和第二接合連接件的第一部分係做為罩幕。利用複數個第一接合連接件和複數個第二接合連接件，將接合結構接合至第三基材，其中第一接合連接件和第二接合連接件係延伸貫穿複數個第三開口，並接觸複數個第三開口所暴露出的導電特徵，且第三開口係形成於第三基材的正面。
根據另一實施例，本發明之方法包括形成複數個第一突出特徵和複數個第二突出特徵於第一基材的背面。第一導電材料係形成於第一突出特徵和第二突出特徵上。複數個第一接合連接件的複數個第一部分係形成於第一突出特徵上。複數個第二接合連接件的複數個第一部分係形成於第二突出特徵上。圖案化第一導電材料，以形成複數個第一接合連接件的複數個第二部分和複數個第二接合連接件的複數個第二部分，其中第一接合連接件的第一部分和第二接合連接件的第一部分係做為罩幕。利用複數個第一接合連接件和複數個第二接合連接件，以將第二基材接合至第一基材。
根據又一實施例，本發明之方法包括圖案化第一基材的背表面，以形成複數個第一突出特徵和複數個第二突出特徵。複數個第一接合連接件的複數個第二部分係形成於第一突出特徵上，且複數個第二接合連接件的複數個第二部分係形成於第二突出特徵上。複數個第一接合連接件的複數個第一部分係形成於複數個第一接合連接件的複數個第二部分上，且複數個第二接合連接件的複數個第一部分係形 成於複數個第二接合連接件的複數個第一部分上。利用複數個第一接合連接件和複數個第二接合連接件，以接合第二基材與第一基材。
前述內容概述多個實施例之特徵，以使於本技術領域具有通常知識者可進一步了解本發明之態樣。本技術領域具通常知識者應可輕易利用本發明作為基礎，設計或潤飾其他製程及結構，藉以執行此處所描述之實施例的相同的目的及/或達到相同的優點。本技術領域具有通常知識者亦應可了解，上述相等的結構並未脫離本發明之精神和範圍，且在不脫離本發明之精神及範圍下，其可經潤飾、取代或替換。
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  1. 一種半導體晶圓之接合結構的形成方法，包含：形成一導電層於一接合結構的一第一表面上，其中該接合結構包含接合至一第二基材之一第一基材，該接合結構之該第一表面為該第一基材之一被暴露出的表面；形成一圖案化罩幕於該導電層上，其中該圖案化罩幕包含複數個第一開口以及複數個第二開口，該些第一開口和該些第二開口暴露出該導電層之複數個部分；形成複數個第一接合連接件之複數個第一部份以及複數個第二接合連接件之複數個第一部份，其中該些第一接合連接件之該些第一部份係設於該些第一開口中，該些第二接合連接件之該些第一部分係設置於該些第二開口中；圖案化該導電層，以形成該些第一接合連接件之複數個第二部分以及該些第二接合連接件之複數個第二部分，其中該些第一接合連接件之該些第一部分以及該些第二接合連接件之該些第一部分係做為一罩幕；以及利用該些第一接合連接件和該些第二接合連接件，來接合該接合結構至一第三基材，其中正面該些第一接合連接件以及該些第二接合連接件延伸貫穿複數個第三開口，並接觸由該些第三開口暴露出的導電元件，該些第三開口係形成於該第三基材之一正面。
  2. 如申請專利範圍第1項所述之半導體晶圓之接合結構的形成方法，其中該第一基材為一微機電系統 (MEMS)晶圓，該第二基材為一蓋晶圓(Cap Wafer)，該第三基材為一互補式金氧半導體(CMOS)晶圓。
  3. 如申請專利範圍第1項所述之半導體晶圓之接合結構的形成方法，其中該些第一接合連接件形成一接合環，該些第二接合連接件係被該接合環所包圍，該些第一接合連接件之一厚度係與該些第二接合連接件之一厚度實質相同。
  4. 如申請專利範圍第1項所述之半導體晶圓之接合結構的形成方法，其中在該接合該接合結構至該第三基材的步驟後，該些第一接合連接件之該些第一部分係分別沿該些第一接合連接件之該些第二部分之側壁延伸。
  5. 一種半導體晶圓之接合結構的形成方法，包含：形成複數個第一突出特徵以及複數個第二突出特徵於一第一基材之一背面上；形成一第一導電材料於該些第一突出特徵以及該些第二突出特徵上；形成複數個第一接合連接件之複數個第一部分於該些第一突出特徵上；形成複數個第二接合連接件之複數個第一部分於該些第二突出特徵上；圖案化該第一導電材料，以形成該些第一接合連接件 之複數個第二部分和該些第二接合連接件之複數個第二部分，其中該些第一接合連接件之該些第一部分與該些第二接合連接件之該些第一部分係做為一罩幕；以及利用該些第一接合連接件以及該些第二接合連接件，以接合一第二基材至該第一基材。
  6. 如申請專利範圍第5項所述之半導體晶圓之接合結構的形成方法，其中該形成該些第一接合連接件之該些第一部分的步驟包含：形成一第一圖案化罩幕於該第一導電材料上，其中該第一圖案化罩幕具有複數個第一開口，該些第一開口暴露出設置於該些第一突出特徵上的該第一導電材料之複數個部分；形成一第二導電材料於該些第一開口中，其中該第二導電材料與該第一導電材料不同；以及移除該第一圖案化罩幕，且其中該形成該些第二接合連接件之該些第一部分的步驟包含：形成一第二圖案化罩幕於該第一導電材料上，其中該第二圖案化罩幕具有複數個第二開口，該些第二開口暴露出設置於該些第二突出特徵上的該第一導電材料之複數個部分；形成該第二導電材料於該些第二開口中；以及移除該第二圖案化罩幕。
  7. 如申請專利範圍第5項所述之半導體晶圓之接合結構的形成方法，其中該些第一接合連接件形成一接合環，該些第二接合連接件係被該接合環所包圍。
  8. 如申請專利範圍第5項所述之半導體晶圓之接合結構的形成方法，更包含在該接合該第二基材至該第一基材的步驟前，形成複數個第三開口和複數個第四開口於該第二基材之一前表面上，其中該些第三開口暴露出複數個第一導電特徵，該些第四開口暴露出複數個第二導電特徵，該些第一接合連接件延伸入該些第三開口中並接觸該些第一導電特徵，該些第二接合連接件延伸入該些第四開口中並接觸該些第二導電特徵。
  9. 一種半導體晶圓之接合結構的形成方法，包含：圖案化一第一基材之一背表面，以形成複數個第一突出特徵和複數個第二突出特徵；形成複數個第一接合連接件之複數個第二部分於該些第一突出特徵上，並形成複數個第二接合連接件之複數個第二部分於該些第二突出特徵上；形成該些第一接合連接件的複數個第一部分於該些第一接合連接件之該些第二部分上，並形成該些第二接合連接件的複數個第一部分於該些第二接合連接件之該些第二部分上；以及利用該些第一接合連接件和該些第二接合連接件，來 接合一第二基材至該第一基材。
  10. 如申請專利範圍第9項所述之半導體晶圓之接合結構的形成方法，其中該形成該些第一接合連接件之該些第二部分以及該些第二接合連接件之該些第二部分的步驟包含：濺鍍一第一導電材料於該些第一突出特徵以及該些第二突出特徵上；以及圖案化該第一導電材料，且其中該形成該些第一接合連接件之該些第一部分以及該些第二接合連接件之該些第一部分的步驟包含：藉由一無電電鍍法，形成一第二導電材料於該第一導電材料上，其中該第二導電材料與該第一導電材料不同，該些第一接合連接件之一厚度係與該些第二接合連接件之一厚度實質相同，該些第一接合連接件形成一接合環，該些第二接合連接件為複數個接合墊，該些接合墊係被該接合環所包圍。
TW104137571A 2014-12-26 2015-11-13 半導體晶圓之接合結構的形成方法 TWI569316B (zh)

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