TW201614531A - Method of designing layout of semiconductor device - Google Patents

Method of designing layout of semiconductor device

Info

Publication number
TW201614531A
TW201614531A TW104129580A TW104129580A TW201614531A TW 201614531 A TW201614531 A TW 201614531A TW 104129580 A TW104129580 A TW 104129580A TW 104129580 A TW104129580 A TW 104129580A TW 201614531 A TW201614531 A TW 201614531A
Authority
TW
Taiwan
Prior art keywords
width
area
standard cell
unit placement
semiconductor device
Prior art date
Application number
TW104129580A
Other languages
Chinese (zh)
Other versions
TWI672600B (en
Inventor
Kwang-Ok Jeong
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW201614531A publication Critical patent/TW201614531A/en
Application granted granted Critical
Publication of TWI672600B publication Critical patent/TWI672600B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.
TW104129580A 2014-09-18 2015-09-08 Method of designing layout of semiconductor device and computer-based system for designing a layout of semiconductor device TWI672600B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201462052076P 2014-09-18 2014-09-18
US62/052,076 2014-09-18
??10-2015-0033280 2015-03-10
KR1020150033280A KR102255450B1 (en) 2014-09-18 2015-03-10 Layout design method for semiconductor device

Publications (2)

Publication Number Publication Date
TW201614531A true TW201614531A (en) 2016-04-16
TWI672600B TWI672600B (en) 2019-09-21

Family

ID=55661982

Family Applications (3)

Application Number Title Priority Date Filing Date
TW104129250A TWI679435B (en) 2014-09-18 2015-09-04 Method for forming semiconductor device for test and method for testing target transistors on front end of line-end-semiconductor device
TW104129443A TWI677965B (en) 2014-09-18 2015-09-07 Semiconductor devices and methods for manufacturing the same
TW104129580A TWI672600B (en) 2014-09-18 2015-09-08 Method of designing layout of semiconductor device and computer-based system for designing a layout of semiconductor device

Family Applications Before (2)

Application Number Title Priority Date Filing Date
TW104129250A TWI679435B (en) 2014-09-18 2015-09-04 Method for forming semiconductor device for test and method for testing target transistors on front end of line-end-semiconductor device
TW104129443A TWI677965B (en) 2014-09-18 2015-09-07 Semiconductor devices and methods for manufacturing the same

Country Status (2)

Country Link
KR (5) KR102423878B1 (en)
TW (3) TWI679435B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10796064B2 (en) 2018-08-14 2020-10-06 International Business Machines Corporation Autonomous placement to satisfy self-aligned double patterning constraints
TWI763667B (en) * 2016-10-05 2022-05-11 南韓商三星電子股份有限公司 Integrated circuit including a modified cell and a method of designing the same

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KR102633141B1 (en) * 2016-12-07 2024-02-02 삼성전자주식회사 Integrated circuit devices
KR102358481B1 (en) 2017-06-08 2022-02-04 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US10741539B2 (en) 2017-08-30 2020-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Standard cells and variations thereof within a standard cell library
DE102017127276A1 (en) 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. STANDARD CELLS AND ADAPTATIONS FROM THEREOF WITHIN A STANDARD CELL LIBRARY
KR102499036B1 (en) * 2017-09-22 2023-02-13 삼성전자주식회사 Critical dimension measurement system and method of measuring critical demesion
KR102419646B1 (en) * 2017-12-22 2022-07-11 삼성전자주식회사 Integrated circuit having cross couple construct and semiconductor including the same

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JP3233347B2 (en) * 1997-11-17 2001-11-26 日本電気株式会社 Integrated circuit test apparatus and integrated circuit test method
US6423558B1 (en) * 2000-02-25 2002-07-23 Advantest Corporation Method for fabricating integrated circuit (IC) dies with multi-layered interconnect structures
US6567967B2 (en) * 2000-09-06 2003-05-20 Monterey Design Systems, Inc. Method for designing large standard-cell base integrated circuits
US6678868B2 (en) * 2002-04-17 2004-01-13 Sun Microsystems, Inc. Using Boolean expressions to represent shapes within a layout of an integrated circuit
JP2007043049A (en) * 2004-12-20 2007-02-15 Matsushita Electric Ind Co Ltd Cell, standard cell, placement method using standard cell, standard cell library, and semiconductor integrated circuit
US7337420B2 (en) * 2005-07-29 2008-02-26 International Business Machines Corporation Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
US7489151B2 (en) * 2005-10-03 2009-02-10 Pdf Solutions, Inc. Layout for DUT arrays used in semiconductor wafer testing
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI763667B (en) * 2016-10-05 2022-05-11 南韓商三星電子股份有限公司 Integrated circuit including a modified cell and a method of designing the same
US10796064B2 (en) 2018-08-14 2020-10-06 International Business Machines Corporation Autonomous placement to satisfy self-aligned double patterning constraints

Also Published As

Publication number Publication date
TW201612535A (en) 2016-04-01
TW201618279A (en) 2016-05-16
KR102255450B1 (en) 2021-05-25
TWI677965B (en) 2019-11-21
TWI672600B (en) 2019-09-21
KR20160034161A (en) 2016-03-29
KR20160034167A (en) 2016-03-29
KR20160034169A (en) 2016-03-29
KR102133377B1 (en) 2020-07-15
KR20160034163A (en) 2016-03-29
KR20160034164A (en) 2016-03-29
KR102335243B1 (en) 2021-12-06
TWI679435B (en) 2019-12-11
KR102423878B1 (en) 2022-07-22

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