TW201611293A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a metal-oxide-semiconductor field effect transistor (MOSFET), in which several silicon controlled rectifier (SCR) equivalent circuits are parasitically formed in the MOSFET, and the MOSFET further includes a drain region. The drain region includes P-type heavy doping regions which are different from each other, in which the P-type heavy doping regions are respectively configured as anodes of the SCR equivalent circuits.

Description

Semiconductor component

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor component, and more particularly to a semiconductor component having a controlled rectifier equivalent circuit.

In general, various electronic devices are provided with an Electrostatic Discharge (ESD) protection mechanism to avoid the moment when the electronic device touches the electronic device when the human body is exposed to excessive static electricity. The current causes damage, or the electronic device is prevented from being affected by static electricity from the environment or the transport tool, resulting in a malfunction.

However, the ESD protection mechanism in general electronic devices usually requires a large layout area to conduct a large ESD current; in other words, the ESD current that can be turned on is generally insufficient in a case where the layout area is constant. The large, and the ESD current that is turned on cannot be evenly dispersed, so that the ESD protection mechanism cannot effectively protect the electronic device.

Embodiments of the present invention relate to a semiconductor device for improving the performance of a semiconductor device.

One aspect of the present invention relates to a semiconductor device including a MOS field effect transistor, wherein the MOS field effect transistor is parasitic with a plurality of 矽-controlled rectifier equivalent circuits, and the MOS field effect The transistor comprises a drain region, an N-well region, and a plurality of N-type heavily doped regions. The drain region includes a plurality of distinct P-type heavily doped regions, wherein each of the P-type heavily doped regions serves as an anode of a pseudo-controlled rectifier equivalent circuit. The aforementioned P-type heavily doped region is formed in the N-type well region. The aforementioned N-type heavily doped region is located in the N-type well region and is alternately disposed laterally with the P-type heavily doped region.

Another embodiment of the present invention is directed to a semiconductor device comprising a MOS field effect transistor. The MOS field effect transistor is parasitic with a plurality of equivalent rectifier rectifier circuits and includes a drain region and a source region. The drain region includes a plurality of distinct P-type heavily doped regions, wherein the P-type heavily doped regions are successively and concentrically surrounded by each other, and the P-type heavily doped regions are each equivalent as the aforementioned controlled rectifier The anode of the circuit. The source area surrounds the bungee area.

A second aspect of the present invention is directed to a semiconductor device including a plurality of distinct patterned semiconductor regions and a plurality of controlled rectifier equivalent circuits. The patterned semiconductor region includes a plurality of N-type heavily doped regions and a plurality of P-type heavily doped regions alternately arranged laterally. The equivalent circuit of the controlled rectifier is parasitic in the semiconductor component and includes a plurality of equivalent PNP type transistors and an equivalent NPN type transistor, wherein the foregoing equivalent The PNP-type electro-crystalline system is formed corresponding to the different patterned semiconductor regions, and the equivalent PNP-type transistors are electrically connected in parallel and electrically connected to an equivalent NPN-type transistor. The aforementioned P-type heavily doped regions each serve as an electrode region of the aforementioned equivalent PNP-type transistor.

This summary is intended to provide a simplified summary of the disclosure This Summary is not an extensive overview of the disclosure, and is intended to be illustrative of the embodiments of the invention.

100, 700‧‧‧ semiconductor components

105, 105a, 105b, 600a, 705‧‧‧ MOS field effect transistor

110, 110a, 604a, 604b, 604c, 604d, 604e, 604f, 710‧‧ ‧ bungee area

112, 114, 712, 714‧‧‧P type heavily doped area

120, 602a, 602b, 602c, 602d, 602e, 602f‧‧‧ source area

210, 230‧‧‧N type well area

222, 224‧‧‧N type heavily doped area

240‧‧‧P type well area

250, 410‧‧‧N type buffer

260‧‧‧N type heavily doped area

302, 304‧‧‧ equivalent PNP type transistor

306‧‧‧ equivalent NPN type transistor

420‧‧‧N type drift zone

603a, 603c, 603d, 603e, 603f‧‧ ‧ gate area

606a, 606b‧‧‧ start

608‧‧‧Contact window

1 is a schematic view showing a layout of a semiconductor device according to a first embodiment of the present invention; and FIG. 2A is a cross-sectional view showing a tangent of AA in the semiconductor device shown in FIG. 1 according to an embodiment of the present invention. 1 is omitted to present the MOS field effect transistor cross-sectional structure; FIG. 2B is a diagram of FIG. 1 FIG. 3 is a schematic diagram showing an equivalent circuit of a parasitic voltage controlled rectifier in a semiconductor device as shown in FIG. 2A according to an embodiment of the present invention; FIG. 4 is a view showing another embodiment of the present invention in accordance with another embodiment of the present invention; FIG. 5 is a cross-sectional view showing a tangent of AA in the semiconductor device shown in FIG. 1; FIG. 5 is a half as shown in FIG. 4 according to an embodiment of the invention. FIG. 6A is a schematic diagram of an equivalent circuit of a parasitic controlled rectifier in a conductor element; FIG. 6A is a single-circle spiral-shaped gold-oxygen half-field effect transistor with a drop-shaped opening at the beginning of the drain according to an embodiment of the invention. FIG. 6B is a top view of a multi-turn elliptical spiral gold oxide half field effect transistor with a drop-shaped beginning portion according to an embodiment of the present invention; FIG. 6C is a schematic view of the present invention; FIG. 6D is a top view of a W-type MOS field effect transistor according to an embodiment of the invention; FIG. 6E is a schematic view of a U-type MOSFET; The figure is a top view of a pair of ferrule MOSFETs according to an embodiment of the invention; FIG. 6F is a MOSFET type field effect according to an embodiment of the invention. A top view of a transistor; and FIG. 7 is a schematic view of a layout of a semiconductor device in accordance with a second embodiment of the present invention.

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of the structure operation is not intended to limit the order of execution, any component recombination The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not based on the original size. Figure. For ease of understanding, the same elements in the following description will be denoted by the same reference numerals.

The terms used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, the content disclosed herein, and the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

As used herein, "about", "about" or "substantially" generally means that the error or range of the index value is within 20%, preferably within 10%, and more preferably It is within 5 percent. In the text, unless otherwise stated, the numerical values referred to are regarded as approximations, such as an error or range indicated by "about", "about" or "substantial", or other approximations.

The terms "first", "second", etc., as used herein, are not intended to refer to the order or the order, and are not intended to limit the invention, only to distinguish the elements described in the same technical terms. Or just operate.

Secondly, the terms "including", "including", "having", "containing", and the like, as used herein, are all open terms, meaning, but not limited to.

In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components operate or act upon each other.

1 is a schematic view showing a layout of a semiconductor device according to a first embodiment of the present invention, which omits the structure of a field oxide layer (FOX) for clarity of the drawing. The semiconductor device 100 shown in FIG. 1 may include an Electrostatic Discharge (ESD) protection element or as an ESD protection element, thereby providing an ESD protection mechanism. As shown in FIG. 1, the semiconductor device 100 includes a MOS field effect transistor 105 (the MOS field effect transistor 105 is merely illustrative here, and the structure of the MOS field effect transistor 105 is specifically as described. 2A shows that the CMOS field effect transistor 105 is parasitic with a Silicon Controlled Rectifier (SCR) equivalent circuit (as shown in FIG. 3), and the MOS field effect transistor 105 includes 汲Polar zone 110. In addition, the drain region 110 includes a plurality of distinct P-type heavily doped regions (eg, P-type heavily doped regions 112 and 114), wherein the aforementioned different P-type heavily doped regions (eg, P-type heavily doped) The miscellaneous regions 112 and 114) each serve as an anode for the equivalent circuit of the controlled rectifier.

In an embodiment, the P-type heavily doped region 114 may surround the P-type heavily doped region 112. In another embodiment, in the case where the drain region 110 includes three or more distinct P-type heavily doped regions, one of the different P-type heavily doped regions may surround the different P The other of the heavily doped regions.

Second, in some embodiments, the distinct P-type heavily doped regions are not directly connected to each other. In other embodiments, the distinct P-type heavily doped regions can be electrically connected to each other through a contact. For specific description, reference may be made to the following description of the embodiment shown in FIG. 2A.

The above-mentioned "different P-type heavily doped region" may refer to a plurality of P-type heavy The doped regions are configured separately from each other or independently in the semiconductor structure.

Although FIG. 1 only shows two P-type heavily doped regions 112 and 114, it is for convenience of description only, and is not intended to limit the present invention; in other words, those skilled in the art can select two according to actual needs. Or more than two P-type heavily doped regions are configured as described above. In other words, the layout of the semiconductor device shown in FIG. 1 may include two or more P-type heavily doped regions, which are not limited to those shown in FIG.

In another embodiment of the invention, the MOS field effect transistor 105 includes a drain region 110 and a source region 120, wherein the source region 120 surrounds the drain region 110. The drain region 110 includes a plurality of distinct P-type heavily doped regions (eg, P-type heavily doped regions 112 and 114), wherein the P-type heavily doped regions (eg, P-type heavily doped regions 112 and 114) The cells may be surrounded by one another in succession and concentricity, for example, the P-type heavily doped region 114 concentrically surrounds the P-type heavily doped region 112.

2A is a cross-sectional view showing a tangent of A-A in the semiconductor device shown in FIG. 1 according to an embodiment of the invention. For the sake of clarity and convenience of explanation, the following description refers to both FIG. 1 and FIG. 2A. As shown in FIGS. 1 and 2A, the source region 120 (S), the gate region (G), and the drain region 110 (D) of the MOS field effect transistor 105 are laterally formed along the AA tangent line. The aforementioned P-type heavily doped regions (eg, P-type heavily doped regions 112 and 114) are laterally formed in the drain region 110 (D).

Next, in an embodiment, as shown in FIG. 1 and FIG. 2A, the MOS field effect transistor 105 may further include an N-type well region 210 (eg, N-type high-pressure deep well region DNW) and a plurality of N-types. Heavyly doped area (eg N type) The heavily doped regions 222 and 224), wherein the aforementioned P-type heavily doped regions (eg, P-type heavily doped regions 112 and 114) may be formed in the N-type well region 210, while the N-type heavily doped regions 222 and 224 It may be located within the N-type well region 210 and may be alternately disposed laterally with the P-type heavily doped regions 112 and 114.

Furthermore, as shown in FIG. 1 and FIG. 2A, a top layer N-doped region N-Top and a linear top-layer P-doped region Linear P-Top may be included, wherein the top layer N-doped region N-Top and linear A top P-type doped region, Linear P-Top, is formed in the N-type well region 210.

As shown in FIG. 2A, in the present embodiment, the P-type heavily doped regions 112 and 114 are disposed separately from each other or independently, and are not directly connected. In other embodiments, the drain region (D) 110 may include a drain contact region (not shown), wherein the drain contact region is formed in the aforementioned P-type heavily doped region (eg, the P-type heavily doped region 112 and 114) and an N-type heavily doped region (eg, N-type heavily doped regions 222 and 224) above the metal junction as a drain. As such, the P-type heavily doped regions 112 and 114 can be electrically connected to each other through a contact.

Furthermore, in the overall layout of the semiconductor device shown in FIG. 1, the P-type heavily doped region 112 may surround the N-type heavily doped region 222, and the N-type heavily doped region 224 may surround the P-type heavily doped region. The impurity region 112, the P-type heavily doped region 114 may surround the N-type heavily doped region 224, and the source region 120 is formed on the outer ring surrounding the P-type heavily doped region 114.

Similarly, it should be noted that although FIG. 2A only shows the two N-type heavily doped regions 222 and 224, it is only for the convenience of the P-type heavily doped regions 112 and 114, and is not intended to limit the present. Inventive; in other words, those skilled in the art can match the number of P-type heavily doped regions according to actual needs. A corresponding number of N-type heavily doped regions are selected for the above configuration.

On the other hand, the source region 120 of the MOS field effect transistor 105 may further include another N-type well region 230 (eg, high-pressure N-type well region HVNW), P-type well region 240, N-type buffer region 250, and An N-type heavily doped region 260, wherein an N-type heavily doped region 260 is formed in the N-type buffer region 250 for use as a source of the MOS field effect transistor 105, and an N-type buffer region 250 is formed in the P-type well Within zone 240, a P-well zone 240 is formed in the N-well zone 230, and N-well zones 210 and 230 are collectively formed in an N-type epitaxial layer N-EPI. Although the P-well region 240 herein is labeled P-Well in the drawings, in other embodiments, it can also be applied under the structure of the P-Body.

2B is a schematic view showing the structure of a semiconductor device as shown in FIG. 1 according to another embodiment of the present invention. Compared with the MOS field effect transistor 105 of FIG. 2A, in the MOS field effect transistor 105a shown in FIG. 2B, the top layer N-type doping region N-Top and the linear top layer P-type doping region Linear P-Top can be omitted.

FIG. 3 is a schematic diagram showing an equivalent circuit of a parallel controlled rectifier in a semiconductor device as shown in FIG. 2A according to an embodiment of the invention. As can be seen from the embodiment shown in FIG. 3, the P-type heavily doped region 112, the N-type well region 210 together with the N-type epitaxial layer N-EPI and N-type well region 230, the P-type well region 240, and the N-type buffer zone are known. 250, together with four parts such as N-type heavily doped region 260, can form a P/N/P/N semiconductor interface, and a SCR equivalent circuit with a P/N/P/N semiconductor interface can be The formation, wherein the P-type heavily doped region 112, the N-type well region 210 together with the N-type epitaxial layer N-EPI and the N-type well region 230, the P-type well region 240, and the like form an equivalent PNP-type transistor 302 , The N-type well region 210 together with the N-type epitaxial layer N-EPI and the N-type well region 230, the P-type well region 240, the N-type buffer region 250, and the N-type heavily doped region 260 form an equivalent NPN type electricity. The crystal 306, and the equivalent PNP type transistor 302 and the equivalent NPN type transistor 306 together form a controlled rectifier equivalent circuit.

Similarly, the P-type heavily doped region 114, the N-type well region 210 together with the N-type epitaxial layer N-EPI and N-type well region 230, the P-type well region 240, and the N-type buffer region 250 together with the N-type heavily doped region Four parts of 260 can also form another P/N/P/N semiconductor interface, and a similar control rectifier (SCR) equivalent circuit can also be formed, wherein P-type heavily doped region 114, N-type well region 210 together with the N-type epitaxial layer N-EPI and the N-type well region 230, the P-type well region 240 and the like form an equivalent PNP-type transistor 304, and the N-type well region 210 together with the N-type epitaxial layer N-EPI and The N-type well region 230, the P-type well region 240, and the N-type buffer region 250 together with the N-type heavily doped region 260 form an equivalent NPN-type transistor 306, and the equivalent PNP-type transistor 304 and the equivalent NPN. The type of transistors 306 together form a controlled rectifier equivalent circuit, and the equivalent PNP type transistor 304 and the equivalent PNP type transistor 302 are electrically connected in parallel with each other.

Secondly, the aforementioned rectifier rectifier equivalent circuit is parasitic between the drain region 110 (D) and the source region 120 (S), and the P-type heavily doped regions 112 and 114 can serve as the anode of the equivalent rectifier circuit of the rectifier. The N-type heavily doped region 260 can serve as a cathode for the equivalent circuit of the controlled rectifier. In operation, when an electrostatic discharge (ESD) occurs, an equivalent circuit of the pseudo-controlled rectifier formed by the equivalent PNP-type transistor 302 and the equivalent PNP-type transistor 304 and the equivalent NPN-type transistor 306 can be formed. Multiple current conduction The path to simultaneously turn on the ESD current to perform ESD protection.

As can be seen from the above, in the case where the semiconductor element 100 (or the MOS field effect transistor 105 or the MOS field effect transistor 105a) is an ultrahigh voltage element, the layout area is sufficiently large, so The P-type heavily doped regions with different turns are arranged to surround each other. In this way, a plurality of different ESD current conduction paths can be formed in the drain region 110 (D) in a case where the layout area is constant. For example, when a human body or an object is positively touched to a contact such as a drain region, the current corresponding to the ESD positive current can pass through a plurality of P-type heavily doped regions disposed in the drain region ( It can be used as an anode of the rectifier rectifier equivalent circuit to flow to a source region. In this case, the component size does not need to be increased, the component can still maintain the small volume advantage, and at the same time, the ESD current conducted by the component can be uniformly dispersed (for example, the ESD current can be conducted through multiple paths), so that the component is turned on. The ability of ESD to increase current is increased, enabling semiconductor components to perform protective actions more effectively.

4 is a cross-sectional view showing a line A-A tangent in the semiconductor device shown in FIG. 1 according to another embodiment of the present invention. As shown in FIG. 4, the drain region 110a(D) of the MOS field effect transistor 105b may further include an N-type buffer region 410 and an N-type drift region, as compared with the embodiment shown in FIG. 2B. 420, wherein the aforementioned P-type heavily doped regions (eg, P-type heavily doped regions 112 and 114) and the aforementioned N-type heavily doped regions (eg, N-type heavily doped regions 222 and 224) are formed in an N-type buffer. Within the region 410, an N-type buffer region 410 is formed in the N-type drift region 420, and an N-type drift region 420 is formed in the N-type well region 210.

FIG. 5 is a schematic diagram showing an equivalent circuit of a parallel controlled rectifier in a semiconductor device as shown in FIG. 4 according to an embodiment of the invention. As can be seen from the embodiment shown in FIG. 5, the P-type heavily doped region 112 serves as a P-type semiconductor interface, and the N-type buffer region 410 together with the N-type drift region 420, the N-type well region 210, and the N-type epitaxial layer N-EPI The N-type well region 230 serves as an N-type semiconductor interface, the P-type well region 240 serves as a P-type semiconductor interface, and the N-type buffer region 250 together with the N-type heavily doped region 260 serves as an N-type semiconductor interface, thereby forming a P/N. The /P/N semiconductor interface can be formed by a controlled rectifier (SCR) equivalent circuit.

Similarly, the P-type heavily doped region 114 acts as a P-type semiconductor interface, and the N-type buffer region 410 together with the N-type drift region 420, the N-type well region 210, the N-type epitaxial layer N-EPI, and the N-type well region 230 serve as N The semiconductor interface, the P-type well region 240 serves as a P-type semiconductor interface, and the N-type buffer region 250 together with the N-type heavily doped region 260 serves as an N-type semiconductor interface, so that a P/N/P/N semiconductor interface can be formed. A voltage controlled rectifier (SCR) equivalent circuit can be formed therefrom.

In some embodiments, the aforementioned drain region may be W-shaped, U-shaped, single-turn elliptical spiral, multi-turn elliptical spiral or other shape. The following is an example of the embodiment shown in FIGS. 6A to 6F, but the embodiment of the present invention is not limited thereto.

FIG. 6A is a top view showing a single-turn elliptical spiral gold-oxygen half-field effect transistor with a drop-shaped beginning portion in accordance with an embodiment of the present invention. The MOS field effect transistor 600a includes a source region 602a, a gate region 603a, and a drain region 604a. Metal oxide field effect transistor 600a In terms of structure, the drain region 604a has an elliptical spiral shape, and the initial portion 606a of the drain region 604a has a drop shape, and the contact window 608 and the initial portion 606a of the elliptical spiral bungee region 604a are electrically connection. Next, the P-type heavily doped regions 112 and 114 and the N-type heavily doped regions 222 and 224 shown in FIG. 1 are identical or similar to an elliptical spiral shape, formed in the drain region 604a, and Surrounded by each other (similar to the configuration shown in Figure 1).

FIG. 6B is a schematic top view of a multi-turn elliptical spiral gold oxide half field effect transistor with a drop-shaped beginning portion according to an embodiment of the invention. Similarly, the source region 602b and the drain region 604b are as shown in FIG. 6B. In the present embodiment, the initial portion 606b of the drain region 604b is still in the shape of a drop, and the drain region 604b is a multi-turn elliptical spiral. Next, the P-type heavily doped regions 112 and 114 and the N-type heavily doped regions 222 and 224 shown in FIG. 1 are the same or similar to a multi-turn elliptical spiral shape, and are formed in the drain region 604b. And surround each other (similar to the configuration shown in Figure 1).

FIG. 6C is a top view of a U-shaped MOS field effect transistor according to an embodiment of the invention. Similarly, the source region 602c, the gate region 603c, and the drain region 604c are as shown in FIG. 6C. In the present embodiment, the drain region 604c is U-shaped. Next, the P-type heavily doped regions 112 and 114 and the N-type heavily doped regions 222 and 224 shown in FIG. 1 are identical or similar to the U-type, are formed in the drain region 604c, and are successive to each other. Surround (similar to the configuration shown in Figure 1).

FIG. 6D is a top view of a W-type MOS field effect transistor according to an embodiment of the invention. Similarly, the source region 602d, the gate region 603d, and the drain region 604d are as shown in FIG. 6D. In this embodiment, The bungee region 604d can be viewed as, but not limited to, drawing a portion that is U-shaped in FIG. 6A, and overlapping the two U-shapes into a W-like shape (or E-shaped as a steering). The P-type heavily doped regions 112 and 114 and the N-type heavily doped regions 222 and 224 shown in FIG. 1 are identical or similar to the W-type, are formed in the drain region 604c, and are successively surrounded by each other ( Similar to the configuration shown in Figure 1.)

FIG. 6E is a top view of a pair of ferrule MOSFETs in accordance with an embodiment of the invention. Similarly, the source region 602e, the gate region 603e, and the drain region 604e are as shown in Fig. 6E. In the present embodiment, the drain region 604e can be regarded as, but not limited to, drawing a U-shaped portion in FIG. 6A, and configuring the two U-types in pairs. The P-type heavily doped regions 112 and 114 and the N-type heavily doped regions 222 and 224 shown in Fig. 1 are formed in the drain region 604e and are successively surrounded by each other (similar to the configuration shown in Fig. 1).

FIG. 6F is a top view of a finger-type MOS field effect transistor according to an embodiment of the invention. Similarly, the source region 602f, the gate region 603f, and the drain region 604f are as shown in FIG. 6F. In the present embodiment, the drain region 604f can be considered as, but not limited to, drawing a portion that is U-shaped in FIG. 6A. The P-type heavily doped regions 112 and 114 and the N-type heavily doped regions 222 and 224 shown in Fig. 1 are formed in the drain region 604f and are successively surrounded by each other (similar to the configuration shown in Fig. 1).

On the other hand, in practice, the P-type heavily doped regions may be mutually different annular patterned semiconductor regions (as in the embodiment shown in FIG. 1), elliptical patterned semiconductor regions, fingers (finger- Type) patterned semiconductor region, A pair of patterned semiconductor regions or other shaped patterned semiconductor regions are formed in a manner similar to the embodiment illustrated in Figure 1 without departing from the spirit and scope of the present invention. In other embodiments, if viewed from the above view, a plurality of P-type heavily doped regions may be formed in the drain region 110, and the shape of the P-type heavily doped region projected onto the surface of the substrate presents an island-like distribution, P-type. The island-like distribution of the heavily doped regions may be regular or irregularly distributed, and each of the P-type heavily doped regions may be in the form of a square, a triangle or other shape. The P-type heavily doped region may be formed in the N-type doped region in the drain region 110, and the N-type doped region may be, for example, the N-type well region 210 of FIG. 2A and the N-type buffer region 410 of FIG. . Each P-type heavily doped region can be used as an anode of a parasitic controlled rectifier equivalent circuit in the semiconductor device, thereby forming a plurality of electrically parallel controlled rectifier equivalent circuits.

FIG. 7 is a schematic view showing a layout of a semiconductor device according to a second embodiment of the present invention (only the portions of the field oxide layer (FOX) and the drain region are shown for clarity of illustration). As shown in FIG. 7, the semiconductor device 700 includes a MOS field effect transistor 705 (the transistor 705 is merely illustrative here), and the MOSFET is parasitic with a sigma-controlled rectifier (SCR) equivalent. The circuit, and the MOS field effect transistor 705 includes a drain region 710. In addition, the drain region 710 includes a plurality of distinct elliptical patterned P-type heavily doped regions (eg, P-type heavily doped regions 712 and 714), wherein the aforementioned distinct P-type heavily doped regions (eg, The P-type heavily doped regions 712 and 714) may each serve as an anode of the equivalent rectifier circuit, and the aforementioned P-type heavily doped regions (eg, P-type heavily doped regions 712 and 714) may be successive and identical. Centered around each other (for example: P-type heavily doped region 712 concentric ring) A P-type heavily doped region 714) is wound, thereby forming a plurality of turns of the P-type heavily doped region.

The cross-sectional structure of the MOS field effect transistor 705 of the present embodiment and the operation and schematic diagrams of the corresponding modified embodiments are similar to those shown in the above FIGS. 2 to 5, and thus will not be described again.

Secondly, in the case where the aforementioned different P-type heavily doped regions are finger-type patterned semiconductor regions or other shaped patterned semiconductor regions, the different P-type heavily doped regions may also be as described above. They are successively and concentrically surrounded by each other, thereby forming a plurality of P-type heavily doped regions, and thus will not be described again.

On the other hand, as can be seen from the embodiments shown in the above 2A and 3, in another embodiment of the present invention, the semiconductor device includes a plurality of different patterned semiconductor regions (e.g., P-type heavily doped region 112). And 114) and a plurality of 矽 control rectifier equivalent circuits, wherein a plurality of 矽 control rectifier equivalent circuits are parasitic in the semiconductor component, and each of the 整流 control rectifier equivalent circuits includes an equivalent PNP type transistor (eg, equivalent PNP type) a transistor 302 or 304) and an equivalent NPN-type transistor (eg, an equivalent NPN-type transistor 306), wherein the aforementioned equivalent PNP-type transistors (eg, equivalent PNP-type transistors 302 and 304) are different The patterned semiconductor regions (eg, P-type heavily doped regions 112 and 114) are formed, and the aforementioned equivalent PNP-type transistors (eg, equivalent PNP-type transistors 302 and 304) are electrically connected in parallel and electrically connected. NPN type transistor (eg, equivalent NPN type transistor 306).

In one embodiment, the patterned semiconductor regions (eg, P-type heavily doped regions 112 and 114) are respectively distinct annular patterned semiconductor regions, elliptical patterned semiconductor regions, or finger patterned semiconductor regions. The aforementioned pattern The semiconductor regions (e.g., P-type heavily doped regions 112 and 114) are successively and concentrically surrounded by each other.

The following list shows the collapse of a MOS field effect transistor 105 having zero (structure 0), one (structure 1) or two (structure 2) P-type heavily doped regions as shown in FIG. 2A. The voltage and the collector current (Id) when 20V is applied to the gate, wherein the structure 2 has been tested by HBM (human body mode) in the case of applying positive static 8KV, and its breakdown voltage can still be maintained above 800V. The doping dose of Linear P-Top in linear top-layer P-doped region is about 1.40E+13/cm ² , and the doping dose of N-Top in top-layer N-doped region is about 2.00E+12/cm ² . The results are shown in Table 1.

The shape and the structural features of the semiconductor region in the above embodiments may be formed separately or in combination with each other. Therefore, the above embodiments are merely for the convenience of description, and a single feature is described, and all the embodiments can be selectively matched with each other according to actual needs to fabricate the semiconductor element in the present disclosure, which is not intended to limit the present invention. .

It can be seen from the embodiments of the present invention that the semiconductor component in the present disclosure can form a plurality of different ESD current conduction paths in the drain region even when the layout area is constant. The size does not need to be increased, the component can still maintain the small volume advantage, and at the same time, the ESD current conducted by the component can be evenly dispersed, so that the ability of the component to conduct a large current of ESD is increased, so that the semiconductor component can perform the protection action more effectively.

The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧Semiconductor components

105‧‧‧Gold-oxide semiconductor field effect transistor

110‧‧‧Bungee Area

112, 114‧‧‧P type heavily doped area

120‧‧‧ source area

210, 230‧‧‧N type well area

222, 224‧‧‧N type heavily doped area

240‧‧‧P type well area

250‧‧‧N type buffer

260‧‧‧N type heavily doped area

Claims (17)

A semiconductor component comprising: a MOS field effect transistor, parasitic having a plurality of 矽-controlled rectifier equivalent circuits, wherein the MOS field effect transistor comprises: a drain region comprising a plurality of different P-types a heavily doped region, wherein the P-type heavily doped regions are each an anode of the equivalent circuit of the controlled rectifier; and an N-type well region, the P-type heavily doped regions are formed in the N-type well region And a plurality of N-type heavily doped regions located in the N-type well region and alternately disposed laterally with the P-type heavily doped regions. The semiconductor device of claim 1, wherein one of the P-type heavily doped regions surrounds the other of the P-type heavily doped regions. The semiconductor device of claim 1, wherein the P-type heavily doped regions are successively and concentrically surrounded by each other. The semiconductor device of claim 1, wherein the P-type heavily doped regions are respective distinct annular patterned semiconductor regions, elliptical patterned semiconductor regions, finger patterned semiconductor regions or paired patterned semiconductors Area. The semiconductor device of claim 1, wherein the P-type heavily doped regions are not directly connected to each other. The semiconductor device according to claim 1, wherein the P-type re-doping The inter-cells are electrically connected to each other through a contact. The semiconductor device of claim 1, wherein the MOS field effect transistor further comprises: an N-type buffer region, wherein the P-type heavily doped regions and the N-type heavily doped regions are formed in the N And a N-type drift region formed in the N-type drift region, the N-type drift region being formed in the N-type well region. The semiconductor device of claim 1, wherein the shape of the P-type heavily doped regions projected onto the surface of the substrate of the MOS field effector exhibits an island-like distribution. The semiconductor device according to claim 1, wherein when the anode has a positively charged static electricity, a current corresponding to the static charge of the positive charge passes through the controlled rectifier equivalent circuits from the P-type heavily doped regions. Flow to a source area. A semiconductor device comprising: a MOS field effect transistor, parasitic a plurality of 矽-controlled rectifier equivalent circuits, and comprising: a drain region comprising a plurality of distinct P-type heavily doped regions, wherein the The P-type heavily doped regions are successively and concentrically surrounded by each other, and the P-type heavily doped regions are each an anode of the equivalent rectifier circuit of the controlled rectifier; and a source region surrounding the drain region around. The semiconductor device of claim 10, wherein the MOS field effect transistor further comprises: an N-type well region, the P-type heavily doped regions are formed in the N-type well region; and a plurality of N-type wells The heavily doped region is located in the N-type well region and is alternately disposed laterally with the P-type heavily doped regions. The semiconductor device according to claim 10, wherein the drain region is W-shaped, U-shaped, single-circle elliptical spiral or multi-turn elliptical spiral. A semiconductor device comprising: a plurality of distinct patterned semiconductor regions comprising a plurality of N-type heavily doped regions alternately arranged laterally and a plurality of P-type heavily doped regions; and a plurality of gated rectifier equivalent circuits, Parasitic in the semiconductor device, and comprising a plurality of equivalent PNP type transistors and an equivalent NPN type transistor, wherein the equivalent PNP type electromorphic systems are formed corresponding to the different patterned semiconductor regions, The equivalent PNP type transistors are electrically connected in parallel with each other and electrically connected to the equivalent NPN type transistors, wherein the P type heavily doped regions each serve as an electrode region of the equivalent PNP type transistors. The semiconductor device of claim 13, wherein the patterned semiconductor regions are respective annular patterned semiconductor regions, elliptical patterned semiconductor regions, finger patterned semiconductor regions or paired patterned semiconductor regions The patterned semiconductor regions are successively and concentrically surrounded by each other. The semiconductor device of claim 13, wherein the patterning The semiconductor regions are not directly connected to each other. The semiconductor device of claim 13, wherein the patterned semiconductor regions are electrically connected to each other through a contact. The semiconductor device of claim 13, wherein the equivalent PNP type transistor and the equivalent NPN type transistor form a plurality of current conduction paths to turn on a current corresponding to the electrostatic discharge when electrostatic discharge occurs.