TW201610681A - Method, apparatus, and computer readable medium for cache configuration - Google Patents

Abstract

In a particular embodiment, a cache is disclosed that includes a tag state array that includes a tag area addressable by a set index. The tag state array also includes a state area addressable by a state address, where the set index and the state address include at least one common bit.

Description

Method, device and non-transitory computer readable medium for cache memory configuration

The present invention is generally directed to configurable cache memory and methods of configuring the same.

Advances in technology have produced smaller and stronger computing devices. For example, there are currently a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by a user. More specifically, portable wireless telephones, such as cellular telephones and Internet Protocol (IP) telephones, can communicate voice and data packets over a wireless network. In addition, many of these wireless telephones include other types of devices incorporated therein. For example, a wireless telephone can also include a static digital camera, a digital video camera, a digital recorder, and an audio file player. Also, the wireless telephones can process executable instructions, including software applications (such as web browser applications) that can be used to access the Internet. Thus, such wireless telephones can include significant computing power.

Digital signal processors (DSPs), image processors, and other processing devices are frequently used in portable personal computing devices and operate in conjunction with one or more cache memories. The cache memory is typically a copy of the material that exists somewhere in the memory hierarchy. In some cases, the cache memory may only have a "latest" copy of the data in the system. A typical component of cache memory is data memory. The data memory is divided into cache lines, each of which is a copy of the unique (and connected) portion of the system memory. Cache memory A typical component is a channel used to associate a system memory address with a particular cache line. This channel, which is used to associate the system memory address with a particular cache line, is often referred to as a tag. Another typical component of the cache memory is the state used to indicate whether a cache line is valid, modified, possessed, and the like.

The configurable cache memory can be resized by modifying the cache line size without changing the number of tags in the cache memory. The mapping between different cache memory sizes can be performed by shifting the position of the index within the memory address used for the cache memory lookup. As an example, a pair of multiplexers may select address bits based on the size of the cache memory during a seek operation to shift the position of the index.

In a particular embodiment, an apparatus is disclosed that includes a cache memory having an array of tag states. The tag status array includes a tag area addressable by a set index. The tag status array also includes a status area addressable by a status address, wherein the set index and the status address include at least one common bit.

In another embodiment, a method is disclosed that includes receiving an address at a tag state array of a cache memory, wherein the cache memory is configurable to have a first size and a greater than the first One of the second size of a size. The method also includes identifying a first portion of the address as a set index, using the set index to locate at least one tag field of the tag array, and identifying a second portion of the address to be stored in the at least one The values in a label field are compared. The method further includes locating at least one status field of the tag status array, the at least one status field being associated with a particular tag field that matches one of the second portions; and based on the third portion of the address A comparison of at least two status bits of at least one status field identifies a cache line. The method also includes extracting the cache line, wherein the first location and the address of the first portion of the address are selected based on whether the cache memory is configured to have the first size or the second size a second location of the second portion, and wherein the first portion of the address has the first portion in the cache memory One hour has the same number of bits as when the cache has the second size.

In another embodiment, a method is disclosed that includes changing a size of a cache memory. The method also includes shifting a position of the index portion of one of the address bits of the data to be retrieved from the cache memory in response to changing the size of the cache memory, wherein the position is shifted When the bit is set, the bit length of one of the index portions is not changed.

In another embodiment, a computer readable medium is disclosed. The computer readable medium tangibly embodyes computer executable instructions executable to cause a computer to change a cache memory from a first configuration having a first data area size to a a second configuration having a second data area size: increasing the amount of data associated with each item of the data array of the cache memory and maintaining an item of the data array addressable via a set index a first number, and maintaining a second number of items of the data array associated with each of the set index. The computer executable instructions are further executable to cause the computer to shift a range of bits of a memory address indexed by a tag state array, the tag state array being associated with the data array, wherein The cache memory is changed from the first configuration to the second configuration to shift the range of bits indexing the tag state array.

A particular advantage provided by the disclosed embodiments is that a configurable mapping between the tag and the cache line is provided to support the tag's greater utilization of multiple data RAM configurations such that when the data RAM is configured When 100% cache memory, 50% cache memory or 25% cache memory, the size of the cache line is reduced by the equivalent amount.

Another advantage provided by the disclosed embodiments is that the number of available tags is substantially maximized in a cost effective and time efficient manner when the data RAM available for cache is reduced, which may be assumed in conventional data locality assumptions. The low-power multi-threaded processor environment that is not established is of particular importance. The cache memory with more tags is a higher performing cache memory because address space conflicts are reduced.

After reviewing the entire application including the following sections, other aspects of the invention, Advantages and features will become apparent: [Simple Description of the Drawings], [Embodiment] and [Scope of Application].

100‧‧‧Configurable Cache Memory System

102‧‧‧ address

104‧‧‧Common bits

106‧‧‧Configurable cache memory

108‧‧‧Label Status Array

110‧‧‧Cache data area

112‧‧‧Cache line

112a‧‧‧section or magnetic zone

112b‧‧‧section or magnetic zone

114‧‧‧Collection

116‧‧‧Label area

118‧‧‧Status area

120‧‧‧ channel

122‧‧‧Set index 1

124‧‧‧Set index 2

126‧‧‧ State Address

128‧‧‧ label address

200‧‧‧Configurable Cache Memory System

202‧‧‧Memory Address Register

206‧‧‧Configurable cache memory

208‧‧‧Label Status Array

210‧‧‧Information area

212‧‧‧Cache line

214‧‧‧Collection

216‧‧‧ label area

218‧‧‧Status area

220‧‧‧ channel

222‧‧‧ verification bit

224‧‧‧ index circuit

226‧‧‧Comparative circuit

228‧‧‧Verification circuit

230‧‧‧Selection circuit

300‧‧‧Storage System

302‧‧‧Memory Address Register for Cache Memory Search

304‧‧‧ Label section

306‧‧‧Shift setting index

308‧‧‧ Common bits

310‧‧‧Label section

312‧‧‧Shift setting index

314‧‧‧ arrow

316‧‧‧ Common bits

318‧‧‧ Label section

320‧‧‧Shift setting index

322‧‧‧ arrow

324‧‧‧Status section

400‧‧‧ system

402‧‧‧Memory Address Register for Cache Memory Search

404‧‧‧Multiplexer

406‧‧‧Multiplexer

408‧‧‧Set index

410‧‧‧ two-dimensional line

414‧‧‧7 bit line

426‧‧‧Selection circuit

428‧‧‧ index circuit

430‧‧‧Cache memory size

500‧‧‧Method for configuring a configurable cache memory

600‧‧‧Method for configuring a configurable cache memory

700‧‧‧Method for configuring a configurable cache memory

800‧‧‧ system

810‧‧‧Signal Processor

822‧‧‧Package level system or crystal system device

826‧‧‧ display controller

828‧‧‧Display device

830‧‧‧ Input device

832‧‧‧ memory

834‧‧‧Encoder/Decoder

836‧‧‧Speaker

838‧‧‧ microphone

840‧‧‧Wireless interface

842‧‧‧Wireless antenna

844‧‧‧Power supply

864‧‧‧Configurable cache memory module

866‧‧‧Computer executable instructions

868‧‧‧ camera interface

870‧‧‧ video camera

900‧‧‧Electronic device manufacturing process

902‧‧‧ Physical Device Information

904‧‧‧User interface

906‧‧‧Research computer

908‧‧‧ processor

910‧‧‧ memory

912‧‧‧Program file

914‧‧‧Design computer

916‧‧‧ processor

918‧‧‧ memory

920‧‧ Electronic Design Automation (EDA) Tools

922‧‧‧Circuit design information

924‧‧‧User interface

926‧‧‧GDSII file

928‧‧‧Manufacture process

930‧‧‧Mask maker

932‧‧‧ representative mask

934‧‧‧ wafer

936‧‧‧ representative grain

938‧‧‧Packaging process

940‧‧‧ representative package

942‧‧‧PCB design information

944‧‧‧User interface

946‧‧‧ computer

948‧‧‧ processor

950‧‧‧ memory

952‧‧‧GERBER file

954‧‧‧ board assembly process

956‧‧‧ representative PCB

958‧‧‧Representative Printed Circuit Assembly (PCA)

960‧‧‧Product manufacturing process

962‧‧‧First representative electronic device

964‧‧‧Second representative electronic device

1 is a block diagram of a particular illustrative embodiment of a configurable cache memory system having a tag state array, a plurality of channels, and a fast coupled to the tag state array Figure 2 is a block diagram of another particular illustrative embodiment of a configurable cache memory system having a tag state array, a plurality of channels, and a coupling to a cached data area of the tag state array; FIG. 3 is a block diagram of a particular illustrative embodiment of a memory address register and a shift setting index for a cache memory lookup; FIG. 4 is for a cache memory FIG. 5 is a block diagram of a specific illustrative embodiment of a memory address register and a selection circuit and an index circuit for generating a set index; FIG. 5 is a method for configuring a configurable cache memory; A flow chart of a first illustrative embodiment; FIG. 6 is a flow chart of a second illustrative embodiment of a method for configuring a configurable cache memory; FIG. 7 is a configuration for configuring a configurable Third Illustrative Embodiment of Method of Cache Memory Figure 8 is a block diagram of a particular embodiment of a portable communication device including a configurable cache memory module; and Figure 9 is an illustration of an electronic device for fabricating a device including a configurable cache memory device A data flow diagram of a particular illustrative embodiment of the manufacturing process.

Referring to FIG. 1, a particular illustrative embodiment of a configurable cache memory system 100 is illustrated having a tag state array 108, a plurality of channels 120, and a coupled to the tag state. The cache data area 110 of the array 108. The configurable cache memory system 100 includes a configurable cache memory 106 and a bit address 102. The configurable cache memory 106 includes a tag state array 108 coupled to the cache data region 110. The cache data area 110 includes one or more cache lines 112. As shown in FIG. 1, the cache data area 110 can be configured to have a first cache memory size corresponding to the first cache memory configuration or a second corresponding to the second cache memory configuration. The memory size is cached, wherein the second cache memory size is greater than the first cache memory size. The cache data area 110 includes a plurality of channels 120 associated with each of a set index, such as set index 1 122 or set index 2 124. The plurality of channels 120 enable the cache data area 110 to store a plurality of data values for each set index value. As shown in FIG. 1, the cache data area 110 has the same number of channels 120 in the first cache configuration and in the second cache configuration.

The tag status array 108 includes a tag area 116 that can be addressed by a set index, such as a set index 1 122 or set index 2 124 that is shown associated with the address 102. Tag status array 108 also includes a status area 118 that can be addressed by status address 126. Each of the cache lines 112 is associated with a tag address 128. As shown in FIG. 1, set index 2124 and status address 126 include at least one common bit 104, such as a common address bit. Set index 1 122 and status address 126 include at least two common bits 104, such as two common address bits. In a particular embodiment, the number of common bits 104 (such as common address bits) between the set index 122, 124 and the status address 126 varies depending on the size of the configurable cache 106. In a particular embodiment, the status address 126 and the set index 1 122 include two common bits 104 in the first configuration, and the status address 126 and the set index 2 124 include a common bit in the second configuration. Element 104. Tag status array 108 also includes one or more sets 114. In a particular embodiment, the tag status array 108 has a set 114 of the same size in the first cache configuration and in the second cache configuration.

As shown in FIG. 1, each of the cache lines 112 includes one or more segments or magnetic regions 112a, 112b. When the cache data area 110 has the first cache memory size, the cache line Each of 112 includes a segment or magnetic region 112a. When the cache data area 110 has a second cache memory size, each of the cache lines 112 includes two sectors or magnetic regions 112a, 112b. In a particular embodiment, the cache data area 110 may have the same cache line segment size in the first cache configuration and in the second cache configuration. In an alternate embodiment, the cache data area 110 has a predetermined number of columns that can be addressed by the set index 122, 124. The cache data area 110 can be configured to store at least a first number of cache lines 112 associated with each column in a first configuration and a second number associated with each column in a second configuration The cache line 112, wherein the second number of cache lines 112 is greater than the first number of cache lines 112.

There may be a relationship between the size of the cache line, the size of the data memory, and the number of tags. This relationship can be expressed by the following formula: . As can be seen from this formula, keeping the size of the cache line while keeping the size of the data memory constant can reduce the number of tags. Reducing the number of tags may require less physical storage, however, reducing the number of tags means that the cache memory may contain fewer unique memory locations (or ranges). As an extreme example, consider a 32-bit tuple memory with only a single tag. All 32 bytes will be a copy of the connected portion of one of the system memories. Conversely, if the cache has 8 tags, the cache can contain 8 unrelated 4 byte regions. By expanding, a connected area of a single 32-bit tuple can also be stored in the cache memory.

In some cases, the data memory portion of the cache memory may not be constant, but may be configurable as in the configurable cache memory system 100 of FIG. The body retains a portion and may retain another portion for the tightly coupled memory (TCM). In one configuration, the cache memory can have a fixed cache line size and a fixed mapping between the tag and the cache line. However, if the size of the cache memory is reduced, the number of cache lines and the number of tags are reduced by this amount. For example, in the data random access memory (RAM) Organized into L2 cache memory of 4 memory groups (each memory group has its own set of tags), if the data RAM is configured as 50% cache memory and 50% TCM, The tag in the TCM is no longer available for cache memory.

By adjusting the size of the cache line along with the size of the data memory, the configurable cache memory system 100 of Figure 1 enables the number of tags to remain substantially the same. Therefore, a configurable mapping between the tag and the cache line is provided to support the tag's greater use of multiple data RAM configurations, such that when the data RAM is configured as 100% cache memory, 50% cache When the memory or 25% of the memory is cached, the size of the cache line is reduced by an equivalent amount. In addition, the number of available tags is substantially maximized in a cost effective and time efficient manner as the data RAM available for cache is reduced. This can be of particular importance in a low-power multi-threaded processor environment where traditional data locality assumptions may not be true. A cache memory with more tags can be a higher performance cache memory because address space conflicts are reduced.

Referring to FIG. 2, a particular illustrative embodiment of a configurable cache memory system 200 is illustrated having a tag state array 208, a plurality of channels 220, and a data region 210 coupled to the tag state array 208. The configurable cache memory system 200 includes a configurable cache memory 206, a memory address register 202 for storing memory addresses, an index circuit 224, a comparison circuit 226, a verification circuit 228, and a selection. Circuit 230. The configurable cache memory 206 includes a tag state array 208 coupled to the data area 210. The data area 210 includes one or more cache lines 212. As shown in FIG. 2, the data area 210 is configurable to have a first cache memory size corresponding to the first cache memory configuration or a second cache size corresponding to the second cache memory configuration. a memory size, wherein the second cache memory size is greater than the first cache memory size, or has a third cache memory size corresponding to the third cache memory configuration, wherein the third cache The memory size is larger than the second cache memory size. Data area 210 includes a plurality of channels 220 associated with each value of a set index. The plurality of channels 220 enable the data area 210 to store a plurality of data values corresponding to each of the set index values. As shown in FIG. 2, the data area 210 is in the first cache memory configuration and There are the same number of channels 220 in the second cache configuration and in the third cache configuration.

Tag status array 208 includes a tag area 216 that can be addressed by a set index. Tag status array 208 also includes a status area 218 that can be addressed by a status address. Each of the cache lines 212 can be addressed by a tag address. Tag status array 208 also includes one or more sets 214. In a particular embodiment, the tag status array 208 can have a set 214 of the same size in the first cache configuration and in the second cache configuration and in the third cache configuration. .

In a particular embodiment, the data area 210 has a predetermined number of sets to store material accessible via the set index and tag status array 208. In the first cache configuration, each of the predetermined number of sets of data areas 210 can be configured to store a first amount of data. In the second cache configuration, each of the predetermined number of sets of data areas 210 can be configured to store a second amount of data.

In a particular embodiment, indexing circuit 224 is coupled to memory address register 202 to identify a plurality of tag entries of tag state array 208 using a set index. For example, indexing circuit 224 can access tag state array 208 and locate and identify a plurality of tag entries received from memory address register 202 corresponding to the set index. As shown in FIG. 2, the indexing circuit can also be coupled to the selection circuit by a two-bit connection.

In a particular embodiment, the comparison circuit 226 is coupled to the memory address register 202 to compare the tag values of the identified plurality of tag items with the tag portion of the memory address. For example, the comparison circuit 226 can access the tag status array 208 and the tag values of the plurality of tag items identified by the index circuit 224 and the respective tag portions of the memory address received from the memory address register 202. Compare.

In a particular embodiment, the verification circuit 228 is coupled to the memory address register 202 to decode the status address and to decode the decoded status address with a predetermined number of sets of identification bits of the data area 210. 222 for comparison. Verification circuit 228 can access the tag shape State array 208 compares verify bit 222 with the decoded status address portion of the memory address received from memory address register 202. As shown in FIG. 2, the verification circuit 228 can be coupled to the memory address register 202 by a two bit connection. As shown in FIG. 2, verification bit 222 can include 4 status bits.

As will be described in more detail below in conjunction with FIG. 4, in a particular embodiment, the selection circuit 230 is coupled to the memory address register 202 and coupled to the index circuit 224 to selectively be in the first cache memory bank. The state includes a specific bit of the memory address in the set index and does not include a specific bit in the set index in the second cache configuration. As shown in FIG. 2, selection circuit 230 can be coupled to indexing circuit 224 by a two bit connection. In a particular embodiment, the selection circuit 230 includes a multiplexer (such as the multiplexer 406 shown in FIG. 4) having an input coupled to receive at least one common bit (as in FIG. 4). Shown at 424) and have an output coupled to the tag area 216 (as shown at 416 in FIG. 4). The multiplexer can be configured to selectively provide the at least one common bit as an optional input to a set index, such as the set index 408 shown in FIG.

Referring to FIG. 3, a particular illustrative embodiment of a memory address register 302 and shift setting indices 306, 312, 320 for a cache memory lookup is shown at 300. The shift setting indexes 306, 312, and 320 enable addressing to the cache memory using the same number of sets for three different cache memory size configurations. In a particular embodiment, the memory address register 302 for the cache memory lookup is the address 102 of FIG. 1 or the memory address register 202 of FIG.

The set index 306 is in the range of 9 bits from bit 13 to bit 5, and shares two common bits 308 (bit 5 and bit 6) with the status portion 324 of the address, wherein the status portion 324 is The two bits of bit 6 to bit 5 are ranges. The tag portion 304 of the address ranges from bit 31 to bit 14.

As indicated by arrow 314, the shift of a 1-bit displacement causes set index 312 to share a common bit 316 (bit 6) with the status portion 324 of the address, the set index 312 being The 9 bits of bit 14 to bit 6 are ranges. In this case, bit 5 of status portion 324 of the address can be used to mark two cache line segments or magnetic regions such that the cache memory having set index 312 can be a cache memory having a set index 306. Twice as big. The tag portion 310 of the address ranges from bit 31 to bit 15, and the newly added least significant bit zero can be concatenated to bit 31:15.

As indicated by arrow 322, the shift of the other 1-bit displacement causes the set index 320 and the status portion 324 of the address to not share a common bit, the set index 320 being 9 bits from bit 15 to bit 7. The bit is a range. In this case, both bit 5 and bit 6 of state portion 324 of the address can be used to mark four cache line segments or magnetic regions such that the cache memory with set index 320 can have a set index. The 312 cache is twice as large as the memory. The tag portion 318 of the address ranges from bit 31 to bit 16, and the two least significant bit zeros can be concatenated to bit 31:16.

The total cache memory size can be given by multiplying the number of sets by the number of channels multiplied by the size of the cache line multiplied by the number of segments or sectors. The number of sets indexed by a 9-bit index is 2 ⁹ = 512. For a 4-channel cache with a 32-bit cache line size, for a cache with a set index 306, the total cache size is 512 times 4 times 32 or about 64. A kilobit (kbit) in which the cache memory has only one sector or magnetic region for each cache line. For a cache memory having a set index 312 (where the cache memory has two sectors or sectors for each cache line), the total cache memory size is about 128 kbit. For a cache memory having a set index 320 (where the cache memory has four sectors or sectors for each cache line), the total cache memory size is about 256 kbit.

Referring to FIG. 4, a particular illustrative embodiment of a memory address register 402 for a cache memory lookup and a selection circuit 426 and indexing circuit 428 for generating a set index 408 is shown at 400. System 400 can be used to determine shift setting indices 306, 312, 320 of scratchpad system 300 of FIG. System 400 can be implemented in the configurable cache memory system 100 of FIG. 1 or The configurable cache memory system 200 of FIG.

The memory address register 402 for the cache memory lookup is configured to store 32 bits from the least significant bit (LSB) (bit 0) to the most significant bit (MSB) (bit 31). Bit value. The multiplexer 404 receives the bit 15 as an input (as indicated at 418) from the memory address register 402 for the cache memory lookup and receives the bit 6 as another input (as indicated at 422). As indicated at 412, multiplexer 404 outputs bit 15 or bit 6 to set index 408. The output of the multiplexer 404 is controlled along the two bit line 410 by the cache memory size 430. Multiplexer 406 receives bit 14 as an input (as indicated at 420) and receives bit 5 as another input (as indicated at 424). As indicated at 416, multiplexer 406 outputs bit 14 or bit 5 to set index 408. The output of the multiplexer 406 is controlled along the two bit line 410 by the cache memory size 430. The set index 408 receives bits in the range from bit 13 to bit 7 from the memory address register 402 for the cache memory lookup along the 7-bit line 414.

When multiplexer 404 outputs bit 6 and multiplexer 406 outputs bit 5, then set index 408 corresponds to set index 306 of FIG. When the multiplexer 404 outputs the bit 6 and the multiplexer 406 outputs the bit 14, the set index 408 corresponds to the set index 312 of FIG. 3, wherein the cache memory having the set index 312 can have the set index 306. The cache memory is twice as large. When the multiplexer 404 outputs the bit 15 and the multiplexer 406 outputs the bit 14, the set index 408 corresponds to the set index 320 of FIG. 3, wherein the cache memory having the set index 320 can have the set index 312. The cache memory is twice as large and can be four times as large as the cache memory with the set index 306.

Referring to FIG. 5, a flow diagram of a first illustrative embodiment of a method for configuring a configurable cache memory is shown at 500. The method 500 includes receiving, at 502, an address at an array of tag states of the cache memory, wherein the cache memory is configurable to have one of a first size and a second size greater than the first size By. For example, as shown in FIG. 1, address address 102 can be received at tag state array 108 of configurable cache memory 106, The cache data area 110 of the configurable cache memory 106 can be configured to have one of a first size and a second size greater than the first size. The method 500 also includes identifying, at 504, the first portion of the address as a set index. For example, as shown in FIG. 1, a first portion of address 102 can be identified as a set index 1 122, or a first portion of address 102 can be identified as a set index 2 124. Similarly, as shown in FIG. 3, the first portion of the address in the memory address register 302 for the cache memory lookup can be identified as the set index 306, or as the set index 312, or as a setting. Index 320.

The method 500 further includes using the set index to locate at least one tag field of the tag status array at 506. For example, at least one tag area 116 of the tag state array 108 shown in FIG. 1 can be located using set index 1 122 or set index 2 124. The method 500 also includes identifying a second portion of the address at 508 for comparison with a value stored at the at least one tag field. For example, the second portion of the address 102 can be identified as the tag 128, which can be compared to a value stored in at least one of the tag regions 116 of FIG. The method 500 further includes locating at 510 at least one status field of the tag status array, the at least one status field being associated with a particular tag field that matches the second portion. For example, at least one status area 118 of the tag status array 108 can be located, the at least one status area 118 being associated with a particular tag area 116 that matches the tag 128 of FIG.

The method 500 also includes identifying a cache line at 512 based on a comparison of the third portion of the address with the at least two status bits of the at least one status field. For example, one of the cache lines 112 can be identified based on a comparison of the status address 126 portion of the address 102 with at least two status bits of the at least one status region 118 of the tag state array 108 of FIG. The method 500 further includes fetching the cache line at 514, wherein the first location of the first portion of the address and the second portion of the address are selected based on whether the cache memory is configured to have a first size or a second size The second location, and wherein the first portion of the address has the same number of bits when the cache memory has the first size and when the cache memory has the second size. For example, the identified one of the cache lines 112 may be retrieved, wherein the cached data area 110 may be based on Configuring to have a first size or a second size to select a first location of the set index portion of the address 102 (set index 1 122 or set index 2 124) and a second location of the portion of the label 128 of the address 102, and wherein The set index portion of the address 102 (set index 1 122 or set index 2 124) has the same number of bits when the cache data area 110 has the first size and when the cache data area 110 has the second size.

In a particular embodiment, the cache memory is further configurable to have a third size greater than the second size. For example, as shown in FIG. 2, the data area 210 of the configurable cache memory 206 can be further configurable to have a third size greater than the second size. In a particular embodiment, when the cache memory is configured to have a first size, the first portion of the address overlaps with the two bits of the third portion of the address, wherein the cache memory is configured And having a second size, the first portion of the address overlaps with a single bit of the third portion of the address, and wherein when the cache memory is configured to have a third size, the first portion of the address is not bit aligned Any bits of the third part of the address overlap. For example, as described above, when the cache memory is configured to have a first size (64 kbit), the set index 306 of FIG. 3 overlaps with the two bits 308 of the status address 324, where the cache is cached. When the memory is configured to have a second size (128 kbit), the set index 312 overlaps with a single bit 316 of the status address 324, and wherein when the cache memory is configured to have a third size (256 kbit), The set index 320 does not overlap with any of the bits of the status address 324.

Referring to Figure 6, a flow diagram of a second illustrative embodiment of a method for configuring a configurable cache memory is shown at 600. The method 600 includes changing the size of the cache memory at 602. For example, the cache data area 110 of the configurable cache memory 106 of FIG. 1 can be changed from a first size to a second size, or from a second size to a first size. Similarly, the data area 210 of the configurable cache memory 206 of FIG. 2 can be changed from a first size to a second size, or from a second size to a third size, or from a first size to a third size. The size, either changes from the second size to the first size, or changes from the third size to the second size, or changes from the third size to the first size.

The method 600 also includes shifting the position of the set index portion of the address of the data to be retrieved from the cache memory in response to changing the size of the cache memory at 604, wherein the position is shifted when the position is shifted The bit length of the index portion does not change. For example, the setting index 306 of FIG. 3 can be shifted to the position of the set index 312 as indicated by the arrow 314 in response to the size of the cache memory changing from 64 kbit to 128 kbit, wherein the set index 306 and the set index 312 each have 9 The bit length of a bit. Similarly, the set index 312 of FIG. 3 can be shifted to the position of the set index 320 as indicated by the arrow 322 in response to the size of the cache memory changing from 128 kbit to 256 kbit, wherein the set index 312 and the set index 320 each have nine The bit length of the bit.

In a particular embodiment, when the cache memory is configured to have a first size or when the cache memory is configured to have a second size greater than the first size, the address index portion and bit are set. At least one bit of the status address portion of the address overlaps. For example, when the cache memory is configured to have a first size of about 64 kbit, the set index 306 of FIG. 3 overlaps with at least one bit 308 of the status address 324, and when the cache memory is configured With a second size of about 128 kbit, the set index 312 overlaps with at least one bit 316 of the status address 324.

In a particular embodiment, the cache memory is further configurable to have a third size greater than the second size. For example, as shown in FIG. 2, the data area 210 of the configurable cache memory 206 can be further configurable to have a third size greater than the second size. In a particular embodiment, when the cache memory is configured to have a first size, the set index portion of the address overlaps with the two bits of the status address portion of the address, wherein when the cache memory is When configured to have the second size, the set index portion of the address overlaps with a single bit of the status address portion of the address, and when the cache memory is configured to have the third size, the address is set. The index portion does not overlap with any bit of the status address portion of the address. For example, as described above, when the cache memory is configured to have a first size (64 kbit), the set index 306 of FIG. 3 overlaps with the two bits 308 of the status address 324, where the cache is cached. When the memory is configured to have a second size (128kbit), the index 312 and the status address are set. A single bit 316 of 324 overlaps, and wherein the cache index is configured to have a third size (256 kbit), the set index 320 does not overlap with any bit of the status address 324.

Referring to Figure 7, a flow diagram of a third illustrative embodiment of a method for configuring a configurable cache memory is shown at 700. The method 700 includes changing, at 702, the cache memory from a first configuration having a first data region size to a second configuration having a second data region size: one of increasing and caching memory The amount of data associated with each item of the data array and maintaining a first number of items of the data array that are addressable via a set index, and maintaining a second item of the data array associated with each value of the set index number. For example, the configurable cache memory 106 of FIG. 1 can be added to the cache line magnetic region or section 112a of each of the cache lines 112 by adding a cache line magnetic field or section 112b. The cache data area 110 is changed from the first size to the second size.

The method 700 also includes shifting, at 704, a range of bits of a memory address indexed to a tag state array, the tag state array being associated with the data array, wherein the cache memory is based on the first group The state changes to a second configuration to shift the range of bits indexing the tag state array. For example, the setting index 306 of FIG. 3 may be in response to shifting the size of the cache memory from 64 kbit to 128 kbit and shifting to the set index 312 as indicated by arrow 314, wherein the set index 306 and the set index 312 are both given. A tag status array associated with the data array is indexed, such as tag status array 108 associated with cache data area 110 of FIG.

In a particular embodiment, method 700 further includes setting control inputs to a pair of multiplexers each receiving at least one input from a range of bits indexed to the tag state array and each of which is selectable The bit is output to the set index. For example, multiplexer 404 and multiplexer 406 of FIG. 4 can have their respective control inputs set along binary bit line 410 by cache memory size 430 control. As described above, multiplexer 404 and multiplexer 406 can each receive at least one of a range of bits indexed from a tag state array (such as tag state array 108 of FIG. 1 or tag state array 208 of FIG. 2). Input, and each can be one The optional bit is output to the set index 408.

In a particular embodiment, method 700 further includes changing the cache memory from a second configuration having a second data region size to a third configuration having a third data region size by: adding and caching The amount of each associated data of the data array of the memory and maintaining a first number of items of the data array that are addressable via the set index, and maintaining an item associated with each value of the set index of the data array The second number. For example, the configurable cache 206 of FIG. 2 can be added to an existing cache line region or segment of each of the cache lines 212 by adding additional cache line regions or segments. The data area 210 is changed from the second size to the third size. The method 700 can further include shifting a range of bits of the memory address indexed to the tag state array, the tag state array being associated with the data array, wherein in response to changing the cache memory from the second configuration to The third configuration shifts the range of bits indexing the tag state array. For example, the setting index 312 of FIG. 3 may be in response to shifting the size of the cache memory from 128 kbit to 256 kbit and shifting to the set index 320 as indicated by arrow 322, wherein the set index 312 and the set index 320 are both given. A tag status array associated with the data array is indexed, such as tag status array 208 associated with data area 210 of FIG.

The configurable cache memory operating according to the methods of Figures 5-7 or other embodiments described herein can be incorporated into a variety of electronic devices, such as mobile phones, set-top devices, computers, personal digital assistants (PDA), music player, video player, any other device that stores or retrieves data or computer instructions, or any combination thereof.

FIG. 8 is a block diagram of a particular embodiment of a system 800 that includes a configurable cache memory module 864. System 800 can be implemented in a portable electronic device and includes a signal processor 810 coupled to a memory 832, such as a digital signal processor (DSP). System 800 includes a configurable cache memory module 864. In an illustrative example, the configurable cache memory module 864 includes any of the systems of FIGS. 1-4, operates according to any of the embodiments of FIGS. 5-7, or Any combination of them. Configurable cache memory module 864 for signal processing The 810 may be a separate device or circuit (not shown). In a particular embodiment, the configurable cache memory 106 of FIG. 1 can be accessed by a digital signal processor. For example, as shown in FIG. 8, the configurable cache memory module 864 can be accessed by a digital signal processor (DSP) 810, and the digital signal processor 810 is configured to access and store in a groupable The data cache or the program instruction of the memory module 864. At least one common bit 104 of FIG. 1 may correspond to a predetermined bit, such as a memory address of address 102, which is coupled to digital signal processor 810 at configurable cache memory 106. The cache memory lookup operation is received.

Camera interface 868 is coupled to signal processor 810 and is also coupled to a camera such as video camera 870. The display controller 826 is coupled to the signal processor 810 and coupled to the display device 828. An encoder/decoder (CODEC) 834 can also be coupled to the signal processor 810. Speaker 836 and microphone 838 can be coupled to CODEC 834. The wireless interface 840 can be coupled to the signal processor 810 and coupled to the wireless antenna 842 such that the wireless data received via the antenna 842 and the wireless interface 840 can be provided to the processor 810.

Signal processor 810 can be configured to execute computer executable instructions 866 stored at a computer readable medium, such as memory 832, executable to cause a computer (such as processor 810) The configurable cache memory module 864 is configured to change the cache memory from a first configuration having a first data area size to a second configuration having a second data area size by: adding and fast Taking the amount of each associated data of the data array of the memory and maintaining a first number of items of the data array that are addressable via the set index, and maintaining the data array associated with each value of the set index The second number of items. The computer executable instructions are further executable to cause the configurable cache memory module 864 to shift a range of bits of a memory address indexed to a tag state array associated with the data array And wherein the range of bits indexing the tag state array is shifted based on changing the cache memory from the first configuration to the second configuration.

In a particular embodiment, signal processor 810, display controller 826, memory 832, CODEC 834, wireless interface 840, and camera interface 868 are included in a package level system or in-line system device 822. In a particular embodiment, input device 830 and power supply 844 are coupled to crystal system device 822. Moreover, in a particular embodiment, as illustrated in FIG. 8, display device 828, input device 830, speaker 836, microphone 838, wireless antenna 842, video camera 870, and power supply 844 are external to crystal system device 822. . However, each of display device 828, input device 830, speaker 836, microphone 838, wireless antenna 842, video camera 870, and power supply 844 can be coupled to one of the components of crystal system device 822, such as an interface or Controller.

The devices and functionality disclosed above can be implemented by providing design information and configured into computer files (eg, RTL, GDSII, GERBER, etc.) stored on a computer readable medium. Some or all of these files may be provided to manufacturing process routines based on such file manufacturing devices. The resulting product includes semiconductor wafers that are then diced into semiconductor dies and packaged into semiconductor wafers. These wafers are then used in the devices described above. FIG. 9 depicts a particular illustrative embodiment of an electronic device fabrication process 900.

The physical device information 902 is received in the manufacturing process 900 (such as at the research computer 906). The physical device information 902 can include a design that represents at least one physical property of a semiconductor device, such as the components of the configurable cache memory of FIG. 1, the components of the configurable cache memory of FIG. 2, or any combination thereof. News. For example, the physical device information 902 can include physical parameters, material features, and structural information entered via a user interface 904 coupled to the research computer 906. The research computer 906 includes a processor 908 (such as one or more processing cores) coupled to a computer readable medium, such as memory 910. The memory 910 can store computer readable instructions executable to cause the processor 908 to transform the physical device information 902 to conform to a file format and generate a library file 912.

In a particular embodiment, the library file 912 includes at least one data file, the at least one data file including the transformed design information. For example, the library file 912 can include a component corresponding to the semiconductor device (including the configurable cache memory of FIG. 1 and the group of FIG. 2). A library of data files for the components of the memory cache, or any combination thereof, is provided for use with an electronic design automation (EDA) tool 920.

At design computer 914, library archive 912 can be utilized in conjunction with EDA tool 920, which includes a processor 916 (such as one or more processing cores) coupled to a memory 918. The EDA tool 920 can be stored as processor executable instructions at the memory 918 to enable the user of the design computer 914 to use the configurable cache memory component of FIG. 1, the configurable cache memory of FIG. The components of the library file 912 are designed by the components of the body or any combination thereof. For example, a user of the design computer 914 can enter circuit design information 922 via a user interface 924 coupled to the design computer 914. Circuit design information 922 may include designing at least one physical characteristic representative of a semiconductor device, such as the components of the configurable cache memory of FIG. 1, the components of the configurable cache memory of FIG. 2, or any combination thereof. News. To illustrate, circuit design features may include identification of particular circuits and relationships to other components in the circuit design, positioning information, feature size information, interconnect information, or other information indicative of the physical characteristics of the semiconductor device.

Design computer 914 can be configured to transform design information (including circuit design information 922) to conform to a file format. To illustrate, the file format can include a database binary file format that represents planar geometry, textual indicia, and other information regarding the circuit layout in a hierarchical format, such as a graphical data system (GDSII) file format. Design computer 914 can be configured to generate a data archive (such as GDSII archive 926) including transformed design information, including, in addition to other circuitry or information, a configurable cache memory depicting FIG. Figure 2 shows the information of the configurable cache or any combination thereof. To illustrate, the data file may include information corresponding to a Crystal Carrying System (SOC) including the configurable cache memory of FIG. 1 and also including additional electronic circuitry and components within the SOC.

The GDSII file 926 can be received at the manufacturing process 928 to produce the configurable cache memory of FIG. 1, the configurable cache memory of FIG. 2, the SOC, or any combination thereof, based on the transformed information in the GDSII archive 926. . For example, a device fabrication process can include GDSII File 926 is provided to mask maker 930 to form one or more masks, such as a mask to be used for photolithography, as illustrated by representative mask 932. Mask 932 may be used during the manufacturing process to produce one or more wafers 934 that may be tested and separated into dies (such as representative dies 936). The die 936 includes a circuit that includes the configurable cache memory of FIG. 1, the configurable cache memory of FIG. 2, or any combination thereof.

The die 936 can be provided to a packaging process 938 in which the die 936 is incorporated into a representative package 940. For example, package 940 can include a single die 936 or multiple dies, such as a package level system (SiP) configuration. Package 940 can be configured to conform to one or more standards or specifications, such as the Joint Electron Device Engineering Conference (JEDEC) standard.

Information about the package 940 can be disseminated to individual product designers, such as via a component library stored at the computer 946. Computer 946 can include a processor 948 coupled to memory 950, such as one or more processing cores. A printed circuit board (PCB) tool can be stored as processor executable instructions at memory 950 to process PCB design information 942 received from a user of computer 946 via user interface 944. The PCB design information 942 can include physical location information for the packaged semiconductor device on the circuit board, the packaged semiconductor device corresponding to the configurable cache memory of FIG. 1, the configurable cache memory of FIG. 2, or Any combination of packages 940.

The computer 946 can be configured to transform the PCB design information 942 to produce a data file (such as GERBER file 952) having physical positioning information including the packaged semiconductor device on the circuit board and electrical connections (such as traces and Information on the layout of the vias, wherein the packaged semiconductor device corresponds to a package 940 comprising the configurable cache of FIG. 1, the configurable cache of FIG. 2, or any combination thereof. In other embodiments, the data file generated by the transformed PCB design information may have a format other than the GERBER format.

The GERBER file 952 can be received at the board assembly process 954 and used to form a PCB fabricated from design information stored in the GERBER file 952, such as a representative PCB 956. For example, the GERBER file 952 can be uploaded to one or more machines for performing various steps of the PCB production process. The PCB 956 can be populated with electronic components including a package 940 to form a representative printed circuit assembly (PCA) 958.

PCA 958 can be received at product manufacturing process 960 and integrated into one or more electronic devices, such as first representative electronic device 962 and second representative electronic device 964. As an illustrative and non-limiting example, the first representative electronic device 962, the second representative electronic device 964, or both may be selected from the group consisting of: a set-top box, a music player, and a video player. Devices, entertainment units, navigation devices, communication devices, personal digital assistants (PDAs), fixed location data units, and computers. As another illustrative and non-limiting example, one or more of electronic devices 962 and 964 can be a remote unit (such as a mobile phone), a palm-type personal communication system (PCS) unit, a portable data unit (such as , Personal Data Assistant), Global Positioning System (GPS)-enabled devices, navigation devices, fixed-location data units (such as meter reading devices), or any other device that stores or retrieves data or computer instructions, or any combination. Although one or more of Figures 1-8 can illustrate a remote unit in accordance with the teachings of the present invention, the invention is not limited to the exemplary units described herein. Embodiments of the present invention are suitably used in any device including an active integrated circuit including a memory and a crystal carrying circuit.

Thus, as described in the illustrative process 900, the configurable cache memory of FIG. 1, the configurable cache memory of FIG. 2, or any combination thereof, can be fabricated, fabricated, and incorporated into an electronic device. One or more aspects of the embodiments disclosed with reference to Figures 1-8 can be included at various processing stages (such as included in library file 912, GDSII file 926, and GERBER file 952), as well as stored in a research computer. Memory 910 of 906, memory 918 of design computer 914, memory 950 of computer 946, one or more other computers or processors used at various stages (such as at board assembly process 954) (not shown) The memory of the display, and is also incorporated in one or more other physical embodiments, such as mask 932, die 936, package 940, PCA 958, other such as prototype circuits or devices (not shown) Product, or any combination thereof. Although various representative stages are depicted from the physical device design to the production of the final product, fewer stages may be used or additional stages may be included in other embodiments. Similarly, process 900 can be performed by a single entity or by performing one or more of the various stages of process 900.

It will be further appreciated by those skilled in the art that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or both. The combination. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Implement this functionality as hardware or software, depending on the specific application and design constraints imposed on the overall system. The described functionality may be implemented by a person skilled in the art for a particular application, and the implementation decisions are not to be construed as a departure from the scope of the invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in the form of a hardware, a software module executed by a processor, or a combination of the two. The software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), and erasable programmable read-only memory. (EPROM), electrically erasable programmable read only memory (EEPROM), scratchpad, hard drive, removable disc, compact disk read-only memory (CD-ROM), or this technology Any other form of storage medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write the information to the storage medium. In the alternative, the storage medium can be integrated into the processor. The processor and the storage medium may reside in a special application integrated circuit (ASIC). The ASIC can be present in a computing device or user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments are familiar to the art. The general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but the broadest scope of the invention may be in accordance with the principles and novel features as defined in the following claims.

100‧‧‧Configurable Cache Memory System

102‧‧‧ address

104‧‧‧Common bits

106‧‧‧Configurable cache memory

108‧‧‧Label Status Array

110‧‧‧Cache data area

112‧‧‧Cache line

112a‧‧‧section or magnetic zone

112b‧‧‧section or magnetic zone

114‧‧‧Collection

116‧‧‧Label area

118‧‧‧Status area

120‧‧‧ channel

122‧‧‧Set index 1

124‧‧‧Set index 2

126‧‧‧ State Address

128‧‧‧ label address

Claims (1)

A method for caching a memory configuration, comprising: receiving an address at a tag state array of a cache memory, wherein the cache memory is configurable to have a first size and a greater than One of the second sizes of the first size; identifying a first portion of the address as a set index; using the set index to locate at least one tag field of the tag state array; identifying one of the addresses Comparing the two portions with a value stored in the at least one tag field; locating at least one status field of the tag status array associated with a particular tag field that matches one of the second portions; based on the bit Comparing a third portion of the address with a comparison of at least two status bits of the at least one status field to identify a cache line; and extracting the cache line, wherein the cache line is selected based on the size of the cache memory a first location of the first portion of the address and a second location of the second portion of the address, and wherein the first portion of the address has the first size in the cache memory and Cache memory has the first A size having the same number of bits.