KR102317248B1 - Cache management apparatus and method of using partial reconfiguration - Google Patents

Abstract

Disclosed are a cache control apparatus and a cache management method using partially associative reconfiguration of a cache. In the cache control apparatus for reconfiguring the form of an n-way set associative cache, a monitoring unit for monitoring a centralized access region composed of intensively used sets among sets included in a cache and the centralized access region Allocating the address space of the main memory mapped to the centralized access area and the reconfiguration unit partially reconfiguring the cache based on the number of sets corresponding to and the number of ways of the cache to the reconfigured portion of the cache Includes allotment.

Description

CACHE MANAGEMENT APPARATUS AND METHOD OF USING PARTIAL RECONFIGURATION

The present invention relates to a cache control apparatus and method, and more particularly, to a cache control apparatus and method used in a multicore microphone platform.

The cache (CACHE) is located between the processor and the main memory of the computer, and is a high-speed memory operating at a speed corresponding to the processor. The cache may store a portion of data stored in the main memory, and the data stored in the cache may be accessed faster than data stored in the main memory. Using such a cache can alleviate the bottleneck caused by the speed difference between the fast processor and the slow main memory.

Cache has a huge impact on the performance of a computer system. Recently, with the development of process technology, research to use various types of memory such as DRAM and PCRAM as a cache using TSV (Through Silicon Via) is being actively conducted, and the size of the cache is expected to continue to increase in the future. In order to accommodate the memory access patterns of various applications, a large cache is required, but since an increase in the cache size causes an increase in circuit area and power consumption, an appropriate size must be designed.

By observing the utilization of entries in a large cache, it can be seen that data misses occur because sets of specific regions are not used evenly, and sets of specific regions are used intensively. Also, a set of specific regions has a spatial correlation due to the spatial locality of the data.

In order to solve the phenomenon of data miss in the cache, the cache generally uses a set associative mapping method. In the aggregate associative mapping cache, there is a fixed number of locations (eg, at least two) in which each block of main memory can be placed. That is, an aggregation associative cache having n placeable locations for each block of memory is called an n-way aggregation associative cache.

The n-way aggregation associative cache is composed of multiple sets of n blocks each. Each block in main memory is mapped into a set in the cache by an index field, and all entries in the set are compared to find a match for the data requested by the processor.

However, as the number of associations increases, the number of entries simultaneously accessed to find matching entries increases, which increases cache power consumption and increases the searching latency. For this reason, it is difficult to expect high cache efficiency.

In one embodiment of the present invention, only a specific entry of a large-capacity cache memory is intensively used, and thus a large portion of the cache memory is not used and is wasted.

In addition, there are provided a cache control apparatus and a cache management method for reducing a miss rate of a cache by partially reconfiguring a cache based on the number of cache sets and the number of ways of the cache to be accessed intensively.

Objects of the present invention are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the object of the present invention described above, the cache control apparatus reconfigures the form of an n-way set associative cache according to an aspect of the present invention is an n-way (n is a natural number greater than or equal to 1) set associative cache In the cache control apparatus for reconfiguring the form of, a monitoring unit for monitoring a centralized access region composed of sets that are intensively used among sets included in a cache, the number of sets corresponding to the centralized access region and the cache and a reconfiguration unit for partially reconfiguring the cache based on the number of ways of , and an allocator for allocating an address space of a main memory mapped to the centralized access area to the reconstructed portion of the cache.

The reconstruction unit arbitrarily selects at least one way from among the n-ways of the cache, and reconstructs the selected way based on the number of sets corresponding to the centralized access area.

When the miss rate of the centralized access set is equal to or greater than a preset miss rate, the allocator replaces data stored in the set corresponding to the centralized access area with data requested by the processor core.

The allocator allocates an address space of the main memory that causes data contention among addresses of the main memory mapped to the set corresponding to the centralized access area as the reconstructed part of the cache.

In the cache control method for reconfiguring the form of an n-way set associative cache according to another aspect of the present invention, a centralized access area composed of sets that are used intensively among sets included in the cache is monitored. step, partially reconfiguring the cache based on the number of sets corresponding to the centralized access region and the number of ways of the cache, and reconfiguring the address space of the main memory mapped to the centralized access region of the cache and allocating to the reconstructed part.

Partially reconfiguring the cache includes randomly selecting at least one way from among the n-ways of the cache and reconfiguring the selected ways based on the number of sets corresponding to the centralized access area.

The allocating to the address space of the main memory includes: obtaining a miss rate of the number of sets corresponding to the centralized access region; and when the obtained miss rate of sets corresponding to the centralized access region is greater than or equal to a preset miss rate and replacing data stored in sets corresponding to the centralized access area with data requested by the processor.

According to the present invention as described above, there is an effect of reducing the miss rate of the cache by partially reconfiguring the cache.

In addition, by allocating the address space of the main memory causing actual data contention to the reconfigured cache, overhead and power consumption are reduced, thereby improving the performance of the computer system.

1 is a diagram schematically illustrating a multi-core processor system including a cache control device according to an embodiment of the present invention.
2 is a diagram showing the configuration of a cache.
3 is a block diagram of a cache control apparatus according to an embodiment of the present invention.
4 is a diagram illustrating an example of cache and main memory mapping according to an embodiment of the present invention.
5 is a diagram illustrating a partially reconfigured cache according to an embodiment of the present invention.
6 is a diagram illustrating an example of allocating an address space causing actual data contention to a reconfigured portion of a cache according to an embodiment of the present invention.
7 is a flowchart illustrating a cache management method according to an embodiment of the present invention.

In the present invention, in order to increase the utilization of the cache, when a centralized access region occurs in the cache, the cache is partially restored based on the number of sets included in the centralized access region and the number of ways in the cache. The present invention relates to a cache control apparatus and a cache management method for reducing a cache miss rate by reconfiguring the cache as .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be embodied in various different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided so that those who have it can easily understand the scope of the invention, and the present invention is defined by the description of the claims. On the other hand, the terms used herein are for the purpose of describing the embodiments and are not intended to limit the present invention. As used herein, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, "comprises" or "comprising" refers to the presence or addition is not excluded. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same components are given the same reference numerals as possible even though they are indicated on different drawings. Also, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a diagram schematically illustrating a multi-core processor system including a cache control apparatus according to an embodiment of the present invention.

1 is a diagram illustrating an example of a multi-core processor 100 system, and the physical location of the blocks shown in FIG. 1 is not limited. Design choices may be tuned by considerations of, for example, hardware size and complexity versus performance, thermal energy and heat dissipation, processor speed, overall throughput, and the like. Those skilled in the art will appreciate that the multi-core processor 100 may be provided in a suitable computing environment, such as a personal computer (PC).

As shown in FIG. 1 , the multi-core processor system includes a multi-core processor 100 and a main memory 140 , and the multi-core processor 100 includes a processor core array 110 , a cache 120 , and a cache. a control device 130 .

The multi-core processor 100 system may include a single integrated circuit having a processor core array 110 .

The processor core array 110 includes a plurality of processor cores 111(1) to 111(N). Each processor core 111(1) - 111(N) may comprise any desired configuration including, but not limited to, a microprocessor (μP), microcontroller (μC), digital signal processor (DSP), or any combination thereof. can have Thus, each of the processor cores 111(1)-111(N) can be configured with an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing (DSP) core, a register, an accumulator, etc. It may include logic for executing program instructions as well as functional blocks. All or only a portion of each of the processor cores 111 ( 1 ) to 111 (N) may include a cache memory (not shown).

The cache 120 is a high-speed storage device in which instructions or programs requested from the processor cores 111(1) to 111(N) are stored. Accordingly, the processor cores 111 ( 1 ) to 111 (N) access the cache 120 to retrieve frequently used data or program instructions. In the cache 120, data or program instructions frequently accessed by the processor cores 111(1) to 111(N) are stored, and the processor cores 111(1) to 111(N) can use the necessary data immediately. make it possible

The cache 120 may be implemented as a volatile or non-volatile memory device. For example, cache 120 may be implemented as, for example, a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, or a flash memory device. The cache 120 may be shared by some or all of the processor cores 111 ( 1 ) to 111 (N).

If data required by the processor cores 111(1) to 111(N) can be found in the cache 120, it is called a hit. On the other hand, if the data required by the processor cores 111(1) to 111(N) cannot be found in the cache 120, this is called a miss. When a miss occurs, the processor cores 111(1) to 111(N) access the main memory 140 to find a block containing the necessary data.

The hit rate of the cache 120 is the access rate of the processor cores 111(1) to 111(N) that can be found in the cache 120 , and the hit rate is used to evaluate the performance of the cache 120 . . The miss rate refers to an access rate of the processor cores 111(1) to 111(N) that cannot be found in the cache 120 .

The cache control device 130 to reduce the miss rate of the cache 120,

Monitoring a centralized access region composed of intensively used sets among sets included in the cache, and selecting the cache based on the number of sets allocated to the centralized access region and the number of ways in the cache. partially reconstructed. In addition, the cache control apparatus 130 allocates the address space of the main memory mapped to the centralized access area to the reconfigured portion of the cache.

The main memory 140 stores programs and various data and instructions necessary for driving the processor cores 111(1) to 111(N). Main memory 140 is a volatile memory such as a DRAM device or SRAM device, a non-volatile memory such as a read-only memory (ROM) device or a flash memory device, a data storage device such as a magnetic disk storage device (eg, a hard disk drive or HDD). , tape storage devices, optical storage devices (eg, compact disks or CDs, digital versatile disks or DVDs), or any suitable form of memory.

In order to help the understanding of the embodiment of the present invention, the cache operation will be described in more detail with reference to FIG. 2 .

2 is a diagram showing the configuration of a cache. The cache 120 includes an index selection unit 210 , a cache tag array 220 , a comparison unit 230 , a cache data array 240 , a data selection unit 240 , and a multiplexer (MUltipleXer; hereinafter MUX) 260 . include

The access of the processor cores 111( 1 ) to 111(N) to the cache 120 may be performed in units of data blocks. Specifically, a unit of access to the cache 120 may be a data block, and the cache 120 may store one or more data blocks. Basically, data blocks are stored in the main memory 140 . When the cache 120 stores specific data blocks, the storage of the specific data block may be limited only to specific slots among all slots used by the cache 120 . Specifically, an address space of the main memory 140 that stores the data block may be mapped to the cache 120 based on the address of the data block.

The index selector 210 determines the position of the index field 14 among the data addresses 10 requested to be accessed from the processor cores 111(1) to 111(N) according to the size of the input to the cache and the output unit of the cache. to adjust Specifically, the index selector 210 selects the position of the bit to be used as the index 14 on the data address 10 requested from the processor cores 111(1) to 111(N) according to the size of the input/output unit. do.

The data address 10 requested access from the processor cores 111 ( 1 ) to 111 (N) includes a tag field 12 , an index field 14 , and an offset field 16 .

The tag field 12 is used to identify whether the data block stored in the location on the cache 120 mapped by the index field 14 matches the data block of the address currently being accessed.

The index field 14 determines where a block of data in the main memory 140 is mapped onto the cache 120 . Here, the location may indicate one set corresponding to the index field 14 among one or more sets of the cache 120 . For example, if the index field 14 is an i bit, the number of positions (sets) to which a data block can be mapped on the cache 120 may be 2i. Specifically, if the value of the index field 14 of the data address 10 is x, the data block may be mapped to the x-th set of the cache. By the above-described tag field 12 and index field 14, data blocks stored in the cache can be identified at which addresses in the address space of the main memory.

The offset field 16 may be the remaining least significant bits other than the index field 14 and the tag field 312 . The offset field 16 may be bits of an address indicating a location in the address space of the main memory 140 that are independent of a mapping between a location on a data block and a cache. The size of the offset field 16 may correspond to the size of a data block that is an access unit of the cache. For example, if the offset field 16 is j bits, the size of the data block is 2 ^j bytes, n2 ^j bytes, or 2 ^j It may be a word or the like. In the above description, i, j and n may each be an integer of 0 or more.

The size of the data address 10, the size of the tag field 12, the size of the index field 14, and the size of the offset 16 may be determined depending on the cache or the computer system including the cache.

A set corresponding to a data block of the main memory 140 among sets in the cache data array 250 is determined by the index field 14 of the data address 10 . When the set in the cache data array 250 is determined by the index field 14, one of the ways of the selected set may be used for accessing the data block. Here, the access may include the storage of data blocks. For example, the data block may be stored in an empty way among the set of ways determined by the index field 14 or a way selected by the cache policy.

The cache tag array 220 stores tags for data blocks in the main memory. The cache tag array 220 may be divided into M sets and N ways. Specifically, a set corresponding to a data block among sets in the cache tag array 220 is determined by the index field 14 of the data address 10 . For example, the tag 12 for the data block stored in the j-way of the i-set of the cache data array 220 is stored in the j-th column of the i-th row of the cache tag array 220 .

The comparison unit 230 compares the tags stored in the cache tag array 220 and the tag field 12 values of the data address 10 . For example, assuming that the set of the cache tag array 220 determined by the index field 14 of the data address 10 is the first set 221 , the comparator 230 is the first set of the cache tag array 220 . For the tags stored in the N ways of 221 , each value of the stored tags and the value of the tag field 12 of the data block address 10 are compared. The above comparison can be made simultaneously for the stored tags. If, as a result of comparison, the tag stored in the second way, which is one of the N ways of the first set 221 , and the value of the tag field 12 of the data address 10 are the same, a cache hit occurs. do. On the other hand, as a result of the above comparison, if there is no value equal to the value of the tag field 12 of the data block address 10 among the values of the tags stored in the N ways of the first set 221, a cache miss occurs. do.

The data selection unit 240 determines whether a cache hit has occurred based on the result obtained by performing the logical AND operation on the comparison result obtained from the comparison unit 230 and the cache hit condition. The data selection unit 240 controls the output of the cache data array 250 according to the cache association. Specifically, at least one way among a plurality of ways of a selected set of the cache data array 240 may be output by the data selection unit 240 , and the number of the at least one way depends on the number of associations of the cache. can be decided.

A set corresponding to a data block of the main memory 140 is determined by the index field 14 among sets in the cache data array 250 . Once the set in the cache data array 250 is determined, one of the ways of the selected set is used for access to the data block. The cache data array 250 may be divided into m rows and n columns. In one example, an I-th row of the cache data array 250 may correspond to an I-set, and a J-th column may correspond to a J-way.

When the MUX 260 obtains a cache hit signal from the data selector 240, the MUX 260 outputs a way designated by the signal of the data selector 240 among one or more ways of the set selected by the index selector 210, It is transferred to the processor cores 111(1) to 111(N). On the other hand, when the MUX 260 obtains a cache miss signal from the data selector 240 , the MUX 260 outputs an access signal to the main memory 140 for the data address 10 .

3 is a block diagram of a cache control apparatus according to an embodiment of the present invention.

As shown in FIG. 3 , the cache control device 130 for reducing the miss rate of the cache 120 includes a monitoring unit 131 , a reconfiguration unit 133 , and an allocator 135 .

The monitoring unit 131 monitors a centralized access area composed of intensively used sets among sets included in the cache. Here, the centralized access area may mean a set in which the access frequency of sets included in the cache is equal to or greater than a preset access frequency.

The reconfiguration unit 133 partially reconfigures the cache based on the number of sets corresponding to the centralized access area and the number of ways of the cache from the monitoring unit 131 . For example, the reconfiguration unit 133 arbitrarily selects one way from among n-ways of the cache (n is a natural number greater than or equal to 1) and reconstructs the selected way into the number of sets corresponding to the centralized access area, or n-ways of the cache At least one way is randomly selected among the ways, and the selected ways are reconstructed into the number of sets corresponding to the centralized access area.

The allocator 135 maps the address space of the main memory that causes data contention among the address spaces of the main memory mapped to the set corresponding to the centralized access area to the reconstructed part of the cache.

4 is a diagram illustrating an example of cache and main memory mapping according to an embodiment of the present invention.

4 shows, as an embodiment, a 4-way associative cache 410 and sets included in the 4-way associative cache 410 in the address space of the main memory 420 . An example of mapping to .

According to an embodiment, when the access frequency of the processor cores 111(1) to 111(N) is monitored with the sets included in the cache 410 through the monitoring unit 131 , all sets included in the cache 410 are monitored. It can be seen that the processor cores 111(1) to 111(N) do not access the processor cores 111(1) to 111(N), and the processor cores 111(1) to 111(N) are intensively accessed only on specific sets 411. The monitoring unit 131 monitors the access frequencies from the processor cores 111(1) to 111(N) of the sets included in the cache, and consists of sets in which the access frequency is equal to or greater than a preset access frequency. It is determined whether the concentrated access area 411 is generated. In general, sets constituting the centralized access region 411 are located adjacent to each other because of spatial correlation due to spatial locality of main memory data allocated to the centralized access region 411 .

When the centralized access regions 411 are mapped to the address space of the main memory 420, the main memory address spaces MAS0 (0 to 128), It can be seen that it is mapped to MAS1 (1024+1 to 1024+128) and MAS2 (2048+1 to 2048+128).

In the case of the 4-way associative cache 410 according to the embodiment shown in Fig. 4, when each address space of the main memory 140 is mapped to the cache 410, the tags of the four selectable caches are have

5 is a diagram illustrating a partially reconfigured cache according to an embodiment of the present invention.

The cache control device 130 partially reconfigures the cache based on the number of sets constituting the centralized access area 510 and the number of ways of the cache in order to reduce a miss rate of the cache. .

In this case, the reconfiguration unit 133 may arbitrarily select one way from among the n-ways of the cache and reconfigure the selected way as the number of sets constituting the centralized access area 510 . For example, as shown in FIG. 5 , the reconfiguration unit 133 arbitrarily selects one way (eg, 4 way) from among the four ways in the 4-way partially associative cache, and sets the centralized access area 510 by selecting the Reconstructs the selected way according to the number. Specifically, in the illustrated embodiment, the reconstruction unit 133 selects one way consisting of nine sets, and three ways according to the number (eg, three) of sets constituting the centralized access area 510 . (520) is reconstructed.

The form of the reconfigured cache may vary depending on the nature of the centralized access region 510 . Here, the property of the concentrated access area 510 means the number of sets corresponding to the concentrated access area 510 . In the illustrated embodiment, since the number of sets corresponding to the centralized access area 510 is three, the reconstructed part 520 is configured to have three sets in one way, and thus has a total of three associations.

As another embodiment, when the number of sets corresponding to the centralized access area among the eight sets of ways is two, the reconfiguration unit 133 reconstructs an arbitrary selected way, eight sets included in one way. It is reconstructed into two sets, which is the number of sets constituting the centralized access area. Then, the cache is reconfigured into 4 ways composed of 2 sets. At this time, the reconfigured portion of the cache is configured to have two sets in one way and thus has a total of two associations. In an embodiment, the number of ways selected to be reconfigured may be arbitrarily set according to the number of associations of the cache and the number of sets included in the way when designing the cache.

Also, the reconfiguration unit 133 may arbitrarily select at least one way from among the n-ways of the cache and reconfigure the selected ways into the number of sets corresponding to the centralized access area. For example, when a centralized access area corresponding to three sets is generated in a 4-way 9-set cache, the reconfiguration unit 133 selects two arbitrary ways and converts each selected way to three, which is the number of sets constituting the centralized access area. can be reconstructed. In an embodiment, the two ways selected by the reconstruction unit 133 are reconstructed into a total of six ways. Accordingly, after the partial reconstruction by the reconfiguration unit 133, the cache has a total of 9 ways.

6 is a diagram illustrating an example of allocating an address space causing actual data contention to a reconstructed portion of a cache according to an embodiment of the present invention.

As shown in FIG. 6 , the address space of the main memory 610 includes address spaces MAS0 to MAS5 mapped to sets constituting the centralized access area.

The address spaces (MAS0 ~ MAS5) mapped to the sets constituting the access area are the address spaces (MAS0, MAS3) that cause severe data contention in the cache because there are actually many accesses, and the address spaces (MAS1, MAS2, MAS4) where data contention is not severe (MAS1, MAS2, MAS4). , MAS5).

The storage space of the cache memory 620 includes a portion 621 to which address spaces MAS0 and MAS3 causing severe data contention are mapped, and a portion 623 to which other address spaces MAS1, MAS2, MAS4, and MAS5 are mapped. includes The portion 621 to which the address spaces MAS0 and MAS3 causing severe data contention are mapped includes the portion 60 reconstructed by the reconstruction unit 133 .

In an embodiment, the reconstruction unit 133 selects one way including nine sets and reconstructs one way into three ways according to the number of sets (three) corresponding to the access area. Therefore, as shown in the reconstructed part 60, one way selected by the reconstruction unit 133 is reconstructed into three ways having three sets.

According to an embodiment of the present invention, when the address spaces (MAS0, MAS3) of the main memory 610 in an area where there is a lot of data contention due to actually many data accesses are mapped to the cache 620, the main memory addresses MAS0, MAS3 is mapped to the storage space 621 of the cache 620 containing the reconstructed portion 60 of the cache 620 . When the address spaces MAS0 and MAS3 of the main memory 610 are mapped to the cache 620 , the number of ways in the allocated cache 620 increases.

Specifically, in the embodiment, when the address spaces (MAS0, MAS3) of the main memory 610 are mapped to the cache 620, the tags mapped to the main memory addresses (MAS0, MAS3) with severe data contention from the 4 way to the 6 way are increases Because of the tag increase due to the reconfiguration of the cache, the cache miss rate can be reduced by storing data that receives many requests from the processor cores 111(1) to 111(N) in the cache.

In addition, in order to reduce the miss rate of the cache, the allocator 135 selectively allocates the address space of the main memory 610 to the reconfigured portion 60 of the cache. Specifically, the allocator 135 allocates the reconstructed part 60 to the address spaces MAS0 and MAS3 that actually cause data contention. In addition, the allocator 135 modifies the replacement policy of the cache 620 in order to reduce the miss rate of the cache, and when a specific set among the centralized access sets exceeds a preset miss rate, the data stored in the specific set is replaced. .

Here, the replacement policy of the cache 620 is a miss in which the processor cores 111(1) to 111(N) access the cache and cannot find the desired data in a state in which all sets of the cache are filled with data. When , data is removed from a specific set of cache and a new block of data is fetched from main memory 140 . When a cache miss occurs, a data block to be accessed may be first stored in the cache. If there is no empty space among the spaces available for storage of the data block in the cache, the data block must be replaced with another data block already stored in the cache. A block of data that is released from the cache through replacement due to a cache miss is called a victim. The victim may be determined according to the cache's replacement policy. The method of determining which set in the cache to remove data from is the replacement policy. Typical replacement policies include Least Recently Used (LRU), Least Frequently Used (LFU), First in First out (FIFO), and Random.

In addition, the allocator 135 determines that the address space (MAS1, MAS2, MAS4, MAS5) of the main memory mapped to the set corresponding to the centralized access area excluding the high contention area is in another set 623 that is not reconfigured in the cache. can be mapped.

As a result, the allocator 135 allocates the main memory spaces MAS0 and MAS3 in the region where data contention is severe to the region 621 including the reconfigured portion 60 of the cache, so that each main memory space is greater than before the reconfiguration. By increasing the cache way allocated to , the cache miss rate is reduced.

7 is a flowchart illustrating a cache management method according to an embodiment of the present invention. Hereinafter, a cache management method according to an embodiment of the present invention will be described in more detail with reference to FIG. 7 .

The monitoring unit 131 monitors the centralized access area composed of intensively used sets among sets included in the cache (S710). For example, in step S710 , the monitoring unit 131 monitors a usage pattern for each set included in the cache for a predetermined time, and the monitoring unit 131 converts the processor core 111 to sets included in the cache. (1)~111(N)) access frequency can be monitored.

The monitoring unit 131 determines whether an intensive access area composed of the intensively used sets occurs (S720). For example, in step S720, the monitoring unit 131 determines whether an intensive access area having an access frequency equal to or greater than a preset access frequency occurs.

The reconfiguration unit 133 partially reconfigures the cache based on the number of sets corresponding to the centralized access area and the number of ways of the cache (S730). For example, in step S730, the reconfiguration unit 133 partially reconfigures the cache based on the number of sets corresponding to the centralized access area and the number of ways of the cache. In this case, the reconfiguration unit 133 arbitrarily selects one or a plurality of ways from among the n-ways of the cache and reconstructs the selected way into the number of sets corresponding to the centralized access area.

The allocator 135 allocates the address space of the main memory that causes data contention among addresses of the main memory mapped to sets corresponding to the centralized access area to the reconfigured part of the cache (S740). At this time, in step S740, the allocator 135 obtains a miss rate of the centralized access set, and when the obtained miss rate of the centralized access set is greater than or equal to a preset miss rate, the data stored in the centralized access set is processed by the processor It can be replaced with data requested from the cores 111(1) to 111(N).

The description described above with reference to FIGS. 1 to 6 may also be applied to the embodiment of FIG. 7 . A duplicate description will be omitted.

The cache control apparatus and method according to an embodiment of the present invention have the advantage of reducing the miss rate of the cache by partially reconfiguring the cache based on the number of sets corresponding to the centralized access area and the number of ways of the cache. provides

Those of ordinary skill in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of protection of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

Claims (7)

In the cache control apparatus for reconfiguring the form of an n-way (n is a natural number greater than or equal to 1) set associative cache,
a monitoring unit for monitoring a centralized access area composed of intensively used sets among sets included in the cache;
a reconfiguration unit for partially reconfiguring the cache based on the number of sets corresponding to the centralized access area and the number of ways of the cache; and
an allocator for allocating the address space of the main memory mapped to the centralized access area to the reconstructed part of the cache;
The reconstruction unit
to randomly select at least one way from among the n-ways of the cache and reconstruct the selected way based on the number of sets corresponding to the centralized access area;
When the number of sets corresponding to the centralized access area is m, the cache control apparatus reconfigures a selected way from among the n-ways of the cache into m ways.
delete The method of claim 1, wherein the allocator
When the miss rate of sets corresponding to the centralized access area is equal to or greater than a preset miss rate, replacing data stored in the set corresponding to the centralized access area with data requested from the processor core
In-cache control unit.
The method of claim 1, wherein the allocator
Allocating an address space of the main memory that causes data contention among addresses of the main memory mapped to the set corresponding to the centralized access area as the reconstructed part of the cache.
In-cache control unit.
A cache management method for reconfiguring the form of an n-way set associative cache, comprising:
monitoring a centralized access region composed of intensively used sets among sets included in the cache;
partially reconfiguring the cache based on the number of sets corresponding to the centralized access area and the number of ways of the cache; and
allocating an address space of a main memory mapped to the centralized access region to a reconstructed portion of the cache;
Partially reconfiguring the cache includes:
In order to randomly select at least one way from among the n-ways of the cache, and to reconstruct the selected ways based on the number of sets corresponding to the centralized access area,
and when the number of sets corresponding to the centralized access area is m, reconfiguring the selected way from among the n-ways of the cache into m ways.
delete 6. The method of claim 5, wherein the allocating to an address space of the main memory comprises:
obtaining a miss rate of sets corresponding to the concentrated access area; and
When the obtained miss rate of sets corresponding to the centralized access area is equal to or greater than a preset miss rate, replacing data stored in sets corresponding to the centralized access area with data requested by the processor;
A cache management method comprising a.

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