CN102541754A - System and method for carrying out configuration on memories - Google Patents
System and method for carrying out configuration on memories Download PDFInfo
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- CN102541754A CN102541754A CN2010106072359A CN201010607235A CN102541754A CN 102541754 A CN102541754 A CN 102541754A CN 2010106072359 A CN2010106072359 A CN 2010106072359A CN 201010607235 A CN201010607235 A CN 201010607235A CN 102541754 A CN102541754 A CN 102541754A
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Abstract
The invention discloses a system and a method for carrying out configuration on memories. The system comprises a memory, a configuration register, an arbiter, a Cache (cache memory) controller and an SRAM (static random access memory) controller, wherein the configuration register is used for storing multiple configuration information of a Cache and an SRAM; the arbiter is coupled with the configuration register and receives a memory access request from the outside of an memory; and the Cache controller and the SRAM controller are parallelly arranged between the arbiter and the memory. The arbiter determines how to configure the memory into a Cache and an SRAM according to the memory access request and the multiple configuration information (stored in the configuration register) of the Cache and the SRAM, and sends obtained determining results to the Cache controller and the SRAM controller. The Cache controller and the SRAM controller respectively initiate an operation on the memory according to the determining results of the arbiter. By using the system and method disclosed by the invention, a memory can be dynamically configured into a Cache and an SRAM, and the proportions of the two can be adjusted, therefore, the memory is suitable for different applications, and high in flexibility.
Description
Technical field
The present invention relates to the digital signal processor design field, particularly a kind of system and method that storer is configured of being used for.
Background technology
Digital signal processor (DSP) is a kind of microprocessor that is suitable for carrying out the digital signal processing computing, is mainly used in the algorithm of realizing various digital signal processing real-time.Digital signal processor is extensive application in computing machine, communication and consumer electronics product.Along with the development of digital processing field, have higher requirement to digital signal processor in ever-increasing application demand and application scenario, and digital signal processor must adapt to the needs of different occasions.
It is fast that SRAM (SRAM) has access speed, can read and write continuously, and advantages such as first level address visit have widespread use in fields such as digital signal processing.Cache memory (Cache; Abbreviate high-speed cache as) have the function of buffer memory low level memory data, but when access, need carry out flag (tag) relatively, and when not hitting, need replacement; Therefore access speed is slow slightly, is widely used in field of microprocessors.In the processor design, in microprocessor, add vector instruction in modern times, merge the function of DSP and central processing unit (CPU), the data processor that DSP is become have more powerful control ability has become a kind of trend.
Specifically, under some occasions, DSP needs control function many, can become the Cache ratio higher memory configurations; And under the other occasion, DSP needs digital signal processing capability more intense, can become the SRAM ratio higher memory configurations.
Yet, in the prior art, but the research of the storer of dynamic-configuration being focused mostly in the design of SRAM basic cell structure, this type design hardware complex structure and deployment cost are higher.
Therefore need a kind of system that can dynamically be configured storer, this system can come ratio and the size of Cache and SRAM in the config memory according to different application requirements.
Summary of the invention
The purpose of this invention is to provide a kind of system and method that can storer dynamically be configured to Cache and SRAM.Said system can come Cache and ratio and the size of SRAM in the config memory according to demand, thereby the function that Cache and SRAM are conducted interviews can be provided respectively.
To achieve these goals, according to one embodiment of present invention, a kind of system that storer is configured of being used for is provided, it is characterized in that said system comprises:
Storer;
Configuration register, it preserves a plurality of configuration informations of Cache and SRAM;
Moderator, itself and said configuration register are coupled and receive from the outside memory access request of said storer;
Cache controller and SRAM controller, said Cache controller and SRAM controller are arranged between said moderator and the said storer by parallel,
Wherein said moderator judges how said memory configurations is become Cache and SRAM according to a plurality of configuration informations of said Cache that stores in said memory access request and the said configuration register and SRAM; And result of determination sent to said Cache controller and said SRAM controller, and
Wherein said Cache controller and said SRAM controller are initiated the operation to said storer respectively according to the result of determination of said moderator.
Preferably, said storer comprises sign storage block and DSB data store block.
Preferably, said system also comprises first data selector and second data selector.First data selector is set between said Cache controller and the said storer.Second data selector is set between said SRAM controller and the said storer.
Preferably, said Cache controller produces the respective identification storage block in the said storer and the control signal of DSB data store block according to the result of determination of said moderator.Said SRAM controller produces the control signal to the respective data storage piece in the said storer according to the result of determination of said moderator.
Preferably, the control signal that is generated by said Cache controller comprises sign control signal and data controlling signal.The control signal that is generated by said SRAM controller comprises data controlling signal.
Preferably; When the operation of initiating through the Cache controller the sign storage block; Moderator indicates first data selector to select the sign control signal from the Cache controller, and indicates second data selector to select the data controlling signal from the Cache controller; When the operation of initiating through the SRAM controller the data storage block, moderator indicates first data selector to select spacing wave, and indicates second data selector to select the data controlling signal from the SRAM controller.
Preferably, a plurality of configuration informations of said Cache and SRAM comprise ratio and the size of base address, Cache and the SRAM of SRAM.Further, a plurality of configuration informations of said Cache and SRAM, and can be made amendment by the user through being programmed in the configuration register by the user.
Preferably, when the part of said storer is configured to Cache, configuration be the group number of Cache, and the way of Cache is constant.
Preferably, can be configured to be Cache or be the pattern of SRAM fully to said storer fully.
Storer is according to pattern arranged, and the way of the ratio of Cache and SRAM and Cache for example is arranged to the form of two-dimensional matrix.In this matrix, each one dimension provisional capital is a kind of of Cache or SRAM; Each one dimension row, when being configured to Cache, expression Cache does not go the same way.When configuration Cache and SRAM big or small, the size of Cache must be 2 n power bit, and the size of SRAM is the size that the total size of storer deducts Cache.Said sign storage block as the tag memory of Cache, and when the respective data storage piece is configured to SRAM, is not used when the respective data storage piece is configured to Cache.Said DSB data store block as the data-carrier store of Cache, and when being configured to SRAM, is used as the data-carrier store of SRAM when being configured to Cache.
Change at the configuration information of Cache and SRAM, when both switch each other, need be by sign storage block and the DSB data store block of corresponding Cache in user's manual refreshing storer, thus reconfigure storer according to new configuration information.
Preferably, outside memory access request can comprise the memory access address from said storer.
According to another embodiment of the invention, a kind of method that storer is configured of being used for is provided, it is characterized in that, said method comprising the steps of:
By the user configuration register is carried out initialization, in configuration register, write a plurality of configuration informations of Cache and SRAM;
Receive from the outside memory access request of storer by moderator; Said moderator judges how memory configurations is become Cache and SRAM according to said memory access request with said Cache in said configuration register and a plurality of configuration informations of SRAM, and result of determination is sent to Cache controller and SRAM controller;
Initiate operation by Cache controller and SRAM controller respectively according to the result of determination of moderator to storer.
Preferably, said storer comprises sign storage block and DSB data store block.
Preferably, first data selector is arranged between said Cache controller and the said storer, and second data selector is arranged between said SRAM controller and the said storer.
Preferably, said Cache controller produces the respective identification storage block in the said storer and the control signal of DSB data store block according to the result of determination of said moderator.Said SRAM controller produces the control signal to the respective data storage piece in the said storer according to the result of determination of said moderator.
Preferably, the control signal that is generated by said Cache controller comprises sign control signal and data controlling signal.The control signal that is generated by said SRAM controller comprises data controlling signal.
Preferably; When the operation of initiating through the Cache controller the sign storage block; Indicate first data selector to select sign control signal by moderator, and indicate second data selector to select data controlling signal from the Cache controller by moderator from the Cache controller; When the operation of initiating through the SRAM controller the data storage block, indicate first data selector to select spacing wave by moderator, and indicate second data selector to select data controlling signal from the SRAM controller by moderator.
Preferably, a plurality of configuration informations of said Cache and SRAM comprise ratio and the size of base address, Cache and the SRAM of SRAM.
Preferably, when the part of said storer is configured to Cache, configuration be the group number of Cache, and the way of Cache is constant.
Preferably, can be configured to be Cache or be the pattern of SRAM fully to said storer fully.
Preferably, outside memory access request can comprise the memory access address from said storer.
Through implementing system and a method according to the invention, the present invention has following advantage:
1. can storer dynamically be configured to Cache and SRAM, and both ratios and size can be conditioned, thereby make storer go for different application, dirigibility is high;
2. compared with prior art, the used steering logic of system of the present invention is fewer, thereby has avoided the control hazard of Cache and SRAM effectively;
3. when storer was configured to a part and is SRAM for Cache and another part, owing to compare with all being configured to Cache, the size of Cache used in the present invention had been reduced, and therefore when not needing big Cache, can save power consumption.
Description of drawings
To describe embodiments of the invention in detail with reference to accompanying drawing now, in the accompanying drawings:
Fig. 1 is the block diagram of the system that is used for according to an embodiment of the invention storer is configured;
Fig. 2 is the principle schematic of the memory configurations in the said according to an embodiment of the invention system;
Fig. 3 is the process flow diagram of the method that is used for according to an embodiment of the invention storer is configured.
Embodiment
Some term is used for indicating particular system component from start to finish in present specification.As person of skill in the art will appreciate that, can indicate identical parts with different titles usually, thereby present specification is unexpectedly schemed to distinguish, and those are just different rather than in the function aspects various parts nominally.In present specification, use a technical term " comprising ", " comprising " and " having " with open form, and so should it be interpreted as mean " including but not limited to ... "
Digital signal processor (DSP) is a kind of machine element that is used to carry out various digital signal processing computings.Integrated DSP in microprocessor, the digital signal processing function of enhancement process device has become a kind of popular project organization.Usually; When operation control task and static data; Need the slow slightly cache memory of access speed (Cache) to mate the speed difference between kernel and the main memory; And when handling a large amount of live signal, then need access speed faster SRAM (SRAM) improve access bandwidth.
The present invention aims to provide and a kind ofly can carry out the system and method for dynamic-configuration to storer, thereby makes storer can satisfy different application requirements.Below in conjunction with the preferred embodiments of the present invention the present invention is described in further detail.
With reference now to Fig. 1,, Fig. 1 is the block diagram of the system 100 that is used for according to an embodiment of the invention storer is configured.
This system 100 comprises configuration register 102, moderator 104, Cache controller 106, SRAM controller 108 and storer 110.
In one embodiment, storer 110 comprises sign storage block 110-1 and DSB data store block 110-2.System 100 also comprises first data selector 112 and second data selector 114.
By the user configuration register 102 is carried out initialization at first, a plurality of configuration informations of Cache and SRAM are write in the configuration register 102.These configuration informations comprise ratio and the size of base address, Cache and the SRAM of SRAM, but are not limited thereto.When to different application, when needing to change ratio or other configuration informations of Cache and SRAM in the storer, also be to come the content in the configuration register 102 is made amendment through coding by the user.
The memory access request (being the read/write data request) that moderator 104 receives from system 100 outsides (for example from ppu, not shown this processor among Fig. 1).
Preferably, the memory access request can comprise the memory access address.
Then, how moderator 104 judges config memory 110 according to the configuration information in memory access request and the configuration register 102, and result of determination is sent to Cache controller 106 and SRAM controller 108 respectively with the form of signal.
Cache controller 106 and SRAM controller 108 are arranged between moderator 104 and the storer 110 concurrently.Cache controller 106 is initiated the operation to storer 110 with SRAM controller 108 bases respectively from the signal (being result of determination) of moderator 104.
Specifically; In response to signal from moderator 104; Cache controller 106 generates Cache sign control signal and the Cache data controlling signal to respective identification storage block in the storer and DSB data store block, the SRAM data controlling signal that SRAM controller 108 generates to the respective data storage piece in the storer.
First data selector 112 is disposed between Cache controller 106 and the storer 110, and second data selector 114 is disposed between SRAM controller 108 and the storer 110.When the operation of initiating by Cache controller 106 sign storage block 110-1; Send command signal by moderator 104 and give first data selector 112; Indicate first data selector 112 to select Cache sign control signal from Cache controller 106; Moderator 104 sends command signal and gives second data selector 114 simultaneously, the Cache data controlling signal of indicating second data selector 114 to select from Cache controller 106.When the operation of initiating through SRAM controller 108 data storage block 110-2; Moderator 104 indications first data selector 112 is selected spacing wave (i.e. the input end grounding of first data selector), and the SRAM data controlling signal of indicating second data selector 114 to select from SRAM controller 108.
Thus, when storer 110 is configured to Cache and the SRAM of different proportion, can realize visit respectively to Cache in the storer 110 and SRAM.
Preferably, when storer 110 was configured to Cache and the SRAM of different proportion, Cache in the storer 110 and SRAM can be by visits simultaneously.
In addition; When being directed against the Another Application demand; User's modification during the configuration information (for example, their ratio and size) of Cache and the SRAM in the configuration register 102, need user's manual refreshing storer 110; Be about to storer 110 and empty, so that reconfigure storer 110 according to amended configuration information.
Utilize system of the present invention, can storer dynamically be configured to Cache and SRAM, and both ratios and adjustable size, therefore make storer can be applicable to different application, dirigibility is high.Further, compared with prior art, in system according to the present invention, used steering logic is fewer, thereby has avoided the control hazard of Cache and SRAM effectively.In addition, when not needing big Cache, can save power consumption.
Come to describe in more detail the profile instance of storer 110 below with reference to Fig. 2.
Fig. 2 is the principle schematic of storer 110 configuration according to an embodiment of the invention.Storer 110 comprises sign storage block 110-1 and DSB data store block 110-2.
As an example, sign storage block 110-1 and DSB data store block 110-2 all are arranged to the matrix of 4x4.Replacedly; Sign storage block 110-1 and DSB data store block 110-2 also can be arranged to the matrix of other spread pattern; For example 8 * 8 matrix, 16 * 16 matrix, 8 * 4 matrix, 4 * 64 matrix, or the like, as long as the line number and the columns of these matrixes satisfy following form: 2
n* 2
n(n is a natural number).
In Fig. 2, the sign storage block of sign 00 expression the 0th row the 0th row, the DSB data store block of data 00 expression the 0th row the 0th row; The sign storage block of sign 01 expression the 0th row the 1st row, the DSB data store block of data 01 expression the 0th row the 1st row; (by that analogy) the sign storage block of sign 33 expressions the 3rd row the 3rd row, the DSB data store block of data 33 expressions the 3rd row the 3rd row.
When storer 110 was configured to Cache, the sign storage block 110-1 and the DSB data store block 110-2 of storer 110 were used.In this case, sign storage block 110-1 is as the tag memory of Cache, and DSB data store block 110-2 is as the data-carrier store of Cache.When storer 110 is configured to SRAM, have only the DSB data store block 110-2 of storer 110 to be used, and in this case, DSB data store block 110-2 is as the data-carrier store of SRAM.
The layout synoptic diagram of the ratio that Fig. 2 a shows Cache and SRAM in the storer 110 sign storage block 110-1 and DSB data store block 110-2 during for 1:3.
In this case, the first line identifier storage block and DSB data store block are configured to Cache, and the second, three, the four lines DSB data store block is configured to SRAM, and the second, three, four lines sign storage block is inoperative.
The layout synoptic diagram of the ratio that Fig. 2 b shows Cache and SRAM in the storer 110 sign storage block 110-1 and DSB data store block 110-2 during for 1:1.
In this case, the first, two line identifier storage block and DSB data store block are configured to Cache, and the 3rd, the four lines DSB data store block is configured to SRAM, and the 3rd, four lines sign storage block is inoperative.
In addition, the ratio of Cache and SRAM can also be configured to 3:1 in the storer 110,7:1,1:7, or the like, this depends on different application requirements.Perhaps, also can storer 110 be configured to Cache or accomplish be configured to SRAM fully.
In above-mentioned various configurations, the size of Cache must be 2
nBit (n is a natural number), and total size of storer must be 2
mBit (m is a natural number), and m>N.
When carrying out above-mentioned various configuration, the attribute one of each row of Cache changes, and attribute of each row of SRAM also one changes.That is to say that each in the memory matrix is gone or is configured to Cache, or is configured to SRAM, is configured to SRAM and can not both be configured to Cache.
Preferably, when storer 110 is configured to a part when the Cache, configuration be the group number (being line number) of Cache, the way of Cache (being columns) is constant.Perhaps, when storer 110 is configured to a part when the Cache, configuration be the way (being columns) of Cache, the group number of Cache (being line number) is constant.
Preferably, Cache can keep 2 always
nThe form of (n is a natural number, and n=2) in this example road set associative.The constant hit rate that guarantees Cache to a certain extent of degree of association.
With instance Cache and different allocation ratios and the size of SRAM in the storer 110 are described below.
Instance 1: in Fig. 2 a, total size of supposing storer 110 is 256KB, and the ratio of Cache and SRAM is 1:3, and the size of Cache is 64KB so.Suppose that Cache is four road set associatives, then every road size is 16KB.If every row size of Cache is 32B, then every road Cache has 512 row.Thus, the size of SRAM is 192KB, i.e. 256KB-64KB=192KB.
In this case, the address of Cache is divided into:
| 31 .. 14 | 13 .. 5 | 4 .. 2 | 1 .. 0 |
| Sign | Group address | Word address in the row | Byte address |
And the address of SRAM is divided into:
| 17 .. 16 | 15 .. 14 | 13 .. 5 | 4 .. 2 | 1 .. 0 |
| The row block address | The row block address | Row address | Word address in the row | Byte address |
In this case, the capable block address of SRAM, i.e. the 17:16 position of SRAM address, only 00,01,10 o'clock are effective, and invalid at 11 o'clock, because this moment, SRAM was unavailable.
Instance 2: in Fig. 2 b, total size of supposing storer 110 is 256KB, and the ratio of Cache and SRAM is 1:1, and the size of Cache is 128KB so.Suppose that Cache is four road set associatives, then every road size is 32KB.If every row size of Cache is 32B, then every road Cache has 1024 row.This Cache can be made up of the storage block of two 16KB.Thus, the size of SRAM is 128KB, i.e. 256KB-128KB=128KB.
In this case, the address of Cache is divided into:
| 31 .. 15 | 14 .. 5 | 4 .. 2 | 1 .. 0 |
| Sign | Group number | Word offset in the row | Byte offset |
The 14th storage block that is used for selecting different rows wherein.And the address of SRAM is divided into:
| 16 | 15 .. 14 | 13 .. 5 | 4 .. 2 | 1 .. 0 |
| The row block address | The row block address | Row address | Word address in the row | Byte address |
When storer 110 was configured to SRAM, it was invalid to identify storage block accordingly, has only corresponding DSB data store block to work.When storer 110 is configured to Cache, identify storage block accordingly and DSB data store block all works.
Fig. 3 is the process flow diagram of the method that is used for according to an embodiment of the invention storer is configured.
At step S10, in configuration register, write a plurality of configuration informations of said Cache and SRAM when memory configurations become Cache and SRAM by the user.
At step S12; How moderator receives from the memory access request of ppu (not shown in Fig. 1) and according to the configuration information in memory access request and the configuration register judges config memory, and result of determination is sent to Cache controller and SRAM controller respectively with the form of signal.Preferably, the memory access request comprises the memory access address.
At step S14, Cache controller and SRAM controller are according to initiating the operation to storer respectively from the signal (being result of determination) of moderator.
Specifically; In response to signal from moderator; The Cache controller generates Cache sign control signal and the Cache data controlling signal to respective identification storage block in the storer and DSB data store block, and the SRAM controller generates the SRAM data controlling signal to the respective data storage piece in the storer.
When the operation of initiating by the Cache controller the sign storage block; Moderator indicates first data selector to select the Cache sign control signal from the Cache controller, and indicates second data selector to select the Cache data controlling signal from the Cache controller.When the operation of initiating through the SRAM controller the data storage block; Moderator indicates first data selector to select spacing wave (i.e. the input end grounding of first data selector), and indicates second data selector to select the SRAM data controlling signal from the SRAM controller.Thus, realization is to the visit respectively of Cache in the storer and SRAM.
Through the description to the foregoing description, it is obvious that advantage of the present invention becomes.That is, utilize the present invention, can storer dynamically be configured to Cache and SRAM, and both ratios and adjustable size, therefore more being applicable to the digital signal processing application, dirigibility is high.Further, compared with prior art, in the system that storer is configured of being used for according to the present invention, used steering logic is fewer, thereby has avoided the control hazard of Cache and SRAM effectively.In addition, when not needing big Cache, can save power consumption.
Although described the present invention by embodiment so that those skilled in the art can realize or use content disclosed by the invention in the above, above these embodiment are not exhaustive.To those skilled in the art; Various modifications to these disclosures all are conspicuous, and the technical scheme of the resulting within the spirit and scope of the present invention any modification of those skilled in the art, conversion, replacement all falls within protection scope of the present invention.In addition; Each step that comprises in the previous embodiment, the sequencing between each parts are just preferred; And the present invention is not limited to this; Those skilled in the art can adjust said sequence under the situation that does not deviate from spirit of the present invention, and resulting technical scheme still falls within protection scope of the present invention after the adjustment.
Claims (10)
1. one kind is used for system that storer is configured, it is characterized in that said system comprises:
Storer;
Configuration register, it preserves a plurality of configuration informations of Cache and SRAM;
Moderator, itself and said configuration register are coupled and receive from the outside memory access request of said storer;
Cache controller and SRAM controller, said Cache controller and SRAM controller are arranged between said moderator and the said storer by parallel,
Wherein said moderator judges how said memory configurations is become Cache and SRAM according to a plurality of configuration informations of said Cache that stores in said memory access request and the said configuration register and SRAM; And result of determination sent to said Cache controller and said SRAM controller, and
Wherein said Cache controller and said SRAM controller are initiated the operation to said storer respectively according to the result of determination of said moderator.
2. system according to claim 1; It is characterized in that; Said storer comprises sign storage block and DSB data store block; And said system also comprises first data selector and second data selector, and first data selector is set between said Cache controller and the said storer, and second data selector is set between said SRAM controller and the said storer.
3. system according to claim 2; It is characterized in that; Said Cache controller produces the respective identification storage block in the said storer and the control signal of DSB data store block according to the result of determination of said moderator, and said SRAM controller produces the control signal to the respective data storage piece in the said storer according to the result of determination of said moderator.
4. system according to claim 3 is characterized in that, the control signal that is generated by said Cache controller comprises sign control signal and data controlling signal, and the control signal that is generated by said SRAM controller comprises data controlling signal.
5. system according to claim 4; It is characterized in that; When the operation of initiating through the Cache controller the sign storage block; Moderator indicates first data selector to select the sign control signal from the Cache controller, and indicates second data selector to select the data controlling signal from the Cache controller; When the operation of initiating through the SRAM controller the data storage block, moderator indicates first data selector to select spacing wave, and indicates second data selector to select the data controlling signal from the SRAM controller.
6. one kind is used for method that storer is configured, it is characterized in that, said method comprising the steps of:
By the user configuration register is carried out initialization, in configuration register, write a plurality of configuration informations of Cache and SRAM;
Receive from the outside memory access request of storer by moderator; Said moderator judges how memory configurations is become Cache and SRAM according to said memory access request with said Cache in said configuration register and a plurality of configuration informations of SRAM, and result of determination is sent to Cache controller and SRAM controller;
Initiate operation by Cache controller and SRAM controller respectively according to the result of determination of moderator to storer.
7. method according to claim 6; It is characterized in that; Said storer comprises sign storage block and DSB data store block; And first data selector is arranged between said Cache controller and the said storer, and second data selector is arranged between said SRAM controller and the said storer.
8. method according to claim 7; It is characterized in that; Said Cache controller produces the respective identification storage block in the said storer and the control signal of DSB data store block according to the result of determination of said moderator, and said SRAM controller produces the control signal to the respective data storage piece in the said storer according to the result of determination of said moderator.
9. method according to claim 8 is characterized in that, the control signal that is generated by said Cache controller comprises sign control signal and data controlling signal, and the control signal that is generated by said SRAM controller comprises data controlling signal.
10. method according to claim 9; It is characterized in that; When the operation of initiating through the Cache controller the sign storage block; Indicate first data selector to select sign control signal by moderator, and indicate second data selector to select data controlling signal from the Cache controller by moderator from the Cache controller; When the operation of initiating through the SRAM controller the data storage block, indicate first data selector to select spacing wave by moderator, and indicate second data selector to select data controlling signal from the SRAM controller by moderator.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105302745A (en) * | 2014-06-30 | 2016-02-03 | 深圳市中兴微电子技术有限公司 | Cache memory and application method therefor |
| CN107526688A (en) * | 2017-09-12 | 2017-12-29 | 上海兆芯集成电路有限公司 | Storage device and collocation method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1429369A (en) * | 2000-03-31 | 2003-07-09 | 英特尔公司 | System with configurable cache/SRAM |
| CN101739235A (en) * | 2008-11-26 | 2010-06-16 | 中国科学院微电子研究所 | Processor unit for seamless connection between 32-bit DSP and universal RISC CPU |
| US20100228941A1 (en) * | 2009-03-03 | 2010-09-09 | Qualcomm Incorporated | Configurable Cache and Method to Configure Same |
-
2010
- 2010-12-27 CN CN2010106072359A patent/CN102541754A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1429369A (en) * | 2000-03-31 | 2003-07-09 | 英特尔公司 | System with configurable cache/SRAM |
| CN101739235A (en) * | 2008-11-26 | 2010-06-16 | 中国科学院微电子研究所 | Processor unit for seamless connection between 32-bit DSP and universal RISC CPU |
| US20100228941A1 (en) * | 2009-03-03 | 2010-09-09 | Qualcomm Incorporated | Configurable Cache and Method to Configure Same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105302745A (en) * | 2014-06-30 | 2016-02-03 | 深圳市中兴微电子技术有限公司 | Cache memory and application method therefor |
| CN105302745B (en) * | 2014-06-30 | 2019-07-19 | 深圳市中兴微电子技术有限公司 | Cache memory and its application method |
| CN107526688A (en) * | 2017-09-12 | 2017-12-29 | 上海兆芯集成电路有限公司 | Storage device and collocation method |
| US10310761B2 (en) * | 2017-09-12 | 2019-06-04 | Shanghai Zhaoxin Semiconductor Co., Ltd. | Storage device with dynamic configuration |
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Application publication date: 20120704 |