TW201608749A - Architecture for 3D memory array and method for manufacturing the same - Google Patents

Abstract

An architecture for 3D memory array includes: a stack structure which is formed by alternatively stacking a dielectric layer and a first conductive layer, wherein the stack structure having a hole penetrated each layers of the stack structure, and the hole having a different aperture in the dielectric layer and the first conductive layer; a second conductive layer which is disposed on the hole of the stack structure; and a data store layer which is deposed between the stack structure and the second conductive layer.

Description

Array structure of three-dimensional memory and manufacturing method thereof

The present invention relates to a structure of a semiconductor device and a method of fabricating the same, and more particularly to an array structure of a three-dimensional memory and a method of fabricating the same.

In recent years, with the complexity of software programming, the speed requirements for microprocessors have become higher and higher, and memory requirements have also increased. In order to create a larger and cheaper memory to meet this demand trend, the technology and process of fabricating memory components has become a driving force for semiconductor technology to continue to accumulate high levels of integration.

The memory can be classified into Non-Volatile Memory (NVM) and Volatile Memory (Volatile Memory) according to the relationship between storage capacity and power. Among them, the rapid growth of Non-Volatile Memory (NVM) has attracted the most attention. Among the non-volatile memory, Resistive Random Access Memory (RRAM) is the most attractive. It has a simple structure, low write operation voltage, high-speed operation, and non-volatile characteristics. Resistive random access memory has the potential to compete with other non-volatile memories.

However, with the miniaturization of the integrated circuit process, the size of the components is constantly The shrinkage causes the line width of the memory structure and the thickness of the electrode to be greatly reduced, and faces a problem that the resistance value of the electrode is greatly increased. Therefore, how to improve the resistance value of the electrode and increase the performance of the memory cell will be a major challenge in the development of three-dimensional memory.

The invention provides an array structure of three-dimensional memory, which can reduce the resistance value of the through-hole electrode, increase the area of the memory cell and control the shape of the memory cell, and increase the performance of the memory cell.

The invention provides a method for manufacturing an array structure of three-dimensional memory, which can simplify the process steps and reduce the production cost.

The array structure of the three-dimensional memory of the present invention comprises: a stacked structure, which is a structure in which a dielectric layer and a first conductive layer are alternately stacked, wherein the stacked structure has holes penetrating through the layers of the stacked structure, and the holes are dielectrically The layer and the first conductive layer respectively have different apertures; the second conductive layer is disposed in the hole in the stacked structure; and the data storage layer is disposed between the stacked structure and the second conductive layer.

In an embodiment of the invention, the array structure of the three-dimensional memory, wherein the aperture at the dielectric layer is A, the aperture at the first conductive layer is B, and the aperture is A>B.

In an embodiment of the invention, the array structure of the three-dimensional memory, wherein the aperture at the dielectric layer is A, the aperture at the first conductive layer is B, and the aperture is A<B.

In an embodiment of the invention, the array structure of the three-dimensional memory, wherein the dielectric layer further comprises a first dielectric layer and a second dielectric layer, and the stacked structure Stacking in the order of the first dielectric layer, the first conductive layer, the second dielectric layer, and the first conductive layer, and the holes are different at the first dielectric layer, the second dielectric layer, and the first conductive layer, respectively Aperture.

In an embodiment of the present invention, the array structure of the three-dimensional memory, wherein the aperture at the first dielectric layer is A1, and the aperture at the second dielectric layer is A2, located at the first conductive layer. The pore size is B, and the pore diameter is A1>A2>B.

In an embodiment of the present invention, the array structure of the three-dimensional memory, wherein the aperture at the first dielectric layer is A1, and the aperture at the second dielectric layer is A2, located at the first conductive layer. The pore size is B, and the pore diameter is A1>B≧A2.

In an embodiment of the present invention, the array structure of the three-dimensional memory, wherein the dielectric layer is made of yttrium oxide, tantalum nitride, hafnium oxynitride, aluminum oxide, titanium oxide, cerium oxide or a combination thereof.

In an embodiment of the present invention, the array structure of the three-dimensional memory, wherein the first dielectric layer is made of yttrium oxide and the second dielectric layer is made of tantalum nitride.

In an embodiment of the present invention, the array structure of the three-dimensional memory, wherein the first conductive layer and the second conductive layer are made of polysilicon.

The method for fabricating a three-dimensional memory array structure of the present invention comprises: forming a stacked structure in which a dielectric layer and a first conductive layer are alternately stacked on a substrate; and then removing a part of the stacked structure to form a hole to penetrate the same Each layer of the stacked structure; followed by removing a portion of the dielectric layer or the first conductive layer such that the holes have different apertures at the dielectric layer and the first conductive layer; respectively, and then forming a data storage on the surface of the hole a layer; and finally a second conductive layer is formed to fill the holes.

In an embodiment of the invention, the method for fabricating an array structure of a three-dimensional memory, wherein the aperture at the dielectric layer is A, the aperture at the first conductive layer is B, and the aperture is A>B.

In an embodiment of the invention, the method for fabricating the array structure of the three-dimensional memory, wherein the aperture at the dielectric layer is A, the aperture at the first conductive layer is B, and the aperture is A<B.

In an embodiment of the present invention, the method for fabricating an array structure of a three-dimensional memory, wherein the dielectric layer further comprises a first dielectric layer and a second dielectric layer, and the stacked structure is a first dielectric layer, A conductive layer, a second dielectric layer and a first conductive layer are stacked in the order.

In an embodiment of the present invention, the method for fabricating an array structure of a three-dimensional memory, wherein the aperture at the first dielectric layer is A1, and the aperture at the second dielectric layer is A2, located at the first conductive The pore size at the layer is B, and the pore diameter is A1>A2>B.

In an embodiment of the present invention, the method for fabricating an array structure of a three-dimensional memory, wherein the aperture at the first dielectric layer is A1, and the aperture at the second dielectric layer is A2, located at the first conductive The pore size at the layer is B, and the pore diameter is A1>B≧A2.

In an embodiment of the present invention, the method for fabricating an array structure of a three-dimensional memory, wherein the dielectric layer is made of yttrium oxide, tantalum nitride, hafnium oxynitride, aluminum oxide, titanium oxide, cerium oxide or a combination thereof. .

In an embodiment of the invention, the method for fabricating the array structure of the three-dimensional memory, wherein the material of the first dielectric layer is yttrium oxide and the material of the second dielectric layer is tantalum nitride.

In an embodiment of the invention, the method for fabricating the array structure of the three-dimensional memory, wherein the material of the first conductive layer and the second conductive layer is polysilicon.

In an embodiment of the invention, the method for fabricating an array structure of a three-dimensional memory, wherein the method of removing a portion of the first conductive layer or the dielectric layer comprises a wet etching method.

In an embodiment of the present invention, the method for fabricating the array structure of the three-dimensional memory, wherein the material storage layer is made of yttrium oxide, tantalum nitride, yttrium oxynitride, aluminum oxide, titanium oxide, cerium oxide, magnesium oxide. Cobalt iron boron (CoFeB), cobalt iron (CoFe), ruthenium (Ru), platinum manganese alloy (PtMn) or a combination thereof.

Based on the above, the array structure of the three-dimensional memory proposed by the present invention has a data storage layer recess structure, which can effectively reduce the resistance value of the resistor and increase the area of the memory cell, and can finely adjust the electric field of the memory cell through the shape of the memory cell. Produced, and greatly improved the performance of memory cells. In addition, since the method for fabricating the array structure of the three-dimensional memory proposed by the present invention is to form a structure having a recess by wet etching, the data storage layer can be disposed on the surface of the hole without using a seed layer, thereby greatly simplifying The process steps reduce the production cost of the memory.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Three-dimensional memory array structure

110‧‧‧ dielectric layer

110a‧‧‧First dielectric layer

110b‧‧‧Second dielectric layer

120‧‧‧First conductive layer

130‧‧‧Stack structure

133‧‧‧ holes

140‧‧‧Data storage layer

150‧‧‧Second conductive layer

160‧‧‧ memory cells

200‧‧‧Substrate

A, A1, A2, B‧‧‧ aperture

1A is a schematic cross-sectional view showing an array structure of a three-dimensional memory according to a first embodiment of the present invention.

FIG. 1B is a schematic perspective view of the memory cell of FIG. 1A.

2A is a schematic cross-sectional view showing an array structure of a three-dimensional memory according to a second embodiment of the present invention.

2B is a perspective view of the memory cell of FIG. 2A.

3A is a cross-sectional view showing an array structure of a three-dimensional memory according to a third embodiment of the present invention.

3B is a perspective view of the memory cell of FIG. 3A.

4 is a cross-sectional view showing an array structure of a three-dimensional memory according to a fourth embodiment of the present invention.

Fig. 5 is a cross-sectional view showing an array structure of a three-dimensional memory according to a fifth embodiment of the present invention.

6A to 6E are process cross-sectional views showing a method of fabricating an array structure of a three-dimensional memory according to an embodiment of the present invention.

Embodiments of the invention are described more fully hereinafter with reference to the accompanying drawings. However, the invention may be practiced in many different forms and is not limited to the embodiments described herein. Directional terms mentioned in the following examples, such as "upper", etc., are only The orientation of the drawings is inferred, and thus the directional terminology used is for the purpose of illustration and not limitation. In addition, the dimensions and relative dimensions of the various layers may be exaggerated in the drawings for clarity.

Hereinafter, an array structure of a three-dimensional memory according to a first embodiment of the present invention will be described.

1A is a schematic cross-sectional view showing an array structure of a three-dimensional memory according to a first embodiment of the present invention. FIG. 1B is a schematic perspective view of the memory cell of FIG. 1A. Referring to FIG. 1A and FIG. 1B , the array structure 100 of the three-dimensional memory of the present embodiment includes a stacked structure 130 (for example, a stack of a plurality of dielectric layers 110 and a plurality of first conductive layers 120 are alternately stacked), and a second conductive layer 150 and Data storage layer 140.

There is a hole 133 in the stack structure 130 that extends through the layers of the stack structure 130. The material of the dielectric layer 110 is, for example, cerium oxide, cerium nitride, cerium oxynitride, aluminum oxide, titanium oxide, cerium oxide or a combination thereof. The material of the first conductive layer 120 is, for example, polysilicon or the like. The hole 133 at the dielectric layer 110 has a hole diameter A, and the hole 133 at the first conductive layer 120 has a hole diameter B and a hole diameter of A>B.

The second conductive layer 150 is disposed, for example, in the hole 133 in the stacked structure 130 and fills the hole 133. The material of the second conductive layer 150 is, for example, polysilicon or the like.

The data storage layer 140 is disposed, for example, between the stacked structure 130 and the second conductive layer 150. That is, the surface of the stacked structure 130 exposed by the holes 133 is provided with a data storage layer 140, and the second conductive layer 150 is filled with the holes 133 provided with the data storage layer 140. The material of the data storage layer 140 is, for example, hafnium oxide, tantalum nitride, niobium oxynitride, Alumina, titanium oxide, cerium oxide, magnesium oxide, cobalt iron boron (CoFeB), cobalt iron (CoFe), ruthenium (Ru), platinum manganese alloy (PtMn) or a combination thereof. The data storage layer 140 of the present invention can be classified into a resistive type, a magnetoresistive type, and a capacitive type according to the form of the recorded data. When the data storage layer 140 is a resistive random access memory (RRAM), the data storage layer 140 is a material that can change the resistance value by an external bias to perform writing and erasing operations, for example, It is alumina, titanium oxide, cerium oxide or a combination thereof. In addition, if the data storage layer 140 is a magnetoresistive random access memory (MRAM), the material storage layer is made of a magnetoresistive memory material such as magnesium oxide or cobalt iron boron (CoFeB). Cobalt iron (CoFe), ruthenium (Ru), platinum manganese alloy (PtMn) or a combination thereof. The data storage layer can also store the memory data by using the principle of the capacitor. For example, it can be used for a flash memory or a dynamic random access memory (DRAM), and the material thereof is, for example, hafnium oxide and nitrogen. Huayu, bismuth oxynitride or a combination thereof.

In an embodiment of the invention, the material of the dielectric layer 110 is yttrium oxide, the material of the first conductive layer 120 is polycrystalline germanium, and the material of the data storage layer 140 is titanium oxide. The dielectric layer 110, the first conductive layer 120, the data storage layer 140, and the second conductive layer 150 constitute a memory cell 160.

FIG. 1B is a schematic perspective view of the memory cell of FIG. 1A. As shown in FIG. 1B, the first conductive layer 120 is wrapped around the trench of the data storage layer 140 as a waistband. In addition, the inside of the data storage layer 140 is filled by the second conductive layer 150. The data storage layer 140 can form an angle at the change of the aperture, the angle can be a right angle or a curvature with a curvature, and the electric field is concentrated at the right angle or the bend, which can enhance the memory electronic injection. Into the speed of erasing with the hole.

Hereinafter, an array structure of a three-dimensional memory according to a second embodiment of the present invention will be described. In the second embodiment, the same components as those in the first embodiment are given the same reference numerals, and the detailed description thereof will be omitted. The following only explains the different points.

2A is a schematic cross-sectional view showing an array structure of a three-dimensional memory according to a second embodiment of the present invention. 2B is a perspective view of the memory cell of FIG. 2A. Referring to FIG. 2A and FIG. 2B, the array structure 100 of the three-dimensional memory of the present embodiment includes a stacked structure 130 (for example, a stack of a plurality of dielectric layers 110 and a plurality of first conductive layers 120), and a second conductive layer 150 and Data storage layer 140.

In the array structure of the three-dimensional memory according to the second embodiment of the present invention, the hole 133 at the dielectric layer 110 has a hole diameter A, and the hole 133 at the first conductive layer 120 has a hole diameter B and a hole diameter of A. <B. In addition, the dielectric layer 110, the first conductive layer 120, the data storage layer 140, and the second conductive layer 150 constitute a memory cell 160.

2B is a perspective view of the memory cell of FIG. 2A. As shown in FIG. 2B, the first conductive layer 120 is wrapped around the protrusion of the data storage layer 140 as a waistband. In addition, the inside of the data storage layer 140 is filled by the second conductive layer 150. The data storage layer 140 can form an angle at a change in the aperture, which can be a right angle or a curvature with a curvature, and where the right angle or the bend is an electric field concentration, the speed of the memory electron injection and the hole erasing can be improved. .

Hereinafter, an array structure of a three-dimensional memory according to a third embodiment of the present invention will be described. In the third embodiment, the same members as those of the first embodiment are given the same reference numerals, and the detailed description thereof will be omitted. The following only explains the different points.

3A is a cross-sectional view showing an array structure of a three-dimensional memory according to a third embodiment of the present invention. 3B is a perspective view of the memory cell of FIG. 3A. Referring to FIG. 3A and FIG. 3B, the array structure 100 of the three-dimensional memory of the present embodiment includes a stacked structure 130 (eg, interleaved from the plurality of first dielectric layers 110a and the plurality of second dielectric layers 110b and the plurality of first conductive layers 120). Stacked), second conductive layer 150 and data storage layer 140.

The stacked structure 130 is stacked in the order of the first dielectric layer 110a, the first conductive layer 120, the second dielectric layer 110b, and the first conductive layer 120. The stacked structure 130 has a hole 133. This hole 133 extends through the various layers of the stacked structure 130. The material of the first dielectric layer 110a is, for example, cerium oxide, cerium nitride, cerium oxynitride, aluminum oxide, titanium oxide, cerium oxide or a combination thereof. The material of the second dielectric layer 110b is, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, aluminum oxide, titanium oxide, hafnium oxide or a combination thereof, and the material of the first dielectric layer 110a and the second dielectric layer 110b. The materials are different. The material of the first conductive layer 120 is, for example, polysilicon or the like. The hole 133 at the first dielectric layer 110a has a hole diameter A1, the hole 133 at the second dielectric layer 110b has a hole diameter A2, and the hole 133 at the first conductive layer 120 has a hole diameter B and a hole diameter A1. >B=A2.

The second conductive layer 150 is disposed, for example, in the hole 133 in the stacked structure 130. The material of the second conductive layer 150 is, for example, polysilicon or the like.

The data storage layer 140 is disposed, for example, between the stacked structure 130 and the second conductive layer 150. That is, the data storage layer 140 is disposed on the surface of the exposed stacked structure 130, and the hole 133 provided with the data storage layer 140 is filled with the second conductive layer 150. The material of the data storage layer 140 is, for example, hafnium oxide, tantalum nitride, niobium oxynitride, oxidation. Aluminum, titanium oxide, cerium oxide, magnesium oxide, cobalt iron boron (CoFeB), cobalt iron (CoFe), ruthenium (Ru), platinum manganese alloy (PtMn) or a combination thereof. The method of manufacturing the data storage layer 140 is, for example, a chemical vapor deposition method.

In one embodiment of the present invention, the material of the first dielectric layer 110a is yttrium oxide, the material of the second dielectric layer 110b is tantalum nitride, the material of the first conductive layer 120 is polysilicon, and the material of the data storage layer 140 is Titanium oxide.

The first dielectric layer 110a, the second dielectric layer 110b, the first conductive layer 120, the data storage layer 140, and the second conductive layer 150 constitute a memory cell 160. Further, in an array structure of a three-dimensional memory according to a third embodiment of the present invention, the memory cell 160 is divided into two memory cells 160 by the second dielectric layer 110b.

3B is a perspective view of the memory cell of FIG. 3A. As shown in FIG. 3B, the first conductive layer 120 is wrapped around the trench of the data storage layer 140 as a waistband. In addition, the inside of the data storage layer 140 is filled by the second conductive layer 150. The data storage layer 140 can form an angle at a change in the aperture, which can be a right angle or a curvature with a curvature, and where the right angle or the bend is an electric field concentration, the speed of the memory electron injection and the hole erasing can be improved. .

Hereinafter, an array structure of a three-dimensional memory according to a fourth embodiment of the present invention will be described. In the fourth embodiment, the same components as those in the third embodiment are given the same reference numerals, and the detailed description thereof will be omitted. The following only explains the different points.

4 is a cross-sectional view showing an array structure of a three-dimensional memory according to a fourth embodiment of the present invention. Referring to FIG. 4, the array structure 100 of the three-dimensional memory of the present embodiment includes a stacked structure 130 (for example, by a plurality of first dielectric layers 110a, multiple layers, and second layers). The dielectric layer 110b is interleaved with the plurality of first conductive layers 120, the second conductive layer 150 and the data storage layer 140.

In the array structure of the three-dimensional memory of the fourth embodiment of the present invention, the aperture 133 at the first dielectric layer 110a has an aperture A1, and the aperture 133 at the second dielectric layer 110b has an aperture A2. The hole 133 at the first conductive layer 120 has a pore diameter B and a pore diameter of A1>B>A2. In addition, the first dielectric layer 110a, the second dielectric layer 110b, the first conductive layer 120, the data storage layer 140, and the second conductive layer 150 constitute a memory cell 160. Further, in an array structure of a three-dimensional memory according to a fourth embodiment of the present invention, the memory cell 160 is divided into two memory cells 160 by the second dielectric layer 110b.

Hereinafter, an array structure of a three-dimensional memory according to a fifth embodiment of the present invention will be described. In the fifth embodiment, the same components as those in the third embodiment are given the same reference numerals, and the detailed description thereof will be omitted. The following only explains the different points.

Fig. 5 is a cross-sectional view showing an array structure of a three-dimensional memory according to a fifth embodiment of the present invention. Referring to FIG. 5 , the array structure 100 of the three-dimensional memory of the present embodiment includes a stack structure 130 (eg, a plurality of first dielectric layers 110 a , a plurality of second dielectric layers 110 b , and a plurality of first conductive layers 120 are alternately stacked). ), the second conductive layer 150 and the data storage layer 140.

In the array structure of the three-dimensional memory of the fifth embodiment of the present invention, the aperture 133 at the first dielectric layer 110a has an aperture A1, and the aperture 133 at the second dielectric layer 110b has an aperture A2. The hole 133 at the first conductive layer 120 has a pore diameter B and a pore diameter of A1>A2>B. In addition, the first dielectric layer 110, The second dielectric layer 110b, the first conductive layer 120, the data storage layer 140, and the second conductive layer 150 constitute a memory cell 160. Further, in an array structure of a three-dimensional memory according to a fifth embodiment of the present invention, the memory cell 160 is divided into two memory cells 160 by the second dielectric layer 110b.

Next, a method of manufacturing the array structure of the three-dimensional memory of the present invention will be described. In this embodiment, the semiconductor element is described by taking a resistive memory as an example, but is not intended to limit the present invention.

6A to 6E are process cross-sectional views showing a method of fabricating an array structure of a three-dimensional memory according to an embodiment of the present invention. The method for fabricating the array structure of the three-dimensional memory of the present embodiment includes: forming a stacked structure 130 (FIG. 6A) formed by interleaving the dielectric layer 110 and the first conductive layer 120 on the substrate 200; removing a part of the stacked structure 130, holes 133 are formed to penetrate the layers of the stacked structure 130 (FIG. 6B); then a portion of the dielectric layer 110 or the first conductive layer 120 in the holes 133 is removed, and the holes 133 are formed in the dielectric layer 110. The first conductive layer 120 has different apertures respectively (FIG. 6C); a data storage layer 140 is formed on the surface of the hole 133 (FIG. 6D); and a second conductive layer 150 is formed to fill the hole 133 (FIG. 6E).

First, referring to FIG. 6A, a stacked structure 130 in which a dielectric layer 110 and a first conductive layer 120 are alternately stacked is formed on a substrate 200. That is, the stacked structure 130 is formed on the substrate 200 in the order of the dielectric layer 110, the first conductive layer 120, the dielectric layer 110, and the first conductive layer 120. However, the substrate 200 is not particularly limited. For example, it may be any semiconductor substrate, or may be a substrate having other film layers thereon.

The method for forming the stacked structure 130 includes the following steps. First, on the substrate 200, the dielectric layer 110 may be formed by chemical vapor deposition, thermal oxidation, or a combination thereof; then, on the substrate on which the dielectric layer 110 is stacked, The first conductive layer 120 may be formed by chemical vapor deposition; then, the stacking of the dielectric layer 110 and the first conductive layer 120 is repeated to form the stacked structure 130. The material of the dielectric layer 110 is, for example, cerium oxide, cerium nitride, cerium oxynitride, aluminum oxide, titanium oxide, cerium oxide or a combination thereof. The material of the first conductive layer 120 is, for example, polysilicon or the like.

Next, referring to FIG. 6B, the formed stacked structure 130 is patterned to form a hole 133. Specifically, the holes 133 of the stacked structure 130 are formed by forming a photoresist layer on the substrate 200 on which the stacked structure 130 is formed. Next, the stacked structure 130 on which the photoresist layer is formed is exposed so that the solubility of the photoresist of the photoresist layer changes. Then, a developing process is performed to remove a portion of the photoresist layer having a higher solubility, and a photoresist layer formed with a desired pattern is obtained as a mask. Next, an etching process is performed, and a hole 133 penetrating each layer of the stacked structure 130 can be formed by a dry etching method such as a plasma etching method. Finally, the photoresist layer is removed from the stacked structure 130 in which the holes 133 are formed.

Then, referring to FIG. 6C, the holes 133 have different apertures therein. A method of making the pores 133 have different pore diameters is, for example, a wet etching method. For example, the wafer is immersed in a suitable etchant, or an etchant is sprayed onto the wafer, and an isotropic etch is performed via a chemical reaction between the etchant and the object to be etched. Moreover, the etching degree to the dielectric layer 110 or the first conductive layer 120 can be adjusted by using an etching solution having an etch selectivity, for example, using an etching solution such as nitric acid or hydrofluoric acid to remove the portion. Dividing the dielectric layer 110 or the first conductive layer 120 such that the holes 133 have different apertures at the dielectric layer 110 and the first conductive layer 120, respectively. Wherein, the aperture at the dielectric layer 110 is A, and the aperture at the first conductive layer 120 is B. The size of the aperture can be determined according to the requirements of the product, and a single etching solution or a mixture of two or more etching liquids or a multi-step etching process can be used to form a desired aperture size. For example, as shown in FIGS. 1A and 1B, the aperture is A>B; as shown in FIGS. 2A and 2B, the aperture is A<B.

In addition, in an embodiment of the invention, as shown in FIG. 3 to FIG. 5 , the dielectric layer may be the first dielectric layer 110 a and the second dielectric layer 110 b of different materials. The etching degree of the first dielectric layer 110a, the second dielectric layer 110b and the first conductive layer 120 can be adjusted by using an etchant having an etch selectivity, for example, an etching solution such as nitric acid or hydrofluoric acid is used to remove a portion. The first dielectric layer 110a, the second dielectric layer 110b and the first conductive layer 120 have holes 133 having different apertures at the first dielectric layer 110a, the second dielectric layer 110b and the first conductive layer 120, respectively. The aperture at the first dielectric layer is A1, the aperture at the second dielectric layer is A2, and the aperture at the first conductive layer 120 is B. The size of the aperture can be determined according to the requirements of the product, and a single etching solution or a mixture of two or more etching liquids or a multi-step etching process can be used to form a desired aperture size. For example, as shown in FIGS. 3A and 3B, the aperture is A1>B=A2; as shown in FIG. 4, the aperture is A1>B>A2; as shown in FIG. 5, the aperture is A1>A2>B.

Next, referring to FIG. 6D, a material storage layer 140 is formed on the surface of the stacked structure 130 exposed by the holes 133. The method of forming the data storage layer 140 is, for example, chemistry. A vapor deposition method, a thermal oxidation method, or a combination thereof. Wherein, if the data storage layer 140 is a resistive random access memory (RRAM), the data storage layer 140 is a material that can change the resistance value by applying a bias voltage to perform writing and erasing operations. . In addition, if the data storage layer 140 is a magnetoresistive random access memory (MRAM), the data storage layer is a material for storing the memory data by the magnetoresistive quality. In addition, the data storage layer can also store memory data by using the principle of capacitance, for example, can be used for flash memory or dynamic random access memory (DRAM).

Referring to FIG. 6E, a second conductive layer 150 is formed in the hole 133. The second conductive layer 150 fills the holes 133. In addition, the material of the second conductive layer 150 is, for example, polysilicon or the like. The method of forming the second conductive layer 150 is, for example, a chemical vapor deposition method and a planarization process using chemical mechanical polishing.

In summary, the present invention provides an array structure of a three-dimensional memory and a method of fabricating the same, by forming a structure having a recess by a wet etching method, and the data storage layer can be disposed on a surface in the hole without using a seed layer, The process steps can be greatly simplified and the production cost of the memory can be reduced. In addition, the resistance value of the via electrode can be effectively reduced because the seed layer is reduced. Moreover, the electric field generation of the memory cell can be finely adjusted by increasing the area of the memory cell and controlling the shape of the memory cell through the formed recessed structure, thereby increasing the efficiency of the memory cell. For example, the use of resistive random access memory (RRAM) can effectively improve the performance of the memory cell, and will have a small formation voltage and a large on-current by increasing the memory cell area. Therefore, the array structure of the three-dimensional memory of the present invention and the manufacturing method thereof can be used for the manufacture of the next generation memory, for example Three-dimensional resistive random access memory, three-dimensional yttrium oxide/tantalum nitride/yttria/silicon flash memory (Silicon-Oxide-Nitride-Oxide-Silicon, SONOS flash) and three-dimensional magnetoresistive random access memory ( Technological developments such as Magnetoresistive Random Access Memory (MRAM) will be of great help.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Three-dimensional memory array structure

110‧‧‧ dielectric layer

120‧‧‧First conductive layer

130‧‧‧Stack structure

133‧‧‧ holes

140‧‧‧Data storage layer

150‧‧‧Second conductive layer

160‧‧‧ memory cells

A, B‧‧‧ aperture

Claims (20)

An array structure of a three-dimensional memory, comprising: a stacked structure, a structure in which a dielectric layer and a first conductive layer are alternately stacked, wherein the stacked structure has holes penetrating through layers of the stacked structure, and the holes are The dielectric layer and the first conductive layer respectively have different apertures; a second conductive layer disposed in the hole in the stacked structure; and a data storage layer disposed on the stacked structure and the Between the second conductive layers. The array structure of the three-dimensional memory according to claim 1, wherein the aperture at the dielectric layer is A, the aperture at the first conductive layer is B, and the aperture is A>B. The array structure of the three-dimensional memory according to claim 1, wherein the aperture at the dielectric layer is A, the aperture at the first conductive layer is B, and the aperture is A<B. The array structure of the three-dimensional memory of claim 1, wherein the dielectric layer further comprises a first dielectric layer and a second dielectric layer, and the stacked structure is the first dielectric layer And sequentially stacking the first conductive layer, the second dielectric layer, and the first conductive layer, and the holes are in the first dielectric layer, the second dielectric layer, and the first Each of the conductive layers has a different aperture. The array structure of the three-dimensional memory of claim 4, wherein the aperture at the first dielectric layer is A1, and the aperture at the second dielectric layer is A2, located at the The pore size at a conductive layer is B, and the pore diameter is A1>A2>B. The array structure of the three-dimensional memory of claim 4, wherein the aperture at the first dielectric layer is A1, and the aperture at the second dielectric layer is A2, located at the The pore size at a conductive layer is B, and the pore diameter is A1>B≧A2. The array structure of the three-dimensional memory according to claim 1, wherein the dielectric layer is made of cerium oxide, cerium nitride, cerium oxynitride, aluminum oxide, titanium oxide, cerium oxide or a combination thereof. The array structure of the three-dimensional memory according to the fourth aspect of the invention, wherein the material of the first dielectric layer is yttrium oxide and the material of the second dielectric layer is tantalum nitride. The array structure of the three-dimensional memory according to claim 1, wherein the material of the first conductive layer and the second conductive layer is polysilicon. A method for fabricating a three-dimensional memory array structure includes: forming a stacked structure in which a dielectric layer and a first conductive layer are alternately stacked on a substrate; removing a portion of the stacked structure to form a hole to penetrate the stacked structure Removing a portion of the dielectric layer or the first conductive layer such that the holes have different apertures at the dielectric layer and the first conductive layer; forming data on the surface of the hole a storage layer; and a second conductive layer is formed to fill the holes. The system of three-dimensional memory array structure as described in claim 10 The method wherein the pore size at the dielectric layer is A, the pore size at the first conductive layer is B, and the pore diameter is A>B. The method of fabricating a three-dimensional memory array structure according to claim 10, wherein the aperture at the dielectric layer is A, the aperture at the first conductive layer is B, and the aperture is A< B. The method of fabricating a three-dimensional memory array structure according to claim 10, wherein the dielectric layer further comprises a first dielectric layer and a second dielectric layer, and the stacked structure is the first dielectric layer The electrical layer, the first conductive layer, the second dielectric layer and the first conductive layer are stacked in the order. The method for fabricating a three-dimensional memory array structure according to claim 13, wherein the aperture at the first dielectric layer is A1, and the aperture at the second dielectric layer is A2. The aperture at the first conductive layer is B, and the aperture is A1>A2>B. The method for fabricating a three-dimensional memory array structure according to claim 13, wherein the aperture at the first dielectric layer is A1, and the aperture at the second dielectric layer is A2. The pore size at the first conductive layer is B, and the pore diameter is A1>B≧A2. The method for fabricating a three-dimensional memory array structure according to claim 10, wherein the dielectric layer is made of yttrium oxide, lanthanum nitride, lanthanum oxynitride, aluminum oxide, titanium oxide, cerium oxide or a combination thereof. . The method for fabricating a three-dimensional memory array structure according to claim 13, wherein the first dielectric layer is made of yttrium oxide, and the second dielectric layer is used. The material is tantalum nitride. The method for fabricating a three-dimensional memory array structure according to claim 10, wherein the material of the first conductive layer and the second conductive layer is polysilicon. The method of fabricating a three-dimensional memory array structure according to claim 10, wherein the method of removing a portion of the dielectric layer or the first conductive layer comprises a wet etching method. The method for fabricating a three-dimensional memory array structure according to claim 10, wherein the material storage layer is made of yttrium oxide, lanthanum nitride, yttrium oxynitride, aluminum oxide, titanium oxide, cerium oxide, magnesium oxide. Cobalt iron boron (CoFeB), cobalt iron (CoFe), ruthenium (Ru), platinum manganese alloy (PtMn) or a combination thereof.