TW201608703A - Semiconductor devices and fabrication methods with reduced topology and reduced word line stringer residual material - Google Patents

Abstract

Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a first dielectric layer over buried oxide regions and the removal of such dielectric layer to prepare a substantially planar substrate for subsequent formation of word lines. The method may allow for the production of semiconductor memory devices of reduced size with reduced word line stringer residual material.

Description

Semiconductor device and method of fabricating the same that is accompanied by reduced surface relief and reduced wordline stringer residual material 【0001】

The present invention is generally related to a structure of a semiconductor device and a method of forming the same. In particular, the present invention relates to an improved memory device and method of making such a memory device.

【0002】

A flash memory device generally includes an array of memory cells arranged in columns and columns. Each memory cell includes a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. The gate corresponds to the word line, and the drain or source corresponds to the bit line of the memory array. The gate of the conventional flash memory cell is substantially a double gate structure, and the double gate structure includes a control gate and a floating gate, wherein the floating gate is sandwiched between two dielectric layers. Between, to capture the carrier (such as electrons) to program the memory cells.

[0003]

The semiconductor industry is increasingly moving toward smaller and more performance electronic devices, such as computing devices, communication devices, and memory devices. In order to maintain or improve their respective performance while reducing the size of such devices, the dimensions of the components within the device must be reduced. However, the problem occurs with this type of reduction.

[0004]

Applicants have discovered deficiencies and problems associated with conventional processes for fabricating memory devices and memory devices made therefrom. For example, with regard to the flash memory device, when the size of the memory cell is reduced, a problem occurs that prevents further reduction in size while maintaining the performance of the memory cell and the respective functions. Traditional processes result in large surface topography on the memory cell. This change is partly due to the presence of a diffusion oxide region. When the word lines are formed and etched to the desired structure, the unwanted residual material can remain in the crevices or along the edges because of the large surface undulations. This residual material is called a "stringer". These "stringers" become a more serious problem as the size of the word lines and/or the space between those word lines decreases.

[0005]

Various problems of the discovered problems have been solved by developing efforts, ingenuity, and innovation, which are included in various embodiments of the present invention, and various embodiments of the present invention will be described in detail below.

[0006]

Thus, embodiments of the present invention provide methods of fabricating semiconductor devices useful for fabricating memory devices, particularly those that are reduced in size, and that provide semiconductor memory devices fabricated by such methods.

【0007】

SUMMARY OF THE INVENTION The present invention provides a method of fabricating a semiconductor device that has reduced surface relief and thus reduced word stringer problems, and a semiconductor memory device fabricated by such methods. The present invention provides the ability to reduce the size of a flash memory device. For example, in the embodiment of Figure 8A, after removal of the first dielectric fill material, the substrate is substantially flat. Without wishing to be bound by theory, the reduced surface relief allows subsequent deposition and formation of word lines without the formation of unwanted residual materials or "stringers".

[0008]

An aspect of the present invention provides a method of fabricating a semiconductor memory device. In a specific embodiment of the present invention, a method of fabricating a semiconductor memory device includes the steps of: providing a substrate, a buffer layer, and a hard mask layer; forming a buried diffusion region in the substrate; depositing a deposition along the substrate a first dielectric fill material; removing excess first dielectric fill material on the hard mask layer; performing self-aligned patterning to form at least one trench in the self-aligned contact region of the semiconductor Depositing a second dielectric fill material along the substrate; removing excess second dielectric fill material from the hard mask layer; removing the hard mask layer; and removing the first dielectric fill material.

【0009】

In one embodiment of the invention, a method of fabricating a semiconductor memory device includes applying a photoresist layer to at least a portion of a semiconductor prior to performing self-aligned patterning. In a particular embodiment of the invention, a method of fabricating a semiconductor memory device includes the step of removing the photoresist layer after self-aligned patterning.

[0010]

In an embodiment of the invention, a method of fabricating a semiconductor memory device may further include the step of depositing a first dielectric layer after removing the first dielectric fill material. In an embodiment of the invention, a method of fabricating a semiconductor memory device can include the step of depositing a first conductive layer along a first dielectric layer. In another embodiment of the present invention, a method of fabricating a semiconductor memory device can include the step of forming a second conductive layer along a first conductive layer. In still another embodiment of the present invention, a method of fabricating a semiconductor memory device can include the step of etching at least one word line in a semiconductor.

[0011]

In one embodiment of the invention, the buried diffusion region can be formed by implanting ions in the substrate. In a particular embodiment of the invention, the buried diffusion region can be formed by doping an n-type dopant in the substrate.

[0012]

In an embodiment of the invention, the step of depositing the first dielectric fill material may include depositing an oxide such as hafnium oxide. In an embodiment of the invention, during the removal of the excess first dielectric fill material, a chemical-mechanical polishing that causes planarization of the first dielectric fill material may be included. In an embodiment of the invention, etching may be included in the process of removing the first dielectric fill material. In a particular embodiment, the removal of the first dielectric fill material may include etching the semiconductor using an etchant that is highly selective to germanium.

[0013]

In an embodiment of the invention, the depositing of the first dielectric layer can include depositing an oxide-nitride-oxide layer. In some embodiments of the invention, depositing the first conductive layer along the first dielectric layer may include depositing polysilicon. In another embodiment of the invention, the forming of the second conductive layer may include forming a tungsten oxide layer.

[0014]

An aspect of the invention also provides a semiconductor device comprising: a substrate; a buried diffusion region in the substrate, wherein the substrate and the buried diffusion region have reduced surface relief; and are disposed along the substrate and the buried diffusion region A word line.

[0015]

According to an embodiment of the invention, the first dielectric layer may comprise an oxynitride layer. In a particular embodiment of the invention, the word line includes a first conductive layer and a second conductive layer. In accordance with certain embodiments of the present invention, the first conductive layer can comprise a polysilicon. In an embodiment of the invention, the second conductive layer may comprise tungsten telluride.

[0016]

In a particular embodiment, the buried diffusion region can include arsenic ions.

[0017]

The embodiments of the present invention, as well as other aspects and embodiments of the present invention, are further described herein, and the following description of the embodiments of the present invention will make the embodiments of the present invention and other aspects and embodiments of the present invention easier. understanding.

[0018]

Since the present invention has been roughly described, reference is now made to the accompanying drawings, in which the drawings may not be drawn

[0062]

100‧‧‧Semiconductor
110‧‧‧Substrate
120‧‧‧buffer layer
130‧‧‧Hard cover layer
140‧‧‧etched area
150‧‧‧ buried diffusion area
160‧‧‧First dielectric filling material
170‧‧‧ trench
180‧‧‧Self-aligned contact area
190‧‧‧ photoresist layer
200‧‧‧Second dielectric filling material
210‧‧‧First dielectric layer
220‧‧‧First conductive layer
230‧‧‧Second conductive layer
240‧‧‧ character line
300‧‧‧Semiconductor memory device
310, 320, 330, 340, 350, 360, 370, 380, 390, 400, 410, 420, 430, 440, 450, 500, 510, 520, 530, 540, 550, 560 ‧ ‧ steps

[0019]

1 is a cross-sectional view of a semiconductor after ion implantation in accordance with an embodiment of the present invention.
2 is a cross-sectional view of a semiconductor after depositing a first dielectric fill material in accordance with an embodiment of the present invention.
3 is a cross-sectional view of the semiconductor after removing excess first dielectric fill material in accordance with an embodiment of the present invention.
4A is a top view of a semiconductor after coating a photoresist layer, in accordance with an embodiment of the present invention.
4B-4C illustrate a semiconductor after coating a photoresist layer to at least a portion of a semiconductor and performing self-aligned patterning to form at least one trench in the self-aligned contact region, in accordance with an embodiment of the invention. Two cross-sectional views.
4D is a top view of the semiconductor after self-aligned patterning and removal of the photoresist layer, in accordance with an embodiment of the present invention.
5A-5B are two cross-sectional views of a semiconductor after deposition of a second dielectric fill material, in accordance with an embodiment of the present invention.
6A-6C are diagrams showing various regions of the semiconductor and a schematic view after removing excess second dielectric fill material in accordance with an embodiment of the present invention.
7A-7C are diagrams showing various regions of the semiconductor and a schematic view after removing the hard mask layer in accordance with an embodiment of the present invention.
8A-8C are diagrams showing various regions of the semiconductor and a schematic view after removing the first dielectric filler material in accordance with an embodiment of the present invention.
9A-9B are two cross-sectional views of a semiconductor after depositing a first dielectric layer, a first conductive layer, and a second conductive layer, in accordance with an embodiment of the present invention.
10A-10D are diagrams showing various regions of the semiconductor and a schematic view after etching a plurality of word lines in accordance with an embodiment of the present invention.
11 is a perspective view of a portion of a semiconductor after etching at least two word lines in accordance with an embodiment of the present invention.
FIG. 12 is a flow chart showing a process of forming a semiconductor memory device according to an embodiment of the invention.
FIG. 13 is a flow chart showing the process of forming a semiconductor memory device according to FIG. 12 according to an embodiment of the invention.

[0020]

Some embodiments of the invention are described more fully hereinafter with reference to the accompanying drawings. In fact, these inventions may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, the embodiments are provided to make the disclosure comply with applicable legal requirements. Like reference numerals in the present disclosure refer to like elements.

[0021]

Non-volatile memory refers to a semiconductor device that is capable of storing information even if electrical supply is removed from the memory. Non-volatile memory includes, but is not limited to, Mask Read-Only Memory, Programmable Read-Only Memory, Erasable Programmable Read -Only Memory), Electronically Erasable Programmable Read-Only Memory and Flash Memory.

[0022]

As used herein, "substrate" can include any material that can be formed below, or on which devices, circuits, epitaxial layers, or semiconductors can be formed. In general, a substrate can be used to define a layer underlying a semiconductor device or even forming a base layer of a semiconductor device. Without wishing to be limited, the substrate may comprise one or any combination of germanium, germanium, antimony, bismuth, germanium, semiconductor compounds, or other semiconductor materials.

[0023]

1 is a cross-sectional view of a semiconductor after ion implantation in accordance with an embodiment of the present invention. The illustrated semiconductor 100 includes a substrate 110, a buffer layer 120, and a hard mask layer 130. The buffer layer may include yttrium oxide (SiO ₂ ), yttrium oxynitride (SiO _x N _y ), or any combination thereof. For example, the hard mask layer can be a nitride layer such as tantalum nitride (Si ₃ N ₄ ).

[0024]

The buffer layer can be formed by any suitable deposition process, such as Chemical Vapor Deposition (CVD) or spin-on dielectric processing. The hard mask layer can be formed by any suitable process, such as a CVD or spin dielectric process. For example, the buffer layer and/or the hard mask layer can be formed by an enhanced high aspect ratio process (eHARP) chamber for chemical vapor deposition; high density plasma deposition such as high High density plasma chemical vapor deposition; Plasma Enhanced Oxide (PEOX) process; use of undoped silicon glass such as chemical vapor deposition; Deposition of tetraethoxysilane (TEOS); or deposition of high temperature oxidation (HTO) film.

[0025]

In the embodiment of FIG. 1, the hard mask layer 130 and the buffer layer 120 are etched to form an etched region 140 in the semiconductor 100. In a particular embodiment, substrate 110 can also be etched. In some embodiments, the etching can be performed by wet or dry etching. Examples of non-limiting wet etching processes include chemical vapor etching, metal assisted etching, and electroless etching. For example, chemical vapor etching can be performed using an acidic etching solution such as a mixture including nitric acid (HNO ₃ ) and/or hydrofluoric acid (HF). In a particular embodiment, the wet etch process can be a buffered oxide etch process or a buffered hydrofluoric acid process. Examples of non-limiting dry etching processes include plasma etching, sputtering etching, ionization etching, and reactive ion etching.

[0026]

Ions may then be implanted in the etched region 140 to form the buried diffusion region 150. In the embodiment of Fig. 1, the step of implanting ions (buried diffusion ("BD") implantation ("IMP") produces buried diffusion regions 150 in the substrate 110 (internal diffusion) (buried diffusion, "BD")). In a particular embodiment of the invention, the buried diffusion region can be formed by doping an n-type dopant in the substrate. For example, in some embodiments, arsenic ions can be doped in the substrate to form a buried diffusion region. In some embodiments, the substrate can be doped with phosphorus ions. In one embodiment, the composition of the dopant can be doped into the substrate. The hard mask layer 130 prevents diffusion of ions in the area covered by the hard mask layer 130.

[0027]

After the buried diffusion region 150 is formed, a first dielectric fill material may be formed along the semiconductor. 2 is a cross-sectional view of a semiconductor after depositing a first dielectric fill material in accordance with an embodiment of the present invention. In FIG. 2, a first dielectric filling material 160 (buried diffusion oxide ("BD OX") is applied on the substrate 110. The first dielectric filling material 160 may be yttrium oxide (SiO ₂ ). And any combination of bismuth oxynitride (SiO _x N _y ) or any combination thereof. In some embodiments, the first dielectric fill material may comprise one or more layers of dielectric material. In an embodiment, the first dielectric fill material substantially fills the etched region 140 and covers the buried diffusion region 150.

[0028]

The first dielectric fill material can be formed by any suitable deposition process, such as a CVD or spin dielectric process. For example, the formation of the first dielectric fill material can be achieved by an enhanced high aspect ratio process (eHARP) chamber for chemical vapor deposition; high density plasma deposition such as high density plasma. High density plasma chemical vapor deposition; Plasma Enhanced Oxide (PEOX) process; use of undoped silicon glass such as chemical vapor deposition; tetraethyl oxime Tetraethoxysilane (TEOS) deposition; or high temperature oxidation (HTO) film deposition.

[0029]

In some embodiments of the invention, excess first dielectric fill material may be removed. For example, the first dielectric fill material 160 covering the hard mask layer 130 can be removed. In a particular embodiment of the invention, the first dielectric fill material 160 overlying the hard mask layer 130 can be removed to planarize the surface of the semiconductor. 3 is a cross-sectional view of the semiconductor 100 after removal of excess first dielectric fill material 160, in accordance with an embodiment of the present invention. In a particular embodiment, the first dielectric fill material 160 can be removed by chemical mechanical polishing. As depicted in Figure 3, the hard mask layer 130 acts as a stop etch layer to prevent further grinding. In one embodiment, the excess first dielectric fill material 160 can be removed by a combination of grinding and etching steps or by an etching step alone. The etch process can be a wet or dry etch as previously defined. In some embodiments, at least a portion of the excess of the first dielectric fill material can be removed by a selective etch process, wherein the first dielectric fill material is preferably removed.

[0030]

In certain embodiments, it may be desirable to form trenches in regions of the semiconductor. In some embodiments, a plurality of trenches can be formed. In one embodiment of the invention, one or more trenches may be formed using photolithography and self-aligned patterning. Photolithography or optical lithography involves exposing and developing a photosensitive polymer or photoresist to form a three-dimensional pattern on a substrate. Typical sequences for lithography processes can include substrate preparation, coating photoresist, prebake, exposure, post-exposure bake, development, and post-baking. In general, it may be important to establish a uniform thickness of photoresist across the substrate. Alternatively, a layer of Bottom Anti-reflective Coating (BAR) may be applied to the substrate before the photoresist layer is applied. An adhesion promoter may be applied to the substrate prior to application of the photoresist.

[0031]

In accordance with certain embodiments of the present invention, self-aligned patterning can be used to form a self-aligned contact region in a semiconductor. 4A-4D illustrate steps of applying a photoresist layer to at least a portion of a semiconductor and performing self-aligned patterning to form at least one trench in the self-aligned contact region, in accordance with an embodiment of the invention. Various regions of the semiconductor and schematics in the process. In particular, FIG. 4A is a top view of the semiconductor after coating the photoresist layer in accordance with an embodiment of the present invention. 4B-4C illustrate a semiconductor after coating a photoresist layer to at least a portion of a semiconductor and performing self-aligned patterning to form at least one trench in the self-aligned contact region, in accordance with an embodiment of the invention. Two cross-sectional views. 4D is a top view of the semiconductor after self-aligned patterning and removal of the photoresist layer, in accordance with an embodiment of the present invention.

[0032]

In the embodiment of FIG. 4A, the photoresist layer 190 is applied to the semiconductor 100. This photoresist can undergo the steps of prebaking, exposure, post-exposure baking, development, and post-baking. After processing, only the particular desired portion of the semiconductor is still covered by the photoresist layer. In some embodiments, only a portion of the semiconductor is covered by the photoresist layer, while in other embodiments, several of the semiconductor are covered by the photoresist layer. Some of the substrates still covered by the photoresist layer will be protected from subsequent etching, ion implantation, and/or other processing techniques.

[0033]

In a particular embodiment of the invention, the uncovered portions of the semiconductor can be etched to form trenches 170 in the substrate 110. After etching, the photoresist can be removed leaving a self-aligned contact region in the semiconductor. FIG. 4D illustrates the self-aligned contact region 180 in the semiconductor 100. The self-aligned contact region 180 includes a trench 170 adjacent the buried diffusion region 150 and the first dielectric fill material 160.

[0034]

FIG. 4B is a cross-sectional view showing a portion of the semiconductor that is still covered by the photoresist layer during the self-aligned patterning process. As shown in FIG. 4B, the substrate 110 is not etched to form trenches. FIG. 4C illustrates etching the uncovered blocks to form trenches 170. In the embodiment of FIG. 4C, a trench 170 is formed on either side of the buried diffusion region 150. Etching can be performed by any suitable etching process, such as wet or dry etching as previously described.

[0035]

In a particular embodiment, the second dielectric fill material 200 can then be applied to the semiconductor. 5A-5B are two cross-sectional views of the semiconductor after deposition of the second dielectric fill material 200, in accordance with an embodiment of the present invention.

[0036]

FIG. 5A is a cross-sectional view showing a region still covered by the photoresist layer 190 during the self-aligned patterning process. Figure 5B is a cross-sectional view of the self-aligned contact region of the semiconductor.

[0037]

In a particular embodiment, the second dielectric fill material 200 is coated to cover at least a portion of the substrate. In the embodiment illustrated in FIG. 5B, the second dielectric fill material 200 fills the trenches 170 in the substrate 110. The second dielectric fill material 200 can be any one or any combination of cerium oxide (SiO ₂ ) and cerium oxynitride (SiO _x N _y ).

[0038]

The second dielectric fill material can be applied by any suitable deposition process. For example, the second dielectric fill material can be applied by a chemical vapor deposition process such as eHARP (enhanced high aspect ratio process) or high density plasma chemical vapor deposition. In a particular embodiment, the second dielectric fill material can be applied by a spin dielectric process. For example, an enhanced high aspect ratio process (eHARP) chamber for chemical vapor deposition; high density plasma deposition such as high density plasma chemical vapor deposition; plasma assisted oxidation (PEOX) process A second dielectric filler material is formed using undoped bismuth glass such as chemical vapor deposition; tetraethyl fluorene oxide (TEOS) deposition; or high temperature oxidation (HTO) thin film deposition.

[0039]

In some embodiments, excess second dielectric fill material can be removed. For example, the second dielectric fill material 200 covering the hard mask layer 130 can be removed. In a particular embodiment of the invention, the second dielectric fill material 200 covering the hard mask layer 130 can be removed to planarize the surface of the semiconductor. In a particular embodiment, the second dielectric fill material 200 can be removed by chemical mechanical polishing, etching, or any combination thereof. 6A-6C are diagrams showing various regions of the semiconductor and a schematic view after removing excess second dielectric fill material in accordance with an embodiment of the present invention.

[0040]

More specifically, FIG. 6A is a cross-sectional view of a region of the semiconductor 100 that is still covered by the photoresist layer during self-aligned patterning. As shown in FIG. 6A, the hard mask layer 130 prevents the first dielectric fill material from being further removed in view of the planarized surface.

[0041]

FIG. 6B is a cross-sectional view of the self-aligned contact region 180 of the semiconductor 100. 6C is a top view of the semiconductor 100 after removal of the excess second dielectric fill material 200, in accordance with an embodiment of the present invention. FIG. 6C shows the second dielectric fill material 200 and the first dielectric fill material 160 in the self-aligned contact region 180 of the semiconductor 100.

[0042]

In accordance with certain embodiments, the hard mask layer 130 can then be removed. 7A-7C are diagrams showing various regions of the semiconductor and a schematic view after removing the hard mask layer 130, in accordance with an embodiment of the present invention.

[0043]

Figure 7A is a cross-sectional view of a region still covered by a photoresist layer during self-aligned patterning. FIG. 7B is a cross-sectional view of the self-aligned contact region 180 of the semiconductor 100. FIG. 7C illustrates a top view of the semiconductor 100 after removal of the hard mask layer 130.

[0044]

As mentioned previously, the hard mask layer can be any suitable material such as tantalum nitride, which prevents diffusion of ions in the coverage area. The hard mask layer also prevents further grinding of the first dielectric fill material in view of the planarized surface. The hard mask layer can be removed by any suitable removal method such as chemical mechanical polishing, etching, or any combination thereof.

[0045]

In a particular embodiment of the invention, the first dielectric fill material can then be removed. In some embodiments, removing the first dielectric fill material provides substantially planarized surface relief. In an embodiment, the buffer layer can be removed along with the first dielectric fill material. 8A-8C are diagrams showing various regions of the semiconductor and a schematic view after removing the first dielectric filling material and the buffer layer, in accordance with an embodiment of the present invention.

[0046]

In particular, Figure 8A depicts a cross-sectional view of a region still covered by a photoresist layer during self-aligned patterning. FIG. 8B is a cross-sectional view of the self-aligned contact region 180 of the semiconductor 100. FIG. 8C is a top view of the semiconductor 100 after the first dielectric fill material 160 and the buffer layer 120 are removed, in accordance with an embodiment of the present invention.

[0047]

The first dielectric fill material can be removed by any suitable method. For example, the first dielectric fill material can be removed by etching, such as wet etching or dry etching, or by chemical mechanical polishing. In some embodiments, the first dielectric fill material can be removed by etching and chemical mechanical polishing. In a particular embodiment, the first dielectric fill material can be removed by a selective etching process. For example, in embodiments where the first dielectric fill material comprises ruthenium oxide, the etch process can have a high selectivity to ruthenium.

[0048]

In some embodiments, the buffer layer 120 can be removed along with the first dielectric fill material 160. In other embodiments, the buffer layer can be partially removed along with the first dielectric fill material and the buffer layer can be completely removed by subsequent processes. The buffer layer can be removed by any suitable removal method such as chemical mechanical polishing, etching, or any combination thereof.

[0049]

In the embodiment of Figure 8A, removing the first dielectric fill material and the buffer layer results in substantially flat surface relief. In the flash memory device, when the size of the memory cell of the flash memory device is reduced, a problem occurs that prevents further reduction in size while maintaining the performance of the memory cell and the respective functions. The traditional process causes large surface undulations on the memory cell. This change is partly due to the presence of buried diffusion oxidation zones. When the word lines are formed and etched to the desired structure, unwanted large amounts of material can remain in or along the crevices because of the large surface undulations. This residual material is called a "stringer".

[0050]

SUMMARY OF THE INVENTION The present invention provides a method of fabricating a semiconductor device that has reduced surface relief and thus reduced word stringer problems, and a semiconductor memory device fabricated by such methods. The present invention provides the ability to reduce the size of a flash memory device. For example, in the embodiment of Figure 8A, after removal of the first dielectric fill material, the substrate is substantially flat. Without wishing to be bound by theory, the reduced surface relief allows subsequent deposition and formation of word lines without the formation of unwanted residual materials or "stringers".

[0051]

In a particular embodiment of the invention, the first dielectric layer can be removed. In a particular embodiment, the first conductive layer and the second conductive layer can then be removed. 9A-9B are two cross-sectional views of the semiconductor 100 after depositing the first dielectric layer 210, the first conductive layer 220, and the second conductive layer 230, in accordance with an embodiment of the present invention. These layers can be formed by any suitable deposition process, such as CVD or spin coating. For example, an enhanced high aspect ratio process (eHARP) chamber for chemical vapor deposition; high density plasma deposition such as high density plasma chemical vapor deposition; plasma assisted oxidation (PEOX) process The first dielectric layer is formed using undoped bismuth glass such as chemical vapor deposition; tetraethyl fluorene oxide (TEOS) deposition; or high temperature oxidation (HTO) thin film deposition.

[0052]

The first dielectric layer 210 can be any suitable dielectric such as hafnium oxide (SiO ₂ ), hafnium nitride (Si ₃ N ₄ ), hafnium oxynitride (SiO _x N _y ), or any combination thereof. In the embodiment illustrated in FIG. 9A, the first dielectric layer includes an oxygen oxynitride (ONO) layer. The first conductive layer can comprise any suitable electrically conductive material such as polysilicon. In the embodiment illustrated in FIG. 9A, the conductive layer comprises polysilicon. The second conductive layer can comprise any suitable electrically conductive material such as a metal silicide. For example, the second conductive layer can include a telluride, titanium telluride, cobalt telluride, nickel telluride, platinum telluride, tungsten telluride, or any combination thereof. In the embodiment illustrated in FIG. 9A, the second conductive layer comprises tungsten telluride.

[0053]

In a particular embodiment of the invention, one or more word lines can be etched into the semiconductor. 10A-10D are diagrams showing various regions of the semiconductor 100 and a schematic view after etching a plurality of word lines 240, in accordance with an embodiment of the present invention.

[0054]

In particular, FIG. 10A depicts a cross-sectional view of a region that is still covered by a photoresist layer and includes word lines 240 during self-aligned patterning. FIG. 10B is a cross-sectional view showing a region that is still covered by the photoresist layer during self-aligned patterning and that does not include word lines after etching. FIG. 10C illustrates a cross-sectional view of the self-aligned contact region 180 of the semiconductor 100 after etching the word line 240.

[0055]

FIG. 10D is a top view of the semiconductor after etching the word line 240, in accordance with an embodiment of the present invention. The word line 240 can be etched by any suitable process, such as wet or dry etching. In the embodiment of FIG. 10D, the etched word line 240 is perpendicular to the buried diffusion region 150.

[0056]

11 is a perspective view of a portion of a semiconductor after etching at least two word lines in accordance with an embodiment of the present invention. In the embodiment of FIG. 11, the word line 240 including the first conductive layer 220 and the second conductive layer 230 is etched perpendicular to the buried diffusion region 150.

[0057]

FIG. 12 is a flow chart showing a process of forming a semiconductor memory device 300 in accordance with an embodiment of the invention. In an exemplary embodiment of the invention, a method of forming a semiconductor memory device includes the step 310 of providing a substrate, a buffer layer, and a hard mask layer. The method shown in FIG. 12 further includes a step 320 of forming a buried diffusion region in the substrate, a step 330 of depositing a first dielectric filling material along the substrate, and removing an excess of the first dielectric on the hard mask layer. Step 340 of filling the material. In a particular embodiment, the step of forming a buried diffusion region in the substrate can include doping the substrate with an n-type dopant, as shown in optional step 500. In a particular embodiment, the step of depositing a first dielectric fill material along the substrate can include depositing ruthenium oxide, as shown in optional step 510. In a particular embodiment, the step of removing excess first dielectric fill material on the hard mask layer can include chemical mechanically grinding the first dielectric fill material, as shown in optional step 520. The embodiment illustrated in FIG. 12 further includes a step 350 of applying a photoresist layer to at least a portion of the semiconductor, performing self-aligned patterning to form at least one trench in the self-aligned contact region of the semiconductor. Step 360 and step 370 of removing the photoresist layer. The method illustrated in Figure 12 further includes the step 380 of depositing a second dielectric fill material along the substrate.

[0058]

FIG. 13 is a flow chart showing the process of forming a semiconductor memory device according to FIG. 12 according to an embodiment of the invention. In an exemplary embodiment of the present invention shown in FIG. 13, a method of forming a semiconductor memory device further includes the step 390 of removing excess second dielectric fill material on the hard mask layer, and removing the hard mask. Step 400 of the layer and step 410 of removing the first dielectric fill material. In a particular embodiment, the step of removing the first dielectric fill material can include etching the semiconductor using an etchant that is highly selective to germanium, as depicted by optional step 530. The method illustrated in FIG. 13 further includes a step 420 of depositing a first dielectric layer. In a particular embodiment, the step of depositing the first dielectric layer can include depositing an oxynitride layer, as depicted by optional step 540. In addition, the word lines formed in this embodiment are performed by a step 430 of depositing a first conductive layer along a first dielectric layer, a step 440 of depositing a second conductive layer along a first conductive layer, and etching in a semiconductor. Step 450 of at least one word line. In a particular embodiment, the step of depositing the first conductive layer along the first dielectric layer can include depositing polysilicon along the first dielectric layer, as depicted by optional step 550. In a particular embodiment, the step of depositing a second conductive layer along the first conductive layer can include depositing tungsten carbide along the first conductive layer, as depicted by optional step 560. The method of the present invention may include various combinations of steps illustrated in Figures 12 and 13.

[0059]

The invention is applicable to any suitable semiconductor fabrication. For example, the method of the present invention can be applied to fabricate any non-volatile memory device. For example, the method can be applied to the manufacture of Nbit memory cells.

[0060]

One aspect of the present invention provides a semiconductor having a memory cell which is fabricated using a process or method for fabricating a semiconductor having a memory cell of the present invention. In other specific embodiments of the invention, the semiconductor device can be fabricated using any of the methods described herein.

[0061]

Many modifications and other embodiments of the inventions set forth herein will be apparent to those skilled in the <RTIgt; Therefore, the invention is to be understood as not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are used herein, they are used in a generic and descriptive sense and not for the purpose of limitation.

310, 320, 330, 340, 350, 360, 370, 380, 500, 510, 520 ‧ ‧ steps

Claims (20)

[Item 1] A method of fabricating a semiconductor memory device, comprising:
Providing a substrate, a buffer layer and a hard mask layer;
Forming a buried diffusion region in the substrate;
Depositing a first dielectric filling material along the substrate;
Removing excess of the first dielectric filler material on the hard mask layer;
Performing self-aligned patterning to form at least one trench in one of the semiconductor memory devices in the self-aligned contact region;
Depositing a second dielectric fill material along the substrate;
Removing excess second dielectric fill material on the hard mask layer;
Removing the hard mask layer; and removing the first dielectric fill material. [Item 2] The method of claim 1, further comprising applying a photoresist layer to at least a portion of the semiconductor prior to performing self-aligned patterning. [Item 3] The method of claim 2, further comprising removing the photoresist layer after performing self-aligned patterning. [Item 4] The method of claim 1, further comprising depositing a first dielectric layer after removing the first dielectric fill material. [Item 5] The method of claim 4, further comprising depositing a first conductive layer along the first dielectric layer. [Item 6] The method of claim 5, further comprising depositing a second conductive layer along the first conductive layer. [Item 7] The method of claim 6, further comprising etching at least one word line in the semiconductor. [Item 8] The method of claim 1, wherein the buried diffusion region is formed by doping an n-type dopant in the substrate. [Item 9] The method of claim 1, wherein the step of depositing the first dielectric filler material comprises depositing yttrium oxide. [Item 10] The method of claim 1, wherein the step of removing excess of the first dielectric fill material comprises chemical mechanical polishing to planarize the first dielectric fill material. [Item 11] The method of claim 1, wherein the removing the first dielectric fill material comprises etching the semiconductor using an etchant having a high selectivity to germanium. [Item 12] The method of claim 4, wherein the depositing the first dielectric layer comprises depositing an oxide-nitride-oxide layer. [Item 13] The method of claim 5, wherein the step of depositing the first conductive layer along the first dielectric layer comprises depositing polysilicon. [Item 14] The method of claim 6, wherein the depositing the second conductive layer comprises depositing tungsten telluride. [Item 15] A semiconductor device comprising:
a substrate;
An embedded diffusion region is disposed in the substrate, wherein the substrate and the buried diffusion region have a reduced surface topography; and a word line disposed along the substrate and the buried diffusion region. [Item 16] The semiconductor device of claim 15, wherein the word line comprises a first conductive layer and a second conductive layer. [Item 17] The semiconductor device of claim 15, wherein the buried diffusion region comprises arsenic ions. [Item 18] The semiconductor device of claim 16, wherein the first dielectric layer comprises an oxygen oxynitride layer. [Item 19] The semiconductor device of claim 16, wherein the first conductive layer comprises polysilicon. [Item 20] The semiconductor device of claim 16, wherein the second conductive layer comprises tungsten telluride.