TW201600651A - Semiconductor device, layered semiconductor device, sealed-then-layered semiconductor device, and manufacturing methods therefor - Google Patents

Semiconductor device, layered semiconductor device, sealed-then-layered semiconductor device, and manufacturing methods therefor Download PDF

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Publication number
TW201600651A
TW201600651A TW104110257A TW104110257A TW201600651A TW 201600651 A TW201600651 A TW 201600651A TW 104110257 A TW104110257 A TW 104110257A TW 104110257 A TW104110257 A TW 104110257A TW 201600651 A TW201600651 A TW 201600651A
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Taiwan
Prior art keywords
insulating layer
semiconductor device
electrode
semiconductor element
forming
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TW104110257A
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Chinese (zh)
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TWI648438B (en
Inventor
Katsuya Takemura
Kyoko Soga
Satoshi Asai
Kazunori Kondo
Michihiro Sugo
Hideto Kato
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Shinetsu Chemical Co
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    • H—ELECTRICITY
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • C08L83/00—Compositions of macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon only; Compositions of derivatives of such polymers
    • C08L83/14—Compositions of macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon only; Compositions of derivatives of such polymers in which at least two but not all the silicon atoms are connected by linkages other than oxygen atoms
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    • C09D183/00—Coating compositions based on macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon, with or without sulfur, nitrogen, oxygen, or carbon only; Coating compositions based on derivatives of such polymers
    • C09D183/14—Coating compositions based on macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon, with or without sulfur, nitrogen, oxygen, or carbon only; Coating compositions based on derivatives of such polymers in which at least two but not all the silicon atoms are connected by linkages other than oxygen atoms
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/10431—Details of mounted components
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    • H05K2201/10515—Stacked components

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Abstract

This invention is a semiconductor device that contains a semiconductor element. Said semiconductor device also contains an above-semiconductor-element metal pad and metal wiring, both of which are electrically connected to the semiconductor element. The metal wiring is electrically connected to a through-electrode and a solder bump. The semiconductor device has a first insulating layer on which the semiconductor element is placed, a second insulating layer formed on top of the semiconductor element, and a third insulating layer formed on top of the second insulating layer. The metal wiring is electrically connected to the semiconductor element via the above-semiconductor-element metal pad on the top surface of the second insulating layer and passes through the second insulating layer from the top surface thereof to electrically connect to the abovementioned through-electrode on the bottom surface of the second insulating layer. This results in a semiconductor device that is easy to place on a circuit board, is easy to stack, and exhibits minimal warpage even if the density of the metal wiring is high.

Description

半導體裝置、層合型半導體裝置、封裝後層合型半導體裝置及此等之製造方法 Semiconductor device, laminated semiconductor device, packaged laminated semiconductor device, and manufacturing method therefor

本發明係關於半導體裝置、層合型半導體裝置、封裝後層合型半導體裝置、及此等之製造方法。 The present invention relates to a semiconductor device, a laminated semiconductor device, a packaged laminated semiconductor device, and a method of manufacturing the same.

伴隨著個人電腦、數位相機、行動電話等各種的電子機器之小型化或高性能化，對於半導體元件之更加小型化、薄型化及高密度化的要求亦急速高漲。因此，期望開發可對應於生產性提昇之基板面積的增大，且在晶片尺寸封裝或晶片規模封裝(CSP)或者立體層合之高密度安裝技術中能夠對應的感光性絕緣材料或加以層合之半導體裝置、其製造方法。 With the miniaturization and high performance of various electronic devices such as personal computers, digital cameras, and mobile phones, the demand for further miniaturization, thinning, and high density of semiconductor devices has been rapidly increasing. Therefore, it is desirable to develop a photosensitive insulating material which can be corresponding to an increase in substrate area which is compatible with productivity improvement, and which can be correspondingly used in wafer size packaging or wafer scale packaging (CSP) or high-density mounting technology of three-dimensional lamination. A semiconductor device and a method of manufacturing the same.

以往，作為將形成於半導體元件上之電極與基板上形成的配線圖型連接所得之半導體裝置的製造方法，係可列舉以線結合所致之半導體元件與基板之接合為例。然而，於以線結合所致之半導體元件與基板之接合中，係必須於半導體元件上配置將金屬線拉出的空間，因此裝置會變大，而難以謀求小型化。 Conventionally, as a method of manufacturing a semiconductor device in which an electrode formed on a semiconductor element and a wiring pattern formed on a substrate are connected, a bonding of a semiconductor element and a substrate by wire bonding is exemplified. However, in the bonding of the semiconductor element and the substrate by the wire bonding, it is necessary to arrange a space in which the metal wire is pulled out on the semiconductor element, so that the device becomes large and it is difficult to achieve miniaturization.

另一方面，於專利文獻1、2中揭示出不使用線結合而將半導體元件載置於配線基板的例子，或將半導體元件載置於立體層合並施以配線之基板的方法。 On the other hand, Patent Documents 1 and 2 disclose an example in which a semiconductor element is placed on a wiring board without using wire bonding, or a method in which a semiconductor element is placed on a substrate in which a three-dimensional layer is combined and a wiring is applied.

於專利文獻1中係揭示出具有如受光元件或發光元件般之半導體元件的半導體裝置之製造方法的例子，如第25圖所示般，半導體裝置50係經由貫穿電極56來將Al電極墊55與再配線圖型52進行連接，並將半導體裝置之再配線圖型52與配線基板53上之再配線圖型57經由焊錫凸塊58進行連接的例子。 Patent Document 1 discloses an example of a method of manufacturing a semiconductor device having a semiconductor element such as a light-receiving element or a light-emitting element. As shown in FIG. 25, the semiconductor device 50 is provided with an Al electrode pad 55 via a through electrode 56. The rewiring pattern 52 is connected, and the rewiring pattern 52 of the semiconductor device and the rewiring pattern 57 on the wiring substrate 53 are connected via the solder bumps 58.

於半導體裝置的上面係形成有裝置形成層59與複數個Al電極墊55。於Al電極墊55與再配線圖型52之間係藉由乾蝕刻而設置有貫穿半導體裝置之貫穿孔54，於貫穿孔54的內部係藉由Cu鍍敷而形成有貫穿電極56。裝置形成層59係配置於半導體裝置的上面，進行受光或發光。 A device formation layer 59 and a plurality of Al electrode pads 55 are formed on the upper surface of the semiconductor device. A through hole 54 penetrating the semiconductor device is provided between the Al electrode pad 55 and the rewiring pattern 52 by dry etching, and a through electrode 56 is formed by Cu plating inside the through hole 54. The device formation layer 59 is disposed on the upper surface of the semiconductor device to receive or emit light.

依據此方法，雖可進行以線結合所致之半導體元件51與配線基板53的接合，但必須於半導體裝置上實施再配線，且配置焊錫凸塊，使伴隨著半導體裝置之小型化的再配線之微細化、焊錫凸塊之高密度化成為必要，而在實際面上遭遇困難。 According to this method, the semiconductor element 51 and the wiring substrate 53 can be bonded by wire bonding. However, it is necessary to perform rewiring on the semiconductor device, and the solder bumps are disposed to re-wiring the semiconductor device. The miniaturization and the high density of the solder bumps are necessary, and it is difficult to encounter the actual surface.

另一方面，於專利文獻2中係揭示出可用於複數個半導體元件之立體層合的半導體裝置之製造方法，如第26圖所示般，例示將半導體元件180與半導體元件280進行層合的結構。 On the other hand, Patent Document 2 discloses a method of manufacturing a semiconductor device which can be used for three-dimensional lamination of a plurality of semiconductor elements, and as shown in FIG. 26, exemplifies lamination of the semiconductor element 180 and the semiconductor element 280. structure.

加以層合的各半導體元件，係於具有芯基材(150、250)、貫穿電極(140、240)與配線層(157、257)的基板(110、210)上，經由焊錫凸塊(170、270)與半導體元件之墊(182、282)而接合有半導體元件(180、280)者。又，配線層(157、257)係具有安裝墊(165、265)、連接墊(164、264)、以及配線(266)。再者，於基板(110、210)之最表面與半導體元件(180、280)之間係填充有底部填充材(184、284)。於專利文獻2中揭示出將如此之接合有半導體元件的基板經由焊錫凸塊(174、176)來進行接合並層合的方法。 Each of the semiconductor elements to be laminated is attached to a substrate (110, 210) having a core substrate (150, 250), a through electrode (140, 240), and a wiring layer (157, 257) via a solder bump (170). 270) A semiconductor element (180, 280) is bonded to the pads (182, 282) of the semiconductor element. Further, the wiring layers (157, 257) have mounting pads (165, 265), connection pads (164, 264), and wiring (266). Further, an underfill (184, 284) is filled between the outermost surface of the substrate (110, 210) and the semiconductor element (180, 280). Patent Document 2 discloses a method in which a substrate on which a semiconductor element is bonded is bonded and laminated via solder bumps (174, 176).

然而，於專利文獻2中，由於是將半導體元件藉由焊錫凸塊來接合於配線基板，因此與專利文獻1相同地，使伴隨著半導體元件之小型化的焊錫凸塊之高密度化成為極重要的一環，而實際上亦遭遇困難。又，設置於第2基板210之貫穿電極的形成係存在有其步驟煩雜且並非容易的問題點。 However, in Patent Document 2, since the semiconductor element is bonded to the wiring board by solder bumps, the density of the solder bumps which are reduced in size with the semiconductor element is increased in the same manner as in Patent Document 1. An important part, but actually encountered difficulties. Moreover, the formation of the through electrodes provided on the second substrate 210 has a problem that the steps are cumbersome and not easy.

又，於專利文獻3係揭示出將載置於配線基板的半導體裝置或其製造方法或者將半導體元件組裝於層合結構的半導體裝置或其製造方法的例子。於專利文獻3中係如第27圖所示般，揭示出一種半導體裝置，或將此半導體裝置載置於配線基板的半導體裝置、將複數個半導體元件進行層合的半導體裝置之製造方法，該半導體裝置係包含：有機基板301、在厚度方向貫穿有機基板301之貫穿孔304、設置於有機基板301之兩面，且電連接於貫 穿孔304之外部電極305b及內部電極305a、經由接著層303以元件電路面為上來搭載於有機基板301之其中一方的主面上之半導體元件302、將半導體元件302及其周邊進行封裝之絕緣材料層306、設置於絕緣材料層306內，且其一部分露出於外部表面之金屬薄膜配線層307、電連接於金屬薄膜配線層307之金屬孔310、配線保護膜311、與形成於金屬薄膜配線層307上之外部電極309，且金屬薄膜配線層307係具有將配置於半導體元件302之元件電路面的電極、內部電極305a、金屬孔310、與形成於金屬薄膜配線層307上的外部電極309電連接的結構。依據專利文獻3，無須於半導體元件上形成多數個焊錫凸塊，可於半導體元件上形成多數個電極，而成為能夠與高密度化相對應地進行半導體裝置之小型化。 Further, Patent Document 3 discloses an example of a semiconductor device mounted on a wiring board, a method of manufacturing the same, or a semiconductor device in which a semiconductor element is incorporated in a laminated structure or a method of manufacturing the same. According to Patent Document 3, as shown in FIG. 27, a semiconductor device, a semiconductor device in which the semiconductor device is placed on a wiring substrate, and a method of manufacturing a semiconductor device in which a plurality of semiconductor elements are laminated are disclosed. The semiconductor device includes an organic substrate 301, a through hole 304 penetrating the organic substrate 301 in the thickness direction, and both surfaces of the organic substrate 301, and is electrically connected to each other. The external electrode 305b and the internal electrode 305a of the through hole 304, the semiconductor element 302 mounted on one of the main surfaces of the organic substrate 301 via the element layer surface of the via layer 303, and the insulating material for encapsulating the semiconductor element 302 and its periphery The layer 306 is disposed in the insulating material layer 306, and a portion thereof is exposed on the outer surface of the metal thin film wiring layer 307, the metal hole 310 electrically connected to the metal thin film wiring layer 307, the wiring protective film 311, and the metal thin film wiring layer. The external electrode 309 on the 307, and the metal thin film wiring layer 307 has an electrode, an internal electrode 305a, a metal hole 310, and an external electrode 309 formed on the metal thin film wiring layer 307, which are disposed on the element circuit surface of the semiconductor element 302. The structure of the connection. According to Patent Document 3, it is not necessary to form a plurality of solder bumps on the semiconductor element, and a plurality of electrodes can be formed on the semiconductor element, and the semiconductor device can be downsized in accordance with the increase in density.

然而，不可否認於上述專利文獻3所記載之半導體裝置的結構體中，對於配線基板之貫穿孔304的形成係有加工困難的情形。雖可例示使用了微細鑽孔之加工或雷射加工，但在期望更進一步之半導體裝置的微細化之際，並不能說是理想的加工技術。 However, it is undeniable that in the structure of the semiconductor device described in Patent Document 3, the formation of the through hole 304 of the wiring substrate is difficult to process. Although processing using a fine drilling or laser processing can be exemplified, it is not an ideal processing technique when further miniaturization of a semiconductor device is desired.

又，於專利文獻3中，係如第28圖所示般，將塗佈於半導體元件表層的感光性樹脂層316進行圖型化，形成開口317，藉此製成形成於半導體元件302上之孔部308。進而，形成於半導體元件之周邊的絕緣材料層306係使用旋轉塗佈等來形成。然而，實際上由於將感光性樹脂層316塗佈於半導體元件302表層的步驟、與於半 導體元件302周邊形成絕緣材料層306的步驟，2次都必須供給樹脂，因此步驟煩雜，又，在以旋轉塗佈進行絕緣材料層306之供給的情況中，半導體元件302的高度係為重要，在如超過數十μm般之高度時，要越過半導體元件而不產生間隙地供給絕緣材料層306實際上係有困難。再者，雖例示出藉由另外的步驟來進行感光性樹脂層316之孔部308的形成與絕緣材料層306之金屬孔310的形成之例子，或藉由雷射等來進行金屬孔310的加工之例子，但此等之步驟係為煩雜，且並不合理。進而，雖可將感光性樹脂層316與絕緣材料層306同時供給至半導體元件302周邊部及電路形成面，但實際上並無具體的方法之例示，於半導體元件周邊不產生間隙地供給此等之樹脂層一事係有困難。又，雖亦有同時進行感光性樹脂層316之孔部308與絕緣材料層306之金屬孔310的形成，但針對具體的方法並無記載。 Further, in Patent Document 3, as shown in FIG. 28, the photosensitive resin layer 316 applied to the surface layer of the semiconductor element is patterned to form an opening 317, thereby being formed on the semiconductor element 302. Hole portion 308. Further, the insulating material layer 306 formed on the periphery of the semiconductor element is formed by spin coating or the like. However, in actuality, the step of applying the photosensitive resin layer 316 to the surface layer of the semiconductor element 302 is The step of forming the insulating material layer 306 around the conductor element 302 requires the resin to be supplied twice, so the steps are cumbersome, and in the case where the insulating material layer 306 is supplied by spin coating, the height of the semiconductor element 302 is important. When the height is more than several tens of μm, it is actually difficult to supply the insulating material layer 306 beyond the semiconductor element without generating a gap. Further, an example in which the formation of the hole portion 308 of the photosensitive resin layer 316 and the formation of the metal hole 310 of the insulating material layer 306 is performed by another step, or the metal hole 310 is performed by laser or the like. Examples of processing, but such steps are cumbersome and unreasonable. Further, although the photosensitive resin layer 316 and the insulating material layer 306 can be simultaneously supplied to the peripheral portion of the semiconductor element 302 and the circuit forming surface, there is no specific method, and the gap is not supplied to the periphery of the semiconductor element. The resin layer is difficult to handle. Further, although the hole portion 308 of the photosensitive resin layer 316 and the metal hole 310 of the insulating material layer 306 are simultaneously formed, there is no description for a specific method.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本特開2007-67016號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2007-67016

[專利文獻2]日本特開2010-245509號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2010-245509

[專利文獻3]日本特開2013-30593號公報 [Patent Document 3] Japanese Patent Laid-Open Publication No. 2013-30593

本發明係鑑於上述情事而完成者，其目的為提供一種對於配線基板之載置或半導體裝置之層合為容易，且即使於金屬配線之密度大的情況中半導體裝置之翹曲亦受到抑制的半導體裝置。 The present invention has been made in view of the above circumstances, and an object thereof is to provide an easy mounting of a wiring substrate or a semiconductor device, and suppressing warpage of a semiconductor device even when the density of the metal wiring is large. Semiconductor device.

又，其目的為提供一種在製造如此之半導體裝置時，能夠容易進行貫穿電極、電極墊部之開口等的加工之半導體裝置之製造方法。 Moreover, it is an object of the invention to provide a method of manufacturing a semiconductor device which can easily perform processing such as an opening of an electrode or an electrode pad portion when manufacturing such a semiconductor device.

進而，其目的為提供將如此之半導體裝置進行層合之層合型半導體裝置、將其載置於配線基板上並予以封裝的封裝後層合型半導體裝置、及此等之製造方法。 Further, an object of the present invention is to provide a laminated semiconductor device in which such a semiconductor device is laminated, a packaged laminated semiconductor device mounted on a wiring substrate, and a packaged laminated semiconductor device, and the like.

為了解決上述課題，於本發明中係提供一種半導體裝置，其係具有半導體元件、與電連接於該半導體元件之半導體元件上金屬墊及金屬配線，且該金屬配線係電連接於貫穿電極及焊錫凸塊，具有：載置前述半導體元件之第一絕緣層、形成於前述半導體元件上之第二絕緣層、以及形成於該第二絕緣層上之第三絕緣層，前述金屬配線係在前述第二絕緣層的上面經由前述半導體元件上金屬墊而電連接於前述半導體元件，且從前述第二絕緣層的上面貫穿前述第二絕緣層而在前述第二絕緣層的下面電連接於前述貫穿電極。 In order to solve the above problems, the present invention provides a semiconductor device including a semiconductor element, a metal pad and a metal wiring electrically connected to the semiconductor element, and the metal wiring is electrically connected to the through electrode and the solder. The bump includes: a first insulating layer on which the semiconductor element is placed, a second insulating layer formed on the semiconductor element, and a third insulating layer formed on the second insulating layer, wherein the metal wiring is in the foregoing The upper surface of the second insulating layer is electrically connected to the semiconductor element via the metal pad on the semiconductor element, and penetrates from the upper surface of the second insulating layer to the second insulating layer and is electrically connected to the through electrode under the second insulating layer .

若為如此之半導體裝置，則藉由於半導體元 件上實施微細的電極形成，並於半導體元件外部形成貫穿電極，而使對於配線基板之載置或半導體裝置之層合為容易，又，藉由於第二絕緣層的兩面形成金屬配線，而成為即使在金屬配線的密度為大之情況中半導體裝置之翹曲亦受到抑制的半導體裝置。 If it is such a semiconductor device, it is due to the semiconductor element Fine electrode formation is performed on the device, and a through electrode is formed on the outside of the semiconductor element, and it is easy to laminate the wiring substrate or the semiconductor device, and the metal wiring is formed on both surfaces of the second insulating layer. A semiconductor device in which warpage of a semiconductor device is suppressed even in a case where the density of the metal wiring is large.

又，此時，較佳為前述第一絕緣層係藉由光硬化性乾膜或光硬化性阻劑塗佈膜所形成者，前述第二絕緣層係藉由前述光硬化性乾膜所形成者，前述第三絕緣層係藉由前述光硬化性乾膜或光硬化性阻劑塗佈膜所形成者。 Further, in this case, it is preferable that the first insulating layer is formed of a photocurable dry film or a photocurable resist coating film, and the second insulating layer is formed by the photocurable dry film. The third insulating layer is formed by the photocurable dry film or the photocurable resist coating film.

藉此，成為即使半導體元件之高度為數十μm亦可無空隙等地埋填於半導體元件周邊的半導體裝置。 Thereby, even if the height of the semiconductor element is several tens of μm, the semiconductor device can be buried in the periphery of the semiconductor element without voids or the like.

又，此時，較佳為前述半導體元件的高度為20~100μm，前述第一絕緣層的膜厚為1~20μm，前述第二絕緣層的膜厚為5~100μm，前述第三絕緣層的膜厚為5~100μm，前述半導體裝置的厚度為50~300μm。 Further, in this case, it is preferable that the height of the semiconductor element is 20 to 100 μm, the thickness of the first insulating layer is 1 to 20 μm, and the thickness of the second insulating layer is 5 to 100 μm, and the third insulating layer is The film thickness is 5 to 100 μm, and the thickness of the semiconductor device is 50 to 300 μm.

藉此，可無空隙等地埋填於半導體元件的周邊，且成為薄型之半導體裝置。 Thereby, it is possible to embed the periphery of the semiconductor element without voids or the like, and to form a thin semiconductor device.

又，此時，較佳為前述光硬化性乾膜係具有由化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層之光硬化性乾膜，該化學增幅型負型阻劑組成物材料係含有：(A)具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物、 (式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基，Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；h為0、1、2中之任一者)(B)由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑、(C)藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑、以及(D)溶劑。 Moreover, in this case, it is preferable that the photocurable dry film has a photocurable dry film of a photocurable resin layer composed of a chemically amplified negative resist composition material, and the chemically amplified negative resist The composition material contains: (A) a polymer compound having an fluorenone skeleton having a weight average molecular weight of 3,000 to 500,000, which has a repeating unit represented by the following general formula (1), (wherein R 1 to R 4 represent a monovalent hydrocarbon group having the same or different carbon number of 1 to 8; m is an integer of 1 to 100; a, b, c, and d are 0 or a positive number, and a, b, c, and d are not 0 at the same time; however, a+b+c+d=1; further, X is an organic group represented by the following general formula (2), and Y is represented by the following general formula (3). Organic basis (where, Z is composed of The divalent organic group selected by any one of them, n is 0 or 1; each of R 5 and R 6 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; k is Any of 0, 1, 2) (where, V is composed of The divalent organic group selected by any one of them, p is 0 or 1; each of R 7 and R 8 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; h is Any one of 0, 1, 2) (B) an amine condensate modified by formaldehyde or formaldehyde-alcohol, having an average of 2 or more methylol groups or alkoxyl groups in one molecule One or two or more kinds of crosslinking agents selected from the group consisting of phenolic compounds, and (C) are decomposed by light having a wavelength of from 190 to 500 nm to produce an acid photoacid generator and (D) a solvent.

藉此，成為可進一步抑制翹曲的半導體裝置。 Thereby, it becomes a semiconductor device which can suppress a warpage further.

又，於本發明中係提供一種將上述半導體裝置倒裝晶片化並複數層合而成的層合型半導體裝置。 Further, in the present invention, a laminated semiconductor device in which the above semiconductor device is flip-chip bonded and laminated in plural is provided.

若為本發明之半導體裝置，則由於半導體裝置之層合為容易，因此適於如此之層合型半導體裝置。 According to the semiconductor device of the present invention, since the lamination of the semiconductor device is easy, it is suitable for such a laminated semiconductor device.

又，於本發明中係提供一種封裝後層合型半導體裝置，其係將上述之層合型半導體裝置載置於具有電路的基板上，並以絕緣封裝樹脂層加以封裝而成。 Further, in the present invention, a post-package laminated semiconductor device in which the above-described laminated semiconductor device is mounted on a substrate having a circuit and encapsulated with an insulating encapsulating resin layer is provided.

若為本發明之半導體裝置，則由於對於半導體裝置的配線基板之載置或半導體裝置之層合為容易，因此適於如此之封裝後層合型半導體裝置。 In the case of the semiconductor device of the present invention, it is suitable for the mounting of the wiring substrate of the semiconductor device or the lamination of the semiconductor device, and thus it is suitable for the post-package laminated semiconductor device.

進而，於本發明中係提供一種半導體裝置之製造方法，其係具有以下步驟：(1)於支撐基板上塗佈暫時性接著劑，於該暫時性接著劑上形成使用阻劑組成物材料作為光硬化性樹脂層之膜厚1~20μm的第一絕緣層之步驟；(2)在對於前述第一絕緣層，藉由隔著遮罩之微影技術進行圖型化而形成成為貫穿電極的通孔圖型之後，進行烘烤，藉此使前述第一絕緣層硬化之步驟；(3)於前述第一絕緣層進行以濺鍍所致之種晶層形成，其後，將前述成為貫穿電極之通孔圖型，藉由鍍敷來填埋，而形成與貫穿電極連接的金屬配線之步驟；(4)使用晶片黏合劑將電極墊露出於上部表面之高度20~100μm的半導體元件晶片黏合於前述硬化後的第一絕緣層上之步驟；(5)準備具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構，且該光硬化性樹脂層為由阻劑組成物材料所構成的光硬化性乾膜之步驟；(6)藉由以覆蓋被晶片黏合於前述第一絕緣層上之半 導體元件的方式將前述光硬化性乾膜之光硬化性樹脂層進行疊層，而形成第二絕緣層之步驟；(7)對於前述第二絕緣層，藉由隔著遮罩之微影技術進行圖型化，而同時形成前述電極墊上之開口、以及用以在與前述貫穿電極連接的金屬配線上形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，之後，進行烘烤，藉此使前述第二絕緣層硬化之步驟；(8)在硬化後，進行以濺鍍所致之種晶層形成，其後，將前述電極墊上之開口、用以形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，藉由鍍敷來填埋，而形成半導體元件上金屬墊、貫穿前述第二絕緣層之金屬配線、以及貫穿電極，並且將藉由前述鍍敷所形成的前述半導體元件上金屬墊與貫穿前述第二絕緣層的金屬配線藉由以鍍敷所得之金屬配線相連結之步驟；(9)金屬配線形成後，將前述光硬化性乾膜之光硬化性樹脂層進行疊層或者將使用於前述光硬化性乾膜之阻劑組成物材料進行旋轉塗佈，藉此形成第三絕緣層之步驟；(10)在對於前述第三絕緣層，藉由隔著遮罩之微影技術進行圖型化而於前述貫穿電極上部形成開口之後，進行烘烤，藉此使前述第三絕緣層硬化之步驟；(11)硬化後，於前述貫穿電極上部之開口形成焊錫凸塊之步驟。 Further, in the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: (1) applying a temporary adhesive to a support substrate, and forming a resist composition material on the temporary adhesive; a step of forming a first insulating layer having a thickness of the photocurable resin layer of 1 to 20 μm; and (2) forming a through electrode by patterning the first insulating layer by a lithography technique through a mask; After the via pattern, baking is performed to cure the first insulating layer; (3) the seed layer formed by sputtering is formed on the first insulating layer, and thereafter, the foregoing is performed a through hole pattern of an electrode, which is filled by plating to form a metal wiring connected to the through electrode; and (4) a semiconductor element wafer having a height of 20 to 100 μm exposed to the upper surface by using a wafer adhesive a step of bonding to the hardened first insulating layer; (5) preparing a photocurable resin layer having a film thickness of 5 to 100 μm as a structure in which the supported film and the protective film are sandwiched, and the photocurable resin layer is Resist composition material Step into the dry film photohardenable; (6) so as to cover the upper half by the wafer is adhered on the first insulating layer a step of forming a second insulating layer by laminating a photocurable resin layer of the photocurable dry film to form a conductor element; and (7) a lithography technique by masking the second insulating layer Patterning, and simultaneously forming an opening in the electrode pad, an opening for forming a metal wiring penetrating the second insulating layer on the metal wiring connected to the through electrode, and an opening for forming the through electrode, Thereafter, baking is performed to thereby harden the second insulating layer; (8) after hardening, seed layer formation by sputtering is performed, and thereafter, an opening on the electrode pad is formed to form An opening of the metal wiring penetrating the second insulating layer and an opening for forming the through electrode are filled by plating to form a metal pad on the semiconductor element, a metal wiring penetrating the second insulating layer, and a through hole An electrode, and the metal pad on the semiconductor element formed by the plating and the metal wiring penetrating the second insulating layer are connected by a metal wiring obtained by plating (9) After the metal wiring is formed, the photocurable resin layer of the photocurable dry film is laminated, or a resist composition material used for the photocurable dry film is spin-coated to form a step of forming a third insulating layer; (10) performing an opening on the upper portion of the through electrode by patterning the third insulating layer by a lithography technique through a mask, and then baking the substrate a step of hardening the third insulating layer; (11) after hardening, forming a solder bump on the opening of the upper portion of the through electrode.

若為如此之半導體裝置之製造方法，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部形成貫穿電極，而可容易進行對於配線基板之載置或半導體裝置之層合，又可容易進行貫穿電極、電極墊部之開口等的加工。又，藉由使用光硬化性乾膜，而可成為即使半導體元件之高度為數十μm，亦可無空隙等地埋填於半導體元件周邊的半導體裝置。進而，藉由於第二絕緣層的兩面形成金屬配線，即使在金屬配線的密度為大之情況中亦可抑制半導體裝置之翹曲。 In the method of manufacturing such a semiconductor device, by forming a fine electrode on the semiconductor element and forming a through electrode outside the semiconductor element, it is possible to easily perform mounting on the wiring substrate or lamination of the semiconductor device. It is easy to process the through electrode, the opening of the electrode pad portion, and the like. In addition, by using a photocurable dry film, the semiconductor device can be buried in the periphery of the semiconductor element without voids even if the height of the semiconductor element is several tens of μm. Further, since the metal wiring is formed on both surfaces of the second insulating layer, the warpage of the semiconductor device can be suppressed even when the density of the metal wiring is large.

又，此時，較佳為將在前述步驟(5)所準備的光硬化性乾膜設為具有由化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層之光硬化性乾膜，該化學增幅型負型阻劑組成物材料係含有：(A)具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物、 (式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、 b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基，Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；h為0、1、2中之任一者)(B)由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑、(C)藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑、以及(D)溶劑。 In this case, it is preferable that the photocurable dry film prepared in the above step (5) is a photocurable dry layer having a photocurable resin layer composed of a chemically amplified negative resist composition material. The film, the chemically amplified negative resist composition material contains: (A) a polymer compound having an anthracene skeleton having a weight average molecular weight of 3,000 to 500,000, which has a repeating unit represented by the following general formula (1), (wherein R 1 to R 4 represent a monovalent hydrocarbon group having the same or different carbon number of 1 to 8; m is an integer of 1 to 100; a, b, c, and d are 0 or a positive number, and a, b, c, and d are not 0 at the same time; however, a+b+c+d=1; further, X is an organic group represented by the following general formula (2), and Y is represented by the following general formula (3). Organic basis (where, Z is composed of The divalent organic group selected by any one of them, n is 0 or 1; each of R 5 and R 6 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; k is Any of 0, 1, 2) (where, V is composed of The divalent organic group selected by any one of them, p is 0 or 1; each of R 7 and R 8 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; h is Any one of 0, 1, 2) (B) an amine condensate modified by formaldehyde or formaldehyde-alcohol, having an average of 2 or more methylol groups or alkoxyl groups in one molecule One or two or more kinds of crosslinking agents selected from the group consisting of phenolic compounds, and (C) are decomposed by light having a wavelength of from 190 to 500 nm to produce an acid photoacid generator and (D) a solvent.

藉此，由於可減輕在個片化後所擔憂之半導體裝置的翹曲，因此使個片化後的半導體裝置之層合或對於配線基板之載置變得更容易。 As a result, it is possible to reduce the warpage of the semiconductor device which is worried about the singulation, and it is easier to laminate the diced semiconductor device or mount the wiring substrate.

又，較佳為於前述步驟(6)中，包含對前述第二絕緣層進行機械性加壓的步驟。 Further, preferably, in the step (6), the step of mechanically pressurizing the second insulating layer is included.

藉此，可使半導體元件上之第二絕緣層的厚度減薄，或予以均勻化，又可使第二絕緣層平坦化。 Thereby, the thickness of the second insulating layer on the semiconductor element can be thinned or homogenized, and the second insulating layer can be planarized.

又，此時，藉由於前述步驟(11)中，具有：於前述貫穿電極上部之開口藉由鍍敷形成貫穿電極上金屬墊之步驟、以及 於前述貫穿電極上金屬墊上形成焊錫球，製成焊錫凸塊之步驟的方法，而可於貫穿電極上部之開口形成焊錫凸塊。 Further, in this case, in the step (11), the step of forming a metal pad on the through electrode by plating at the opening of the upper portion of the through electrode, and A method of forming a solder ball on the metal pad on the through electrode to form a solder bump, and forming a solder bump on the opening penetrating the upper portion of the electrode.

又，若為於前述步驟(8)之以鍍敷所致之前述 貫穿電極的形成中，包含進行以SnAg所致之鍍敷之步驟，並且具有：於前述步驟(10)中，以於前述貫穿電極上部形成開口的方式進行圖型化，藉此使前述鍍敷後的SnAg露出之步驟、以及於前述步驟(11)中，藉由將前述鍍敷後的SnAg進行熔融而於前述貫穿電極上部之開口處使電極隆起而形成焊錫凸塊之步驟的方法，則可進一步容易且合理地於前述貫穿電極上部之開口形成焊錫凸塊。 Further, if the plating is performed in the above step (8), The formation of the through electrode includes a step of performing plating by SnAg, and the patterning is performed in such a manner that an opening is formed in the upper portion of the through electrode in the step (10), thereby performing the plating. a step of exposing the succeeding SnAg and a method of forming a solder bump by swelling the electrode after the plating of SnAg at the opening of the upper portion of the through electrode by the step S11 Solder bumps can be further easily and reasonably formed on the openings in the upper portion of the through electrodes.

又，藉由在前述步驟(11)之後，進行：將在前述步驟(1)與第一絕緣層暫時接著的支撐基板去除之步驟、以及在將前述基板去除後，進行切割，藉此予以個片化之步驟，而可製造經個片化的半導體裝置。 Further, after the step (11), the step of removing the support substrate temporarily after the step (1) and the first insulating layer is removed, and after the substrate is removed, cutting is performed, thereby performing a cutting process. In the step of singulation, a singulated semiconductor device can be fabricated.

又，可製造將以上述之製造方法來藉由切割而個片化的複數個半導體裝置，包夾絕緣樹脂層，並藉由前述焊錫凸塊電接合而進行層合的層合型半導體裝置。 Further, it is possible to manufacture a laminated semiconductor device in which a plurality of semiconductor devices are formed by dicing by the above-described manufacturing method, and an insulating resin layer is sandwiched and electrically bonded by the solder bumps.

進而，藉由具有：將以上述之製造方法所製造的層合型半導體裝置載置於具有電路的基板之步驟、以及將載置於前述基板之層合型半導體裝置以絕緣封裝樹脂層進行封裝之步驟的方法而可製造封裝後層合型半導體裝置。 Furthermore, the method of placing a laminated semiconductor device manufactured by the above-described manufacturing method on a substrate having a circuit and packaging the laminated semiconductor device placed on the substrate with an insulating encapsulating resin layer A post-package laminated semiconductor device can be fabricated by the method of the steps.

依據本發明之半導體裝置及其製造方法，可賦予如以下所示般的效果。 According to the semiconductor device of the present invention and the method of manufacturing the same, the effects as described below can be imparted.

亦即，由於在將載置於形成在支撐基板上的第一絕緣層上之半導體元件周邊藉由將阻劑組成物材料使用於光硬化性樹脂層的光硬化性乾膜進行填埋時，光硬化性樹脂層為膜厚5~100μm，因此即使於半導體元件的高度為數十μm之情況中也能夠於半導體元件周邊不產生空隙等地將光硬化性乾膜進行填埋，且更加容易。 In other words, when the periphery of the semiconductor element placed on the first insulating layer formed on the support substrate is filled with the photocurable dry film using the resist composition material for the photocurable resin layer, Since the photocurable resin layer has a thickness of 5 to 100 μm, it is possible to fill the photocurable dry film without causing voids or the like around the semiconductor element even when the height of the semiconductor element is several tens of μm. .

具有藉由在將載置於形成在支撐基板上的第一絕緣層上之半導體元件周邊藉由將阻劑組成物材料使用於光硬化性樹脂層的光硬化性乾膜進行疊層之後，對半導體元件上之光硬化性樹脂層(第二絕緣層)進行機械性加壓，而能夠進行膜厚之調整、薄膜化的優點，且機械性加壓係具有能夠使半導體元件外周之經疊層的光硬化性樹脂層的膜厚均勻化、平坦化的優點。 After laminating a photocurable dry film using a resist composition material for a photocurable resin layer on a periphery of a semiconductor element placed on a first insulating layer formed on a support substrate, The photocurable resin layer (second insulating layer) on the semiconductor element is mechanically pressurized, and the film thickness can be adjusted and thinned, and the mechanical pressurization system can laminate the outer periphery of the semiconductor element. The film thickness of the photocurable resin layer is uniform and flat.

於經疊層的光硬化性乾膜(第二絕緣層)中，可將位於半導體元件上之電極墊上的開口、用以形成貫穿第二絕緣層之金屬配線的開口、以及成為貫穿電極的開口之形成藉由隔著遮罩的微影技術所致之圖型化來整批、同時地進行。 In the laminated photocurable dry film (second insulating layer), an opening on the electrode pad on the semiconductor element, an opening for forming a metal wiring penetrating the second insulating layer, and an opening serving as a through electrode The formation is performed in batches and simultaneously by patterning due to the lithography technique of the mask.

在將具有半導體元件之結構體進行立體層合，或載置於配線基板上時成為電極之貫穿電極孔 (TMV=Through Metal Via)，係可藉由使用周知廣泛使用的隔著遮罩之微影技術而容易地進行。 A through-electrode hole that becomes an electrode when a structure having a semiconductor element is three-dimensionally laminated or placed on a wiring substrate (TMV = Through Metal Via) can be easily carried out by using a well-known lithographic technique that is widely used.

將半導體元件上之電極墊上的開口、用以形成貫穿第二絕緣層之金屬配線的開口、以及貫穿電極形成用的開口，藉由鍍敷進行填埋，形成半導體元件上金屬墊、貫穿第二絕緣層之金屬配線、以及貫穿電極，將半導體元件上金屬墊與貫穿第二絕緣層之金屬配線藉由鍍敷往經金屬配線的配線上疊層光硬化性乾膜，藉此再度進行層合，並進行於配置在半導體元件之外部的貫穿電極(TMV)上部形成開口的圖型化，於形成在貫穿電極上部之開口的貫穿電極上金屬墊之上形成焊錫球，藉此而在將支撐基板移除之後進行個片化，此方法係為可容易地製造半導體裝置的方法。 Openings on the electrode pads on the semiconductor element, openings for forming metal wirings penetrating the second insulating layer, and openings for forming through electrodes are filled by plating to form metal pads on the semiconductor elements, and through the second In the metal wiring of the insulating layer and the through electrode, the metal pad on the semiconductor element and the metal wiring penetrating the second insulating layer are laminated on the wiring of the metal wiring, and the photocurable dry film is laminated thereon, thereby performing lamination again. And forming an opening pattern in the upper portion of the through electrode (TMV) disposed outside the semiconductor element, and forming a solder ball on the metal pad formed on the through electrode formed in the opening of the upper portion of the electrode, thereby supporting The substrate is removed after being removed, and this method is a method in which a semiconductor device can be easily fabricated.

作為更容易且合理地製造半導體裝置的方法係提供以下方法：於貫穿電極(TMV)之鍍敷埋填中，包含進行以SnAg所致之鍍敷的步驟，藉由將光硬化性乾膜進行疊層而再度進行層合，在進行於貫穿電極上部形成開口的圖型化之後，經過使SnAg之鍍敷露出的步驟、與圖型化後，藉由烘烤使薄膜硬化的步驟之後，將藉由鍍敷所填充的SnAg熔融，藉此使其朝向貫穿電極開口部隆起。 As a method for fabricating a semiconductor device more easily and reasonably, the following method is provided: in the plating implantation of the through electrode (TMV), the step of performing plating by SnAg is performed by performing the photocurable dry film After laminating and laminating again, after the patterning of the opening is formed in the upper portion of the penetrating electrode, after the step of exposing the plating of SnAg and the step of patterning and curing the film by baking, The SnAg filled by the plating is melted, thereby being raised toward the through electrode opening.

藉由暫時性接著劑來進行形成在支撐基板上的第一絕緣層與支撐基板之接著，接著，在容易地去除支撐基板的步驟，與將支撐基板移除後藉由切割而進行個片化者係對於製造經個片化的半導體裝置而言為容易且合 理。 The first insulating layer formed on the support substrate and the support substrate are subsequently formed by a temporary adhesive, and then, the step of easily removing the support substrate is performed by cutting after removing the support substrate. Is easy and consistent for manufacturing a singulated semiconductor device Reason.

以上述製造方法所得之經個片化的半導體裝置，上部係焊錫球或作為隆起後的SnAg之焊錫凸塊會突出，且下部係脫離基板，藉此可使貫穿電極容易露出，因此，使用突出的焊錫凸塊與露出的電極，可將複數個經個片化的半導體裝置容易地進行電接合，而可進行層合，故非常合理。 In the chip-formed semiconductor device obtained by the above-described manufacturing method, the upper solder ball or the solder bump as the SnAg after the bump protrudes, and the lower portion is separated from the substrate, whereby the through electrode can be easily exposed, and therefore, the protruding electrode is used. The solder bumps and the exposed electrodes can be easily electrically connected by a plurality of individualized semiconductor devices, and lamination can be performed, which is very reasonable.

又，於以往之僅在半導體元件上金屬墊側施以金屬配線的單面配線圖型中，若配線密度過大，則有半導體裝置本身的翹曲變大之傾向，但本發明之半導體裝置係藉由於第二絕緣層的兩面形成金屬配線，即使配線密度變大亦可抑制半導體裝置本身的翹曲。又，今後將來，由於為了對應於半導體裝置之訊號數量的增加亦會要求多層配線，因此將半導體裝置本身的翹曲極度縮小一事係為重要，但於第二絕緣層的兩面施以金屬配線之本發明之半導體裝置係由於能夠將翹曲極度縮小，因此亦適於多層配線。 Moreover, in the conventional single-sided wiring pattern in which the metal wiring is applied to the metal pad side of the semiconductor element, if the wiring density is too large, the warpage of the semiconductor device itself tends to be large, but the semiconductor device of the present invention is By forming metal wiring on both surfaces of the second insulating layer, warpage of the semiconductor device itself can be suppressed even if the wiring density is increased. In the future, in order to increase the number of signals corresponding to the semiconductor device, multilayer wiring is required. Therefore, it is important to minimize the warpage of the semiconductor device itself, but metal wiring is applied to both sides of the second insulating layer. The semiconductor device of the present invention is also suitable for multilayer wiring because it can extremely reduce warpage.

又，於將本發明之化學增幅型負型阻劑組成物材料使用於光硬化性樹脂層的情況中，由於能夠減輕在個片化時所顧慮之半導體裝置的翹曲，因此適於層合或對於配線基板之載置。 In addition, when the chemically amplified negative-resistance composition material of the present invention is used for a photocurable resin layer, it is possible to reduce the warpage of the semiconductor device which is considered at the time of singulation, and thus is suitable for lamination. Or for mounting on a wiring substrate.

如以上所述般，若為本發明之半導體裝置，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而使對於配線基板之載置或半導 體裝置之層合為容易，進而，成為即使半導體元件的高度為數十μm亦可於半導體元件周邊無空隙等地進行填埋，即使在金屬配線的密度為大之情況中半導體裝置之翹曲亦受到抑制的半導體裝置。 As described above, in the semiconductor device of the present invention, the fine electrode is formed on the semiconductor element, and the through electrode is applied to the outside of the semiconductor element to mount or semi-conductive the wiring substrate. It is easy to laminate the body device, and even if the height of the semiconductor element is several tens of μm, it can be filled without voids around the semiconductor element, and the warpage of the semiconductor device can be made even when the density of the metal wiring is large. A semiconductor device that is also suppressed.

又，若為本發明之半導體裝置之製造方法，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而可容易進行對於配線基板之載置或半導體裝置之層合，又可容易進行貫穿電極、電極墊部之開口等的加工。 Further, in the method of manufacturing a semiconductor device of the present invention, by forming a fine electrode on the semiconductor element and applying a through electrode to the outside of the semiconductor element, it is possible to easily perform mounting on the wiring substrate or a layer of the semiconductor device. Further, the processing of the through electrode, the opening of the electrode pad portion, and the like can be easily performed.

進而，以如此方式所得到的本發明之半導體裝置係由於對於配線基板之載置或半導體裝置之層合為容易，因此可製成將半導體裝置進行層合之層合型半導體裝置或將其載置於配線基板並加以封裝之封裝後層合型半導體裝置。 Further, the semiconductor device of the present invention obtained in this manner is easy to laminate the wiring substrate or the semiconductor device, and thus it is possible to form a laminated semiconductor device in which a semiconductor device is laminated or to carry it. A packaged laminated semiconductor device placed on a wiring substrate and packaged.

1‧‧‧半導體裝置 1‧‧‧Semiconductor device

2‧‧‧半導體元件 2‧‧‧Semiconductor components

3‧‧‧半導體元件上金屬墊 3‧‧‧Metal components on metal pads

4‧‧‧金屬配線 4‧‧‧Metal wiring

4a‧‧‧上面金屬配線 4a‧‧‧Top metal wiring

4b‧‧‧下面金屬配線 4b‧‧‧Under metal wiring

4c‧‧‧貫穿金屬配線 4c‧‧‧through metal wiring

5‧‧‧貫穿電極 5‧‧‧through electrode

6‧‧‧焊錫凸塊 6‧‧‧ solder bumps

7‧‧‧第一絕緣層 7‧‧‧First insulation

8‧‧‧第二絕緣層 8‧‧‧Second insulation

9‧‧‧第三絕緣層 9‧‧‧ Third insulation

10‧‧‧晶片黏合劑 10‧‧‧ wafer adhesive

11‧‧‧層合型半導體裝置 11‧‧‧Laminated semiconductor device

12‧‧‧絕緣樹脂層 12‧‧‧Insulating resin layer

13‧‧‧封裝後層合型半導體裝置 13‧‧‧Package laminated semiconductor device

14‧‧‧配線基板 14‧‧‧Wiring substrate

15‧‧‧絕緣封裝樹脂層 15‧‧‧Insulating encapsulation resin layer

16‧‧‧支撐基板 16‧‧‧Support substrate

17‧‧‧暫時性接著劑 17‧‧‧ temporary adhesive

18‧‧‧金屬鍍敷 18‧‧‧Metal plating

19‧‧‧貫穿電極上金屬墊 19‧‧‧Metal pad on the electrode

20‧‧‧焊錫球 20‧‧‧ solder balls

21‧‧‧SnAg鍍敷 21‧‧‧SnAg plating

22‧‧‧使SnAg隆起的電極 22‧‧‧The electrode that makes SnAg bulge

23、24‧‧‧經個片化之半導體裝置 23, 24‧‧‧Diated semiconductor devices

A‧‧‧成為貫穿電極之通孔圖型 A‧‧‧ becomes the through hole pattern of the through electrode

B‧‧‧電極墊上之開口 B‧‧‧ Openings on the electrode pads

C‧‧‧用以形成貫穿金屬配線之開口 C‧‧‧ used to form openings through metal wiring

D‧‧‧用以形成貫穿電極之開口 D‧‧‧ used to form the opening through the electrode

E‧‧‧貫穿電極上部之開口 E‧‧‧ openings through the upper part of the electrode

[第1圖]係顯示本發明之半導體裝置的一例子之概略剖面圖。 [Fig. 1] is a schematic cross-sectional view showing an example of a semiconductor device of the present invention.

[第2圖]係顯示本發明之層合型半導體裝置的一例子之概略剖面圖。 [Fig. 2] is a schematic cross-sectional view showing an example of a laminated semiconductor device of the present invention.

[第3圖]係顯示本發明之封裝後層合型半導體裝置的一例子之概略剖面圖。 [Fig. 3] Fig. 3 is a schematic cross-sectional view showing an example of a post-package laminated semiconductor device of the present invention.

[第4圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(1)之概略剖面圖。 [Fig. 4] is a schematic cross-sectional view showing a step (1) of an example of a method of manufacturing a semiconductor device of the present invention.

[第5圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(2)之概略剖面圖。 [Fig. 5] is a schematic cross-sectional view showing a step (2) of an example of a method of manufacturing a semiconductor device of the present invention.

[第6圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(3)之概略剖面圖。 [Fig. 6] is a schematic cross-sectional view showing a step (3) of an example of a method of manufacturing a semiconductor device of the present invention.

[第7圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(4)之概略剖面圖。 [Fig. 7] is a schematic cross-sectional view showing a step (4) of an example of a method of manufacturing a semiconductor device of the present invention.

[第8圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(6)之概略剖面圖。 [Fig. 8] is a schematic cross-sectional view showing a step (6) of an example of a method of manufacturing a semiconductor device of the present invention.

[第9圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(7)之概略剖面圖。 [Fig. 9] is a schematic cross-sectional view showing a step (7) of an example of a method of manufacturing a semiconductor device of the present invention.

[第10圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(8)之概略剖面圖。 [Fig. 10] is a schematic cross-sectional view showing a step (8) of an example of a method of manufacturing a semiconductor device of the present invention.

[第11圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(8)之概略剖面圖。 [Fig. 11] is a schematic cross-sectional view showing a step (8) of an example of a method of manufacturing a semiconductor device of the present invention.

[第12圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(9)之概略剖面圖。 [Fig. 12] is a schematic cross-sectional view showing a step (9) of an example of a method of manufacturing a semiconductor device of the present invention.

[第13圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(10)之概略剖面圖。 [Fig. 13] is a schematic cross-sectional view showing a step (10) of an example of a method of manufacturing a semiconductor device of the present invention.

[第14圖]係用以說明本發明之半導體裝置之製造方法的一例子之步驟(11)之概略剖面圖。 [Fig. 14] is a schematic cross-sectional view showing a step (11) of an example of a method of manufacturing a semiconductor device of the present invention.

[第15圖]係用以說明本發明之半導體裝置之製造方法的另外一例之步驟(8)之概略剖面圖。 [Fig. 15] Fig. 15 is a schematic cross-sectional view showing a step (8) of another example of the method of manufacturing the semiconductor device of the present invention.

[第16圖]係用以說明本發明之半導體裝置之製造方法的另外一例之步驟(11)之概略剖面圖。 [Fig. 16] Fig. 16 is a schematic cross-sectional view showing a step (11) of another example of the method of manufacturing the semiconductor device of the present invention.

[第17圖]係顯示於本發明之半導體裝置之製造方法中經個片化之半導體裝置的一例子之概略剖面圖。 [Fig. 17] Fig. 17 is a schematic cross-sectional view showing an example of a semiconductor device which is diced in the method of manufacturing a semiconductor device of the present invention.

[第18圖]係顯示於本發明之半導體裝置之製造方法中經個片化之半導體裝置的另外一例之概略剖面圖。 [Fig. 18] Fig. 18 is a schematic cross-sectional view showing another example of a semiconductor device which is diced in the method of manufacturing a semiconductor device of the present invention.

[第19圖]係用以說明本發明之層合型半導體裝置之製造方法的一例子之概略剖面圖。 [Fig. 19] is a schematic cross-sectional view for explaining an example of a method of manufacturing the laminated semiconductor device of the present invention.

[第20圖]係用以說明本發明之層合型半導體裝置之製造方法的另外一例之概略剖面圖。 [Fig. 20] Fig. 20 is a schematic cross-sectional view showing another example of a method of manufacturing a laminated semiconductor device of the present invention.

[第21圖]係顯示載置於配線基板上的本發明之層合型半導體裝置的一例子之概略剖面圖。 [21] Fig. 21 is a schematic cross-sectional view showing an example of a laminated semiconductor device of the present invention placed on a wiring board.

[第22圖]係顯示載置於配線基板上的本發明之層合型半導體裝置的另外一例之概略剖面圖。 [Fig. 22] Fig. 22 is a schematic cross-sectional view showing another example of the laminated semiconductor device of the present invention placed on a wiring board.

[第23圖]係用以說明本發明之封裝後層合型半導體裝置之製造方法的一例子之概略剖面圖。 [Fig. 23] Fig. 23 is a schematic cross-sectional view showing an example of a method of manufacturing a package-sealed semiconductor device of the present invention.

[第24圖]係用以說明本發明之封裝後層合型半導體裝置之製造方法的另外一例之概略剖面圖。 [Fig. 24] Fig. 24 is a schematic cross-sectional view showing another example of a method of manufacturing a package-sealed semiconductor device of the present invention.

[第25圖]係顯示以往之半導體裝置之製造方法之說明圖。 [Fig. 25] is an explanatory view showing a method of manufacturing a conventional semiconductor device.

[第26圖]係顯示以往之半導體裝置之製造方法之說明圖。 [Fig. 26] is an explanatory view showing a method of manufacturing a conventional semiconductor device.

[第27圖]係顯示以往之半導體裝置之製造方法之說明圖。 [Fig. 27] is an explanatory view showing a method of manufacturing a conventional semiconductor device.

[第28圖]係顯示以往之半導體裝置之製造方法之說明圖。 [Fig. 28] is an explanatory view showing a method of manufacturing a conventional semiconductor device.

如上述般地，於半導體裝置中，對於更加小型化、薄型化及高密度化的要求急速高漲，而要求開發對於配線基板之載置或半導體裝置之層合為容易的半導體裝置及其製造方法。又，今後將來，由於為了對應於半導體裝置之訊號數量的增加亦會要求多層配線，因此要求開發即使於多層配線等金屬配線的密度為大的情況中亦能夠抑制半導體裝置本身之翹曲的半導體裝置及其製造方法。 As described above, in semiconductor devices, demands for further miniaturization, thinning, and higher density are rapidly increasing, and it is required to develop a semiconductor device that facilitates lamination of a wiring substrate or a semiconductor device, and a method of manufacturing the same. . In the future, in order to increase the number of signals corresponding to the semiconductor device, multilayer wiring is required. Therefore, it is required to develop a semiconductor capable of suppressing warpage of the semiconductor device itself even when the density of the metal wiring such as the multilayer wiring is large. Device and method of manufacturing the same.

本發明者們係為了達成上述目的屢經努力探討的結果，發現藉由進行下述所示之步驟來克服課題，而可容易地製造半導體裝置及層合型半導體裝置，因而完成本發明。 As a result of intensive efforts to achieve the above object, the inventors of the present invention have found that the semiconductor device and the laminated semiconductor device can be easily fabricated by performing the steps described below, and thus the present invention has been completed.

首先，於塗佈有暫時性接著劑的支撐基板上，使用阻劑組成物材料來形成第一絕緣層，對於此第一絕緣層進行圖型化，而形成成為貫穿電極的通孔圖型。在以烘烤所致之硬化後，將成為貫穿電極之通孔圖型藉由鍍敷進行埋填，形成與貫穿電極連接的金屬配線，將半導體元件晶片黏合於第一絕緣層上。接著，將經晶片黏合的半導體元件周邊，藉由將阻劑組成物材料使用於光硬化性樹脂層的光硬化性乾膜進行疊層，藉此可於半導體元件周邊不產生間隙等地將薄膜進行埋填(第二絕緣層之形成)。得知：由於是對於此第二絕緣層，藉由隔著遮罩之微影技術進行圖型化，藉此可同時形成電極墊上之開口、用以形成 貫穿第二絕緣層的金屬配線之開口、以及用以形成貫穿電極之開口，因此可容易地進行加工，因而完成本發明。 First, a first insulating layer is formed on a support substrate coated with a temporary adhesive using a resist composition material, and the first insulating layer is patterned to form a via pattern which is a through electrode. After hardening by baking, the via pattern of the through electrode is buried by plating to form a metal wiring connected to the through electrode, and the semiconductor element wafer is bonded to the first insulating layer. Then, the film-bonded semiconductor element is laminated on the photocurable dry film of the photocurable resin layer by using a resist composition material, whereby the film can be formed without a gap or the like around the semiconductor element. Buried (formation of the second insulating layer). It is known that since the second insulating layer is patterned by the lithography technique through the mask, the opening on the electrode pad can be simultaneously formed to form The opening of the metal wiring penetrating the second insulating layer and the opening for forming the through electrode can be easily processed, and thus the present invention has been completed.

進而，在藉由烘烤使第二絕緣層硬化後，將電極墊上之開口、用以形成貫穿第二絕緣層的金屬配線之開口、以及用以形成貫穿電極之開口，藉由鍍敷來填埋，而形成半導體元件上金屬墊、貫穿第二絕緣層之金屬配線、以及貫穿電極，並且將藉由鍍敷所形成的半導體元件上金屬墊與貫穿第二絕緣層的金屬配線藉由以鍍敷所得之金屬配線相連結。其後，於其上形成第三絕緣層，對於第三絕緣層進行圖型化而於貫穿電極上部形成開口，使其硬化後，於此開口形成焊錫凸塊。進而，將以暫時性接著劑所接著的支撐基板去除，並藉由切割而進行個片化，此係能夠非常合理地形成半導體裝置的方法，而將本發明之目的予以具體呈現。 Further, after the second insulating layer is cured by baking, the opening on the electrode pad, the opening for forming the metal wiring penetrating the second insulating layer, and the opening for forming the through electrode are filled by plating Buried to form a metal pad on the semiconductor element, a metal wiring penetrating the second insulating layer, and a through electrode, and the metal pad on the semiconductor element formed by plating and the metal wiring penetrating the second insulating layer are plated The metal wiring obtained by the application is connected. Thereafter, a third insulating layer is formed thereon, and the third insulating layer is patterned to form an opening in the upper portion of the through electrode, and after hardening, a solder bump is formed in the opening. Further, the support substrate which is followed by the temporary adhesive is removed and diced by dicing, which is a method for forming a semiconductor device very reasonably, and the object of the present invention is specifically shown.

又，發現若為以上述製造方法所製造的半導體裝置，則藉由於第二絕緣層的兩面形成金屬配線，即使配線密度變大亦可抑制半導體裝置本身的翹曲。 In addition, in the semiconductor device manufactured by the above-described manufacturing method, it is found that the metal wiring is formed on both surfaces of the second insulating layer, and the warpage of the semiconductor device itself can be suppressed even if the wiring density is increased.

進而，得知以下見解：以上述製造方法所製造之半導體裝置，上部係焊錫凸塊會突出，且下部係藉由去除支撐基板而可使貫穿電極容易露出，因此，使用突出的焊錫凸塊與露出的電極，可將複數個半導體裝置容易地進行電接合，而可進行層合，又，得知以下見解：可將經層合的半導體裝置容易地載置於配線基板，因而完成本發明。 Further, it has been found that the semiconductor device manufactured by the above-described manufacturing method has the upper solder bump protruding, and the lower portion is formed by removing the supporting substrate, so that the through electrode can be easily exposed. Therefore, the protruding solder bump is used. The exposed electrode can be electrically bonded to a plurality of semiconductor devices, and can be laminated. Further, it has been found that the laminated semiconductor device can be easily placed on the wiring substrate, and thus the present invention has been completed.

亦即，本發明係一種半導體裝置，其係具有半導體元件、與電連接於該半導體元件之半導體元件上金屬墊及金屬配線，且該金屬配線係電連接於貫穿電極及焊錫凸塊，具有：載置有前述半導體元件之第一絕緣層、形成於前述半導體元件上之第二絕緣層、以及形成於該第二絕緣層上之第三絕緣層，前述金屬配線係在前述第二絕緣層的上面經由前述半導體元件上金屬墊而電連接於前述半導體元件，且從前述第二絕緣層的上面貫穿前述第二絕緣層而在前述第二絕緣層的下面電連接於前述貫穿電極者。 That is, the present invention is a semiconductor device having a semiconductor element, a metal pad and a metal wiring electrically connected to the semiconductor element, and the metal wiring is electrically connected to the through electrode and the solder bump, and has: a first insulating layer on which the semiconductor element is placed, a second insulating layer formed on the semiconductor element, and a third insulating layer formed on the second insulating layer, the metal wiring being on the second insulating layer The upper surface is electrically connected to the semiconductor element via a metal pad on the semiconductor element, and the second insulating layer is inserted through the second insulating layer from the upper surface of the second insulating layer, and is electrically connected to the through electrode on the lower surface of the second insulating layer.

以下，雖一邊參照附圖一邊針對本發明進行詳細地說明，但本發明並不限定於此等。 Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.

本發明之半導體裝置1，係如第1圖所示般，具有半導體元件2、與電連接於半導體元件2的半導體元件上金屬墊3及金屬配線4，且金屬配線4電連接於貫穿電極5及焊錫凸塊6的半導體裝置，且具有：載置有半導體元件2的第一絕緣層7、形成於半導體元件2上的第二絕緣層8、以及形成於第二絕緣層8上的第三絕緣層9，金屬配線4係在第二絕緣層8的上面經由半導體元件上金屬墊3而電連接於半導體元件2，且從第二絕緣層8的上面貫穿第二絕緣層8而在第二絕緣層8的下面電連接於貫穿電極5之半導體裝置。 The semiconductor device 1 of the present invention has a semiconductor element 2, a metal pad 3 and a metal wiring 4 on the semiconductor element electrically connected to the semiconductor element 2, and the metal wiring 4 is electrically connected to the through electrode 5 as shown in Fig. 1 . And a semiconductor device of the solder bump 6 and having: a first insulating layer 7 on which the semiconductor element 2 is placed, a second insulating layer 8 formed on the semiconductor element 2, and a third layer formed on the second insulating layer 8. The insulating layer 9, the metal wiring 4 is electrically connected to the semiconductor element 2 via the metal pad 3 on the semiconductor element on the upper surface of the second insulating layer 8, and penetrates the second insulating layer 8 from the upper surface of the second insulating layer 8 in the second The lower surface of the insulating layer 8 is electrically connected to the semiconductor device of the through electrode 5.

另外，金屬配線4係由在第二絕緣層8的上 面與半導體元件上金屬墊3連接之金屬配線(上面金屬配線)4a、在第二絕緣層8的下面與貫穿電極5連接之金屬配線(下面金屬配線)4b、以及貫穿第二絕緣層8，並將上面金屬配線4a與下面金屬配線4b進行連接之金屬配線(貫穿金屬配線)4c所構成。 In addition, the metal wiring 4 is on the second insulating layer 8 a metal wiring (upper metal wiring) 4a whose surface is connected to the metal pad 3 on the semiconductor element, a metal wiring (lower metal wiring) 4b connected to the through electrode 5 on the lower surface of the second insulating layer 8, and a second insulating layer 8 are penetrated. The metal wiring (through metal wiring) 4c that connects the upper metal wiring 4a and the lower metal wiring 4b is formed.

又，於第1圖之半導體裝置1中，半導體元件2係藉由晶片黏合劑10而晶片黏合於第一絕緣層7。 Further, in the semiconductor device 1 of FIG. 1, the semiconductor element 2 is bonded to the first insulating layer 7 by the wafer adhesive 10.

若為如此之半導體裝置，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而容易進行對於配線基板之載置或半導體裝置之層合，又，藉由於第二絕緣層的兩面形成金屬配線，而成為即使在金屬配線的密度為大之情況中半導體裝置之翹曲亦受到抑制的半導體裝置。 In the case of such a semiconductor device, by forming a fine electrode on the semiconductor element and applying a through electrode to the outside of the semiconductor element, it is easy to perform mounting on the wiring substrate or lamination of the semiconductor device, and The metal wiring is formed on both surfaces of the two insulating layers, and the semiconductor device is suppressed even when the density of the metal wiring is large.

又，此時，若為藉由光硬化性乾膜或者光硬化性阻劑塗佈膜而形成第一絕緣層7者，藉由光硬化性乾膜而形成第二絕緣層8者，藉由光硬化性乾膜或者光硬化性阻劑塗佈膜而形成第三絕緣層9者，則成為即使半導體元件2之高度為數十μm亦於半導體元件周邊無空隙等地進行填埋的半導體裝置，故為佳。 In this case, if the first insulating layer 7 is formed by a photocurable dry film or a photocurable resist coating film, the second insulating layer 8 is formed by a photocurable dry film. When the third insulating layer 9 is formed by the photocurable dry film or the photocurable resist coating film, the semiconductor device is filled with a space of tens of μm or the like in the periphery of the semiconductor element without voids. Therefore, it is better.

又，此時，若為半導體元件2的高度為20~100μm，第一絕緣層7的膜厚為1~20μm，第二絕緣層8的膜厚為5~100μm，第三絕緣層9的膜厚為5~100μm，半導體裝置1的厚度為50~300μm，則成為於半導體元件 周邊無空隙等地進行填埋，且薄型的半導體裝置，故為佳。 Further, in this case, when the height of the semiconductor element 2 is 20 to 100 μm, the film thickness of the first insulating layer 7 is 1 to 20 μm, and the film thickness of the second insulating layer 8 is 5 to 100 μm, and the film of the third insulating layer 9 is used. The thickness is 5 to 100 μm, and the thickness of the semiconductor device 1 is 50 to 300 μm, which is a semiconductor element. It is preferable to carry out landfill without voids and the like, and a thin semiconductor device.

又此時，使用於上述之第一絕緣層7、第二絕緣層8、及第三絕緣層9之形成的光硬化性乾膜，就翹曲之抑制、殘留應力之減低、可靠性或加工特性之提昇等的觀點而言，較佳為具有由含有以下之(A)~(D)成分而成的化學增幅型負型阻劑組成物材料所構成之光硬化性樹脂層的光硬化性乾膜。 Further, at this time, the photocurable dry film formed by the first insulating layer 7, the second insulating layer 8, and the third insulating layer 9 described above is suppressed in warpage, reduced in residual stress, reliability, or processed. From the viewpoint of improvement in characteristics, etc., it is preferable to have photocurability of a photocurable resin layer composed of a chemically amplified negative resist composition material containing the following components (A) to (D). Dry film.

另外，當然亦可使用其他的感光性樹脂。 Further, of course, other photosensitive resin can also be used.

(A)成分係具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物。 The component (A) is a polymer compound having an fluorenone skeleton having a weight average molecular weight of 3,000 to 500,000 in a repeating unit represented by the following general formula (1).

(式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基，Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同； h為0、1、2中之任一者)。 (wherein R 1 to R 4 represent a monovalent hydrocarbon group having the same or different carbon number of 1 to 8; m is an integer of 1 to 100; a, b, c, and d are 0 or a positive number, and a, b, c, and d are not 0 at the same time; however, a+b+c+d=1; further, X is an organic group represented by the following general formula (2), and Y is represented by the following general formula (3). Organic basis (where, Z is composed of The divalent organic group selected by any one of them, n is 0 or 1; each of R 5 and R 6 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; k is Any of 0, 1, 2) (where, V is composed of The divalent organic group selected by any one of them, p is 0 or 1; each of R 7 and R 8 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; h is Any of 0, 1, 2).

(B)成分係由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑。 The component (B) is one selected from the group consisting of an amine condensate modified with formaldehyde or formaldehyde-alcohol, and a phenol compound having an average of two or more methylol groups or alkoxymethylol groups per molecule. Or two or more kinds of crosslinking agents.

(C)成分係藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑。 The component (C) is decomposed by light having a wavelength of 190 to 500 nm to produce an acid photoacid generator.

(D)成分為溶劑。 The component (D) is a solvent.

作為(B)成分之交聯劑雖可使用周知者，但可使用由藉由甲醛或甲醛-醇改質而成的胺基縮合物及1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上。 Although a known crosslinking agent can be used as the crosslinking agent of the component (B), an amine condensate modified by formaldehyde or formaldehyde-alcohol and an average of two or more methylol groups or alkane in one molecule can be used. One or two or more kinds of phenolic compounds of the oxymethylol group are selected.

作為如此之藉由甲醛或甲醛-醇改質而成的胺基縮合物係可列舉例如：藉由甲醛或甲醛-醇改質而成的三聚氰胺縮合物，或者藉由甲醛或甲醛-醇改質而成的脲縮合物。 The amine condensate thus modified by formaldehyde or formaldehyde-alcohol may, for example, be a melamine condensate modified by formaldehyde or formaldehyde-alcohol, or modified by formaldehyde or formaldehyde-alcohol. A urea condensate.

另外，此等改質三聚氰胺縮合物及改質脲縮合物係可1種或將2種以上進行混合而使用。 In addition, these modified melamine condensate and modified urea condensate system may be used alone or in combination of two or more.

又，作為1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物係可列舉例如：(2-羥基-5-甲基)-1,3-苯二甲醇、2,2’,6,6’-四甲氧基甲基雙酚A等。 In addition, examples of the phenol compound having an average of two or more methylol groups or alkoxymethylol groups per molecule include (2-hydroxy-5-methyl)-1,3-benzenedimethanol and 2 , 2', 6, 6'-tetramethoxymethyl bisphenol A and the like.

另外，此等酚化合物係可1種或將2種以上進行混合而使用。 In addition, these phenolic compounds may be used alone or in combination of two or more.

作為(C)成分之酸產生劑係可使用藉由波長190~500nm之光照射產生酸，而使其成為硬化觸媒者。 As the acid generator of the component (C), an acid can be generated by irradiation with light having a wavelength of 190 to 500 nm to make it a hardening catalyst.

作為如此之光酸產生劑係可列舉：鎓鹽、重氮甲烷衍生物、乙二醛二肟(glyoxime)衍生物、β-酮碸(ketosulphone)衍生物、二碸衍生物、硝苄基磺酸酯衍生物、磺酸酯衍生物、醯亞胺-基-磺酸酯衍生物、肟磺酸酯衍生物、亞胺基磺酸酯衍生物、三嗪衍生物等。 Examples of such a photoacid generator include a phosphonium salt, a diazomethane derivative, a glyoxal glyoxime derivative, a β-ketosulphone derivative, a dioxane derivative, and a nitroxide sulfonate. An acid ester derivative, a sulfonate derivative, a quinone imine-based-sulfonate derivative, an oxime sulfonate derivative, an imidosulfonate derivative, a triazine derivative, and the like.

作為(D)成分之溶劑係可使用能夠溶解(A)含有矽酮骨架之高分子化合物、(B)交聯劑、及(C)光酸產生劑者。 As the solvent of the component (D), those capable of dissolving (A) a polymer compound containing an anthracene skeleton, (B) a crosslinking agent, and (C) a photoacid generator can be used.

作為如此之溶劑係可列舉例如：環己酮、環戊酮、甲基-2-n-戊基酮等之酮類；3-甲氧基丁醇、3-甲基-3-甲氧基丁醇、1-甲氧基-2-丙醇、1-乙氧基-2-丙醇等之醇類；丙二醇單甲基醚、乙二醇單甲基醚、丙二醇單乙基醚、乙二醇單乙基醚、丙二醇二甲基醚、二乙二醇二甲基醚等之醚類；丙二醇單甲基醚乙酸酯、丙二醇單乙基醚乙酸酯、乳酸乙酯、丙酮酸乙酯、乙酸丁酯、3-甲氧基丙酸甲酯、3-乙氧基丙酸乙酯、乙酸tert-丁酯、丙酸tert-丁酯、丙二醇-單-tert-丁基醚乙酸酯、γ-丁內酯等之酯類等。 Examples of such a solvent include ketones such as cyclohexanone, cyclopentanone, and methyl-2-n-amyl ketone; 3-methoxybutanol and 3-methyl-3-methoxy Alcohols such as butanol, 1-methoxy-2-propanol, 1-ethoxy-2-propanol; propylene glycol monomethyl ether, ethylene glycol monomethyl ether, propylene glycol monoethyl ether, B An ether such as diol monoethyl ether, propylene glycol dimethyl ether or diethylene glycol dimethyl ether; propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether acetate, ethyl lactate, pyruvic acid Ethyl ester, butyl acetate, methyl 3-methoxypropionate, ethyl 3-ethoxypropionate, tert-butyl acetate, tert-butyl propionate, propylene glycol-mono-tert-butyl ether An ester such as an acid ester or γ-butyrolactone.

又，第一絕緣層7與第三絕緣層9係可為藉由旋轉塗佈等塗佈有含有上述之(A)~(D)成分而成之化學增幅型負型阻劑組成物材料的光硬化性阻劑塗佈膜，當然，亦可為藉由旋轉塗佈等塗佈有其他之感光性樹脂的光硬化性阻劑塗佈膜。 Further, the first insulating layer 7 and the third insulating layer 9 may be formed by coating a chemically amplified negative resist composition material containing the above components (A) to (D) by spin coating or the like. The photocurable resist coating film may of course be a photocurable resist coating film coated with another photosensitive resin by spin coating or the like.

進而，於本發明中，係提供將上述之半導體裝置倒裝晶片化並複數層合而成的層合型半導體裝置。 Further, in the present invention, a laminated semiconductor device in which the above-described semiconductor device is flip-chip bonded and laminated in plural is provided.

本發明之層合型半導體裝置11，如第2圖所示般，係將上述之半導體裝置1倒裝晶片化並藉由貫穿電極5與焊錫凸塊6電接合並複數層合而成者，於各半導體裝置間亦可封入有絕緣樹脂層12。 As shown in FIG. 2, the laminated semiconductor device 11 of the present invention is obtained by flip-chip the above-described semiconductor device 1 and electrically bonding the through bumps 5 to the solder bumps 6 to form a plurality of layers. The insulating resin layer 12 may be sealed between the semiconductor devices.

又，於本發明中係提供一種封裝後層合型半導體裝置，其係將上述之層合型半導體裝置載置於具有電路的基板上，並以絕緣封裝樹脂層加以封裝而成。 Further, in the present invention, a post-package laminated semiconductor device in which the above-described laminated semiconductor device is mounted on a substrate having a circuit and encapsulated with an insulating encapsulating resin layer is provided.

本發明之封裝後層合型半導體裝置13，係如第3圖所示般，將上述之層合型半導體裝置11經由焊錫凸塊6而載置於具有電路之基板(配線基板14)上，並以絕緣封裝樹脂層15加以封裝而成者。 In the package-sealed semiconductor device 13 of the present invention, as shown in FIG. 3, the above-described laminated semiconductor device 11 is placed on a substrate (wiring substrate 14) having a circuit via solder bumps 6. It is encapsulated by an insulating encapsulating resin layer 15.

如上述般之半導體裝置係可藉由以下所示之本發明的半導體裝置之製造方法進行製造。本發明之半導體裝置之製造方法係具有以下步驟：(1)於支撐基板上塗佈暫時性接著劑，於該暫時性接著劑上形成使用阻劑組成物材料作為光硬化性樹脂層之膜厚1~20μm的第一絕緣層之步驟；(2)在對於前述第一絕緣層，藉由隔著遮罩之微影技術進行圖型化而形成成為貫穿電極的通孔圖型之後，進行烘烤，藉此使前述第一絕緣層硬化之步驟；(3)於前述第一絕緣層進行以濺鍍所致之種晶層形成，其後，將前述成為貫穿電極之通孔圖型，藉由鍍敷來填埋，而形成與貫穿電極連接的金屬配線之步驟；(4)使用晶片黏合劑將電極墊露出於上部表面之高度 20~100μm的半導體元件晶片黏合於前述硬化後的第一絕緣層上之步驟；(5)準備具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構，且該光硬化性樹脂層為由阻劑組成物材料所構成的光硬化性乾膜之步驟；(6)藉由以覆蓋被晶片黏合於前述第一絕緣層上之半導體元件的方式將前述光硬化性乾膜之光硬化性樹脂層進行疊層，而形成第二絕緣層之步驟；(7)對於前述第二絕緣層，藉由隔著遮罩之微影技術進行圖型化，而同時形成前述電極墊上之開口、以及用以在與前述貫穿電極連接的金屬配線上形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，之後，進行烘烤，藉此使前述第二絕緣層硬化之步驟；(8)在硬化後，進行以濺鍍所致之種晶層形成，其後，將前述電極墊上之開口、用以形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，藉由鍍敷來填埋，而形成半導體元件上金屬墊、貫穿前述第二絕緣層之金屬配線、以及貫穿電極，並且將藉由前述鍍敷所形成的前述半導體元件上金屬墊與貫穿前述第二絕緣層的金屬配線藉由以鍍敷所得之金屬配線相連結之步驟；(9)金屬配線形成後，將前述光硬化性乾膜之光硬化性樹脂層進行疊層或者將使用於前述光硬化性乾膜之阻劑 組成物材料進行旋轉塗佈，藉此形成第三絕緣層之步驟；(10)在對於前述第三絕緣層，藉由隔著遮罩之微影技術進行圖型化而於前述貫穿電極上部形成開口之後，進行烘烤，藉此使前述第三絕緣層硬化之步驟；(11)硬化後，於前述貫穿電極上部之開口形成焊錫凸塊之步驟。 The semiconductor device as described above can be manufactured by the method of manufacturing a semiconductor device of the present invention shown below. The method of manufacturing a semiconductor device of the present invention comprises the steps of: (1) applying a temporary adhesive to a support substrate, and forming a film thickness using a resist composition material as a photocurable resin layer on the temporary adhesive; a step of forming a first insulating layer of 1 to 20 μm; and (2) performing a pattern of a through hole pattern which is formed as a through electrode by patterning the first insulating layer by a lithography technique through a mask Baking, thereby curing the first insulating layer; (3) forming a seed layer by sputtering on the first insulating layer, and thereafter, forming the through-hole pattern of the through electrode a step of filling with a plating to form a metal wiring connected to the through electrode; (4) exposing the electrode pad to a height of the upper surface using a wafer adhesive a step of bonding a 20-100 μm semiconductor element wafer to the cured first insulating layer; (5) preparing a photocurable resin layer having a film thickness of 5 to 100 μm as a structure in which the supported film and the protective film are sandwiched, and The photocurable resin layer is a photocurable dry film composed of a resist composition material; (6) the photohardening is performed by covering a semiconductor element bonded to the first insulating layer by a wafer. a step of laminating the photocurable resin layer of the dry film to form a second insulating layer; (7) patterning the second insulating layer by lithography through a mask while forming An opening in the electrode pad, an opening for forming a metal wiring penetrating the second insulating layer on the metal wiring connected to the through electrode, and an opening for forming the through electrode, and then baking a step of hardening the second insulating layer; (8) after hardening, forming a seed layer by sputtering, and thereafter, opening the opening on the electrode pad to form a metal penetrating the second insulating layer The opening of the wire and the opening for forming the through electrode are filled by plating to form a metal pad on the semiconductor element, a metal wiring penetrating the second insulating layer, and a through electrode, and the plating is performed by the foregoing a step of bonding the metal pad on the semiconductor element formed by the coating and the metal wiring penetrating the second insulating layer by a metal wiring obtained by plating; (9) after forming the metal wiring, the photocurable dry film is formed The photocurable resin layer is laminated or used as a resist for the above photocurable dry film a step of forming a third insulating layer by spin coating the composition material; (10) forming a third insulating layer on the upper portion of the through electrode by patterning by a lithography technique through a mask After the opening, baking is performed to thereby cure the third insulating layer; and (11), after hardening, a step of forming solder bumps on the opening of the upper portion of the through electrode.

以下，針對各步驟進行詳細地說明。 Hereinafter, each step will be described in detail.

首先，於步驟(1)中，如第4圖所示般，於支撐基板16上塗佈暫時性接著劑17，於暫時性接著劑17上形成使用阻劑組成物材料作為光硬化性樹脂層之膜厚1~20μm的第一絕緣層7。 First, in step (1), as shown in FIG. 4, a temporary adhesive 17 is applied onto the support substrate 16, and a resist composition material is formed on the temporary adhesive 17 as a photocurable resin layer. The first insulating layer 7 having a film thickness of 1 to 20 μm.

作為支撐基板16雖無特別限定，但可使用例如矽晶圓或玻璃基板等。 The support substrate 16 is not particularly limited, and for example, a tantalum wafer or a glass substrate can be used.

又，作為暫時性接著劑17雖無特別限定，但較佳為例如熱塑性樹脂。 Further, the temporary adhesive 17 is not particularly limited, but is preferably a thermoplastic resin.

可列舉：烯烴系熱塑性彈性體、聚丁二烯系熱塑性彈性體、苯乙烯系熱塑性彈性體、苯乙烯/丁二烯系熱塑性彈性體、苯乙烯/聚烯烴系熱塑性彈性體等，尤其以耐熱性優異之氫化聚苯乙烯系彈性體較為理想。具體而言係可列舉：Tuftec(Asahi Kasei Chemicals製)、ESPOLEX SB系列(住友化學製)、RABALON(三菱化學製)、Septon(KURARAY製)、DYNARON(JSR製)等。又，可列舉以ZEONEX(日本ZEON製)為代表之環烯烴聚合物及以TOPAS(日本Polyplastics製)為代表之環狀烯烴共聚物。 又，亦可使用矽酮系熱塑性樹脂。較佳可使用例如二甲基矽酮、苯基矽酮、烷基改質矽酮、矽酮樹脂。具體而言係可列舉KF96、KF54、X-40-9800(皆為信越化學製)。 Examples thereof include an olefin thermoplastic elastomer, a polybutadiene thermoplastic elastomer, a styrene thermoplastic elastomer, a styrene/butadiene thermoplastic elastomer, a styrene/polyolefin thermoplastic elastomer, and the like, particularly heat resistant. A hydrogenated polystyrene elastomer excellent in properties is preferred. Specific examples include Tuftec (manufactured by Asahi Kasei Chemicals), ESPOLEX SB series (manufactured by Sumitomo Chemical Co., Ltd.), RABALON (manufactured by Mitsubishi Chemical Corporation), Septon (manufactured by KURARAY), and DYNARON (manufactured by JSR). Further, a cycloolefin polymer typified by ZEONEX (manufactured by Nippon Zeon Co., Ltd.) and a cyclic olefin copolymer typified by TOPAS (manufactured by Polyplastics, Japan) are mentioned. Further, an anthrone-based thermoplastic resin can also be used. For example, dimethyl fluorenone, phenyl fluorenone, alkyl modified fluorenone, fluorenone resin can be preferably used. Specifically, KF96, KF54, and X-40-9800 (all manufactured by Shin-Etsu Chemical Co., Ltd.) can be cited.

又，第一絕緣層7，係如上述般地，可藉由使用具有由含有例如(A)~(D)成分所成之化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層的光硬化性乾膜來進行疊層，或者將此阻劑組成物材料藉由旋轉塗佈等進行塗佈而形成。當然，亦可使用其他的感光性樹脂。 Further, the first insulating layer 7 can be made of a photocurable resin having a chemically amplified negative resist composition material containing, for example, (A) to (D) components, as described above. The layer of the photocurable dry film is laminated, or the resist composition material is applied by spin coating or the like. Of course, other photosensitive resins can also be used.

第一絕緣層的膜厚係1~20μm，較佳為5~10μm，若為如此之膜厚則可將所製造之半導體裝置予以薄型化，故為佳。 The film thickness of the first insulating layer is 1 to 20 μm, preferably 5 to 10 μm. If the film thickness is such a thickness, the semiconductor device to be fabricated can be made thinner.

接著，於步驟(2)中，在對於第一絕緣層7，藉由隔著遮罩之微影技術進行圖型化，如第5圖所示般地形成成為貫穿電極的通孔圖型A之後，進行烘烤，藉此使第一絕緣層7硬化。 Next, in step (2), patterning is performed on the first insulating layer 7 by a lithography technique via a mask, and a via pattern A as a through electrode is formed as shown in FIG. Thereafter, baking is performed, whereby the first insulating layer 7 is hardened.

於此圖型化中，係在形成第一絕緣層7之後，進行曝光、曝光後加熱處理(曝光後烘烤；PEB)，予以顯像，進而因應需要而進行後硬化來形成圖型。亦即，可使用周知之微影技術來進行圖型之形成。 In the patterning, after the first insulating layer 7 is formed, exposure, post-exposure heat treatment (post-exposure baking; PEB) is performed, development is performed, and post-hardening is performed as needed to form a pattern. That is, the formation of patterns can be performed using well-known lithography techniques.

在此，亦可在為了有效率地進行第一絕緣層之光硬化反應或提昇第一絕緣層7與支撐基板16之密著性，或者提昇密著後之第一絕緣層7的平坦性之目的下，因應需要而進行預備加熱(預烘烤)。預烘烤例如可以40~140℃進行1分鐘~1小時左右。 Here, in order to efficiently perform the photohardening reaction of the first insulating layer or to improve the adhesion between the first insulating layer 7 and the support substrate 16, or to improve the flatness of the first insulating layer 7 after adhesion. For the purpose, preliminary heating (prebaking) is performed as needed. The prebaking can be carried out, for example, at 40 to 140 ° C for about 1 minute to 1 hour.

接著，隔著光罩以波長190~500nm之光進行曝光，並使其硬化。光罩亦可為例如挖鑿出所期望之圖型者。另外，光罩的材質係較佳為將波長190~500nm之光遮蔽者，雖較佳可使用例如鉻等，但並不限定於此。 Next, exposure is performed with light having a wavelength of 190 to 500 nm through a photomask, and hardened. The reticle can also be, for example, a person who has dug out the desired pattern. Further, the material of the photomask is preferably such that light having a wavelength of 190 to 500 nm is shielded, and for example, chromium or the like is preferably used, but is not limited thereto.

作為波長190~500nm之光係藉由例如敏輻射線產生裝置所產生之各種波長的光，可列舉例如：g線、i線等之紫外線光、遠紫外線光(248nm、193nm)等。且，波長係較佳為248~436nm。曝光量係較佳為例如10~3,000mJ/cm2。藉由如此般地進行曝光，將曝光部分進行交聯而形成不溶於顯像液的圖型。 The light having a wavelength of 190 to 500 nm is light of various wavelengths generated by, for example, a sensitive radiation generating device, and examples thereof include ultraviolet light such as g-line or i-line, and far-ultraviolet light (248 nm, 193 nm). Further, the wavelength system is preferably 248 to 436 nm. The exposure amount is preferably, for example, 10 to 3,000 mJ/cm 2 . By performing exposure as described above, the exposed portion is crosslinked to form a pattern insoluble in the developing liquid.

進而，為了提高顯像感度而進行PEB。PEB，例如可設為以40~140℃進行0.5~10分鐘。 Further, PEB is performed in order to improve the development sensitivity. The PEB can be, for example, 0.5 to 10 minutes at 40 to 140 °C.

其後，以顯像液進行顯像。作為較佳之顯像液係可列舉IPA或PGMEA之有機溶劑。又，較佳之作為鹼水溶液的顯像液係為例如2.38%之氫氧化四甲基銨(TMAH)水溶液。於本發明之半導體裝置之製造方法中，作為顯像液係較佳可使用有機溶劑。 Thereafter, development was carried out with a developing solution. As a preferred developing liquid system, an organic solvent of IPA or PGMEA can be cited. Further, a developing solution which is preferably an aqueous alkali solution is, for example, a 2.38% aqueous solution of tetramethylammonium hydroxide (TMAH). In the method for producing a semiconductor device of the present invention, an organic solvent can be preferably used as the developer liquid.

顯像係可藉由通常之方法，例如將形成有圖型之基板浸漬於顯像液中等而進行。其後，因應需要進行洗淨、清洗、乾燥等，而得到具有期望之圖型的光硬化性樹脂層之被膜(第一絕緣層)。 The development system can be carried out by a usual method, for example, by immersing a substrate on which a pattern is formed in a developing liquid or the like. Thereafter, if necessary, washing, washing, drying, or the like is required to obtain a film (first insulating layer) having a photocurable resin layer of a desired pattern.

接著，如此般地將形成有圖型之第一絕緣層使用烘箱或加熱板，以較佳為溫度100~250℃，更佳為150~220℃，再更佳為170~190℃進行烘烤，使其硬化(後 硬化)。只要後硬化溫度為100~250℃，則可提昇第一絕緣層之交聯密度，並將殘留的揮發性成分去除，就對於支撐基板之密著力、耐熱性或強度，進而電特性之觀點而言為佳。且，後硬化時間係可設為10分鐘~10小時。 Then, the first insulating layer formed with the pattern is used to be baked using an oven or a heating plate, preferably at a temperature of 100 to 250 ° C, more preferably 150 to 220 ° C, and even more preferably 170 to 190 ° C. To harden it (after hardening). As long as the post-hardening temperature is 100 to 250 ° C, the crosslinking density of the first insulating layer can be increased, and the residual volatile components can be removed, which is in view of the adhesion, heat resistance or strength of the supporting substrate, and electrical properties. The words are better. Moreover, the post-hardening time can be set to 10 minutes to 10 hours.

接著，於步驟(3)中，於第一絕緣層7進行以濺鍍所致之種晶層形成，其後，將成為貫穿電極之通孔圖型A，藉由鍍敷來填埋，而如第6圖所示般地形成與貫穿電極連接的金屬配線(下面金屬配線)4b。 Next, in the step (3), the seed layer formed by sputtering is formed on the first insulating layer 7, and then the via pattern A of the through electrode is filled and buried by plating. As shown in Fig. 6, a metal wiring (lower metal wiring) 4b connected to the through electrode is formed.

在進行鍍敷時，例如，於第一絕緣層7上藉由濺鍍而形成種晶層之後，進行鍍敷阻劑之圖型化，其後，進行電鍍等，於成為貫穿電極之通孔圖型A進行金屬鍍敷之填埋與下面金屬配線4b之形成。在形成金屬配線之後，藉由蝕刻去除種晶層，使第一絕緣層7露出。 When plating is performed, for example, after forming a seed layer on the first insulating layer 7 by sputtering, patterning of the plating resist is performed, and then plating or the like is performed to form a through hole through the electrode. The pattern A is formed by filling a metal plating and forming the metal wiring 4b below. After the metal wiring is formed, the seed layer is removed by etching to expose the first insulating layer 7.

另外，下面金屬配線4b雖只要如同成為所期望之配線寬度般地進行適當調整即可，但尤其以成為0.1~10μm之厚度的方式形成於第一絕緣層上為佳。 In addition, the lower metal wiring 4b may be appropriately adjusted as long as the desired wiring width, but it is preferably formed on the first insulating layer so as to have a thickness of 0.1 to 10 μm.

接著，於步驟(4)中，如第7圖所示般，使用晶片黏合劑10將電極墊露出於上部表面之高度20~100μm的半導體元件2晶片黏合於硬化後的第一絕緣層7上。 Next, in the step (4), as shown in FIG. 7, the semiconductor element 2 having the electrode pad exposed to the upper surface at a height of 20 to 100 μm is bonded to the hardened first insulating layer 7 by using the wafer adhesive 10. .

另外，晶片黏合劑10係可為周知之接著劑。 In addition, the wafer adhesive 10 can be a well-known adhesive.

又，只要半導體元件2的高度為20~100μm，則可將所製造之半導體裝置進行薄型化，故為佳。 Moreover, as long as the height of the semiconductor element 2 is 20 to 100 μm, it is preferable to reduce the thickness of the semiconductor device to be manufactured.

接著，於步驟(5)中，準備具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構， 且該光硬化性樹脂層為由阻劑組成物材料所構成的光硬化性乾膜。 Next, in the step (5), a photocurable resin layer having a film thickness of 5 to 100 μm is prepared as a structure in which the supported film and the protective film are sandwiched. Further, the photocurable resin layer is a photocurable dry film composed of a resist composition material.

以下，針對於本發明所使用之光硬化性乾膜與其製造方法進行詳細地說明。 Hereinafter, the photocurable dry film used in the present invention and a method for producing the same will be described in detail.

於本發明之半導體裝置之製造方法中，於第二絕緣層之形成所使用的光硬化性乾膜，係具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構，且光硬化性樹脂層為由阻劑組成物材料所構成者。 In the method for producing a semiconductor device of the present invention, the photocurable dry film used for forming the second insulating layer is a photocurable resin layer having a film thickness of 5 to 100 μm, which is sandwiched between the supported film and the protective film. The structure and the photocurable resin layer are composed of a resist composition material.

於本發明之半導體裝置之製造方法中，於第二絕緣層之形成所使用的光硬化性乾膜之光硬化性樹脂層的膜厚為5~100μm，若為如此之膜厚則可將所製造之半導體裝置進行薄型化，故為佳。 In the method for producing a semiconductor device of the present invention, the film thickness of the photocurable resin layer of the photocurable dry film used for forming the second insulating layer is 5 to 100 μm, and if it is such a film thickness, the film thickness can be It is preferable that the manufactured semiconductor device is made thinner.

另外，於在第一絕緣層及第三絕緣層之形成使用光硬化性乾膜的情況中，只要準備使光硬化性樹脂層之膜厚成為任意的厚度者來進行使用即可。 In the case where a photocurable dry film is used for the formation of the first insulating layer and the third insulating layer, the film thickness of the photocurable resin layer may be used to have an arbitrary thickness.

於本發明所使用之光硬化性乾膜中，係藉由將感光性材料之組成物的各成分進行攪拌混合，其後，藉由過濾器等進行過濾，而可調製用來形成光硬化性樹脂層之阻劑組成物材料。 In the photocurable dry film used in the present invention, each component of the composition of the photosensitive material is stirred and mixed, and then filtered by a filter or the like to prepare photocurability. Resist composition material of the resin layer.

在此，作為阻劑組成物材料係以含有上述之(A)~(D)成分而成之化學增幅型負型阻劑組成物材料較為理想。 Here, as the resist composition material, a chemically amplified negative resist composition material containing the above components (A) to (D) is preferable.

另外，當然亦可使用其他的感光性樹脂。 Further, of course, other photosensitive resin can also be used.

於本發明所使用之光硬化性乾膜中所使用的支撐薄膜係可為單一，亦可為將複數之聚合物薄膜進行層 合而成的多層薄膜。另外，乾膜係被支撐薄膜及保護薄膜所包夾之薄膜。 The support film used in the photocurable dry film used in the present invention may be a single layer or may be a layer of a plurality of polymer films. A multilayer film formed. In addition, the dry film is a film sandwiched between the support film and the protective film.

作為支撐薄膜的材質係可列舉：聚乙烯、聚丙烯、聚碳酸酯、聚對苯二甲酸乙二酯等之合成樹脂薄膜等，較佳為具有適度之可撓性、機械性強度及耐熱性之聚對苯二甲酸乙二酯。又，針對此等之薄膜亦可為進行了如電暈處理或塗佈有剝離劑般之各種處理者。 Examples of the material of the support film include synthetic resin films such as polyethylene, polypropylene, polycarbonate, and polyethylene terephthalate, and preferably have moderate flexibility, mechanical strength, and heat resistance. Polyethylene terephthalate. Further, the film for such a film may be subjected to various treatments such as corona treatment or application of a release agent.

此等係可使用市售品，可列舉例如：Cerapeel WZ(RX)、Cerapeel BX8(R)(以上，Toray Films加工(股)製)、E7302、E7304(以上，東洋紡績(股)製)、PUREX G31、PUREX G71T1(以上，Teijin DuPont Films(股)製)、PET38×1-A3、PET38×1-V8、PET38×1-X08(以上，NIPPA(股)製)等。 Commercially available products can be used, and examples thereof include Cerapeel WZ (RX), Cerapeel BX8 (R) (above, Toray Films Processing Co., Ltd.), E7302, and E7304 (above, Toyo Textile Co., Ltd.). PUREX G31, PUREX G71T1 (above, manufactured by Teijin DuPont Films Co., Ltd.), PET38×1-A3, PET38×1-V8, PET38×1-X08 (above, manufactured by NIPPA Co., Ltd.).

於本發明所使用之光硬化性乾膜中所使用的保護薄膜雖可使用與上述之支撐薄膜相同者，但較佳為具有適度的可撓性之聚對苯二甲酸乙二酯及聚乙烯。此等係可使用市售品，作為聚對苯二甲酸乙二酯係已例示者，作為聚乙烯係可列舉例如GF-8(TAMAPOLY(股)製)、PE薄膜0型(NIPPA(股)製)。 The protective film used in the photocurable dry film used in the present invention may be the same as the above-mentioned support film, but preferably has a moderate flexibility of polyethylene terephthalate and polyethylene. . Commercially available products can be used as the polyethylene terephthalate system. Examples of the polyethylene system include GF-8 (manufactured by TAMAPOLY Co., Ltd.) and PE film type 0 (NIPPA). system).

上述之支撐薄膜及保護薄膜的厚度，就光硬化性乾膜製造之安定性及對於捲芯之捲翹，所謂的防止捲曲之觀點而言，任一者皆較佳為5~100μm。 The thickness of the above-mentioned support film and protective film is preferably from 5 to 100 μm from the viewpoint of the stability of the photocurable dry film production and the curling of the core, so-called curl prevention.

接著，針對於本發明所使用之光硬化性乾膜之製造方法進行說明。上述光硬化性乾膜之製造裝置係可 使用一般用以製造黏著劑製品的薄膜塗佈機。作為上述薄膜塗佈機係可列舉例如：點塗佈機、反轉逗點塗佈機(Comma Reverse Coater)、多層塗佈機(Multi Coater)、模具塗佈機、唇口塗佈機、唇式反轉塗佈機(Lip reverse Coater)、直接槽輥塗佈機(direct gravure coater)、補償槽輥塗佈機(offset gravure coater)、三輥式底層反轉塗佈機、四輥式底層反轉塗佈機等。 Next, a method of producing a photocurable dry film used in the present invention will be described. The above photocurable dry film manufacturing apparatus is A film coater generally used to make adhesive articles is used. Examples of the film coating machine include a dot coater, a Comma Reverse Coater, a Multi Coater, a die coater, a lip coater, and a lip. Lip reverse Coater, direct gravure coater, offset gravure coater, three-roll bottom coater, four-roller bottom coat Reverse the coater and the like.

將支撐薄膜從薄膜塗佈機之捲出軸放出，通過薄膜塗佈機之塗佈頭時，於支撐薄膜上以特定的厚度塗佈阻劑組成物材料來形成光硬化性樹脂層，之後，以特定的溫度與特定的時間通過熱風循環烘箱，將在支撐薄膜上乾燥後的光硬化性樹脂層與從薄膜塗佈機之其他的捲出軸放出之保護薄膜一起以特定的壓力通過疊層輥來與支撐薄膜上之光硬化性樹脂層貼合後，捲取於薄膜塗佈機之捲取軸，藉此而製造。於此情況中，作為熱風循環烘箱之溫度係較佳為25~150℃，作為通過時間係較佳為1~100分鐘，作為疊層輥之壓力係較佳為0.01~5MPa。 The support film is discharged from the winding shaft of the film coater, and when passing through the coating head of the film coater, the resist composition material is applied to the support film at a specific thickness to form a photocurable resin layer. Thereafter, The photocurable resin layer dried on the support film is passed through the hot air circulation oven at a specific temperature and for a specific time, and is laminated with a protective film discharged from the other winding shaft of the film coater at a specific pressure. The roll is bonded to the photocurable resin layer on the support film, and then wound up on a take-up reel of the film coater to be manufactured. In this case, the temperature of the hot air circulation oven is preferably 25 to 150 ° C, and the passage time is preferably 1 to 100 minutes, and the pressure of the laminating roller is preferably 0.01 to 5 MPa.

可利用上述般的方法製作光硬化性乾膜，藉由使用如此之光硬化性乾膜，將載置於支撐基板上之第一絕緣層上的半導體元件進行填埋的特性優異，又可緩和在形成半導體裝置後將支撐基板去除時，或進行個片化時所產生的應力，因此，作為目的之半導體裝置並不會翹曲，而適於將半導體裝置進行層合，或載置於實施了配線之基板。 The photocurable dry film can be produced by the above-described method, and by using such a photocurable dry film, the semiconductor element mounted on the first insulating layer on the support substrate can be filled with excellent characteristics and can be alleviated. When the support substrate is removed after the semiconductor device is formed, or the stress generated during the sheet formation is performed, the intended semiconductor device does not warp, and is suitable for laminating or mounting the semiconductor device. The substrate of the wiring.

接著，於步驟(6)中，將保護薄膜從以上述方式準備好的光硬化性乾膜剝離，如第8圖(a)所示般，以覆蓋晶片黏合於第一絕緣層7上之半導體元件2的方式來將光硬化性乾膜之光硬化性樹脂層進行疊層，藉此而形成第二絕緣層8。 Next, in the step (6), the protective film is peeled off from the photocurable dry film prepared in the above manner, as shown in FIG. 8(a), to cover the semiconductor to which the wafer is bonded to the first insulating layer 7. In the form of the element 2, the photocurable resin layer of the photocurable dry film is laminated, whereby the second insulating layer 8 is formed.

作為貼附光硬化性乾膜的裝置係較佳為真空疊層機。將光硬化性乾膜安裝於裝置上，在特定真空度之真空腔內，使用特定壓力之貼附輥，在特定之溫度的工作台上，使光硬化性乾膜之保護膜剝離而露出後的光硬化性樹脂層密著於基板。另外，作為上述溫度係較佳為60~120℃，作為上述壓力係較佳為0~5.0MPa，作為上述真空度係較佳為50~500Pa。藉由進行真空疊層，而不會於半導體元件周邊發生空隙，故為佳。 The apparatus to which the photocurable dry film is attached is preferably a vacuum laminator. The photocurable dry film is attached to the apparatus, and the protective film of the photocurable dry film is peeled off after being exposed on a specific temperature table in a vacuum chamber having a specific degree of vacuum. The photocurable resin layer is adhered to the substrate. Further, the temperature is preferably 60 to 120 ° C, the pressure is preferably 0 to 5.0 MPa, and the vacuum is preferably 50 to 500 Pa. It is preferable to carry out vacuum lamination without causing voids in the periphery of the semiconductor element.

又，此時，如第8圖(b)所示般，在於半導體元件2上將光硬化性乾膜進行疊層而形成第二絕緣層8時，有時半導體元件2上之第二絕緣層8的膜厚會變厚，或隨著從半導體元件2往周邊偏離而使膜厚漸漸變薄。可較佳地使用藉由機械性地加壓而使此膜厚的變化平坦化，如第8圖(a)所示般，使半導體元件上之膜厚減薄的方法。 Moreover, in this case, as shown in FIG. 8(b), when the photocurable dry film is laminated on the semiconductor element 2 to form the second insulating layer 8, the second insulating layer on the semiconductor element 2 may be present. The film thickness of 8 becomes thick, or the film thickness becomes gradually thinner as it deviates from the semiconductor element 2 to the periphery. It is preferable to use a method of flattening the change in film thickness by mechanical pressurization, and to reduce the film thickness on the semiconductor element as shown in Fig. 8(a).

接著，於步驟(7)中，如第9圖所示般，對於第二絕緣層8，藉由隔著遮罩之微影技術進行圖型化，而同時形成電極墊上之開口B、用以在與貫穿電極連接的金屬配線(下面金屬配線)4b上形成貫穿第二絕緣層的金屬配線(貫穿金屬配線)之開口C、以及用以形成貫穿電極之開 口D，之後，進行烘烤，藉此使第二絕緣層8硬化。 Next, in step (7), as shown in FIG. 9, the second insulating layer 8 is patterned by a lithography technique through a mask, and an opening B on the electrode pad is simultaneously formed for An opening C through which a metal wiring (through metal wiring) penetrating the second insulating layer is formed on the metal wiring (lower metal wiring) 4b connected to the through electrode, and an opening for forming the through electrode Port D, after which baking is performed, whereby the second insulating layer 8 is hardened.

於此圖型化中，係在形成第二絕緣層8之後，進行曝光、曝光後加熱處理(曝光後烘烤；PEB)，予以顯像，進而因應需要而進行後硬化來形成圖型。亦即，可使用周知之微影技術來進行圖型之形成，只要以與上述之第一絕緣層之圖型化相同的方法進行即可。 In the patterning, after the second insulating layer 8 is formed, exposure, post-exposure heat treatment (post-exposure baking; PEB) is performed, development is performed, and post-hardening is performed as needed to form a pattern. That is, the pattern formation can be performed using a well-known lithography technique, and it is only necessary to perform the same method as the patterning of the first insulating layer described above.

於本發明之半導體裝置之製造方法中，由於是藉由將電極墊上之開口B、用以形成貫穿金屬配線之開口C、以及用以形成貫穿電極之開口D進行整批曝光而同時形成，因此為合理。 In the method of fabricating the semiconductor device of the present invention, since the opening B on the electrode pad, the opening C for forming the through metal wiring, and the opening D for forming the through electrode are simultaneously exposed and formed in a batch, To be reasonable.

進而，於步驟(8)中，如第10圖所示般，在第二絕緣層8之硬化後，進行以濺鍍所致之種晶層形成，其後，將電極墊上之開口B、用以形成貫穿第二絕緣層的金屬配線(貫穿金屬配線)之開口C、以及用以形成貫穿電極之開口D，藉由鍍敷來填埋，而形成半導體元件上金屬墊3、貫穿第二絕緣層之金屬配線(貫穿金屬配線)4c、以及貫穿電極5，並且將藉由鍍敷所形成的半導體元件上金屬墊3與貫穿第二絕緣層的金屬配線(貫穿金屬配線)4c藉由以鍍敷所得之金屬配線(上面金屬配線)4a相連結。 Further, in the step (8), as shown in FIG. 10, after the second insulating layer 8 is cured, the seed layer formation by sputtering is performed, and thereafter, the opening B on the electrode pad is used. An opening C for forming a metal wiring (through metal wiring) penetrating through the second insulating layer, and an opening D for forming a through electrode are filled by plating to form a metal pad 3 on the semiconductor element and penetrate the second insulation Metal wiring (through metal wiring) 4c of the layer, and through electrode 5, and metal pad 3 on the semiconductor element formed by plating and metal wiring (through metal wiring) 4c penetrating the second insulating layer are plated The metal wiring (upper metal wiring) 4a obtained by the application is connected.

在進行鍍敷時，係與上述之步驟(3)相同地，例如，在藉由濺鍍而形成種晶層之後，進行鍍敷阻劑之圖型化，其後，進行電鍍等，形成半導體元件上金屬墊3、貫穿金屬配線4c、以及貫穿電極5，並且形成上面金屬配線4a而使半導體元件上金屬墊3與貫穿金屬配線4c相連 結。 In the case of plating, similarly to the above step (3), for example, after the seed layer is formed by sputtering, patterning of the plating resist is performed, and then plating or the like is performed to form a semiconductor. The metal pad 3, the through metal wiring 4c, and the through electrode 5 are formed on the element, and the upper metal wiring 4a is formed to connect the metal pad 3 on the semiconductor element to the through metal wiring 4c. Knot.

另外，上面金屬配線4a雖只要如同成為所期望之配線寬度般地進行適當調整即可，但尤其以成為0.1~10μm之厚度的方式形成於第二絕緣層上為佳。 In addition, the upper metal wiring 4a may be appropriately adjusted as long as the desired wiring width, but it is preferably formed on the second insulating layer so as to have a thickness of 0.1 to 10 μm.

又，為了使貫穿電極5之鍍敷充足，如第11圖所示般，亦可另外再對貫穿電極5實施電鍍，並以金屬鍍敷18將貫穿電極5進行填埋。 Moreover, in order to make the plating of the penetrating electrode 5 sufficient, as shown in FIG. 11, the penetrating electrode 5 may be further plated, and the penetrating electrode 5 may be filled with the metal plating 18.

又，為了使貫穿金屬配線4c之鍍敷充足，亦可另外再對貫穿金屬配線4c實施電鍍。 Further, in order to sufficiently plate the through metal wiring 4c, the through metal wiring 4c may be additionally plated.

接著，於步驟(9)中，金屬配線之形成後，將光硬化性乾膜之光硬化性樹脂層進行疊層或者將使用於光硬化性乾膜之阻劑組成物材料進行旋轉塗佈，藉此如第12圖所示般地形成第三絕緣層9。 Next, in step (9), after the formation of the metal wiring, the photocurable resin layer of the photocurable dry film is laminated, or the resist composition material used for the photocurable dry film is spin-coated. Thereby, the third insulating layer 9 is formed as shown in Fig. 12.

第三絕緣層9之形成，係與上述之第一絕緣層之形成相同地，可藉由使用具有由含有例如(A)~(D)成分所成之化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層的光硬化性乾膜來進行疊層，或者將此阻劑組成物材料藉由旋轉塗佈等進行塗佈而形成。當然，亦可使用其他的感光性樹脂。 The third insulating layer 9 is formed by using a chemically amplified negative resist composition material containing, for example, (A) to (D) components, in the same manner as the formation of the first insulating layer described above. The photocurable dry film of the photocurable resin layer is laminated, or the resist composition material is applied by spin coating or the like. Of course, other photosensitive resins can also be used.

又，若第三絕緣層之膜厚為5~100μm，則可將所製造之半導體裝置進行薄型化，故為佳。 Further, when the thickness of the third insulating layer is 5 to 100 μm, the semiconductor device to be manufactured can be made thinner, which is preferable.

接著，於步驟(10)中，如第13圖所示般，在對於第三絕緣層9，藉由隔著遮罩之微影技術進行圖型化而於貫穿電極5上部形成開口E之後，進行烘烤，藉此使 第三絕緣層9硬化。 Next, in step (10), as shown in FIG. 13, after the opening E is formed in the upper portion of the through electrode 5 by patterning the third insulating layer 9 by the lithography technique through the mask, Baking, thereby making The third insulating layer 9 is hardened.

於此圖型化中，係在形成第三絕緣層9之 後，進行曝光、曝光後加熱處理(曝光後烘烤；PEB)，予以顯像，進而因應需要而進行後硬化來形成圖型。亦即，可使用周知之微影技術來進行圖型之形成，只要以與上述之第一絕緣層之圖型化相同的方法進行即可。 In this patterning, the third insulating layer 9 is formed. Thereafter, exposure treatment, post-exposure heat treatment (post-exposure baking; PEB), development, and post-hardening as needed are required to form a pattern. That is, the pattern formation can be performed using a well-known lithography technique, and it is only necessary to perform the same method as the patterning of the first insulating layer described above.

接著，於步驟(11)中，係在第三絕緣層之硬化後，於貫穿電極上部之開口E形成焊錫凸塊。 Next, in the step (11), after the third insulating layer is cured, solder bumps are formed in the opening E of the upper portion of the through electrode.

作為焊錫凸塊之形成方法，例如，如第14圖所示般，於貫穿電極上部之開口E藉由鍍敷來形成貫穿電極上金屬墊19。接著，可於貫穿電極上金屬墊19上形成焊錫球20，將此製成焊錫凸塊。 As a method of forming the solder bump, for example, as shown in Fig. 14, the metal pad 19 on the through electrode is formed by plating in the opening E of the upper portion of the through electrode. Next, a solder ball 20 can be formed on the metal pad 19 on the through electrode to form a solder bump.

又，可於上述步驟(8)中，如第15圖所示般，為了使貫穿電極5之鍍敷充足，而以SnAg進行另外實施的鍍敷來施以SnAg鍍敷21，其後，於步驟(9)中，係與上述相同地形成第三絕緣層9，於步驟(10)中以於貫穿電極上部形成開口E的方式進行圖型化，藉此而使SnAg鍍敷21露出，之後，藉由烘烤使其硬化，作為步驟(11)係藉由使SnAg鍍敷21熔融而如第16圖所示般地使電極朝貫穿電極上部之開口E隆起，而形成使SnAg隆起後的電極22之焊錫凸塊。 Further, in the above step (8), as shown in Fig. 15, in order to sufficiently plate the penetrating electrode 5, SnAg plating 21 is applied by plating which is additionally performed by SnAg, and thereafter, In the step (9), the third insulating layer 9 is formed in the same manner as described above, and in the step (10), the opening E is formed in the upper portion of the through electrode, whereby the SnAg plating 21 is exposed, and thereafter By baking and hardening, as the step (11), the SnAg plating 21 is melted, and as shown in Fig. 16, the electrode is raised toward the opening E of the penetrating electrode upper portion, thereby forming the SnAg bulging. Solder bumps of the electrodes 22.

進而，於上述之步驟(11)之後，如第17圖所示般，將於上述之步驟(1)中與第一絕緣層7暫時接著的支撐基板16去除，藉此而可使貫穿電極5之焊錫球20的 相反側(下面金屬配線4b)露出，將露出後的種晶層藉由蝕刻去除，而使金屬鍍敷部露出，藉此可使貫穿電極5之上部與下部電導通。進而，其後，藉由進行切割而予以個片化，可得到經個片化的半導體裝置23。 Further, after the above step (11), as shown in FIG. 17, the support substrate 16 temporarily in contact with the first insulating layer 7 in the above step (1) is removed, whereby the through electrode 5 can be formed. Solder ball 20 The opposite side (the lower metal wiring 4b) is exposed, and the exposed seed layer is removed by etching to expose the metal plating portion, whereby the upper portion and the lower portion of the through electrode 5 can be electrically conducted. Further, thereafter, by dicing, the diced semiconductor device 23 can be obtained.

於形成有使SnAg隆起後的電極22之焊錫凸塊的情況中亦相同地，如第18圖所示般，藉由將支撐基板16去除，而可使貫穿電極5之SnAg隆起後的電極22的相反側(下面金屬配線4b)露出，將露出後的種晶層藉由蝕刻去除，而使金屬鍍敷部露出，藉此可使貫穿電極5之上部與下部電導通。進而，其後，藉由進行切割而予以個片化，可得到經個片化的半導體裝置24。 Similarly, in the case where the solder bumps of the electrode 22 after the SnAg is raised are formed, as shown in FIG. 18, the electrode 22 after the SnAg bumping of the through electrode 5 can be removed by removing the support substrate 16. The opposite side (the lower metal wiring 4b) is exposed, and the exposed seed layer is removed by etching to expose the metal plating portion, whereby the upper portion and the lower portion of the through electrode 5 can be electrically conducted. Further, thereafter, by dicing, the diced semiconductor device 24 can be obtained.

另外，如上述般之本發明之製造方法係特別適於小型化、薄型化者，且可得到作為半導體裝置之厚度為50~300μm，較佳為70~150μm之薄的小型化之半導體裝置。 In addition, the manufacturing method of the present invention is particularly suitable for miniaturization and thinning, and a semiconductor device having a thickness of 50 to 300 μm, preferably 70 to 150 μm, which is a semiconductor device, can be obtained.

上述之經個片化的半導體裝置23或者經個片化之半導體裝置24，係如第19圖、第20圖所示般，分別將複數個，包夾絕緣樹脂層12，並藉由焊錫凸塊而電接合，進行層合而可製成層合型半導體裝置。又，如第21圖、第22圖所示般，亦可將層合後的半導體裝置載置於具有電路的基板(配線基板14)。另外，第19圖、第20圖、第21圖、第22圖係分別將經個片化的半導體裝置23或24進行倒裝晶片黏合的例子。 The above-described diced semiconductor device 23 or the diced semiconductor device 24 is formed by sandwiching the insulating resin layer 12 and soldering the bumps as shown in FIG. 19 and FIG. 20, respectively. The laminate is electrically bonded and laminated to form a laminated semiconductor device. Further, as shown in FIGS. 21 and 22, the laminated semiconductor device may be placed on a substrate (wiring substrate 14) having a circuit. Further, Fig. 19, Fig. 20, Fig. 21, and Fig. 22 show an example in which the individualized semiconductor devices 23 or 24 are flip-chip bonded.

又，如第23圖、第24圖所示般，在將以上 述方式所製造的層合型半導體裝置載置於配線基板14之後，以絕緣封裝樹脂層15進行封裝，藉此而可製造封裝後層合型半導體裝置。 Moreover, as shown in Fig. 23 and Fig. 24, The laminated semiconductor device manufactured in the above-described manner is placed on the wiring substrate 14 and then encapsulated by the insulating encapsulating resin layer 15, whereby a post-package laminated semiconductor device can be manufactured.

在此，作為絕緣樹脂層12或絕緣封裝樹脂層15所使用之樹脂係可使用一般於該用途中所使用者，可使用例如環氧樹脂或矽酮樹脂或此等之複合樹脂。 Here, as the resin used for the insulating resin layer 12 or the insulating encapsulating resin layer 15, a user generally used for this application can be used, and for example, an epoxy resin or an anthrone resin or a composite resin thereof can be used.

以上述方式所製造的本發明之半導體裝置、層合型半導體裝置、及封裝後層合型半導體裝置係可適合使用於對半導體晶片所實施之扇出配線(fan-out wiring)或WCSP(晶圓級晶片尺寸封裝)用。 The semiconductor device, the laminated semiconductor device, and the package-sealed semiconductor device of the present invention manufactured in the above manner can be suitably used for fan-out wiring or WCSP (crystal) performed on a semiconductor wafer. Round wafer size package).

如以上所述般，若為本發明之半導體裝置，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而使對於配線基板之載置或半導體裝置之層合為容易，進而，成為即使半導體元件的高度為數十μm亦可於半導體元件周邊無空隙等地進行填埋，即使在金屬配線的密度為大之情況中半導體裝置之翹曲亦受到抑制的半導體裝置。 As described above, in the case of the semiconductor device of the present invention, the semiconductor element is formed by fine electrode formation, and the through electrode is applied to the outside of the semiconductor element, thereby mounting the wiring substrate or laminating the semiconductor device. In addition, even if the height of the semiconductor element is several tens of μm, the semiconductor element can be filled without voids, and the semiconductor device can be warped even when the density of the metal wiring is large. Device.

又，若為本發明之半導體裝置之製造方法，則藉由於半導體元件上實施微細的電極形成，並於半導體元件外部施以貫穿電極，而可容易進行對於配線基板之載置或半導體裝置之層合，又可容易進行貫穿電極、電極墊部之開口等的加工。 Further, in the method of manufacturing a semiconductor device of the present invention, by forming a fine electrode on the semiconductor element and applying a through electrode to the outside of the semiconductor element, it is possible to easily perform mounting on the wiring substrate or a layer of the semiconductor device. Further, the processing of the through electrode, the opening of the electrode pad portion, and the like can be easily performed.

進而，以如此方式所得到的本發明之半導體裝置係由於對於配線基板之載置或半導體裝置之層合為容易，因此 可製成將半導體裝置進行層合之層合型半導體裝置或將其載置於配線基板並加以封裝之封裝後層合型半導體裝置。 Further, the semiconductor device of the present invention obtained in this manner is easy to laminate on a wiring substrate or a semiconductor device, and therefore A laminated semiconductor device in which a semiconductor device is laminated or a packaged laminated semiconductor device in which a semiconductor device is mounted on a wiring substrate and packaged can be prepared.

另外，本發明並不限定於上述實施形態。上述實施形態係為例示，具有與本發明之申請專利範圍所記載之技術思想實質上相同的構造，且發揮相同的作用效果者係任一者皆包含於本發明之技術範圍內。 Further, the present invention is not limited to the above embodiment. The above-described embodiments are exemplified, and have substantially the same structure as the technical idea described in the patent application scope of the present invention, and any one of the same effects is included in the technical scope of the present invention.

1‧‧‧半導體裝置 1‧‧‧Semiconductor device

2‧‧‧半導體元件 2‧‧‧Semiconductor components

3‧‧‧半導體元件上金屬墊 3‧‧‧Metal components on metal pads

4‧‧‧金屬配線 4‧‧‧Metal wiring

4a‧‧‧上面金屬配線 4a‧‧‧Top metal wiring

4b‧‧‧下面金屬配線 4b‧‧‧Under metal wiring

4c‧‧‧貫穿金屬配線 4c‧‧‧through metal wiring

5‧‧‧貫穿電極 5‧‧‧through electrode

6‧‧‧焊錫凸塊 6‧‧‧ solder bumps

7‧‧‧第一絕緣層 7‧‧‧First insulation

8‧‧‧第二絕緣層 8‧‧‧Second insulation

9‧‧‧第三絕緣層 9‧‧‧ Third insulation

10‧‧‧晶片黏合劑 10‧‧‧ wafer adhesive

Claims (14)

一種半導體裝置，其係具有半導體元件、與電連接於該半導體元件之半導體元件上金屬墊及金屬配線，且該金屬配線係電連接於貫穿電極及焊錫凸塊，其特徵為，具有：載置有前述半導體元件之第一絕緣層、形成於前述半導體元件上之第二絕緣層、以及形成於該第二絕緣層上之第三絕緣層，前述金屬配線係在前述第二絕緣層的上面經由前述半導體元件上金屬墊而電連接於前述半導體元件，且從前述第二絕緣層的上面貫穿前述第二絕緣層而在前述第二絕緣層的下面電連接於前述貫穿電極者。 A semiconductor device comprising a semiconductor element, a metal pad and a metal wiring electrically connected to the semiconductor element, wherein the metal wiring is electrically connected to the through electrode and the solder bump, and is characterized in that: a first insulating layer of the semiconductor element, a second insulating layer formed on the semiconductor element, and a third insulating layer formed on the second insulating layer, wherein the metal wiring is on the upper surface of the second insulating layer via The semiconductor element is electrically connected to the semiconductor element via a metal pad, and is electrically connected to the through electrode from the upper surface of the second insulating layer through the second insulating layer and under the second insulating layer. 如請求項1之半導體裝置，其中，前述第一絕緣層係藉由光硬化性乾膜或光硬化性阻劑塗佈膜所形成者，前述第二絕緣層係藉由前述光硬化性乾膜所形成者，前述第三絕緣層係藉由前述光硬化性乾膜或光硬化性阻劑塗佈膜所形成者。 The semiconductor device according to claim 1, wherein the first insulating layer is formed of a photocurable dry film or a photocurable resist coating film, and the second insulating layer is formed by the photocurable dry film. In the case where the third insulating layer is formed by the photocurable dry film or the photocurable resist coating film. 如請求項1或2之半導體裝置，其中，前述半導體元件的高度為20~100μm，前述第一絕緣層的膜厚為1~20μm，前述第二絕緣層的膜厚為5~100μm，前述第三絕緣層的膜厚為5~100μm，前述半導體裝置的厚度為50~300μm。 The semiconductor device according to claim 1 or 2, wherein the semiconductor element has a height of 20 to 100 μm, the first insulating layer has a thickness of 1 to 20 μm, and the second insulating layer has a thickness of 5 to 100 μm. The thickness of the three insulating layers is 5 to 100 μm, and the thickness of the semiconductor device is 50 to 300 μm. 如請求項1或2之半導體裝置，其中，前述光硬化性乾膜係具有由化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層之光硬化性乾膜，該化學增幅型負型阻 劑組成物材料係含有：(A)具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物、 (式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基；Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係 各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；h為0、1、2中之任一者)(B)由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑、(C)藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑、以及(D)溶劑。 The semiconductor device according to claim 1 or 2, wherein the photocurable dry film has a photocurable dry film of a photocurable resin layer composed of a chemically amplified negative resist composition material, the chemically amplified type The negative resist composition material contains: (A) a polymer compound having an anthracene skeleton having a weight average molecular weight of 3,000 to 500,000, which has a repeating unit represented by the following general formula (1), (wherein R 1 to R 4 represent a monovalent hydrocarbon group having the same or different carbon number of 1 to 8; m is an integer of 1 to 100; a, b, c, and d are 0 or a positive number, and a, b, c, and d are not 0 at the same time; however, a+b+c+d=1; further, X is an organic group represented by the following general formula (2); Y is represented by the following general formula (3) Organic basis (where, Z is composed of The divalent organic group selected by any one of them, n is 0 or 1; each of R 5 and R 6 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; k is Any of 0, 1, 2) (where, V is composed of The divalent organic group selected by any one of them, p is 0 or 1; each of R 7 and R 8 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; h is Any one of 0, 1, 2) (B) an amine condensate modified by formaldehyde or formaldehyde-alcohol, having an average of 2 or more methylol groups or alkoxyl groups in one molecule One or two or more kinds of crosslinking agents selected from the group consisting of phenolic compounds, and (C) are decomposed by light having a wavelength of from 190 to 500 nm to produce an acid photoacid generator and (D) a solvent. 一種層合型半導體裝置，其特徵為，將如請求項1至4中任一項之半導體裝置倒裝晶片化並複數層合而成者。 A laminated semiconductor device characterized in that the semiconductor device according to any one of claims 1 to 4 is flip-chip bonded and laminated in plural. 一種封裝後層合型半導體裝置，其特徵為，將如請求項5之層合型半導體裝置載置於具有電路的基板上，並以絕緣封裝樹脂層加以封裝而成者。 A post-package laminated semiconductor device characterized in that a laminated semiconductor device according to claim 5 is placed on a substrate having a circuit and encapsulated with an insulating encapsulating resin layer. 一種半導體裝置之製造方法，其特徵為，具有以下步驟：(1)於支撐基板上塗佈暫時性接著劑，於該暫時性接著劑上形成使用阻劑組成物材料作為光硬化性樹脂層之膜厚1~20μm的第一絕緣層之步驟；(2)在對於前述第一絕緣層，藉由隔著遮罩之微影技術進行圖型化而形成成為貫穿電極的通孔圖型之後，進行烘烤，藉此使前述第一絕緣層硬化之步驟；(3)於前述第一絕緣層進行以濺鍍所致之種晶層形成，其後，將前述成為貫穿電極之通孔圖型，藉由鍍敷來填埋，而形成與貫穿電極連接的金屬配線之步驟；(4)使用晶片黏合劑將電極墊露出於上部表面之高度20~100μm的半導體元件晶片黏合於前述硬化後的第一絕緣層上之步驟；(5)準備具有膜厚5~100μm之光硬化性樹脂層為被支撐薄膜與保護薄膜包夾的結構，且該光硬化性樹脂層為由阻劑組成物材料所構成的光硬化性乾膜之步驟；(6)藉由以覆蓋被晶片黏合於前述第一絕緣層上之半導體元件的方式將前述光硬化性乾膜之光硬化性樹脂層進行疊層，而形成第二絕緣層之步驟；(7)對於前述第二絕緣層，藉由隔著遮罩之微影技術 進行圖型化，而同時形成前述電極墊上之開口、用以在與前述貫穿電極連接的金屬配線上形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，之後，進行烘烤，藉此使前述第二絕緣層硬化之步驟；(8)在硬化後，進行以濺鍍所致之種晶層形成，其後，將前述電極墊上之開口、用以形成貫穿前述第二絕緣層的金屬配線之開口、以及用以形成前述貫穿電極之開口，藉由鍍敷來填埋，而形成半導體元件上金屬墊、貫穿前述第二絕緣層之金屬配線、以及貫穿電極，並且將藉由前述鍍敷所形成的前述半導體元件上金屬墊與貫穿前述第二絕緣層的金屬配線藉由以鍍敷所得之金屬配線相連結之步驟；(9)金屬配線形成後，將前述光硬化性乾膜之光硬化性樹脂層進行疊層或者將使用於前述光硬化性乾膜之阻劑組成物材料進行旋轉塗佈，藉此形成第三絕緣層之步驟；(10)在對於前述第三絕緣層，藉由隔著遮罩之微影技術進行圖型化而於前述貫穿電極上部形成開口之後，進行烘烤，藉此使前述第三絕緣層硬化之步驟；(11)硬化後，於前述貫穿電極上部之開口形成焊錫凸塊之步驟。 A method of manufacturing a semiconductor device, comprising the steps of: (1) applying a temporary adhesive to a support substrate, and forming a resist composition material as a photocurable resin layer on the temporary adhesive; a step of forming a first insulating layer having a thickness of 1 to 20 μm; (2) after patterning the first insulating layer by a lithography technique with a mask to form a via pattern as a through electrode; a step of baking to thereby cure the first insulating layer; (3) forming a seed layer by sputtering in the first insulating layer, and thereafter forming the through-hole pattern of the through electrode a step of forming a metal wiring connected to the through electrode by plating, and (4) bonding the semiconductor element wafer having a height of 20 to 100 μm exposed to the upper surface of the electrode pad using a wafer adhesive to the hardened portion. (5) preparing a photocurable resin layer having a film thickness of 5 to 100 μm as a structure in which a supported film and a protective film are sandwiched, and the photocurable resin layer is composed of a resist composition material Photohardenable (6) a step of forming a second insulating layer by laminating the photocurable resin layer of the photocurable dry film so as to cover the semiconductor element bonded to the first insulating layer by the wafer (7) for the aforementioned second insulating layer, by lithography through the mask Patterning, while simultaneously forming an opening in the electrode pad, an opening for forming a metal wiring penetrating the second insulating layer on the metal wiring connected to the through electrode, and an opening for forming the through electrode, and then a step of baking to thereby cure the second insulating layer; (8) after hardening, forming a seed layer by sputtering, and thereafter, opening the opening on the electrode pad to form a through The opening of the metal wiring of the second insulating layer and the opening for forming the through electrode are filled by plating to form a metal pad on the semiconductor element, a metal wiring penetrating the second insulating layer, and a through electrode And the step of connecting the metal pad on the semiconductor element formed by the plating and the metal wiring penetrating the second insulating layer by metal wiring obtained by plating; (9) after the metal wiring is formed, The photocurable resin layer of the photocurable dry film is laminated or the resist composition material used for the photocurable dry film is spin-coated. a step of forming a third insulating layer; (10) forming a pattern in the upper portion of the through electrode by patterning the third insulating layer by a lithography technique through a mask, and then baking The step of hardening the third insulating layer; and (11) after hardening, forming a solder bump on the opening of the upper portion of the through electrode. 如請求項7之半導體裝置之製造方法，其中，將在前述步驟(5)所準備的光硬化性乾膜設為具有由化學增幅型負型阻劑組成物材料所構成的光硬化性樹脂層之光硬化性乾膜，該化學增幅型負型阻劑組成物材料係含有： (A)具有以下述一般式(1)所示之重複單元的重量平均分子量為3,000~500,000之含矽酮骨架之高分子化合物、 (式中，R1~R4係表示可相同或相異之碳數1~8的1價烴基；m為1~100之整數；a、b、c、d為0或正數，且a、b、c、d不同時為0；但，a+b+c+d=1；再者，X係以下述一般式(2)所示之有機基，Y係以下述一般式(3)所示之有機基) (式中，Z係由 中任一者所選出的2價之有機基，n為0或1；R5及R6係 各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；k為0、1、2中之任一者) (式中，V係由 中任一者所選出的2價之有機基，p為0或1；R7及R8係各自為碳數1~4之烷基或烷氧基，且可彼此相異或相同；h為0、1、2中之任一者)(B)由藉由甲醛或甲醛-醇改質而成的胺基縮合物、1分子中平均具有2個以上之羥甲基或烷氧基羥甲基的酚化合物所選出之1種或2種以上之交聯劑、(C)藉由波長190~500nm之光進行分解，而產生酸之光酸產生劑、以及(D)溶劑。 The method of manufacturing a semiconductor device according to claim 7, wherein the photocurable dry film prepared in the above step (5) is a photocurable resin layer having a chemically amplified negative resist composition material. The photo-curable dry film comprising: (A) an anthranone skeleton having a weight average molecular weight of 3,000 to 500,000 having a repeating unit represented by the following general formula (1); Polymer compound, (wherein R 1 to R 4 represent a monovalent hydrocarbon group having the same or different carbon number of 1 to 8; m is an integer of 1 to 100; a, b, c, and d are 0 or a positive number, and a, b, c, and d are not 0 at the same time; however, a+b+c+d=1; further, X is an organic group represented by the following general formula (2), and Y is represented by the following general formula (3). Organic basis (where, Z is composed of The divalent organic group selected by any one of them, n is 0 or 1; each of R 5 and R 6 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; k is Any of 0, 1, 2) (where, V is composed of The divalent organic group selected by any one of them, p is 0 or 1; each of R 7 and R 8 is an alkyl group or alkoxy group having 1 to 4 carbon atoms, and may be different from each other or the same; h is Any one of 0, 1, 2) (B) an amine condensate modified by formaldehyde or formaldehyde-alcohol, having an average of 2 or more methylol groups or alkoxyl groups in one molecule One or two or more kinds of crosslinking agents selected from the group consisting of phenolic compounds, and (C) are decomposed by light having a wavelength of from 190 to 500 nm to produce an acid photoacid generator and (D) a solvent. 如請求項7或8之半導體裝置之製造方法，其中，於前述步驟(6)中，包含對前述第二絕緣層進行機械性加壓之步驟。 The method of manufacturing a semiconductor device according to claim 7 or 8, wherein in the step (6), the step of mechanically pressurizing the second insulating layer is included. 如請求項7或8之半導體裝置之製造方法，其中，於前述步驟(11)中，具有：於前述貫穿電極上部之開口藉由鍍敷形成貫穿電極上金屬墊之步驟、以及於前述貫穿電極上金屬墊上形成焊錫球，製成焊錫凸塊之步驟。 The method of manufacturing a semiconductor device according to claim 7 or 8, wherein in the step (11), the step of forming a metal pad on the through electrode by plating at an opening in the upper portion of the through electrode, and the through electrode A step of forming a solder ball on the metal pad to form a solder bump. 如請求項7或8之半導體裝置之製造方法，其中，於前述步驟(8)之以鍍敷所致之前述貫穿電極的形成中，包含進行以SnAg所致之鍍敷之步驟，並且具有：於前述步驟(10)中，以於前述貫穿電極上部形成開口的方式進行圖型化，藉此使前述鍍敷後的SnAg露出之步驟、以及於前述步驟(11)中，藉由將前述鍍敷後的SnAg進行熔融而於前述貫穿電極上部之開口處使電極隆起而形成焊錫凸塊之步驟。 The method of manufacturing a semiconductor device according to claim 7 or 8, wherein in the forming of the through electrode by plating in the step (8), the step of performing plating by SnAg is included, and has: In the step (10), the pattern is formed so as to form an opening in the upper portion of the through electrode, thereby exposing the SnAg after the plating, and in the step (11), by plating the plating The applied SnAg is melted to form a solder bump by bulging the electrode at the opening of the upper portion of the through electrode. 如請求項7或8之半導體裝置之製造方法，其中在前述步驟(11)之後，具有：將在前述步驟(1)與第一絕緣層暫時接著的支撐基板去除之步驟、以及在將前述基板去除後，進行切割，藉此予以個片化之步驟。 The method of manufacturing a semiconductor device according to claim 7 or 8, wherein after the step (11), the step of removing the support substrate temporarily followed by the step (1) and the first insulating layer, and the substrate After removal, the cutting is carried out, thereby being subjected to a step of singulation. 一種層合型半導體裝置之製造方法，其特徵為，將以如請求項12之製造方法來藉由切割而個片化的複數個半導體裝置，包夾絕緣樹脂層，並藉由前述焊錫凸塊電接合而進行層合。 A method of manufacturing a laminated semiconductor device, comprising: sandwiching an insulating resin layer by a plurality of semiconductor devices which are formed by dicing according to the manufacturing method of claim 12, and using the solder bump Lamination is performed by electrical bonding. 一種封裝後層合型半導體裝置之製造方法，其特 徵為，具有：將以如請求項13之製造方法所製造的層合型半導體裝置載置於具有電路的基板之步驟、以及將載置於前述基板之層合型半導體裝置以絕緣封裝樹脂層進行封裝之步驟。 Method for manufacturing packaged laminated semiconductor device And a method of placing a laminated semiconductor device manufactured by the manufacturing method of claim 13 on a substrate having a circuit, and a laminated semiconductor device placed on the substrate to insulatively encapsulate a resin layer The step of encapsulation.
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US10141272B2 (en) 2018-11-27
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TWI648438B (en) 2019-01-21

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