TW201545150A - Sensing apparatus of display panel - Google Patents
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Description
本發明是有關於一種電子裝置,且特別是有關於一種顯示面板的感測裝置。 The present invention relates to an electronic device, and more particularly to a sensing device for a display panel.
圖1是說明習知主動式有機發光二極體(Active matrix organic light emitting diode,AMOLED)顯示器的電路方塊圖。此AMOLED顯示器包括閘極驅動器(gate driver)110、源極驅動器(source driver)120與顯示面板130。顯示面板130具有多條掃描線(閘極線,例如掃描線S_1與掃描線S_2)、多條資料線(源極線,例如資料線D_1與資料線D_2)以及多個像素電路(例如像素電路131)。像素電路131具有開關132、電流源電晶體133與有機發光二極體(organic LED,OLED)134。 1 is a circuit block diagram illustrating a conventional active matrix organic light emitting diode (AMOLED) display. The AMOLED display includes a gate driver 110, a source driver 120, and a display panel 130. The display panel 130 has a plurality of scan lines (gate lines, such as scan lines S_1 and scan lines S_2), a plurality of data lines (source lines, such as data lines D_1 and data lines D_2), and a plurality of pixel circuits (eg, pixel circuits) 131). The pixel circuit 131 has a switch 132, a current source transistor 133, and an organic LED (OLED) 134.
閘極驅動器110可以依序掃描顯示面板130的不同掃描線,以便讓源極驅動器120可以將資料電壓寫入像素電路。以圖1所示像素電路131為例,在閘極驅動器110透過掃描線S_1將開關132打開(turn on)的期間,源極驅動器120可以透過資料線D_1與開關132將資料電壓傳送至電流源電晶體133的閘極。電 流源電晶體133的閘極電壓可以決定電流源電晶體133的電流I1。流經有機發光二極體134的電流I1可以決定有機發光二極體134的亮度。電流源電晶體133的閘源極電壓VGS與電流I1的關係式為I1=k(VGS-Vt)2,其中係數k為實數,而Vt表示電流源電晶體133的閾電壓(threshold voltage)。由於製程漂移或是其他因素,使得不同像素電路中的電流源電晶體的閾電壓可能會互有差異。閾電壓的差異/漂移可能導致影像之Mura(光源不均)或其他瑕疵。若能測知電流源電晶體133的閾電壓,則源極驅動器120可以對應調整寫入像素電路131的資料電壓來補償閾電壓的漂移。 The gate driver 110 can sequentially scan different scan lines of the display panel 130 to allow the source driver 120 to write data voltages to the pixel circuits. Taking the pixel circuit 131 shown in FIG. 1 as an example, during the period in which the gate driver 110 turns the switch 132 through the scan line S_1, the source driver 120 can transmit the data voltage to the current source through the data line D_1 and the switch 132. The gate of the transistor 133. The gate voltage of the current source transistor 133 can determine the current I1 of the current source transistor 133. The current I1 flowing through the organic light-emitting diode 134 can determine the brightness of the organic light-emitting diode 134. The relationship between the gate-source voltage V GS of the current source transistor 133 and the current I1 is I1=k(V GS -Vt) 2 , where the coefficient k is a real number and Vt represents the threshold voltage of the current source transistor 133 (threshold voltage) ). The threshold voltages of the current source transistors in different pixel circuits may differ from each other due to process drift or other factors. Differences/drifts in threshold voltage may result in Mura (uneven source) or other artifacts of the image. If the threshold voltage of the current source transistor 133 can be detected, the source driver 120 can adjust the data voltage written in the pixel circuit 131 to compensate for the drift of the threshold voltage.
本發明提供一種顯示面板的感測裝置,可以感測顯示面板的像素電路中的電流源電晶體的閾電壓(threshold voltage)。 The present invention provides a sensing device for a display panel that can sense a threshold voltage of a current source transistor in a pixel circuit of the display panel.
本發明的實施例揭示一種顯示面板的感測裝置。感測裝置包括感測器以及取樣放大器。感測器的輸入端經由顯示面板的資料線耦接至像素電路,以於感測期間感測像素電路中的電流源電晶體的閾電壓。取樣放大器的第一輸入端與第二輸入端分別耦接至感測器的第一輸出端與第二輸出端。感測器包括第一開關、第二開關、第三開關、第一電容、第一增益放大器以及第二增益放大器。第一開關的第一端經由資料線耦接至像素電路。第二開關的第一端耦接至共模電壓(common mode voltage)。第三開關的第一端與第二端分別耦接至第一開關的第二端與第二開關的第二 端。第一電容的第一端與第二端分別耦接至第一參考電壓與第一開關的第二端。第一增益放大器的輸入端耦接至第一開關的該第二端,而第一增益放大器的輸出端作為感測器的第一輸出端而耦接至取樣放大器的第一輸入端。第二增益放大器的輸入端耦接至第二開關的第二端,而第二增益放大器的輸出端作為感測器的第二輸出端而耦接至取樣放大器的第二輸入端。 Embodiments of the present invention disclose a sensing device for a display panel. The sensing device includes a sensor and a sampling amplifier. The input end of the sensor is coupled to the pixel circuit via a data line of the display panel to sense a threshold voltage of the current source transistor in the pixel circuit during sensing. The first input end and the second input end of the sampling amplifier are respectively coupled to the first output end and the second output end of the sensor. The sensor includes a first switch, a second switch, a third switch, a first capacitor, a first gain amplifier, and a second gain amplifier. The first end of the first switch is coupled to the pixel circuit via a data line. The first end of the second switch is coupled to a common mode voltage. The first end and the second end of the third switch are respectively coupled to the second end of the first switch and the second end of the second switch end. The first end and the second end of the first capacitor are respectively coupled to the first reference voltage and the second end of the first switch. The input end of the first gain amplifier is coupled to the second end of the first switch, and the output end of the first gain amplifier is coupled to the first input end of the sampling amplifier as a first output end of the sensor. The input end of the second gain amplifier is coupled to the second end of the second switch, and the output end of the second gain amplifier is coupled to the second input of the sampling amplifier as a second output of the sensor.
本發明的另一實施例揭示一種顯示面板的感測裝置。感 測裝置包括感測器以及取樣放大器。感測器的輸入端經由顯示面板的資料線耦接至像素電路,以於感測期間感測該像素電路中電流源電晶體的閾電壓。取樣放大器的第一輸入端與第二輸入端分別耦接至該感測器的第一輸出端與第二輸出端。取樣放大器包括差動放大器、第一電容、第二電容、第三電容、第四電容、第一開關、第二開關、第三開關、第四開關、第五開關以及第六開關。 差動放大器的第一輸出端與第二輸出端分別耦接至取樣放大器的第一輸出端與第二輸出端。第一電容的第一端與第二端分別耦接至感測器的第一輸出端與差動放大器的第一輸入端。第二電容的第一端與第二端分別耦接至感測器的第二輸出端與差動放大器的第二輸入端。第三電容的第一端耦接至差動放大器的第一輸入端。第四電容的第一端耦接至差動放大器的第二輸入端。第一開關的第一端與第二端分別耦接至差動放大器的第一輸入端與差動放大器的第一輸出端。第二開關的第一端與第二端分別耦接至第三電容的第二端與共模電壓。第三開關的第一端與第二端分別耦 接至第三電容的第二端與差動放大器的第一輸出端。第四開關的第一端與第二端分別耦接至差動放大器的第二輸入端與差動放大器的第二輸出端。第五開關的第一端與第二端分別耦接至第四電容的第二端與共模電壓。第六開關的第一端與第二端分別耦接至第四電容的第二端與差動放大器的第二輸出端。 Another embodiment of the present invention discloses a sensing device for a display panel. sense The measuring device includes a sensor and a sampling amplifier. The input end of the sensor is coupled to the pixel circuit via a data line of the display panel to sense a threshold voltage of the current source transistor in the pixel circuit during sensing. The first input end and the second input end of the sampling amplifier are respectively coupled to the first output end and the second output end of the sensor. The sampling amplifier includes a differential amplifier, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch. The first output end and the second output end of the differential amplifier are respectively coupled to the first output end and the second output end of the sampling amplifier. The first end and the second end of the first capacitor are respectively coupled to the first output end of the sensor and the first input end of the differential amplifier. The first end and the second end of the second capacitor are respectively coupled to the second output end of the sensor and the second input end of the differential amplifier. The first end of the third capacitor is coupled to the first input of the differential amplifier. The first end of the fourth capacitor is coupled to the second input of the differential amplifier. The first end and the second end of the first switch are respectively coupled to the first input end of the differential amplifier and the first output end of the differential amplifier. The first end and the second end of the second switch are respectively coupled to the second end of the third capacitor and the common mode voltage. The first end and the second end of the third switch are respectively coupled Connected to the second end of the third capacitor and the first output of the differential amplifier. The first end and the second end of the fourth switch are respectively coupled to the second input end of the differential amplifier and the second output end of the differential amplifier. The first end and the second end of the fifth switch are respectively coupled to the second end of the fourth capacitor and the common mode voltage. The first end and the second end of the sixth switch are respectively coupled to the second end of the fourth capacitor and the second output end of the differential amplifier.
基於上述,本發明實施例提供一種顯示面板的感測裝置,可以減少感測器及/或取樣放大器中放大電路的偏移(offset)。因此,感測裝置可以精確地感測顯示面板的像素電路中的電流源電晶體的閾電壓。 Based on the above, an embodiment of the present invention provides a sensing device for a display panel, which can reduce an offset of an amplifying circuit in a sensor and/or a sampling amplifier. Therefore, the sensing device can accurately sense the threshold voltage of the current source transistor in the pixel circuit of the display panel.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
110、210‧‧‧閘極驅動器 110, 210‧‧ ‧ gate driver
120、220‧‧‧源極驅動器 120, 220‧‧‧ source drive
130、230‧‧‧顯示面板 130, 230‧‧‧ display panel
131、231‧‧‧像素電路 131, 231‧‧‧ pixel circuits
132、232、236、237‧‧‧開關 132, 232, 236, 237‧ ‧ switch
133‧‧‧電流源電晶體 133‧‧‧current source transistor
134‧‧‧有機發光二極體 134‧‧‧Organic Luminescent Diodes
200‧‧‧顯示裝置 200‧‧‧ display device
233‧‧‧電流源電晶體 233‧‧‧current source transistor
234‧‧‧發光二極體 234‧‧‧Lighting diode
235‧‧‧儲存電容 235‧‧‧ storage capacitor
300‧‧‧感測裝置 300‧‧‧Sensing device
310_1、310_2、310_n‧‧‧感測器 310_1, 310_2, 310_n‧‧‧ sensors
320‧‧‧取樣放大器 320‧‧‧Sampling amplifier
330‧‧‧類比數位轉換器 330‧‧‧ Analog Digital Converter
410‧‧‧第一增益放大器 410‧‧‧First Gain Amplifier
420‧‧‧第二增益放大器 420‧‧‧second gain amplifier
510‧‧‧電流鏡 510‧‧‧current mirror
511、512‧‧‧PMOS電晶體 511, 512‧‧‧ PMOS transistor
520‧‧‧電晶體 520‧‧‧Optoelectronics
530‧‧‧電流源 530‧‧‧current source
710‧‧‧差動放大器 710‧‧‧Differential Amplifier
B[K:1]‧‧‧數位偵測結果 B[K:1]‧‧‧ digital detection results
C1‧‧‧第一電容 C1‧‧‧first capacitor
C2‧‧‧第二電容 C2‧‧‧second capacitor
C3‧‧‧第三電容 C3‧‧‧ third capacitor
C4‧‧‧第四電容 C4‧‧‧fourth capacitor
C5‧‧‧第五電容 C5‧‧‧ fifth capacitor
C6‧‧‧第六電容 C6‧‧‧ sixth capacitor
C7‧‧‧第七電容 C7‧‧‧ seventh capacitor
C8‧‧‧第八電容 C8‧‧‧ eighth capacitor
D_1、D_2、D_n‧‧‧資料線 D_1, D_2, D_n‧‧‧ data lines
gm1、gm2、M*gm2‧‧‧轉導 g m1 , g m2 , M*g m2 ‧‧‧ transduction
GND‧‧‧接地電壓 GND‧‧‧ Grounding voltage
I1、I2‧‧‧電流 I1, I2‧‧‧ current
IIN‧‧‧電流源530的電流 I IN ‧‧‧current of current source 530
M_1、M_2、M_m‧‧‧模式線 M_1, M_2, M_m‧‧‧ mode lines
RIN‧‧‧第一增益放大器410的內電阻 R IN ‧‧‧ Internal resistance of the first gain amplifier 410
S_1、S_2、S_m‧‧‧掃描線 S_1, S_2, S_m‧‧‧ scan lines
SW1‧‧‧第一開關 SW1‧‧‧ first switch
SW2‧‧‧第二開關 SW2‧‧‧second switch
SW3‧‧‧第三開關 SW3‧‧‧ third switch
SW4‧‧‧第四開關 SW4‧‧‧fourth switch
SW5‧‧‧第五開關 SW5‧‧‧ fifth switch
SW6‧‧‧第六開關 SW6‧‧‧ sixth switch
SW7‧‧‧第七開關 SW7‧‧‧ seventh switch
SW8‧‧‧第八開關 SW8‧‧‧ eighth switch
SW9‧‧‧第九開關 SW9‧‧‧ninth switch
SW10‧‧‧第十開關 SW10‧‧‧ tenth switch
SW11‧‧‧第十一開關 SW11‧‧‧ eleventh switch
VCM‧‧‧共模電壓 VCM‧‧‧ Common mode voltage
VDD‧‧‧系統電壓 VDD‧‧‧ system voltage
VI‧‧‧第一增益放大器410的輸入端 VI‧‧‧ input of the first gain amplifier 410
VIN_GA‧‧‧取樣放大器320的第二輸入端 VIN_GA‧‧‧ second input of sampling amplifier 320
VIP_GA‧‧‧取樣放大器320的第一輸入端 The first input of the VIP_GA‧‧ sampling amplifier 320
VO‧‧‧第一增益放大器410的輸出端 VO‧‧‧output of the first gain amplifier 410
VON‧‧‧感測器310_n的第二輸出端 The second output of the VON‧‧ sensor 310_n
VON_GA‧‧‧取樣放大器320的第二輸出端 VON_GA‧‧‧ second output of sampling amplifier 320
VOP‧‧‧感測器310_n的第一輸出端 The first output of the VOP‧‧ sensor 310_n
VOP_GA‧‧‧取樣放大器320的第一輸出端 VOP_GA‧‧‧ first output of sampling amplifier 320
圖1是說明習知主動式有機發光二極體顯示器的電路方塊圖。 1 is a circuit block diagram illustrating a conventional active organic light emitting diode display.
圖2是依照本發明實施例說明一種顯示裝置的電路示意圖。 2 is a circuit diagram showing a display device in accordance with an embodiment of the invention.
圖3是依照本發明實施例說明一種感測裝置的電路示意圖。 3 is a circuit diagram illustrating a sensing device in accordance with an embodiment of the invention.
圖4是依照本發明一實施例說明圖3所示感測器的電路示意圖。 4 is a circuit diagram showing the sensor of FIG. 3 according to an embodiment of the invention.
圖5是依照本發明一實施例說明圖4所示增益放大器的電路示意圖。 FIG. 5 is a circuit diagram showing the gain amplifier of FIG. 4 according to an embodiment of the invention.
圖6是依照本發明另一實施例說明圖3所示感測器的電路示意圖。 FIG. 6 is a circuit diagram showing the sensor of FIG. 3 according to another embodiment of the present invention.
圖7是依照本發明一實施例說明圖3所示取樣放大器的電路示意圖。 FIG. 7 is a circuit diagram showing the sampling amplifier of FIG. 3 according to an embodiment of the invention.
在本案說明書全文(包括申請專利範圍)中所使用的「耦 接」一詞可指任何直接或間接的連接手段。舉例而言,若文中描述第一裝置耦接於第二裝置,則應該被解釋成該第一裝置可以直接連接於該第二裝置,或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。另外,凡可能之處,在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似部分。不同實施例中使用相同標號或使用相同用語的元件/構件/步驟可以相互參照相關說明。 "Coupling" used in the full text of this prospectus (including the scope of patent application) The term "接接" can refer to any direct or indirect means of attachment. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. In addition, wherever possible, the elements and/ Elements/components/steps that use the same reference numbers or use the same terms in different embodiments may refer to the related description.
圖2是依照本發明實施例說明一種顯示裝置200的電路示意圖。此顯示裝置200包括閘極驅動器(gate driver)210、源極驅動器(source driver)220與顯示面板230。顯示面板130具有多條掃描線(或稱閘極線,例如掃描線S_1、S_2、…、S_m)、多條資料線(或稱源極線,例如資料線D_1、D_2、…、D_n)以及多個像素電路(例如像素電路231)。像素電路231具有開關232、電流源電晶體233、發光二極體234、儲存電容235、開關236與開關237。發光二極體234可以是有機發光二極體(organic LED,OLED)或是其他類型的發光二極體。顯示面板130中的其他像素電路可以參照像素電路231的相關說明而類推之。 2 is a circuit diagram illustrating a display device 200 in accordance with an embodiment of the invention. The display device 200 includes a gate driver 210, a source driver 220, and a display panel 230. The display panel 130 has a plurality of scan lines (or gate lines, such as scan lines S_1, S_2, ..., S_m), a plurality of data lines (or source lines, such as data lines D_1, D_2, ..., D_n), and A plurality of pixel circuits (eg, pixel circuit 231). The pixel circuit 231 has a switch 232, a current source transistor 233, a light emitting diode 234, a storage capacitor 235, a switch 236, and a switch 237. The light emitting diode 234 can be an organic light emitting diode (organic) LED, OLED) or other types of light-emitting diodes. Other pixel circuits in the display panel 130 can be analogized with reference to the related description of the pixel circuit 231.
在正常操作期間,閘極驅動器210可以將模式線M_1、M_2、…、M_m的信號設定為第一邏輯準位(例如低邏輯準位)。 當模式線M_1~M_m的信號為低邏輯準位時,顯示面板230中每一個像素電路的開關236會關閉(turn off),而開關237會導通(turn on)。在正常操作期間,閘極驅動器210還可以依序掃描顯示面板230的不同掃描線S_1~S_m,以便讓源極驅動器220可以將資料電壓透過資料線D_1~D_n寫入像素電路。以圖2所示像素電路231為例,在閘極驅動器210透過掃描線S_m將開關232打開(turn on)的期間,源極驅動器220可以透過資料線D_n與開關232將資料電壓傳送至電流源電晶體233的閘極。此資料電壓可以被儲存於儲存電容235。電流源電晶體233的閘極電壓可以決定電流源電晶體233的電流I2。流經有機發光二極體234的電流I2可以決定有機發光二極體234的亮度。電流源電晶體233的閘源極電壓VGS與電流I2的關係式為I2=k(VGS-Vt)2,其中係數k為實數,而Vt表示電流源電晶體233的閾電壓(threshold voltage)。 During normal operation, the gate driver 210 can set the signals of the mode lines M_1, M_2, . . . , M_m to a first logic level (eg, a low logic level). When the signals of the mode lines M_1~M_m are at a low logic level, the switch 236 of each pixel circuit in the display panel 230 is turned off, and the switch 237 is turned on. During normal operation, the gate driver 210 can also scan the different scan lines S_1~S_m of the display panel 230 in order to allow the source driver 220 to write the data voltage through the data lines D_1~D_n into the pixel circuit. Taking the pixel circuit 231 shown in FIG. 2 as an example, during the period in which the gate driver 210 turns the switch 232 through the scan line S_m, the source driver 220 can transmit the data voltage to the current source through the data line D_n and the switch 232. The gate of the transistor 233. This data voltage can be stored in the storage capacitor 235. The gate voltage of the current source transistor 233 can determine the current I2 of the current source transistor 233. The current I2 flowing through the organic light-emitting diode 234 can determine the brightness of the organic light-emitting diode 234. The relationship between the gate-source voltage V GS of the current source transistor 233 and the current I2 is I2=k(V GS -Vt) 2 , where the coefficient k is a real number and Vt represents the threshold voltage of the current source transistor 233 (threshold voltage) ).
在感測期間,閘極驅動器210可以將模式線M_1~M_m的信號設定為第二邏輯準位(例如高邏輯準位)。當模式線M_1~M_m的信號為高邏輯準位時,顯示面板230中每一個像素電路的開關236會導通(turn on),而開關237會關閉(turn off)。在感測期間,由於開關236的導通致使電流源電晶體233的閘源極電 壓VGS可以被拉低至接近0V。在感測期間,閘極驅動器210還可以依序掃描顯示面板230的不同掃描線S_1~S_m,以便讓源極驅動器220內部的感測裝置300(容後說明)可以透過資料線D_1~D_n感測不同像素電路中電流源電晶體的閾電壓。以圖2所示像素電路231為例,在閘極驅動器210透過掃描線S_m將開關232打開(turn on)的期間,源極驅動器220內部的感測裝置300(容後說明)可以透過資料線D_n與開關232感測像素電路231中電流源電晶體233的閾電壓。在測知電流源電晶體233的閾電壓後,源極驅動器220可以對應調整欲寫入像素電路231的資料電壓來補償閾電壓的漂移。 During sensing, the gate driver 210 can set the signals of the mode lines M_1~M_m to a second logic level (eg, a high logic level). When the signals of the mode lines M_1~M_m are at a high logic level, the switch 236 of each pixel circuit in the display panel 230 will turn on, and the switch 237 will turn off. During sensing, the gate-source voltage V GS of the current source transistor 233 can be pulled down to near 0V due to the conduction of the switch 236. During the sensing, the gate driver 210 can also scan the different scan lines S_1 S S_m of the display panel 230 in order to allow the sensing device 300 (described later) of the source driver 220 to pass through the data lines D_1~D_n. The threshold voltage of the current source transistor in different pixel circuits is measured. Taking the pixel circuit 231 shown in FIG. 2 as an example, during the period in which the gate driver 210 turns the switch 232 through the scan line S_m, the sensing device 300 inside the source driver 220 can be transmitted through the data line. D_n and switch 232 sense the threshold voltage of current source transistor 233 in pixel circuit 231. After the threshold voltage of the current source transistor 233 is sensed, the source driver 220 can adjust the data voltage to be written to the pixel circuit 231 to compensate for the drift of the threshold voltage.
圖3是依照本發明實施例說明一種感測裝置300的電路示意圖。請參照圖2與圖3,顯示面板230的感測裝置300可以被嵌入源極驅動器220中。感測裝置300包括感測器(例如圖3所示感測器310_1、310_2、…、310_n)、取樣放大器320以及類比數位轉換器330。感測器310_1~310_n的輸入端以一對一方式耦接至顯示面板230的資料線D_1~D_n。舉例來說,感測器310_n的輸入端經由顯示面板230的資料線D_n耦接至顯示面板230的像素電路231,以於感測期間感測像素電路231中的電流源電晶體233的閾電壓,然後將感測結果輸出至取樣放大器320的輸入端。 取樣放大器320的第一輸入端VIP_GA與第二輸入端VIN_GA分別耦接至感測器310_1~310_n的第一輸出端與第二輸出端,例如耦接至感測器310_n的第一輸出端VOP與第二輸出端VON。取樣 放大器320可以對感測器310_1~310_n的輸出進行取樣與放大,而對應輸出類比偵測結果至類比數位轉換器330的輸入端。類比數位轉換器330可以將所述類比偵測結果轉換為數位偵測結果B[K:1]。因此,源極驅動器220可以依據數位偵測結果B[K:1](或依據類比偵測結果)對應調整欲寫入像素電路的資料電壓來補償閾電壓的漂移。 FIG. 3 is a circuit diagram illustrating a sensing device 300 in accordance with an embodiment of the invention. Referring to FIGS. 2 and 3 , the sensing device 300 of the display panel 230 can be embedded in the source driver 220 . The sensing device 300 includes a sensor (such as the sensors 310_1, 310_2, ..., 310_n shown in FIG. 3), a sampling amplifier 320, and an analog-to-digital converter 330. The input ends of the sensors 310_1~310_n are coupled to the data lines D_1~D_n of the display panel 230 in a one-to-one manner. For example, the input end of the sensor 310_n is coupled to the pixel circuit 231 of the display panel 230 via the data line D_n of the display panel 230 to sense the threshold voltage of the current source transistor 233 in the pixel circuit 231 during sensing. And then output the sensed result to the input of the sampling amplifier 320. The first input terminal VIP_GA and the second input terminal VIN_GA of the sampling amplifier 320 are respectively coupled to the first output end and the second output end of the sensors 310_1~310_n, for example, coupled to the first output end VOP of the sensor 310_n. And the second output terminal VON. sampling The amplifier 320 can sample and amplify the outputs of the sensors 310_1~310_n, and correspondingly output the analog detection results to the input of the analog-to-digital converter 330. The analog digital converter 330 can convert the analog detection result into a digital detection result B[K:1]. Therefore, the source driver 220 can adjust the drift of the threshold voltage according to the digital detection result B[K:1] (or according to the analog detection result) correspondingly adjusting the data voltage to be written into the pixel circuit.
圖4是依照本發明一實施例說明圖3所示感測器310_n的電路示意圖。圖3所示其他感測器可以參照感測器310_n的相關說明而類推之。請參照圖2、圖3與圖4,感測器310_n包括第一開關SW1、第二開關SW2、第三開關SW3、第一電容C1、第二電容C2、第一增益放大器410以及第二增益放大器420。第一開關SW1的第一端經由資料線D_n耦接至顯示面板230的像素電路(例如像素電路231等)。第二開關SW2的第一端耦接至共模電壓(common mode voltage)VCM。第三開關SW3的第一端與第二端分別耦接至第一開關SW1的第二端與第二開關SW2的第二端。 FIG. 4 is a circuit diagram showing the sensor 310_n of FIG. 3 according to an embodiment of the invention. Other sensors shown in FIG. 3 can be analogized with reference to the relevant description of the sensor 310_n. Referring to FIG. 2, FIG. 3 and FIG. 4, the sensor 310_n includes a first switch SW1, a second switch SW2, a third switch SW3, a first capacitor C1, a second capacitor C2, a first gain amplifier 410, and a second gain. Amplifier 420. The first end of the first switch SW1 is coupled to the pixel circuit (eg, the pixel circuit 231 or the like) of the display panel 230 via the data line D_n. The first end of the second switch SW2 is coupled to a common mode voltage VCM. The first end and the second end of the third switch SW3 are respectively coupled to the second end of the first switch SW1 and the second end of the second switch SW2.
第一電容C1的第一端與第二端分別耦接至第一參考電壓VR1與第一開關SW1的第二端。第一參考電壓VR1可以是任何準位的固定電壓,例如系統電壓VDD、接地電壓GND或是其他固定電壓。第二電容C2的第一端與第二端分別耦接至第二參考電壓VR2與第二開關SW2的第二端。第二參考電壓VR2可以是任何準位的固定電壓,例如系統電壓VDD、接地電壓GND或是 其他固定電壓。第一參考電壓VR1可以相同或不同於第二參考電壓VR2。 The first end and the second end of the first capacitor C1 are respectively coupled to the first reference voltage VR1 and the second end of the first switch SW1. The first reference voltage VR1 may be a fixed voltage of any level, such as a system voltage VDD, a ground voltage GND, or other fixed voltage. The first end and the second end of the second capacitor C2 are respectively coupled to the second reference voltage VR2 and the second end of the second switch SW2. The second reference voltage VR2 can be a fixed voltage of any level, such as a system voltage VDD, a ground voltage GND, or Other fixed voltages. The first reference voltage VR1 may be the same or different from the second reference voltage VR2.
第一增益放大器410的輸入端耦接至第一開關SW1的第二端。第一增益放大器410的輸出端作為感測器310_n的第一輸出端VOP而耦接至取樣放大器320的第一輸入端VIP_GA。第二增益放大器420的輸入端耦接至第二開關SW2的第二端。第二增益放大器420的輸出端作為感測器310_n的第二輸出端VON而耦接至取樣放大器320的第二輸入端VIN_GA。第一增益放大器410與第二增益放大器420可以是任何類型的放大電路。例如,在本實施例中,第一增益放大器410與第二增益放大器420可以是單元增益(Unit Gain)放大器。 The input end of the first gain amplifier 410 is coupled to the second end of the first switch SW1. The output of the first gain amplifier 410 is coupled to the first input terminal VIP_GA of the sampling amplifier 320 as the first output terminal VOP of the sensor 310_n. The input end of the second gain amplifier 420 is coupled to the second end of the second switch SW2. The output of the second gain amplifier 420 is coupled to the second input terminal VIN_GA of the sampling amplifier 320 as the second output terminal VON of the sensor 310_n. The first gain amplifier 410 and the second gain amplifier 420 can be any type of amplification circuit. For example, in the present embodiment, the first gain amplifier 410 and the second gain amplifier 420 may be unit Gain amplifiers.
當顯示面板230操作於所述感測期間時,於感測期間的第一期間(第一相位)T1,第一開關SW1與第二開關SW2為導通,而第三開關SW3為截止。因此在第一期間T1中,第一增益放大器410的輸出VOP(T1)=D_n+Voffset1,而第二增益放大器420的輸出VON(T1)=VCM+Voffset2。其中,Voffset1表示第一增益放大器410的電壓偏移,Voffset2表示第二增益放大器420的電壓偏移。取樣放大器320可以在第一期間T1中計算VOP(T1)-VON(T1)=(D_n+Voffset1)-(VCM+Voffset2)。於感測期間的第二期間(第二相位)T2,第一開關SW1與第二開關SW2為截止,而第三開關SW3為導通。因此在第二期間T2中,第一增益放大器410的輸出VOP(T2)=Vreset+Voffset1,而第二增益放大器420的輸出 VON(T2)=Vreset+Voffset2。其中,Vreset表示第三開關SW3導通時第一增益放大器410與第二增益放大器420的輸入端電壓。取樣放大器320可以在第二期間T2中計算VOP(T2)-VON(T2)=Voffset1-Voffset2。取樣放大器320可以計算[VOP(T1)-VON(T1)]-[VOP(T2)-VON(T2)]=D_n-VCM。因此,第一增益放大器410與第二增益放大器420的電壓偏移可以被消除。 When the display panel 230 operates during the sensing period, during the first period (first phase) T1 of the sensing period, the first switch SW1 and the second switch SW2 are turned on, and the third switch SW3 is turned off. Therefore, in the first period T1, the output VOP (T1) of the first gain amplifier 410 = D_n + V offset1 , and the output VON (T1) of the second gain amplifier 420 = VCM + V offset2 . Wherein, V offset1 represents the voltage offset of the first gain amplifier 410, and V offset2 represents the voltage offset of the second gain amplifier 420. The sampling amplifier 320 can calculate VOP(T1) - VON(T1) = (D_n + V offset1 ) - (VCM + V offset2 ) in the first period T1. During the second period (second phase) T2 of the sensing period, the first switch SW1 and the second switch SW2 are turned off, and the third switch SW3 is turned on. Therefore, in the second period T2, the output VOP (T2) of the first gain amplifier 410 = V reset + V offset1 , and the output VON (T2) of the second gain amplifier 420 = V reset + V offset 2 . Wherein V reset represents the input terminal voltage of the first gain amplifier 410 and the second gain amplifier 420 when the third switch SW3 is turned on. The sampling amplifier 320 can calculate VOP(T2) - VON(T2) = V offset1 - V offset2 in the second period T2. The sampling amplifier 320 can calculate [VOP(T1)-VON(T1)]-[VOP(T2)-VON(T2)]=D_n-VCM. Therefore, the voltage offset of the first gain amplifier 410 and the second gain amplifier 420 can be eliminated.
第一增益放大器410與第二增益放大器420可以是任何類型的放大電路。例如,圖5是依照本發明一實施例說明圖4所示第一增益放大器410的電路示意圖。圖4所示其他增益放大器可以參照第一增益放大器410的相關說明而類推之。請參照圖5,第一增益放大器包括電流鏡510、電晶體520以及電流源530。於本實施例中,電流鏡510包括P型通道金氧半(P-channel metal oxide semiconductor,PMOS)電晶體511與PMOS電晶體512。 PMOS電晶體511的閘極耦接至PMOS電晶體511的汲極與PMOS電晶體512的閘極。PMOS電晶體511可以提供電流鏡510的主電流路徑,而PMOS電晶體512可以提供電流鏡510的僕電流路徑。於本實施例中,PMOS電晶體512的通道長寬比可以是PMOS電晶體511的通道長寬比的M倍。也就是說,若PMOS電晶體511的轉導為gm2,則PMOS電晶體512的轉導為M*gm2。 The first gain amplifier 410 and the second gain amplifier 420 can be any type of amplification circuit. For example, FIG. 5 is a circuit diagram illustrating the first gain amplifier 410 of FIG. 4 in accordance with an embodiment of the present invention. Other gain amplifiers shown in FIG. 4 can be analogized with reference to the related description of the first gain amplifier 410. Referring to FIG. 5, the first gain amplifier includes a current mirror 510, a transistor 520, and a current source 530. In the present embodiment, the current mirror 510 includes a P-channel metal oxide semiconductor (PMOS) transistor 511 and a PMOS transistor 512. The gate of the PMOS transistor 511 is coupled to the drain of the PMOS transistor 511 and the gate of the PMOS transistor 512. The PMOS transistor 511 can provide the main current path of the current mirror 510, while the PMOS transistor 512 can provide the servant current path of the current mirror 510. In this embodiment, the channel aspect ratio of the PMOS transistor 512 may be M times the channel aspect ratio of the PMOS transistor 511. That is, if the transduction of the PMOS transistor 511 is g m2 , the transduction of the PMOS transistor 512 is M*g m2 .
電流鏡510的主電流路徑的第一端與僕電流路徑的第一端耦接至系統電壓VDD,而電流鏡510的僕電流路徑的第二端耦接至第一增益放大器410的輸出端VO。電晶體520的控制端(例 如閘極)耦接至第一增益放大器410的輸入端VI。電晶體520的第一端(例如汲極)耦接至電流鏡510的主電流路徑的第二端。 電流源530的一端耦接至電晶體520的第二端(例如源極)與電流鏡510的僕電流路徑的第二端。電流源530的另一端耦接至接地電壓GND。假設電流源530的電流為IIN,則IIN=gm1VI+ ,其中gm1表示電晶體520的轉 導。第一增益放大器410的內電阻 。因此,第一增益放大器410的內電阻RIN可以被有效降 低。 The first end of the main current path of the current mirror 510 is coupled to the first end of the current path to the system voltage VDD, and the second end of the current path of the current mirror 510 is coupled to the output end of the first gain amplifier 410. . A control terminal (e.g., a gate) of the transistor 520 is coupled to the input terminal VI of the first gain amplifier 410. A first end (eg, a drain) of the transistor 520 is coupled to a second end of the main current path of the current mirror 510. One end of the current source 530 is coupled to the second end of the transistor 520 (eg, the source) and the second end of the current path of the current mirror 510. The other end of the current source 530 is coupled to the ground voltage GND. Assuming that the current of current source 530 is I IN , then I IN = g m1 VI+ Where g m1 represents the transduction of the transistor 520. Internal resistance of the first gain amplifier 410 . Therefore, the internal resistance R IN of the first gain amplifier 410 can be effectively reduced.
圖6是依照本發明另一實施例說明圖3所示感測器310_n的電路示意圖。圖3所示其他感測器可以參照感測器310_n的相關說明而類推之。請參照圖2、圖3與圖6,感測器310_n包括第一開關SW1、第二開關SW2、第三開關SW3、第四開關SW4、第五開關SW5、第一電容C1、第二電容C2、第三電容C3、第四電容C4、第一增益放大器410以及第二增益放大器420。圖6所示實施例可以參照圖4的相關說明而類推之。第一開關SW1的第一端經由資料線D_n耦接至顯示面板230的像素電路(例如像素電路231等)。第二開關SW2的第一端耦接至共模電壓VCM。第三開關SW3的第一端與第二端分別耦接至第一開關SW1的第二端與第二開關SW2的第二端。 FIG. 6 is a circuit diagram illustrating the sensor 310_n of FIG. 3 according to another embodiment of the present invention. Other sensors shown in FIG. 3 can be analogized with reference to the relevant description of the sensor 310_n. Referring to FIG. 2, FIG. 3 and FIG. 6, the sensor 310_n includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a first capacitor C1, and a second capacitor C2. a third capacitor C3, a fourth capacitor C4, a first gain amplifier 410, and a second gain amplifier 420. The embodiment shown in FIG. 6 can be analogized with reference to the related description of FIG. The first end of the first switch SW1 is coupled to the pixel circuit (eg, the pixel circuit 231 or the like) of the display panel 230 via the data line D_n. The first end of the second switch SW2 is coupled to the common mode voltage VCM. The first end and the second end of the third switch SW3 are respectively coupled to the second end of the first switch SW1 and the second end of the second switch SW2.
第一電容C1的第一端與第二端分別耦接至第一參考電壓VR1與第一開關SW1的第二端。第二電容C2的第一端與第二端分別耦接至第二參考電壓VR2與第二開關SW2的第二端。第三電容C3的第一端與第二端分別耦接於第一開關SW1的第二端與第一增益放大器410的輸入端。第四電容C4的第一端與第二端分別耦接於該第二開關SW2的第二端與第二增益放大器420的輸入端。第四開關SW4的第一端與第二端分別耦接至第一增益放大器410的輸入端與偏壓電壓VBIAS。第五開關SW5的第一端與第二端分別耦接至第二增益放大器420的輸入端與偏壓電壓VBIAS。第一增益放大器410的輸出端作為感測器310_n的第一輸出端VOP而耦接至取樣放大器320的第一輸入端VIP_GA。第二增益放大器420的輸出端作為感測器310_n的第二輸出端VON而耦接至取樣放大器320的第二輸入端VIN_GA。在本實施例中,第一增益放大器410與第二增益放大器420可以是單元增益放大器。第一增益放大器410與/或第二增益放大器420的實施方式可以參照圖5的相關說明而類推之。 The first end and the second end of the first capacitor C1 are respectively coupled to the first reference voltage VR1 and the second end of the first switch SW1. The first end and the second end of the second capacitor C2 are respectively coupled to the second reference voltage VR2 and the second end of the second switch SW2. The first end and the second end of the third capacitor C3 are respectively coupled to the second end of the first switch SW1 and the input end of the first gain amplifier 410. The first end and the second end of the fourth capacitor C4 are respectively coupled to the second end of the second switch SW2 and the input end of the second gain amplifier 420. The first end and the second end of the fourth switch SW4 are respectively coupled to the input end of the first gain amplifier 410 and the bias voltage V BIAS . The first end and the second end of the fifth switch SW5 are respectively coupled to the input end of the second gain amplifier 420 and the bias voltage V BIAS . The output of the first gain amplifier 410 is coupled to the first input terminal VIP_GA of the sampling amplifier 320 as the first output terminal VOP of the sensor 310_n. The output of the second gain amplifier 420 is coupled to the second input terminal VIN_GA of the sampling amplifier 320 as the second output terminal VON of the sensor 310_n. In the present embodiment, the first gain amplifier 410 and the second gain amplifier 420 may be unit gain amplifiers. Embodiments of the first gain amplifier 410 and/or the second gain amplifier 420 can be analogized with reference to the related description of FIG.
當顯示面板230操作於所述感測期間時,於感測期間的第一期間(第一相位)T1,第一開關SW1、第二開關SW2、第四開關SW4與第五開關SW5為導通,而第三開關SW3為截止。因此在第一期間T1中,第一增益放大器410的輸出VOP(T1)=VBIAS+Voffset1,而第二增益放大器420的輸出VON(T1)=VBIAS+Voffset2。其中,Voffset1表示第一增益放大器410的電壓偏移,Voffset2 表示第二增益放大器420的電壓偏移。取樣放大器320可以在第一期間T1中計算VOP(T1)-VON(T1)=(VBIAS+Voffset1)-(VBIAS+Voffset2)=Voffset1-Voffset2。於感測期間的第二期間(第二相位)T2,第一開關SW1、第二開關SW2、第四開關SW4與第五開關SW5為截止,而第三開關SW3為導通。因此在第二期間T2中,第一增益放大器410的輸出VOP(T2)=VBIAS+Voffset1- ,而第二增益放大器420的輸出VON(T2)=VBIAS+ 。取樣放大器320可以在第二期間T2中計算 VOP(T2)-VON(T2)=(Voffset1-Voffset2)-(D_n-VCM)。取樣放大器320可以計算[VOP(T1)-VON(T1)]-[VOP(T2)-VON(T2)]=D_n-VCM。因此,第一增益放大器410的電壓偏移Voffset1與第二增益放大器420的電壓偏移Voffset2可以被消除。 When the display panel 230 is operated during the sensing period, the first switch SW1, the second switch SW2, the fourth switch SW4, and the fifth switch SW5 are turned on during the first period (first phase) T1 of the sensing period. The third switch SW3 is turned off. Therefore, in the first period T1, the output VOP (T1) of the first gain amplifier 410 = V BIAS + V offset1 , and the output VON (T1) of the second gain amplifier 420 = V BIAS + V offset 2 . Wherein, V offset1 represents the voltage offset of the first gain amplifier 410, and V offset2 represents the voltage offset of the second gain amplifier 420. The sampling amplifier 320 may calculate VOP(T1) - VON(T1) = (V BIAS + V offset1 ) - (V BIAS + V offset2 ) = V offset1 - V offset2 in the first period T1. During the second period (second phase) T2 of the sensing period, the first switch SW1, the second switch SW2, the fourth switch SW4, and the fifth switch SW5 are turned off, and the third switch SW3 is turned on. Therefore, in the second period T2, the output VOP of the first gain amplifier 410 (T2) = V BIAS + V offset1 - And the output of the second gain amplifier 420 is VON(T2)=V BIAS + . The sampling amplifier 320 can calculate VOP(T2) - VON(T2) = (V offset1 - V offset2 ) - (D_n - VCM) in the second period T2. The sampling amplifier 320 can calculate [VOP(T1)-VON(T1)]-[VOP(T2)-VON(T2)]=D_n-VCM. Thus, the voltage gain of the first amplifier 410 and the offset voltage V offset1 second gain offset V offset2 amplifier 420 can be eliminated.
圖7是依照本發明一實施例說明圖3所示取樣放大器320的電路示意圖。請參照圖2、圖3與圖7,取樣放大器320包括、差動放大器710、第五電容C5、第六電容C6、第七電容C7、第八電容C8、第六開關SW6、第七開關SW7、第八開關SW8、第九開關SW9、第十開關SW10以及第十一開關SW11。差動放大器710的第一輸出端(例如非反相輸出端)與第二輸出端(例如反相輸出端)分別耦接至取樣放大器320的第一輸出端VOP_GA與第二輸出端VON_GA。第五電容C5的第一端作為取樣放大器320的第一輸入端VIP_GA,以耦接至感測器310_1~310_n的第一輸出端。第五電容C5的第二端耦接至差動放大器710的第一輸入端 (例如反相輸入端)。第六電容C6的第一端作為取樣放大器320的第二輸入端VIN_GA,以耦接至感測器310_1~310_n的第二輸出端。第六電容C6的第二端耦接至差動放大器710的第二輸入端(例如非反相輸入端)。 FIG. 7 is a circuit diagram showing the sampling amplifier 320 of FIG. 3 in accordance with an embodiment of the invention. Referring to FIG. 2, FIG. 3 and FIG. 7, the sampling amplifier 320 includes a differential amplifier 710, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a sixth switch SW6, and a seventh switch SW7. The eighth switch SW8, the ninth switch SW9, the tenth switch SW10, and the eleventh switch SW11. The first output terminal (eg, the non-inverting output terminal) and the second output terminal (eg, the inverting output terminal) of the differential amplifier 710 are coupled to the first output terminal VOP_GA and the second output terminal VON_GA of the sampling amplifier 320, respectively. The first end of the fifth capacitor C5 serves as the first input terminal VIP_GA of the sampling amplifier 320 to be coupled to the first output end of the sensors 310_1~310_n. The second end of the fifth capacitor C5 is coupled to the first input end of the differential amplifier 710 (eg inverting input). The first end of the sixth capacitor C6 serves as the second input terminal VIN_GA of the sampling amplifier 320 to be coupled to the second output end of the sensors 310_1~310_n. The second end of the sixth capacitor C6 is coupled to the second input of the differential amplifier 710 (eg, a non-inverting input).
第七電容C7的第一端耦接至差動放大器710的第一輸入端。第八電容C8的第一端耦接至差動放大器710的第二輸入端。第六開關SW6的第一端與第二端分別耦接至差動放大器710的第一輸入端與差動放大器的第一輸出端。第七開關SW7的第一端與第二端分別耦接至第七電容C7的第二端與共模電壓VCM。第八開關SW8的第一端與第二端分別耦接至第七電容C7的第二端與差動放大器710的第一輸出端。第九開關SW9的第一端與第二端分別耦接至差動放大器710的第二輸入端與差動放大器710的第二輸出端。第十開關SW10的第一端與第二端分別耦接至第八電容C8的第二端與共模電壓VCM。第十一開關SW11的第一端與第二端分別耦接至第八電容C8的第二端與差動放大器710的第二輸出端。於本實施例中,第五電容C5的電容值相同於第六電容C6,而第七電容C7的電容值相同於第八電容C8。 The first end of the seventh capacitor C7 is coupled to the first input end of the differential amplifier 710. The first end of the eighth capacitor C8 is coupled to the second input of the differential amplifier 710. The first end and the second end of the sixth switch SW6 are respectively coupled to the first input end of the differential amplifier 710 and the first output end of the differential amplifier. The first end and the second end of the seventh switch SW7 are respectively coupled to the second end of the seventh capacitor C7 and the common mode voltage VCM. The first end and the second end of the eighth switch SW8 are respectively coupled to the second end of the seventh capacitor C7 and the first output end of the differential amplifier 710. The first end and the second end of the ninth switch SW9 are respectively coupled to the second input end of the differential amplifier 710 and the second output end of the differential amplifier 710. The first end and the second end of the tenth switch SW10 are respectively coupled to the second end of the eighth capacitor C8 and the common mode voltage VCM. The first end and the second end of the eleventh switch SW11 are respectively coupled to the second end of the eighth capacitor C8 and the second output end of the differential amplifier 710. In this embodiment, the capacitance value of the fifth capacitor C5 is the same as the sixth capacitor C6, and the capacitance value of the seventh capacitor C7 is the same as the eighth capacitor C8.
當顯示面板230操作於所述感測期間時,於感測期間的第一期間(第一相位)T1,第六開關SW6、第七開關SW7、第九開關SW9與第十開關SW10為導通,而第八開關SW8與第十一開關SW11為截止。第一期間T1中第五電容C5與第七電容C7的電 荷為 -VCM],其中Voffset表示差動放大器710的電壓偏移,而A表示差動放大器710的增益值。於第二期間(第二相位)T2,第六開關SW6、第七開關SW7、第九開關SW9與第十開關SW10為截止,而第八開關SW8與第十一開關SW11為導通。第二期間T2中第五電容C5與第七電容C7的電荷為C5*[VIP_GA’-(VCM+ ,其 中VIP_GA’表示差動放大器710於第二期間T2中第一輸入端的電壓。 When the display panel 230 is operated during the sensing period, the sixth switch SW6, the seventh switch SW7, the ninth switch SW9, and the tenth switch SW10 are turned on during the first period (first phase) T1 of the sensing period. The eighth switch SW8 and the eleventh switch SW11 are turned off. The charge of the fifth capacitor C5 and the seventh capacitor C7 in the first period T1 is -VCM], where V offset represents the voltage offset of the differential amplifier 710 and A represents the gain value of the differential amplifier 710. In the second period (second phase) T2, the sixth switch SW6, the seventh switch SW7, the ninth switch SW9, and the tenth switch SW10 are turned off, and the eighth switch SW8 and the eleventh switch SW11 are turned on. The charge of the fifth capacitor C5 and the seventh capacitor C7 in the second period T2 is C5*[VIP_GA'-(VCM+ Where VIP_GA' represents the voltage at the first input of the differential amplifier 710 during the second period T2.
藉由整理等式
綜上所述,上述諸實施例所提供的感測裝置300可以減少感測器310_1~310_n及/或取樣放大器320中放大電路的偏移(offset)。因此,感測裝置300可以精確地感測顯示面板230的像素電路中的電流源電晶體233的閾電壓。 In summary, the sensing device 300 provided by the above embodiments can reduce the offset of the amplifying circuit in the sensors 310_1~310_n and/or the sampling amplifier 320. Accordingly, the sensing device 300 can accurately sense the threshold voltage of the current source transistor 233 in the pixel circuit of the display panel 230.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
300‧‧‧感測裝置 300‧‧‧Sensing device
310_1、310_2、310_n‧‧‧感測器 310_1, 310_2, 310_n‧‧‧ sensors
320‧‧‧取樣放大器 320‧‧‧Sampling amplifier
330‧‧‧類比數位轉換器 330‧‧‧ Analog Digital Converter
B[K:1]‧‧‧數位偵測結果 B[K:1]‧‧‧ digital detection results
D_1、D_2、D_n‧‧‧資料線 D_1, D_2, D_n‧‧‧ data lines
VIN_GA‧‧‧取樣放大器320的第二輸入端 VIN_GA‧‧‧ second input of sampling amplifier 320
VIP_GA‧‧‧取樣放大器320的第一輸入端 The first input of the VIP_GA‧‧ sampling amplifier 320
VON‧‧‧感測器310_n的第二輸出端 The second output of the VON‧‧ sensor 310_n
VON_GA‧‧‧取樣放大器320的第二輸出端 VON_GA‧‧‧ second output of sampling amplifier 320
VOP‧‧‧感測器310_n的第一輸出端 The first output of the VOP‧‧ sensor 310_n
VOP_GA‧‧‧取樣放大器320的第一輸出端 VOP_GA‧‧‧ first output of sampling amplifier 320
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TWI637380B (en) * | 2017-01-03 | 2018-10-01 | 昂寶電子(上海)有限公司 | System and method for implementing gate driving circuit |
CN110599934A (en) * | 2018-06-12 | 2019-12-20 | 联咏科技股份有限公司 | Sensing circuit of display driver |
CN111243529A (en) * | 2018-11-29 | 2020-06-05 | 乐金显示有限公司 | Pixel sensing device and method, data driver and organic light emitting display device |
TWI724846B (en) * | 2020-03-30 | 2021-04-11 | 友達光電股份有限公司 | Sensing device and sensing method |
TWI815667B (en) * | 2021-10-28 | 2023-09-11 | 南韓商樂金顯示科技股份有限公司 | Display device |
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TWI637380B (en) * | 2017-01-03 | 2018-10-01 | 昂寶電子(上海)有限公司 | System and method for implementing gate driving circuit |
CN110599934A (en) * | 2018-06-12 | 2019-12-20 | 联咏科技股份有限公司 | Sensing circuit of display driver |
CN110599934B (en) * | 2018-06-12 | 2022-12-13 | 联咏科技股份有限公司 | Sensing circuit of display driver |
CN111243529A (en) * | 2018-11-29 | 2020-06-05 | 乐金显示有限公司 | Pixel sensing device and method, data driver and organic light emitting display device |
CN111243529B (en) * | 2018-11-29 | 2022-07-08 | 乐金显示有限公司 | Pixel sensing device and method, data driver and organic light emitting display device |
TWI724846B (en) * | 2020-03-30 | 2021-04-11 | 友達光電股份有限公司 | Sensing device and sensing method |
TWI815667B (en) * | 2021-10-28 | 2023-09-11 | 南韓商樂金顯示科技股份有限公司 | Display device |
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