TW201543454A - Output buffer - Google Patents

Abstract

An output buffer includes an amplifying-stage circuit configured to receiving an analog display voltage and accordingly to generate an amplified display voltage; a driving-stage circuit configured to receive the amplified display voltage and accordingly to generate a buffered display voltage for driving a display panel; and a switching device disposed between the amplifying-stage circuit and the driving-stage circuit. In a high-output-impedance state, the switching device is open to electrically insulate the driving-stage circuit from the amplifying-stage circuit; and in a driving state, the switching device is close to electrically couple the driving-stage circuit with the amplifying-stage circuit.

Description

Output buffer

This invention relates to an output buffer, and more particularly to an output buffer for a source driver.

When the resolution of the liquid crystal display panel becomes higher and higher, the source driver may have a problem of excessive temperature. One of the causes of excessive temperature is that when the source driver drives the liquid crystal display panel, the driving current flows through the multiplexer in the source driver. Generally, the heat-resistant temperature range of the tantalum process is about 150 to 200 degrees Celsius. When it exceeds the heat-resistant temperature range, it may cause abnormalities in the function of the component. Therefore, how to reduce the temperature of the source driver becomes an important circuit design issue. The general method of reducing the temperature of the source driver is to increase the size of the multiplexer. However, as a result, the overall area of the integrated circuit becomes excessive.

Therefore, it is urgent to propose a novel architecture to effectively reduce the temperature of the source driver without increasing the circuit area.

In view of the above, one of the objects of embodiments of the present invention is to provide an output buffer that does not flow through the multiplexer when the display panel is driven, thereby reducing the overall temperature of the source driver and/or the circuit area.

According to an embodiment of the invention, the output buffer comprises an amplifier stage circuit, a driver stage circuit and a switch. The amplifier stage circuit receives an analog display voltage to produce an amplified display voltage. The driver stage circuit receives the amplified display voltage to generate a buffer display voltage for driving the display panel. The switch is disposed between the amplifier stage circuit and the driver stage circuit. When in the high output impedance state, the switch is disconnected, so that the driver stage circuit and the amplifier stage circuit are electrically separated from each other; when in the driving state, the switch is closed, so that the driver stage circuit and the amplifier stage circuit are electrically coupled to each other. .

The first figure shows a functional block diagram of an output buffer 100 in accordance with an embodiment of the present invention that can be used to drive a display panel 2 (e.g., a liquid crystal display panel). In a specific example, the output buffer 100 of the present embodiment is provided in the source driver 1, for example, at the output stage of the source driver 1. The input of the output buffer 100 can receive an analog display voltage from a digital analog converter (DAC) 110, and the output of the output buffer 100 outputs a buffer display voltage to the display panel 2.

In the present embodiment, the output buffer 100 mainly includes an amplifier stage circuit 11 and a driver stage circuit 12, wherein the amplifier stage circuit 11 receives an analog display voltage from a digital analog converter (DAC) 110, and an enlarged display generated by the amplifier stage circuit 11. The voltage is fed to the driver stage circuit 12, and the buffer display voltage generated by the driver stage circuit 12 is used to drive the display panel 2. The output buffer 100 of this embodiment further includes a switch SW disposed between the amplifier stage circuit 11 and the driver stage circuit 12. When the output buffer 100 is in a high output impedance state, the switch SW is turned off, so that the driver stage circuit 12 and the amplifier stage circuit 11 are electrically separated from each other. When the output buffer 100 is in the driving state, the switch SW is closed, so that the driver stage circuit 12 and the amplifier stage circuit 11 are electrically coupled to each other. According to one of the features of the embodiment, when the output buffer 100 is in the driving state, the large current flowing through the driving stage circuit 12 does not pass through the multiplexer, so that the temperature does not rise and the large size is not required. Work tool.

The second figure shows a circuit diagram of the output buffer 100 of the first figure. The output buffer 100 shown in the second figure uses a differential circuit architecture, although the invention is not limited to this architecture. As shown in the second figure, the output buffer 100 includes a positive output buffer 100A and a negative output buffer 100B. In detail, the positive output buffer 100A includes an amplifier stage circuit 11A and a driver stage circuit 12A, wherein the amplifier stage circuit 11A includes a differential operational amplifier HVOP having a positive input terminal (+) and a negative input terminal (-). The positive input terminal (+) receives the analog display voltage Vin1 from the digital analog converter (DAC) 110. The amplifier stage circuit 11A further includes a first transistor M1 and a second transistor M2 connected in series between the power source and the ground. In this embodiment, the first transistor M1 may be a P-type metal oxide semiconductor (PMOS) transistor, and the second transistor M2 may be an N-type metal oxide semiconductor (NMOS) transistor, the first transistor M1 and The drain of the second transistor M2 is coupled to the intermediate node A and coupled to the negative input terminal (-) of the differential operational amplifier HVOP, and the gates of the first transistor M1 and the second transistor M2 are respectively coupled to Positive and negative outputs of the differential op amp HVOP. A first capacitor CA may be coupled between the gate and the drain of the first transistor M1, and a second capacitor CB may be coupled between the gate and the drain of the second transistor M2.

The driver stage circuit 12A of this embodiment includes a third transistor M3 and a fourth transistor M4 connected in series between the power source and the ground. In this embodiment, the third transistor M3 may be a P-type metal oxide semiconductor (PMOS) transistor, the fourth transistor M4 may be an N-type metal oxide semiconductor (NMOS) transistor, and the third transistor M3 and The drain of the fourth transistor M4 is connected to the output node B and is coupled to the intermediate node A (or the negative input terminal (-) of the differential operational amplifier HVOP) via the first switch SW1. The gate of the third transistor M3 is selectively coupled to the gate of the first transistor M1 (or the positive output of the differential operational amplifier HVOP) via the first selector SEL1 or selectively coupled to the power source. The gate of the fourth transistor M4 is selectively coupled to the gate of the second transistor M2 (or the negative output of the differential operational amplifier HVOP) via the second selector SEL2 or selectively coupled to ground. The element sizes of the third transistor M3 and the fourth transistor M4 are generally larger than those of the first transistor M1 and the second transistor M2, so that a larger driving current can flow through the third transistor M3, fourth. Transistor M4.

The circuit configuration of the negative polarity output buffer 100B is the same as that of the positive polarity output buffer 100A. In detail, the negative polarity output buffer 100B includes an amplifier stage circuit 11B and a driver stage circuit 12B, wherein the amplifier stage circuit 11B includes a differential operational amplifier LVOP having a positive input terminal (+) and a negative input terminal (-). The positive input terminal (+) receives the analog display voltage Vin2 from the digital analog converter (DAC) 110. The amplifier stage circuit 11B further includes a first transistor M1 and a second transistor M2 connected in series between the power source and the ground. In this embodiment, the first transistor M1 may be a P-type metal oxide semiconductor (PMOS) transistor, and the second transistor M2 may be an N-type metal oxide semiconductor (NMOS) transistor, the first transistor M1 and The drain of the second transistor M2 is coupled to the intermediate node A and coupled to the negative input terminal (-) of the differential operational amplifier LVOP, and the gates of the first transistor M1 and the second transistor M2 are respectively coupled to Positive and negative outputs of the differential op amp LVOP. A first capacitor CA may be coupled between the gate and the drain of the first transistor M1, and a second capacitor CB may be coupled between the gate and the drain of the second transistor M2.

The driver stage circuit 12B of this embodiment includes a third transistor M3 and a fourth transistor M4 connected in series between the power source and the ground. In this embodiment, the third transistor M3 may be a P-type metal oxide semiconductor (PMOS) transistor, the fourth transistor M4 may be an N-type metal oxide semiconductor (NMOS) transistor, and the third transistor M3 and The drain of the fourth transistor M4 is connected to the output node B and is coupled to the intermediate node A (or the negative input terminal (-) of the differential operational amplifier HVOP) via the first switch SW1. The gate of the third transistor M3 is selectively coupled to the gate of the first transistor M1 (or the positive output of the differential operational amplifier HVOP) via the first selector SEL1 or selectively coupled to the power source. The gate of the fourth transistor M4 is selectively coupled to the gate of the second transistor M2 (or the negative output of the differential operational amplifier HVOP) via the second selector SEL2 or selectively coupled to ground. The element sizes of the third transistor M3 and the fourth transistor M4 are generally larger than those of the first transistor M1 and the second transistor M2, so that a larger driving current can flow through the third transistor M3, fourth. Transistor M4. In addition, the driver stage circuit 12 of the present embodiment further includes a second switch SW2, the two ends of which are respectively coupled to the output node B of the driver stage circuits 12A, 12B.

According to the output buffer 100 shown in the first and second figures, the present embodiment can be sequentially operated in the following states. The third figure shows that the output buffer 100 of the second figure is in a high output impedance state. At this time, the first switch SW1 of the positive polarity output buffer 100A and the negative polarity output buffer 100B, the first selector SEL1 and the second selector SEL2 is all disconnected, so that the driver stage circuit 12 and the amplifier stage circuit 11 are electrically separated from each other. In the high output impedance state, the analog display voltages Vin1, Vin2 are amplified by the differential operational amplifiers HVOP, LVOP, respectively, and the charge is stored at node A. At the same time, the second switch SW2 is closed to facilitate the display panel 2 to perform charge sharing. When the high output impedance state ends, it enters the drive state.

The fourth figure shows that the output buffer 100 of the second diagram is in a driving state. At this time, the first switch SW1 of the positive polarity output buffer 100A and the negative polarity output buffer 100B, the first selector SEL1 and the second selector SEL2 are both closed, and the second switch SW2 is turned off. In the driving state, the positive polarity output buffer 100A and the drive stage circuits 12A, 12B of the negative polarity output buffer 100B drive the display panel 2. Compared with the traditional output buffer, the drive current will pass through the multiplexer, thus causing the temperature to rise. In contrast, the large current during the driving of this embodiment does not pass through the multiplexer, so the temperature does not rise and does not need to be Use a large multiplexer. In addition, the driving current of the conventional output buffer also passes through the first switch SW1, so it is necessary to use a larger switch; in contrast, the driving current of the embodiment does not pass through the first switch SW1, so only a general switch needs to be used.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

1‧‧‧Source Driver
11‧‧‧Amplified stage circuit
11A‧‧‧Amplifier circuit
11B‧‧‧Amplified stage circuit
12‧‧‧Drive level circuit
12A‧‧‧Driver Circuit
12B‧‧‧Driver Circuit
100‧‧‧Output buffer
100A‧‧‧Positive output buffer
100B‧‧‧negative output buffer
110‧‧‧Digital Analog Converter
2‧‧‧ display panel
HVOP‧‧‧Differential Operational Amplifier
LVOP‧‧‧Differential Operational Amplifier
A‧‧‧intermediate node
B‧‧‧Output node
M1‧‧‧first transistor
M2‧‧‧second transistor
M3‧‧‧ third transistor
M4‧‧‧ fourth transistor
CA‧‧‧First Capacitor
CB‧‧‧second capacitor
SW‧‧‧Switch
SW1‧‧‧ first switch
SW2‧‧‧second switch
SEL1‧‧‧First selector
SEL2‧‧‧Second Selector
Vin1~Vin2‧‧‧ analog display voltage

The first figure shows a functional block diagram of an output buffer in accordance with an embodiment of the present invention. The second figure shows the circuit diagram of the output buffer of the first figure. The third figure shows that the output buffer of the second figure is in a high output impedance state. The fourth figure shows that the output buffer of the second figure is in the drive state.

1‧‧‧Source Driver

11‧‧‧Amplified stage circuit

12‧‧‧Drive level circuit

100‧‧‧Output buffer

110‧‧‧Digital Analog Converter

2‧‧‧ display panel

SW‧‧‧Switch

Claims (9)

An output buffer comprising: an amplifier stage circuit for receiving an analog display voltage to generate an amplified display voltage; a driver stage circuit for receiving the amplified display voltage to generate a buffer display voltage for driving a display panel; and a switcher, Provided between the amplifier stage circuit and the driver stage circuit, when in a high output impedance state, the switch is disconnected, so that the driver stage circuit and the amplifier stage circuit are electrically separated from each other, when in the driving state, The switch is closed such that the driver stage circuit and the amplifier stage circuit are electrically coupled to each other. The output buffer of claim 1, wherein the amplifier stage circuit comprises: a differential operational amplifier, wherein an input terminal receives the analog display voltage; a first transistor; and a second transistor, The first transistor and the second transistor are connected in series between the power source and the ground, and the first transistor and the second transistor are connected to the intermediate node, and the second transistor is coupled to the other of the differential operational amplifiers. Input. The output buffer of claim 2, wherein the first transistor is a P-type metal oxide semiconductor (PMOS) transistor, and the second transistor is an N-type metal oxide semiconductor (NMOS) transistor The first transistor and the drain of the second transistor are connected to the intermediate node and coupled to the negative input terminal of the differential operational amplifier, and the positive input terminal of the differential operational amplifier receives the analog display voltage. The gates of the first transistor and the second transistor are respectively coupled to the positive and negative outputs of the differential operational amplifier. The output buffer of claim 2, wherein the amplifier stage circuit further comprises: a first capacitor coupled between the gate and the drain of the first transistor; and a second capacitor, It is coupled between the gate and the drain of the second transistor. The output buffer of claim 2, wherein the driver stage circuit comprises: a third transistor; and a fourth transistor, wherein the third transistor and the fourth transistor are connected in series with the power supply And the ground, and the third transistor and the fourth transistor are connected to the output node for outputting the buffer display voltage. The output buffer of claim 5, wherein the third transistor is a P-type metal oxide semiconductor (PMOS) transistor, and the fourth transistor is an N-type metal oxide semiconductor (NMOS) transistor. And the third transistor and the drain of the fourth transistor are connected to the output node. The output buffer of claim 5, wherein the switch comprises: a first switch connected between the intermediate node and the output node; a first selector for selectively coupling the first And a second selector for selectively coupling one of the fourth transistor to the ground or the second transistor. The output buffer of claim 7, wherein the first transistor and the third transistor are P-type metal oxide semiconductor (PMOS) transistors, and the second transistor and the fourth transistor are N. a metal-oxide-semiconductor (NMOS) transistor, the gate of the third transistor is selectively coupled to the gate of the first transistor or selectively coupled to the power source via the first selector, and the fourth The gate of the crystal is selectively coupled to the gate of the second transistor or selectively coupled to ground via the second selector. The output buffer of claim 5, wherein an element size of the third transistor and the fourth transistor is larger than an element size of the first transistor and the second transistor.