TWI711308B - Output buffer - Google Patents

Abstract

An output buffer includes an amplifier, a switch transistor, and a switching circuit. The first input terminal of the amplifier receives an input voltage. The control terminal of the switch transistor is controlled by a control signal, wherein the control signal at least defines a driving period and a high impedance period. The first terminal of the switch transistor is coupled to the output terminal of the amplifier. The second terminal of the switch transistor provides an output voltage to the data line of a display panel. During the driving period, the switching circuit electrically connects the bulk of the switch transistor to the first terminal of the switch transistor or the second terminal of the switch transistor. During the high impedance period, the switching circuit electrically connects the bulk of the switch transistor to a power supply voltage.

Description

Output buffer

The present invention relates to a display device, and particularly relates to an output buffer.

The source driver is used to drive multiple data lines (or source lines) of the display panel. The source driver is configured with a plurality of drive channel circuits, and each of these drive channel circuits drives a corresponding one of the data lines through a different output buffer. In the source driver, the output buffer can gain the analog voltage of the digital-to-analog converter and output it to the data line of the display panel. As the resolution and/or frame rate of the display panel becomes higher and higher, the charging time for one scan line becomes shorter and shorter. In order to drive (charge or discharge) a pixel in a short time, the output buffer must have a sufficiently high drive capability. That is, the output buffer needs a sufficiently high slew rate.

Generally speaking, the output buffer is configured with switching transistors. When the switching transistor is turned on, the output buffer can output an analog voltage to the data line of the display panel, that is, the output buffer is in the driving period. When the switching transistor is turned off, the output buffer does not output analog voltage to the data line of the display panel, that is, the output buffer is in a high impedance period. The switching transistor of the conventional output buffer has an on-resistance (Ron) that cannot be ignored due to the body effect. The larger the on-resistance of the output buffer, the smaller the slew rate of the output buffer.

The present invention provides an output buffer to reduce the body effect of the switching transistor.

An embodiment of the present invention provides an output buffer. The output buffer includes an amplifier, a switching transistor, and a first switching circuit. The first input terminal of the amplifier is coupled to the input terminal of the output buffer to receive the input voltage. The control terminal of the switching transistor is controlled by a control signal, wherein the control signal at least defines a driving period and a high impedance period. The first terminal of the switching transistor is coupled to the output terminal of the amplifier. The second terminal of the switching transistor is coupled to the output terminal of the output buffer to provide an output voltage to the data line of the display panel. The common terminal of the first switching circuit is coupled to the base of the switching transistor. During the driving period, the first switching circuit electrically connects the base of the switching transistor to the first end of the switching transistor or the second end of the switching transistor. During the high impedance period, the first switching circuit electrically connects the base of the switching transistor to the power supply voltage.

An embodiment of the present invention provides an output buffer. The output buffer includes an amplifier, a switching transistor, and a switching circuit. The first input terminal of the amplifier is coupled to the input terminal of the output buffer to receive the input voltage. The control terminal of the switching transistor is controlled by a control signal, wherein the control signal at least defines a driving period and a high impedance period. The first terminal of the switching transistor is coupled to the output terminal of the amplifier. The second terminal of the switching transistor is coupled to the output terminal of the output buffer to provide an output voltage to the data line of the display panel. The common terminal of the switching circuit is coupled to the second input terminal of the amplifier. During the driving period, the switching circuit electrically connects the second input terminal of the amplifier to the second terminal of the switching transistor or the output bonding pad, wherein the output bonding pad is coupled to the second terminal of the switching transistor via an electrostatic discharge resistor. During the high impedance period, the switching circuit electrically connects the second input terminal of the amplifier to the output terminal of the amplifier.

Based on the above, the output buffers of the embodiments of the present invention can electrically connect the base of the switching transistor to the power supply voltage during the high impedance period, and electrically connect the base of the switching transistor to the switching transistor during the driving period. The first end (or second end). Therefore, the output buffer can reduce the matrix effect of the switching transistor. Due to the reduced matrix effect, the on-resistance (Ron) of the switching transistor can be effectively reduced, thereby increasing the slew rate of the output buffer.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The term "coupling (or connection)" used in the full description of the case (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if the text describes that the first device is coupled (or connected) to the second device, it should be interpreted as that the first device can be directly connected to the second device, or the first device can be connected through other devices or some This kind of connection means is indirectly connected to the second device. In addition, wherever possible, elements/components/steps with the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps using the same reference numerals or using the same terms in different embodiments may refer to related descriptions.

FIG. 1 is a schematic diagram illustrating a circuit block of a display device 100 according to an embodiment of the present invention. The display device 100 shown in FIG. 1 includes a gate driver 110, a source driver 120 and a display panel 130. The display panel 130 may be any type of flat panel display, such as a liquid crystal display panel, an organic light emitting diode display panel, or other display panels. The display panel 130 includes multiple scan lines (or gate lines), multiple data lines (or source lines), and multiple pixel circuits. For example, as shown in FIG. 1, the multiple scan lines include n scan lines SL_1, SL_2,..., SL_n, and the multiple data lines include m data lines DL_1, DL_2,..., DL_m, and the multiple pixels The circuit contains m*n pixel circuits P(1,1),...,P(m,1),...,P(1,n),...,P(m,n), where m and n can be designed according to the design Any integer determined by demand.

The multiple output terminals of the gate driver 110 are coupled to different scan lines of the display panel 130 in a one-to-one manner. The gate driver 110 can scan/drive each scan line of the display panel 130. The gate driver 110 may be any type of gate driver. For example, the gate driver 110 may be a conventional gate driver or other gate drivers according to design requirements.

The source driver 120 has a plurality of driving channel circuits, for example, m driving channel circuits 121_1, 121_2,..., 121_m shown in FIG. 1. The output terminals of these driving channel circuits 121_1 to 121_m are coupled to different data lines of the display panel 130 in a one-to-one manner. The driving channel circuits 121_1 to 121_m can convert digital pixel data into corresponding output voltages (pixel voltages), and output these output voltages to different data lines of the display panel 130 respectively. In accordance with the scanning timing of the gate driver 110, the source driver 120 can write these output voltages into the corresponding pixel circuits of the display panel 130 through the data lines DL_1 to DL_m to display images.

FIG. 2 is a circuit block diagram illustrating the driving channel circuit 121_1 shown in FIG. 1 according to an embodiment of the present invention. The other driving channel circuits 121_2 to 121_m shown in FIG. 1 can be deduced by referring to the related description of the driving channel circuit 121_1 shown in FIG. The driving channel circuit 121_1 shown in FIG. 2 includes a latch 210, a channel circuit 220, and an output buffer 230. The latch 210 can provide current pixel data to the channel circuit 220. The latch 210 may be any type of latch. For example, the latch 210 may be a conventional wire latch or other latches according to design requirements.

The channel circuit 220 can convert the current pixel data into an analog voltage (hereinafter referred to as the input voltage Vi), and output the input voltage Vi to the output buffer 230. In the embodiment shown in FIG. 2, the channel circuit 220 may include a level shifter 221 and a digital to analog converter (DAC) 222. The level shifter 221 can increase the voltage swing of the current pixel data, and the digital-to-analog converter 222 can convert the current pixel data into the input voltage Vi. The digital-to-analog converter 222 can output the input voltage Vi to the output buffer 230. In other embodiments, the quasi-shifter 221 may be omitted due to design requirements, so that the digital-to-analog converter 222 can directly receive the current pixel data from the latch 210.

In the embodiment shown in FIG. 2, the output buffer 230 includes an amplifier 231, a switching transistor 232 and a switching circuit 233. The amplifier 231 may be any type of buffer circuit, amplifying circuit or gain circuit. For example, according to design requirements, the amplifier 231 may include a conventional operational amplifier or other amplifiers. The first input terminal (for example, a non-inverting input terminal) of the amplifier 231 is coupled to the input terminal of the output buffer 230 (that is, coupled to the output terminal of the digital-to-analog converter 222) to receive the input voltage Vi. The output terminal of the amplifier 231 can generate an output voltage Vo. The output terminal of the amplifier 231 is coupled to the second input terminal (for example, an inverting input terminal) of the amplifier 231.

The first terminal (for example, the source or the drain) of the switching transistor 232 is coupled to the output terminal of the amplifier 231. The second terminal (eg, drain or source) of the switching transistor 232 is coupled to the output terminal of the output buffer 230 to provide the output voltage Vo to the data line DL_1 of the display panel 130. The control terminal of the switching transistor 232 is controlled by a control signal Sc1, where the control signal Sc1 at least defines a driving period and a high impedance period. The high impedance period can also be called the HI-Z period. During the driving period, the switching transistor 232 is turned on. During the high impedance period, the switching transistor 232 is turned off.

The common terminal of the switching circuit 233 is coupled to the body (or bulk) of the switching transistor 232. The first selection terminal of the switching circuit 233 is coupled to the second terminal of the switching transistor 232. The second selection terminal of the switching circuit 233 is coupled to the power supply voltage. In the embodiment shown in FIG. 2, the switching transistor 232 is a P-channel transistor, such as a P-channel Metal-Oxide-Semiconductor (PMOS) transistor. When the switching transistor 232 is a P-channel transistor, the power supply voltage may be any voltage higher than the voltage swing of the output voltage Vo (for example, the system voltage VDDA).

During the driving period (a period when the switching transistor 232 is on), the switching circuit 233 can electrically connect the base of the switching transistor 232 to the second end of the switching transistor 232. Therefore, the output buffer 230 can reduce the matrix effect of the switching transistor 232. Since the matrix effect is reduced, the on-resistance (Ron) of the switching transistor 232 can be effectively reduced, thereby increasing the slew rate of the output buffer 230. During the high impedance period (the period when the switching transistor 232 is off), the switching circuit 233 can electrically connect the base of the switching transistor 232 to the power supply voltage (for example, the system voltage VDDA) to ensure that the switching transistor 232 is off.

In the embodiment shown in FIG. 2, the switching circuit 233 includes a switch SW1 and a switch SW2. The first end of the switch SW1 is coupled to the base of the switching transistor 232. The second end of the switch SW1 is coupled to the second end of the switching transistor 232. The first end of the switch SW2 is coupled to the base of the switching transistor 232. The second end of the switch SW2 is coupled to the power supply voltage (for example, the system voltage VDDA). In the driving period (a period when the switching transistor 232 is on), the switch SW1 is on and the switch SW2 is off. In the high impedance period (a period when the switching transistor 232 is off), the switch SW1 is off, and the switch SW2 is on.

FIG. 3 is a circuit block diagram illustrating the output buffer 330 according to another embodiment of the invention. According to design requirements, the output buffer 330 shown in FIG. 3 can be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 3, the output buffer 330 includes an amplifier 231, a switching transistor 232 and a switching circuit 233. The amplifier 231, the switching transistor 232, and the switching circuit 233 shown in FIG. 3 can be deduced by referring to the related descriptions of the amplifier 231, the switching transistor 232, and the switching circuit 233 shown in FIG.

In the embodiment shown in FIG. 3, the first selection terminal of the switching circuit 233 is coupled to the first terminal of the switching transistor 232. That is, the second end of the switch SW1 is coupled to the first end of the switching transistor 232. During the driving period (a period when the switching transistor 232 is on), the switching circuit 233 can electrically connect the base of the switching transistor 232 to the first end of the switching transistor 232. Therefore, the output buffer 330 can reduce the matrix effect of the switching transistor 232. Since the matrix effect is reduced, the on-resistance (Ron) of the switching transistor 232 can be effectively reduced, thereby increasing the slew rate of the output buffer 330. During the high impedance period (the period when the switching transistor 232 is off), the switching circuit 233 can electrically connect the base of the switching transistor 232 to the power supply voltage (for example, the system voltage VDDA) to ensure that the switching transistor 232 is off.

FIG. 4 is a circuit block diagram illustrating the output buffer 430 according to another embodiment of the present invention. According to design requirements, the output buffer 430 shown in FIG. 4 can be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 4, the output buffer 430 includes an amplifier 231, a switching transistor 234, and a switching circuit 235. The amplifier 231, the switching transistor 234, and the switching circuit 235 shown in FIG. 4 can be deduced by analogy with reference to the related description of the amplifier 231, the switching transistor 232, and the switching circuit 233 shown in FIG.

In the embodiment shown in FIG. 4, the first terminal (for example, the drain or the source) of the switching transistor 234 is coupled to the output terminal of the amplifier 231. The second terminal (for example, the source or the drain) of the switching transistor 234 is coupled to the output terminal of the output buffer 230 to provide the output voltage Vo to the data line DL_1 of the display panel 130. The control terminal of the switching transistor 234 is controlled by the control signal Sc2, where the control signal Sc2 at least defines a driving period and a high impedance period. The high impedance period can also be called the HI-Z period. During the driving period, the switching transistor 234 is turned on. During the high impedance period, the switching transistor 234 is turned off.

The common terminal of the switching circuit 235 is coupled to the base of the switching transistor 234. The first selection terminal of the switching circuit 235 is coupled to the second terminal of the switching transistor 234. The second selection terminal of the switching circuit 235 is coupled to the power supply voltage. In the embodiment shown in FIG. 4, the switching transistor 234 is an N-channel transistor, such as an N-channel Metal-Oxide-Semiconductor (NMOS) transistor. When the switching transistor 234 is an N-channel transistor, the power supply voltage may be any voltage lower than the voltage swing of the output voltage Vo (for example, the reference voltage VSSA, or the ground voltage).

During the driving period (a period when the switching transistor 234 is on), the switching circuit 235 can electrically connect the base of the switching transistor 234 to the second end of the switching transistor 234. Therefore, the output buffer 430 can reduce the matrix effect of the switching transistor 234. Since the matrix effect is reduced, the on-resistance (Ron) of the switching transistor 234 can be effectively reduced, thereby increasing the slew rate of the output buffer 430. During the high impedance period (the period when the switching transistor 234 is off), the switching circuit 235 can electrically connect the base of the switching transistor 234 to the power supply voltage (for example, the reference voltage VSSA) to ensure that the switching transistor 234 is off.

In the embodiment shown in FIG. 4, the switching circuit 235 includes a switch SW3 and a switch SW4. The first end of the switch SW3 is coupled to the base of the switching transistor 234. The second end of the switch SW3 is coupled to the second end of the switching transistor 234. The first end of the switch SW4 is coupled to the base of the switching transistor 234. The second end of the switch SW4 is coupled to the power supply voltage (for example, the reference voltage VSSA). During the driving period (a period during which the switching transistor 234 is on), the switch SW3 is on and the switch SW4 is off. In the high impedance period (a period in which the switching transistor 234 is off), the switch SW3 is off, and the switch SW4 is on.

FIG. 5 is a circuit block diagram illustrating the output buffer 530 according to another embodiment of the invention. According to design requirements, the output buffer 530 shown in FIG. 5 may be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 5, the output buffer 530 includes an amplifier 231, a switching transistor 234, and a switching circuit 235. The amplifier 231, the switching transistor 234, and the switching circuit 235 shown in FIG. 5 can be deduced by analogy with reference to the related description of the amplifier 231, the switching transistor 234, and the switching circuit 235 shown in FIG.

In the embodiment shown in FIG. 5, the first selection terminal of the switching circuit 235 is coupled to the first terminal of the switching transistor 234. That is, the second terminal of the switch SW3 is coupled to the first terminal of the switching transistor 234. During the driving period (a period when the switching transistor 234 is on), the switching circuit 235 can electrically connect the base of the switching transistor 234 to the first end of the switching transistor 234. Therefore, the output buffer 530 can reduce the matrix effect of the switching transistor 234. Since the matrix effect is reduced, the on-resistance (Ron) of the switching transistor 234 can be effectively reduced, thereby increasing the slew rate of the output buffer 530. During the high impedance period (the period when the switching transistor 234 is off), the switching circuit 235 can electrically connect the base of the switching transistor 234 to the power supply voltage (for example, the reference voltage VSSA) to ensure that the switching transistor 234 is off.

FIG. 6 is a circuit block diagram illustrating the output buffer 630 according to still another embodiment of the present invention. According to design requirements, the output buffer 630 shown in FIG. 6 can be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 6, the output buffer 630 includes an amplifier 231, a switching transistor 236 and a switching circuit 237. The amplifier 231 shown in FIG. 6 can refer to the related description of the amplifier 231 shown in FIG. 2. The switching transistor 236 shown in FIG. 6 can refer to the related descriptions of the switching transistor 232 and the switching circuit 233 shown in FIG. 2 or FIG. 3, or the switching transistor 236 shown in FIG. 6 may refer to the switch shown in FIG. 4 or FIG. The related descriptions of the transistor 234 and the switching circuit 235 are analogized, so they will not be repeated. In other embodiments, according to design requirements, the switching transistor 236 shown in FIG. 6 may be any switching element/circuit, such as a conventional switching transistor or other switching elements.

The first terminal of the switching transistor 236 is coupled to the output terminal of the amplifier 231. The second end of the switching transistor 236 is coupled to the output pad 240 via the electrostatic discharge resistor ESDR. When the switching transistor 236 is turned on, the output voltage Vo of the amplifier 231 can be transmitted to the data line DL_1 via the switching transistor 236, the electrostatic discharge resistor ESDR, and the output pad 240.

The common terminal of the switching circuit 237 shown in FIG. 6 is coupled to the second input terminal of the amplifier 231. The first selection terminal of the switching circuit 237 is coupled to the second terminal of the switching transistor 236. The second selection terminal of the switching circuit 237 is coupled to the output terminal of the amplifier 231. During the driving period (a period when the switching transistor 236 is on), the switching circuit 237 electrically connects the second input terminal of the amplifier 231 to the second terminal of the switching transistor 236. During the high impedance period (a period when the switching transistor 236 is off), the switching circuit 237 electrically connects the second input terminal of the amplifier 231 to the output terminal of the amplifier 231.

In the embodiment shown in FIG. 6, the switching circuit 237 includes a switch SW5 and a switch SW6. The first terminal of the switch SW5 is coupled to the second input terminal of the amplifier 231. The second end of the switch SW5 is coupled to the second end of the switching transistor 236. The first terminal of the switch SW6 is coupled to the second input terminal of the amplifier 231. The second terminal of the switch SW6 is coupled to the output terminal of the amplifier 231. During the driving period (a period during which the switching transistor 236 is on), the switch SW5 is on and the switch SW6 is off. In the high impedance period (a period in which the switching transistor 236 is off), the switch SW5 is off, and the switch SW6 is on.

FIG. 7 is a circuit block diagram illustrating the output buffer 730 according to another embodiment of the present invention. According to design requirements, the output buffer 730 shown in FIG. 7 can be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 7, the output buffer 730 includes an amplifier 231, a switching transistor 236 and a switching circuit 237. The amplifier 231, the switching transistor 236, and the switching circuit 237 shown in FIG. 7 can be deduced by referring to the related descriptions of the amplifier 231, the switching transistor 236, and the switching circuit 237 shown in FIG.

In the embodiment shown in FIG. 7, the first selection terminal of the switching circuit 237 is coupled to the output pad 240 via the electrostatic discharge resistor ESDR'. That is, the second end of the switch SW5 is coupled to the output pad 240. The output pad 240 is coupled to the second end of the switching transistor 236 via the electrostatic discharge resistor ESDR. During the driving period (a period during which the switching transistor 236 is turned on), the switching circuit 237 can electrically connect the second input terminal of the amplifier 231 to the bonding pad 240. During the high impedance period (a period when the switching transistor 236 is off), the switching circuit 237 can electrically connect the second input terminal of the amplifier 231 to the output terminal of the amplifier 231.

In summary, the output buffers described in the embodiments of the present invention can electrically connect the base of the switching transistor to the power supply voltage during the high impedance period, and electrically connect the base of the switching transistor to the switch during the driving period. The first end (or second end) of the transistor. Therefore, the output buffer can reduce the matrix effect of the switching transistor. Due to the reduced matrix effect, the on-resistance (Ron) of the switching transistor can be effectively reduced, thereby increasing the slew rate of the output buffer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: display device 110: Gate driver 120: source driver 121_1, 121_2, 121_m: drive channel circuit 130: display panel 210: Latch 220: Channel circuit 221: Quasi-shifter 222: Digital to Analog Converter 230, 330, 430, 530, 630, 730: output buffer 231: Amplifier 232, 234, 236: switching transistor 233, 235, 237: switching circuit 240: Output pad DL_1, DL_2, DL_m: data line ESDR, ESDR’: Electrostatic discharge resistance P(1,1), P(m,1), P(1,n), P(m,n): pixel circuit Sc1, Sc2: control signal SL_1, SL_2, SL_n: scan line SW1, SW2, SW3, SW4, SW5, SW6: switches VDDA: system voltage Vi: input voltage Vo: output voltage VSSA: Reference voltage

FIG. 1 is a schematic diagram illustrating a circuit block of a display device according to an embodiment of the present invention. FIG. 2 is a circuit block diagram illustrating the driving channel circuit shown in FIG. 1 according to an embodiment of the present invention. FIG. 3 is a schematic block diagram illustrating the circuit of the output buffer according to another embodiment of the present invention. FIG. 4 is a block diagram illustrating the circuit block diagram of the output buffer according to another embodiment of the present invention. FIG. 5 is a circuit block diagram illustrating the output buffer according to another embodiment of the invention. FIG. 6 is a circuit block diagram illustrating the output buffer according to still another embodiment of the present invention. FIG. 7 is a circuit block diagram illustrating the output buffer according to a further embodiment of the invention.

121_1: drive channel circuit 210: Latch 220: Channel circuit 221: Quasi-shifter 222: Digital to Analog Converter 230: output buffer 231: Amplifier 232: Switching transistor 233: Switching circuit DL_1: Data line Sc1: control signal SW1, SW2: switch VDDA: system voltage Vi: input voltage Vo: output voltage

Claims (10)

An output buffer, including: An amplifier having a first input terminal coupled to an input terminal of the output buffer to receive an input voltage; A switching transistor having a control terminal controlled by a control signal, wherein the control signal defines at least a driving period and a high impedance period, a first terminal of the switching transistor is coupled to an output terminal of the amplifier, A second terminal of the switching transistor is coupled to an output terminal of the output buffer to provide an output voltage to a data line of a display panel; and A first switching circuit having a common terminal coupled to a substrate of the switching transistor, wherein the first switching circuit electrically connects the substrate of the switching transistor to the substrate of the switching transistor during the driving period The first terminal or the second terminal of the switching transistor, and the first switching circuit electrically connects the base of the switching transistor to a power supply voltage during the high impedance period. The output buffer according to claim 1, wherein the switching transistor is on during the driving period, and the switching transistor is off during the high impedance period. The output buffer as described in item 1 of the scope of patent application, wherein: When the switching transistor is a P-channel transistor, the power supply voltage is a system voltage higher than a voltage swing of the output voltage; and When the switching transistor is an N-channel transistor, the power supply voltage is a reference voltage lower than the voltage swing of the output voltage. According to the output buffer described in item 1 of the scope of patent application, the first switching circuit includes: A first switch having a first terminal coupled to the base body of the switching transistor, wherein a second terminal of the first switch is coupled to the first terminal of the switching transistor or the switching transistor At the second end, the first switch is turned on during the driving period, and the first switch is turned off during the high impedance period; and A second switch having a first terminal coupled to the base body of the switching transistor, wherein a second terminal of the second switch is coupled to the power supply voltage, and the second switch is turned off during the driving period, And the second switch is turned on during the high impedance period. The output buffer according to the first item of the scope of patent application, wherein the output terminal of the amplifier is coupled to a second input terminal of the amplifier. The output buffer described in item 1 of the scope of patent application further includes: A second switching circuit having a common terminal coupled to a second input terminal of the amplifier, wherein the second switching circuit electrically connects the second input terminal of the amplifier to the switching transistor during the driving period The second end of the output pad or an output pad, the output pad is coupled to the second end of the switching transistor via an electrostatic discharge resistor, and during the high impedance period the second switching circuit of the amplifier The second input terminal is electrically connected to the output terminal of the amplifier. According to the output buffer described in item 6 of the scope of patent application, the second switching circuit includes: A first switch having a first terminal coupled to the second input terminal of the amplifier, wherein a second terminal of the first switch is coupled to the second terminal of the switching transistor or the output pad, The first switch is turned on during the driving period, and the first switch is turned off during the high impedance period; and A second switch having a first terminal coupled to the second input terminal of the amplifier, wherein a second terminal of the second switch is coupled to the output terminal of the amplifier, and during the driving period, the second The switch is off, and the second switch is on during the high impedance period. An output buffer, including: An amplifier having a first input terminal coupled to an input terminal of the output buffer to receive an input voltage; A switching transistor having a control terminal controlled by a control signal, wherein the control signal defines at least a driving period and a high impedance period, a first terminal of the switching transistor is coupled to an output terminal of the amplifier, A second terminal of the switching transistor is coupled to an output terminal of the output buffer to provide an output voltage to a data line of a display panel; and A switching circuit having a common terminal coupled to a second input terminal of the amplifier, wherein the switching circuit electrically connects the second input terminal of the amplifier to the second input terminal of the switching transistor during the driving period Terminal or an output bonding pad, the output bonding pad is coupled to the second terminal of the switching transistor via an electrostatic discharge resistor, and the switching circuit electrically electrically connects the second input terminal of the amplifier during the high impedance period Connect to the output terminal of the amplifier. The output buffer according to item 8 of the scope of patent application, wherein the switching transistor is turned on during the driving period, and the switching transistor is turned off during the high impedance period. The output buffer according to item 8 of the scope of patent application, wherein the switching circuit includes: A first switch having a first terminal coupled to the second input terminal of the amplifier, wherein a second terminal of the first switch is coupled to the second terminal of the switching transistor or the output pad, The first switch is turned on during the driving period, and the first switch is turned off during the high impedance period; and A second switch having a first terminal coupled to the second input terminal of the amplifier, wherein a second terminal of the second switch is coupled to the output terminal of the amplifier, and during the driving period, the second The switch is off, and the second switch is on during the high impedance period.

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