TWI711308B - Output buffer - Google Patents

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TWI711308B
TWI711308B TW108106214A TW108106214A TWI711308B TW I711308 B TWI711308 B TW I711308B TW 108106214 A TW108106214 A TW 108106214A TW 108106214 A TW108106214 A TW 108106214A TW I711308 B TWI711308 B TW I711308B
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terminal
switching transistor
coupled
switch
amplifier
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TW108106214A
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TW202032971A (en
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錢佳駒
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奇景光電股份有限公司
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Abstract

An output buffer includes an amplifier, a switch transistor, and a switching circuit. The first input terminal of the amplifier receives an input voltage. The control terminal of the switch transistor is controlled by a control signal, wherein the control signal at least defines a driving period and a high impedance period. The first terminal of the switch transistor is coupled to the output terminal of the amplifier. The second terminal of the switch transistor provides an output voltage to the data line of a display panel. During the driving period, the switching circuit electrically connects the bulk of the switch transistor to the first terminal of the switch transistor or the second terminal of the switch transistor. During the high impedance period, the switching circuit electrically connects the bulk of the switch transistor to a power supply voltage.

Description

輸出緩衝器Output buffer

本發明是有關於一種顯示裝置,且特別是有關於一種輸出緩衝器。The present invention relates to a display device, and particularly relates to an output buffer.

源極驅動器被用來驅動顯示面板的多條資料線(或稱源極線)。源極驅動器配置有多個驅動通道電路,這些驅動通道電路的每一個經由不同的輸出緩衝器去驅動這些資料線中的一條對應資料線。在源極驅動器中,輸出緩衝器可以將數位類比轉換器的類比電壓增益後輸出給顯示面板的資料線。隨著顯示面板的解析度以及/或是幀率(frame rate)越來越高,對一條掃描線的充電時間越來越短。為了要在短時間內對一個像素(pixel)進行驅動(充電或放電),輸出緩衝器須要足夠高的驅動能力。亦即,輸出緩衝器須要足夠高的迴轉率(slew rate)。The source driver is used to drive multiple data lines (or source lines) of the display panel. The source driver is configured with a plurality of drive channel circuits, and each of these drive channel circuits drives a corresponding one of the data lines through a different output buffer. In the source driver, the output buffer can gain the analog voltage of the digital-to-analog converter and output it to the data line of the display panel. As the resolution and/or frame rate of the display panel becomes higher and higher, the charging time for one scan line becomes shorter and shorter. In order to drive (charge or discharge) a pixel in a short time, the output buffer must have a sufficiently high drive capability. That is, the output buffer needs a sufficiently high slew rate.

一般而言,輸出緩衝器配置有開關電晶體。當開關電晶體為導通(turn on),輸出緩衝器可以輸出類比電壓給顯示面板的資料線,亦即此輸出緩衝器處於驅動期間。當開關電晶體為截止(turn off),輸出緩衝器便不輸出類比電壓給顯示面板的資料線,亦即此輸出緩衝器處於與高阻抗期間。習知的輸出緩衝器的開關電晶體因為基體效應(body effect)而具有不容忽視的導通電阻(Ron)。輸出緩衝器的導通電阻越大,則輸出緩衝器的迴轉率越小。Generally speaking, the output buffer is configured with switching transistors. When the switching transistor is turned on, the output buffer can output an analog voltage to the data line of the display panel, that is, the output buffer is in the driving period. When the switching transistor is turned off, the output buffer does not output analog voltage to the data line of the display panel, that is, the output buffer is in a high impedance period. The switching transistor of the conventional output buffer has an on-resistance (Ron) that cannot be ignored due to the body effect. The larger the on-resistance of the output buffer, the smaller the slew rate of the output buffer.

本發明提供一種輸出緩衝器,以降低開關電晶體的基體效應(body effect)。The present invention provides an output buffer to reduce the body effect of the switching transistor.

本發明的一實施例提供一種輸出緩衝器。所述輸出緩衝器包括放大器、開關電晶體以及第一切換電路。放大器的第一輸入端耦接至輸出緩衝器的輸入端,以接收輸入電壓。開關電晶體的控制端受控於控制訊號,其中該控制訊號至少定義驅動期間與高阻抗期間。開關電晶體的第一端耦接至放大器的輸出端。開關電晶體的第二端耦接至輸出緩衝器的輸出端,以提供輸出電壓給顯示面板的資料線。第一切換電路的共同端耦接至開關電晶體的基體。在驅動期間中,第一切換電路將開關電晶體的基體電性連接至開關電晶體的第一端或開關電晶體的第二端。在高阻抗期間中,第一切換電路將開關電晶體的基體電性連接至電源電壓。An embodiment of the present invention provides an output buffer. The output buffer includes an amplifier, a switching transistor, and a first switching circuit. The first input terminal of the amplifier is coupled to the input terminal of the output buffer to receive the input voltage. The control terminal of the switching transistor is controlled by a control signal, wherein the control signal at least defines a driving period and a high impedance period. The first terminal of the switching transistor is coupled to the output terminal of the amplifier. The second terminal of the switching transistor is coupled to the output terminal of the output buffer to provide an output voltage to the data line of the display panel. The common terminal of the first switching circuit is coupled to the base of the switching transistor. During the driving period, the first switching circuit electrically connects the base of the switching transistor to the first end of the switching transistor or the second end of the switching transistor. During the high impedance period, the first switching circuit electrically connects the base of the switching transistor to the power supply voltage.

本發明的一實施例提供一種輸出緩衝器。所述輸出緩衝器包括放大器、開關電晶體以及切換電路。放大器的第一輸入端耦接至輸出緩衝器的輸入端,以接收輸入電壓。開關電晶體的控制端受控於控制訊號,其中控制訊號至少定義驅動期間與高阻抗期間。開關電晶體的第一端耦接至放大器的輸出端。開關電晶體的第二端耦接至輸出緩衝器的輸出端,以提供輸出電壓給顯示面板的資料線。切換電路的共同端耦接至放大器的第二輸入端。在驅動期間中,切換電路將放大器的第二輸入端電性連接至開關電晶體的第二端或輸出焊墊,其中該輸出焊墊經由靜電放電電阻耦接至開關電晶體的第二端。在高阻抗期間中,切換電路將放大器的第二輸入端電性連接至放大器的輸出端。An embodiment of the present invention provides an output buffer. The output buffer includes an amplifier, a switching transistor, and a switching circuit. The first input terminal of the amplifier is coupled to the input terminal of the output buffer to receive the input voltage. The control terminal of the switching transistor is controlled by a control signal, wherein the control signal at least defines a driving period and a high impedance period. The first terminal of the switching transistor is coupled to the output terminal of the amplifier. The second terminal of the switching transistor is coupled to the output terminal of the output buffer to provide an output voltage to the data line of the display panel. The common terminal of the switching circuit is coupled to the second input terminal of the amplifier. During the driving period, the switching circuit electrically connects the second input terminal of the amplifier to the second terminal of the switching transistor or the output bonding pad, wherein the output bonding pad is coupled to the second terminal of the switching transistor via an electrostatic discharge resistor. During the high impedance period, the switching circuit electrically connects the second input terminal of the amplifier to the output terminal of the amplifier.

基於上述,本發明諸實施例所述輸出緩衝器可以在高阻抗期間中將開關電晶體的基體電性連接至電源電壓,以及在驅動期間中將開關電晶體的基體電性連接至開關電晶體的第一端(或第二端)。因此,所述輸出緩衝器可以降低開關電晶體的基體效應。由於降低了基體效應,使得開關電晶體的導通電阻(Ron)可以被有效地減少,進而提升輸出緩衝器的迴轉率(slew rate)。Based on the above, the output buffers of the embodiments of the present invention can electrically connect the base of the switching transistor to the power supply voltage during the high impedance period, and electrically connect the base of the switching transistor to the switching transistor during the driving period. The first end (or second end). Therefore, the output buffer can reduce the matrix effect of the switching transistor. Due to the reduced matrix effect, the on-resistance (Ron) of the switching transistor can be effectively reduced, thereby increasing the slew rate of the output buffer.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

在本案說明書全文(包括申請專利範圍)中所使用的「耦接(或連接)」一詞可指任何直接或間接的連接手段。舉例而言,若文中描述第一裝置耦接(或連接)於第二裝置,則應該被解釋成該第一裝置可以直接連接於該第二裝置,或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。另外,凡可能之處,在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似部分。不同實施例中使用相同標號或使用相同用語的元件/構件/步驟可以相互參照相關說明。The term "coupling (or connection)" used in the full description of the case (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if the text describes that the first device is coupled (or connected) to the second device, it should be interpreted as that the first device can be directly connected to the second device, or the first device can be connected through other devices or some This kind of connection means is indirectly connected to the second device. In addition, wherever possible, elements/components/steps with the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps using the same reference numerals or using the same terms in different embodiments may refer to related descriptions.

圖1是依照本發明實施例說明一種顯示裝置100的電路方塊(circuit block)示意圖。圖1所示顯示裝置100包括閘極驅動器110、源極驅動器120以及顯示面板130。顯示面板130可以是任何類型的平面面板顯示器,例如液晶顯示面板、有機發光二極體顯示面板或是其他顯示面板。顯示面板130包含多條掃描線(或稱閘極線)、多條資料線(或稱源極線)與多個像素電路。例如圖1所示,所述多條掃描線包含n條掃描線SL_1、SL_2、…、SL_n,所述多條資料線包含m條資料線DL_1、DL_2、…、DL_m,以及所述多個像素電路包含m*n個像素電路P(1,1)、…、P(m,1)、…、P(1,n)、…、P(m,n),其中m與n可以是依照設計需求所決定的任何整數。FIG. 1 is a schematic diagram illustrating a circuit block of a display device 100 according to an embodiment of the present invention. The display device 100 shown in FIG. 1 includes a gate driver 110, a source driver 120 and a display panel 130. The display panel 130 may be any type of flat panel display, such as a liquid crystal display panel, an organic light emitting diode display panel, or other display panels. The display panel 130 includes multiple scan lines (or gate lines), multiple data lines (or source lines), and multiple pixel circuits. For example, as shown in FIG. 1, the multiple scan lines include n scan lines SL_1, SL_2,..., SL_n, and the multiple data lines include m data lines DL_1, DL_2,..., DL_m, and the multiple pixels The circuit contains m*n pixel circuits P(1,1),...,P(m,1),...,P(1,n),...,P(m,n), where m and n can be designed according to the design Any integer determined by demand.

閘極驅動器110的多個輸出端以一對一方式耦接至顯示面板130的不同掃描線。閘極驅動器110可以掃描/驅動顯示面板130的每一條掃描線。閘極驅動器110可以是任何類型的閘極驅動器。例如,依照設計需求,閘極驅動器110可以是習知的閘極驅動器或是其他閘極驅動器。The multiple output terminals of the gate driver 110 are coupled to different scan lines of the display panel 130 in a one-to-one manner. The gate driver 110 can scan/drive each scan line of the display panel 130. The gate driver 110 may be any type of gate driver. For example, the gate driver 110 may be a conventional gate driver or other gate drivers according to design requirements.

源極驅動器120具有多個驅動通道電路,例如圖1所示m個驅動通道電路121_1、121_2、…、121_m。這些驅動通道電路121_1~121_m的輸出端以一對一方式耦接至顯示面板130的不同資料線。驅動通道電路121_1~121_m可以將數位的像素資料轉換為對應的輸出電壓(像素電壓),以及將這些輸出電壓分別輸出給顯示面板130的不同資料線。配合閘極驅動器110的掃描時序,源極驅動器120可以經由資料線DL_1~DL_m將這些輸出電壓寫入顯示面板130的對應像素電路中以顯示影像。The source driver 120 has a plurality of driving channel circuits, for example, m driving channel circuits 121_1, 121_2,..., 121_m shown in FIG. 1. The output terminals of these driving channel circuits 121_1 to 121_m are coupled to different data lines of the display panel 130 in a one-to-one manner. The driving channel circuits 121_1 to 121_m can convert digital pixel data into corresponding output voltages (pixel voltages), and output these output voltages to different data lines of the display panel 130 respectively. In accordance with the scanning timing of the gate driver 110, the source driver 120 can write these output voltages into the corresponding pixel circuits of the display panel 130 through the data lines DL_1 to DL_m to display images.

圖2是依照本發明的一實施例說明圖1所示驅動通道電路121_1的電路方塊示意圖。圖1所示其他驅動通道電路121_2~121_m可以參照圖2所示驅動通道電路121_1的相關說明而類推,故不再贅述。圖2所示驅動通道電路121_1包括閂鎖器210、通道電路220以及輸出緩衝器230。閂鎖器210可以提供目前像素資料給通道電路220。閂鎖器210可以是任何類型的閂鎖器。例如,依照設計需求,閂鎖器210可以是習知的線閂鎖器或是其他閂鎖器。FIG. 2 is a circuit block diagram illustrating the driving channel circuit 121_1 shown in FIG. 1 according to an embodiment of the present invention. The other driving channel circuits 121_2 to 121_m shown in FIG. 1 can be deduced by referring to the related description of the driving channel circuit 121_1 shown in FIG. The driving channel circuit 121_1 shown in FIG. 2 includes a latch 210, a channel circuit 220, and an output buffer 230. The latch 210 can provide current pixel data to the channel circuit 220. The latch 210 may be any type of latch. For example, the latch 210 may be a conventional wire latch or other latches according to design requirements.

通道電路220可以將目前像素資料轉換為類比電壓(以下稱為輸入電壓Vi),以及將輸入電壓Vi輸出給輸出緩衝器230。於圖2所示實施例中,通道電路220可以包括準位移位器(level shifter)221以及數位類比轉換器(digital to analog converter, DAC)222。準位移位器221可以調大目前像素資料的電壓擺幅(voltage swing),而數位類比轉換器222可以將目前像素資料轉換為輸入電壓Vi。數位類比轉換器222可以將輸入電壓Vi輸出給輸出緩衝器230。在其他實施例中,準位移位器221可能會因為設計需求而被省略,使得數位類比轉換器222可以直接從閂鎖器210接收目前像素資料。The channel circuit 220 can convert the current pixel data into an analog voltage (hereinafter referred to as the input voltage Vi), and output the input voltage Vi to the output buffer 230. In the embodiment shown in FIG. 2, the channel circuit 220 may include a level shifter 221 and a digital to analog converter (DAC) 222. The level shifter 221 can increase the voltage swing of the current pixel data, and the digital-to-analog converter 222 can convert the current pixel data into the input voltage Vi. The digital-to-analog converter 222 can output the input voltage Vi to the output buffer 230. In other embodiments, the quasi-shifter 221 may be omitted due to design requirements, so that the digital-to-analog converter 222 can directly receive the current pixel data from the latch 210.

於圖2所示實施例中,輸出緩衝器230包括放大器231、開關電晶體232以及切換電路233。放大器231可以是任何類型的緩衝電路、放大電路或是增益電路。例如,依照設計需求,放大器231可以包括習知的運算放大器或是其他放大器。放大器231的第一輸入端(例如是非反相輸入端)耦接至輸出緩衝器230的輸入端(亦即耦接至數位類比轉換器222的輸出端),以接收輸入電壓Vi。放大器231的輸出端可以產生輸出電壓Vo。放大器231的輸出端耦接至放大器231的第二輸入端(例如是反相輸入端)。In the embodiment shown in FIG. 2, the output buffer 230 includes an amplifier 231, a switching transistor 232 and a switching circuit 233. The amplifier 231 may be any type of buffer circuit, amplifying circuit or gain circuit. For example, according to design requirements, the amplifier 231 may include a conventional operational amplifier or other amplifiers. The first input terminal (for example, a non-inverting input terminal) of the amplifier 231 is coupled to the input terminal of the output buffer 230 (that is, coupled to the output terminal of the digital-to-analog converter 222) to receive the input voltage Vi. The output terminal of the amplifier 231 can generate an output voltage Vo. The output terminal of the amplifier 231 is coupled to the second input terminal (for example, an inverting input terminal) of the amplifier 231.

開關電晶體232的第一端(例如源極或汲極)耦接至放大器231的輸出端。開關電晶體232的第二端(例如汲極或源極)耦接至輸出緩衝器230的輸出端,以提供輸出電壓Vo給顯示面板130的資料線DL_1。開關電晶體232的控制端受控於控制訊號Sc1,其中控制訊號Sc1至少定義了一個驅動期間與一個高阻抗期間。高阻抗期間又可稱為HI-Z期間。在驅動期間中,開關電晶體232為導通。在高阻抗期間中,開關電晶體232為截止。The first terminal (for example, the source or the drain) of the switching transistor 232 is coupled to the output terminal of the amplifier 231. The second terminal (eg, drain or source) of the switching transistor 232 is coupled to the output terminal of the output buffer 230 to provide the output voltage Vo to the data line DL_1 of the display panel 130. The control terminal of the switching transistor 232 is controlled by a control signal Sc1, where the control signal Sc1 at least defines a driving period and a high impedance period. The high impedance period can also be called the HI-Z period. During the driving period, the switching transistor 232 is turned on. During the high impedance period, the switching transistor 232 is turned off.

切換電路233的共同端耦接至開關電晶體232的基體(body,或稱bulk)。切換電路233的第一選擇端耦接至開關電晶體232的第二端。切換電路233的第二選擇端耦接至電源電壓。於圖2所示實施例中,開關電晶體232為P通道電晶體,例如是P通道金屬氧化物半導體(P-channel Metal-Oxide-Semiconductor, PMOS)電晶體。當開關電晶體232為P通道電晶體時,所述電源電壓可以是高於輸出電壓Vo的電壓擺幅(swing)的任何電壓(例如系統電壓VDDA)。The common terminal of the switching circuit 233 is coupled to the body (or bulk) of the switching transistor 232. The first selection terminal of the switching circuit 233 is coupled to the second terminal of the switching transistor 232. The second selection terminal of the switching circuit 233 is coupled to the power supply voltage. In the embodiment shown in FIG. 2, the switching transistor 232 is a P-channel transistor, such as a P-channel Metal-Oxide-Semiconductor (PMOS) transistor. When the switching transistor 232 is a P-channel transistor, the power supply voltage may be any voltage higher than the voltage swing of the output voltage Vo (for example, the system voltage VDDA).

在驅動期間中(開關電晶體232為導通的期間),切換電路233可以將開關電晶體232的基體電性連接至開關電晶體232的第二端。因此,所述輸出緩衝器230可以降低開關電晶體232的基體效應。由於降低了基體效應,使得開關電晶體232的導通電阻(Ron)可以被有效地減少,進而提升輸出緩衝器230的迴轉率(slew rate)。在高阻抗期間中(開關電晶體232為截止的期間),切換電路233可以將開關電晶體232的基體電性連接至電源電壓(例如系統電壓VDDA),以確保開關電晶體232為截止。During the driving period (a period when the switching transistor 232 is on), the switching circuit 233 can electrically connect the base of the switching transistor 232 to the second end of the switching transistor 232. Therefore, the output buffer 230 can reduce the matrix effect of the switching transistor 232. Since the matrix effect is reduced, the on-resistance (Ron) of the switching transistor 232 can be effectively reduced, thereby increasing the slew rate of the output buffer 230. During the high impedance period (the period when the switching transistor 232 is off), the switching circuit 233 can electrically connect the base of the switching transistor 232 to the power supply voltage (for example, the system voltage VDDA) to ensure that the switching transistor 232 is off.

在圖2所示實施例中,切換電路233包括開關SW1以及開關SW2。開關SW1的第一端耦接至開關電晶體232的基體。開關SW1的第二端耦接至開關電晶體232的第二端。開關SW2的第一端耦接至開關電晶體232的基體。開關SW2的第二端耦接至電源電壓(例如系統電壓VDDA)。在驅動期間中(開關電晶體232為導通的期間),開關SW1為導通,以及開關SW2為截止。在高阻抗期間中(開關電晶體232為截止的期間),開關SW1為截止,以及開關SW2為導通。In the embodiment shown in FIG. 2, the switching circuit 233 includes a switch SW1 and a switch SW2. The first end of the switch SW1 is coupled to the base of the switching transistor 232. The second end of the switch SW1 is coupled to the second end of the switching transistor 232. The first end of the switch SW2 is coupled to the base of the switching transistor 232. The second end of the switch SW2 is coupled to the power supply voltage (for example, the system voltage VDDA). In the driving period (a period when the switching transistor 232 is on), the switch SW1 is on and the switch SW2 is off. In the high impedance period (a period when the switching transistor 232 is off), the switch SW1 is off, and the switch SW2 is on.

圖3是依照本發明的另一實施例說明輸出緩衝器330的電路方塊示意圖。依照設計需求,圖3所示輸出緩衝器330可以被結合至圖2所示實施例(取代圖2所示輸出緩衝器230)。於圖3所示實施例中,輸出緩衝器330包括放大器231、開關電晶體232以及切換電路233。圖3所示放大器231、開關電晶體232以及切換電路233可以參照圖2所示放大器231、開關電晶體232以及切換電路233的相關說明來類推,故不再贅述。FIG. 3 is a circuit block diagram illustrating the output buffer 330 according to another embodiment of the invention. According to design requirements, the output buffer 330 shown in FIG. 3 can be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 3, the output buffer 330 includes an amplifier 231, a switching transistor 232 and a switching circuit 233. The amplifier 231, the switching transistor 232, and the switching circuit 233 shown in FIG. 3 can be deduced by referring to the related descriptions of the amplifier 231, the switching transistor 232, and the switching circuit 233 shown in FIG.

於圖3所示實施例中,切換電路233的第一選擇端耦接至開關電晶體232的第一端。亦即,開關SW1的第二端耦接至開關電晶體232的第一端。在驅動期間中(開關電晶體232為導通的期間),切換電路233可以將開關電晶體232的基體電性連接至開關電晶體232的第一端。因此,所述輸出緩衝器330可以降低開關電晶體232的基體效應。由於降低了基體效應,使得開關電晶體232的導通電阻(Ron)可以被有效地減少,進而提升輸出緩衝器330的迴轉率(slew rate)。在高阻抗期間中(開關電晶體232為截止的期間),切換電路233可以將開關電晶體232的基體電性連接至電源電壓(例如系統電壓VDDA),以確保開關電晶體232為截止。In the embodiment shown in FIG. 3, the first selection terminal of the switching circuit 233 is coupled to the first terminal of the switching transistor 232. That is, the second end of the switch SW1 is coupled to the first end of the switching transistor 232. During the driving period (a period when the switching transistor 232 is on), the switching circuit 233 can electrically connect the base of the switching transistor 232 to the first end of the switching transistor 232. Therefore, the output buffer 330 can reduce the matrix effect of the switching transistor 232. Since the matrix effect is reduced, the on-resistance (Ron) of the switching transistor 232 can be effectively reduced, thereby increasing the slew rate of the output buffer 330. During the high impedance period (the period when the switching transistor 232 is off), the switching circuit 233 can electrically connect the base of the switching transistor 232 to the power supply voltage (for example, the system voltage VDDA) to ensure that the switching transistor 232 is off.

圖4是依照本發明的又一實施例說明輸出緩衝器430的電路方塊示意圖。依照設計需求,圖4所示輸出緩衝器430可以被結合至圖2所示實施例(取代圖2所示輸出緩衝器230)。於圖4所示實施例中,輸出緩衝器430包括放大器231、開關電晶體234以及切換電路235。圖4所示放大器231、開關電晶體234以及切換電路235可以參照圖2所示放大器231、開關電晶體232以及切換電路233的相關說明來類推。FIG. 4 is a circuit block diagram illustrating the output buffer 430 according to another embodiment of the present invention. According to design requirements, the output buffer 430 shown in FIG. 4 can be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 4, the output buffer 430 includes an amplifier 231, a switching transistor 234, and a switching circuit 235. The amplifier 231, the switching transistor 234, and the switching circuit 235 shown in FIG. 4 can be deduced by analogy with reference to the related description of the amplifier 231, the switching transistor 232, and the switching circuit 233 shown in FIG.

於圖4所示實施例中,開關電晶體234的第一端(例如汲極或源極)耦接至放大器231的輸出端。開關電晶體234的第二端(例如源極或汲極)耦接至輸出緩衝器230的輸出端,以提供輸出電壓Vo給顯示面板130的資料線DL_1。開關電晶體234的控制端受控於控制訊號Sc2,其中控制訊號Sc2至少定義了一個驅動期間與一個高阻抗期間。高阻抗期間又可稱為HI-Z期間。在驅動期間中,開關電晶體234為導通。在高阻抗期間中,開關電晶體234為截止。In the embodiment shown in FIG. 4, the first terminal (for example, the drain or the source) of the switching transistor 234 is coupled to the output terminal of the amplifier 231. The second terminal (for example, the source or the drain) of the switching transistor 234 is coupled to the output terminal of the output buffer 230 to provide the output voltage Vo to the data line DL_1 of the display panel 130. The control terminal of the switching transistor 234 is controlled by the control signal Sc2, where the control signal Sc2 at least defines a driving period and a high impedance period. The high impedance period can also be called the HI-Z period. During the driving period, the switching transistor 234 is turned on. During the high impedance period, the switching transistor 234 is turned off.

切換電路235的共同端耦接至開關電晶體234的基體。切換電路235的第一選擇端耦接至開關電晶體234的第二端。切換電路235的第二選擇端耦接至電源電壓。於圖4所示實施例中,開關電晶體234為N通道電晶體,例如是N通道金屬氧化物半導體(N-channel Metal-Oxide-Semiconductor, NMOS)電晶體。當開關電晶體234為N通道電晶體時,所述電源電壓可以是低於輸出電壓Vo的電壓擺幅的任何電壓(例如參考電壓VSSA,或是接地電壓)。The common terminal of the switching circuit 235 is coupled to the base of the switching transistor 234. The first selection terminal of the switching circuit 235 is coupled to the second terminal of the switching transistor 234. The second selection terminal of the switching circuit 235 is coupled to the power supply voltage. In the embodiment shown in FIG. 4, the switching transistor 234 is an N-channel transistor, such as an N-channel Metal-Oxide-Semiconductor (NMOS) transistor. When the switching transistor 234 is an N-channel transistor, the power supply voltage may be any voltage lower than the voltage swing of the output voltage Vo (for example, the reference voltage VSSA, or the ground voltage).

在驅動期間中(開關電晶體234為導通的期間),切換電路235可以將開關電晶體234的基體電性連接至開關電晶體234的第二端。因此,所述輸出緩衝器430可以降低開關電晶體234的基體效應。由於降低了基體效應,使得開關電晶體234的導通電阻(Ron)可以被有效地減少,進而提升輸出緩衝器430的迴轉率(slew rate)。在高阻抗期間中(開關電晶體234為截止的期間),切換電路235可以將開關電晶體234的基體電性連接至電源電壓(例如參考電壓VSSA),以確保開關電晶體234為截止。During the driving period (a period when the switching transistor 234 is on), the switching circuit 235 can electrically connect the base of the switching transistor 234 to the second end of the switching transistor 234. Therefore, the output buffer 430 can reduce the matrix effect of the switching transistor 234. Since the matrix effect is reduced, the on-resistance (Ron) of the switching transistor 234 can be effectively reduced, thereby increasing the slew rate of the output buffer 430. During the high impedance period (the period when the switching transistor 234 is off), the switching circuit 235 can electrically connect the base of the switching transistor 234 to the power supply voltage (for example, the reference voltage VSSA) to ensure that the switching transistor 234 is off.

在圖4所示實施例中,切換電路235包括開關SW3以及開關SW4。開關SW3的第一端耦接至開關電晶體234的基體。開關SW3的第二端耦接至開關電晶體234的第二端。開關SW4的第一端耦接至開關電晶體234的基體。開關SW4的第二端耦接至電源電壓(例如參考電壓VSSA)。在驅動期間中(開關電晶體234為導通的期間),開關SW3為導通,以及開關SW4為截止。在高阻抗期間中(開關電晶體234為截止的期間),開關SW3為截止,以及開關SW4為導通。In the embodiment shown in FIG. 4, the switching circuit 235 includes a switch SW3 and a switch SW4. The first end of the switch SW3 is coupled to the base of the switching transistor 234. The second end of the switch SW3 is coupled to the second end of the switching transistor 234. The first end of the switch SW4 is coupled to the base of the switching transistor 234. The second end of the switch SW4 is coupled to the power supply voltage (for example, the reference voltage VSSA). During the driving period (a period during which the switching transistor 234 is on), the switch SW3 is on and the switch SW4 is off. In the high impedance period (a period in which the switching transistor 234 is off), the switch SW3 is off, and the switch SW4 is on.

圖5是依照本發明的另一實施例說明輸出緩衝器530的電路方塊示意圖。依照設計需求,圖5所示輸出緩衝器530可以被結合至圖2所示實施例(取代圖2所示輸出緩衝器230)。於圖5所示實施例中,輸出緩衝器530包括放大器231、開關電晶體234以及切換電路235。圖5所示放大器231、開關電晶體234以及切換電路235可以參照圖4所示放大器231、開關電晶體234以及切換電路235的相關說明來類推,故不再贅述。FIG. 5 is a circuit block diagram illustrating the output buffer 530 according to another embodiment of the invention. According to design requirements, the output buffer 530 shown in FIG. 5 may be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 5, the output buffer 530 includes an amplifier 231, a switching transistor 234, and a switching circuit 235. The amplifier 231, the switching transistor 234, and the switching circuit 235 shown in FIG. 5 can be deduced by analogy with reference to the related description of the amplifier 231, the switching transistor 234, and the switching circuit 235 shown in FIG.

於圖5所示實施例中,切換電路235的第一選擇端耦接至開關電晶體234的第一端。亦即,開關SW3的第二端耦接至開關電晶體234的第一端。在驅動期間中(開關電晶體234為導通的期間),切換電路235可以將開關電晶體234的基體電性連接至開關電晶體234的第一端。因此,所述輸出緩衝器530可以降低開關電晶體234的基體效應。由於降低了基體效應,使得開關電晶體234的導通電阻(Ron)可以被有效地減少,進而提升輸出緩衝器530的迴轉率(slew rate)。在高阻抗期間中(開關電晶體234為截止的期間),切換電路235可以將開關電晶體234的基體電性連接至電源電壓(例如參考電壓VSSA),以確保開關電晶體234為截止。In the embodiment shown in FIG. 5, the first selection terminal of the switching circuit 235 is coupled to the first terminal of the switching transistor 234. That is, the second terminal of the switch SW3 is coupled to the first terminal of the switching transistor 234. During the driving period (a period when the switching transistor 234 is on), the switching circuit 235 can electrically connect the base of the switching transistor 234 to the first end of the switching transistor 234. Therefore, the output buffer 530 can reduce the matrix effect of the switching transistor 234. Since the matrix effect is reduced, the on-resistance (Ron) of the switching transistor 234 can be effectively reduced, thereby increasing the slew rate of the output buffer 530. During the high impedance period (the period when the switching transistor 234 is off), the switching circuit 235 can electrically connect the base of the switching transistor 234 to the power supply voltage (for example, the reference voltage VSSA) to ensure that the switching transistor 234 is off.

圖6是依照本發明的再一實施例說明輸出緩衝器630的電路方塊示意圖。依照設計需求,圖6所示輸出緩衝器630可以被結合至圖2所示實施例(取代圖2所示輸出緩衝器230)。於圖6所示實施例中,輸出緩衝器630包括放大器231、開關電晶體236以及切換電路237。圖6所示放大器231可以參照圖2所示放大器231的相關說明。圖6所示開關電晶體236可以參照圖2或圖3所示開關電晶體232以及切換電路233的相關說明來類推,或者圖6所示開關電晶體236可以參照圖4或圖5所示開關電晶體234以及切換電路235的相關說明來類推,故不再贅述。在其他實施例中,依照設計需求,圖6所示開關電晶體236可以是任何開關元件/電路,例如習知的開關電晶體或是其他開關元件。FIG. 6 is a circuit block diagram illustrating the output buffer 630 according to still another embodiment of the present invention. According to design requirements, the output buffer 630 shown in FIG. 6 can be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 6, the output buffer 630 includes an amplifier 231, a switching transistor 236 and a switching circuit 237. The amplifier 231 shown in FIG. 6 can refer to the related description of the amplifier 231 shown in FIG. 2. The switching transistor 236 shown in FIG. 6 can refer to the related descriptions of the switching transistor 232 and the switching circuit 233 shown in FIG. 2 or FIG. 3, or the switching transistor 236 shown in FIG. 6 may refer to the switch shown in FIG. 4 or FIG. The related descriptions of the transistor 234 and the switching circuit 235 are analogized, so they will not be repeated. In other embodiments, according to design requirements, the switching transistor 236 shown in FIG. 6 may be any switching element/circuit, such as a conventional switching transistor or other switching elements.

開關電晶體236的第一端耦接至放大器231的輸出端。開關電晶體236的第二端經由靜電放電電阻ESDR耦接至輸出焊墊240。當開關電晶體236為導通時,放大器231的輸出電壓Vo可以經由開關電晶體236、靜電放電電阻ESDR、輸出焊墊240而被傳送至資料線DL_1。The first terminal of the switching transistor 236 is coupled to the output terminal of the amplifier 231. The second end of the switching transistor 236 is coupled to the output pad 240 via the electrostatic discharge resistor ESDR. When the switching transistor 236 is turned on, the output voltage Vo of the amplifier 231 can be transmitted to the data line DL_1 via the switching transistor 236, the electrostatic discharge resistor ESDR, and the output pad 240.

圖6所示切換電路237的共同端耦接至放大器231的第二輸入端。切換電路237的第一選擇端耦接至開關電晶體236的第二端。切換電路237的第二選擇端耦接至放大器231的輸出端。在驅動期間中(開關電晶體236為導通的期間),切換電路237將放大器231的第二輸入端電性連接至開關電晶體236的第二端。在高阻抗期間中(開關電晶體236為截止的期間),切換電路237將放大器231的第二輸入端電性連接至放大器231的輸出端。The common terminal of the switching circuit 237 shown in FIG. 6 is coupled to the second input terminal of the amplifier 231. The first selection terminal of the switching circuit 237 is coupled to the second terminal of the switching transistor 236. The second selection terminal of the switching circuit 237 is coupled to the output terminal of the amplifier 231. During the driving period (a period when the switching transistor 236 is on), the switching circuit 237 electrically connects the second input terminal of the amplifier 231 to the second terminal of the switching transistor 236. During the high impedance period (a period when the switching transistor 236 is off), the switching circuit 237 electrically connects the second input terminal of the amplifier 231 to the output terminal of the amplifier 231.

在圖6所示實施例中,切換電路237包括開關SW5以及開關SW6。開關SW5的第一端耦接至放大器231的第二輸入端。開關SW5的第二端耦接至開關電晶體236的第二端。開關SW6的第一端耦接至放大器231的第二輸入端。開關SW6的第二端耦接至放大器231的輸出端。在驅動期間中(開關電晶體236為導通的期間),開關SW5為導通,以及開關SW6為截止。在高阻抗期間中(開關電晶體236為截止的期間),開關SW5為截止,以及開關SW6為導通。In the embodiment shown in FIG. 6, the switching circuit 237 includes a switch SW5 and a switch SW6. The first terminal of the switch SW5 is coupled to the second input terminal of the amplifier 231. The second end of the switch SW5 is coupled to the second end of the switching transistor 236. The first terminal of the switch SW6 is coupled to the second input terminal of the amplifier 231. The second terminal of the switch SW6 is coupled to the output terminal of the amplifier 231. During the driving period (a period during which the switching transistor 236 is on), the switch SW5 is on and the switch SW6 is off. In the high impedance period (a period in which the switching transistor 236 is off), the switch SW5 is off, and the switch SW6 is on.

圖7是依照本發明的更一實施例說明輸出緩衝器730的電路方塊示意圖。依照設計需求,圖7所示輸出緩衝器730可以被結合至圖2所示實施例(取代圖2所示輸出緩衝器230)。於圖7所示實施例中,輸出緩衝器730包括放大器231、開關電晶體236以及切換電路237。圖7所示放大器231、開關電晶體236以及切換電路237可以參照圖6所示放大器231、開關電晶體236以及切換電路237的相關說明來類推,故不再贅述。FIG. 7 is a circuit block diagram illustrating the output buffer 730 according to another embodiment of the present invention. According to design requirements, the output buffer 730 shown in FIG. 7 can be combined with the embodiment shown in FIG. 2 (instead of the output buffer 230 shown in FIG. 2). In the embodiment shown in FIG. 7, the output buffer 730 includes an amplifier 231, a switching transistor 236 and a switching circuit 237. The amplifier 231, the switching transistor 236, and the switching circuit 237 shown in FIG. 7 can be deduced by referring to the related descriptions of the amplifier 231, the switching transistor 236, and the switching circuit 237 shown in FIG.

於圖7所示實施例中,切換電路237的第一選擇端經由靜電放電電阻ESDR’耦接至輸出焊墊240。亦即,開關SW5的第二端耦接至輸出焊墊240。輸出焊墊240經由靜電放電電阻ESDR耦接至開關電晶體236的第二端。在驅動期間中(開關電晶體236為導通的期間),切換電路237可以將放大器231的第二輸入端電性連接至焊墊240。在高阻抗期間中(開關電晶體236為截止的期間),切換電路237可以將放大器231的第二輸入端電性連接至放大器231的輸出端。In the embodiment shown in FIG. 7, the first selection terminal of the switching circuit 237 is coupled to the output pad 240 via the electrostatic discharge resistor ESDR'. That is, the second end of the switch SW5 is coupled to the output pad 240. The output pad 240 is coupled to the second end of the switching transistor 236 via the electrostatic discharge resistor ESDR. During the driving period (a period during which the switching transistor 236 is turned on), the switching circuit 237 can electrically connect the second input terminal of the amplifier 231 to the bonding pad 240. During the high impedance period (a period when the switching transistor 236 is off), the switching circuit 237 can electrically connect the second input terminal of the amplifier 231 to the output terminal of the amplifier 231.

綜上所述,本發明諸實施例所述輸出緩衝器可以在高阻抗期間中將開關電晶體的基體電性連接至電源電壓,以及在驅動期間中將開關電晶體的基體電性連接至開關電晶體的第一端(或第二端)。因此,所述輸出緩衝器可以降低開關電晶體的基體效應。由於降低了基體效應,使得開關電晶體的導通電阻(Ron)可以被有效地減少,進而提升輸出緩衝器的迴轉率(slew rate)。In summary, the output buffers described in the embodiments of the present invention can electrically connect the base of the switching transistor to the power supply voltage during the high impedance period, and electrically connect the base of the switching transistor to the switch during the driving period. The first end (or second end) of the transistor. Therefore, the output buffer can reduce the matrix effect of the switching transistor. Due to the reduced matrix effect, the on-resistance (Ron) of the switching transistor can be effectively reduced, thereby increasing the slew rate of the output buffer.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100:顯示裝置 110:閘極驅動器 120:源極驅動器 121_1、121_2、121_m:驅動通道電路 130:顯示面板 210:閂鎖器 220:通道電路 221:準位移位器 222:數位類比轉換器 230、330、430、530、630、730:輸出緩衝器 231:放大器 232、234、236:開關電晶體 233、235、237:切換電路 240:輸出焊墊 DL_1、DL_2、DL_m:資料線 ESDR、ESDR’:靜電放電電阻 P(1,1)、P(m,1)、P(1,n)、P(m,n):像素電路 Sc1、Sc2:控制訊號 SL_1、SL_2、SL_n:掃描線 SW1、SW2、SW3、SW4、SW5、SW6:開關 VDDA:系統電壓 Vi:輸入電壓 Vo:輸出電壓 VSSA:參考電壓 100: display device 110: Gate driver 120: source driver 121_1, 121_2, 121_m: drive channel circuit 130: display panel 210: Latch 220: Channel circuit 221: Quasi-shifter 222: Digital to Analog Converter 230, 330, 430, 530, 630, 730: output buffer 231: Amplifier 232, 234, 236: switching transistor 233, 235, 237: switching circuit 240: Output pad DL_1, DL_2, DL_m: data line ESDR, ESDR’: Electrostatic discharge resistance P(1,1), P(m,1), P(1,n), P(m,n): pixel circuit Sc1, Sc2: control signal SL_1, SL_2, SL_n: scan line SW1, SW2, SW3, SW4, SW5, SW6: switches VDDA: system voltage Vi: input voltage Vo: output voltage VSSA: Reference voltage

圖1是依照本發明實施例說明一種顯示裝置的電路方塊(circuit block)示意圖。 圖2是依照本發明的一實施例說明圖1所示驅動通道電路的電路方塊示意圖。 圖3是依照本發明的另一實施例說明輸出緩衝器的電路方塊示意圖。 圖4是依照本發明的又一實施例說明輸出緩衝器的電路方塊示意圖。 圖5是依照本發明的另一實施例說明輸出緩衝器的電路方塊示意圖。 圖6是依照本發明的再一實施例說明輸出緩衝器的電路方塊示意圖。 圖7是依照本發明的更一實施例說明輸出緩衝器的電路方塊示意圖。 FIG. 1 is a schematic diagram illustrating a circuit block of a display device according to an embodiment of the present invention. FIG. 2 is a circuit block diagram illustrating the driving channel circuit shown in FIG. 1 according to an embodiment of the present invention. FIG. 3 is a schematic block diagram illustrating the circuit of the output buffer according to another embodiment of the present invention. FIG. 4 is a block diagram illustrating the circuit block diagram of the output buffer according to another embodiment of the present invention. FIG. 5 is a circuit block diagram illustrating the output buffer according to another embodiment of the invention. FIG. 6 is a circuit block diagram illustrating the output buffer according to still another embodiment of the present invention. FIG. 7 is a circuit block diagram illustrating the output buffer according to a further embodiment of the invention.

121_1:驅動通道電路 210:閂鎖器 220:通道電路 221:準位移位器 222:數位類比轉換器 230:輸出緩衝器 231:放大器 232:開關電晶體 233:切換電路 DL_1:資料線 Sc1:控制訊號 SW1、SW2:開關 VDDA:系統電壓 Vi:輸入電壓 Vo:輸出電壓 121_1: drive channel circuit 210: Latch 220: Channel circuit 221: Quasi-shifter 222: Digital to Analog Converter 230: output buffer 231: Amplifier 232: Switching transistor 233: Switching circuit DL_1: Data line Sc1: control signal SW1, SW2: switch VDDA: system voltage Vi: input voltage Vo: output voltage

Claims (10)

一種輸出緩衝器,包括: 一放大器,具有一第一輸入端耦接至該輸出緩衝器的一輸入端以接收一輸入電壓; 一開關電晶體,具有一控制端受控於一控制訊號,其中該控制訊號至少定義一驅動期間與一高阻抗期間,該開關電晶體的一第一端耦接至該放大器的一輸出端,該開關電晶體的一第二端耦接至該輸出緩衝器的一輸出端以提供一輸出電壓給一顯示面板的一資料線;以及 一第一切換電路,具有一共同端耦接至該開關電晶體的一基體,其中在該驅動期間中該第一切換電路將該開關電晶體的該基體電性連接至該開關電晶體的該第一端或該開關電晶體的該第二端,以及在該高阻抗期間中該第一切換電路將該開關電晶體的該基體電性連接至一電源電壓。 An output buffer, including: An amplifier having a first input terminal coupled to an input terminal of the output buffer to receive an input voltage; A switching transistor having a control terminal controlled by a control signal, wherein the control signal defines at least a driving period and a high impedance period, a first terminal of the switching transistor is coupled to an output terminal of the amplifier, A second terminal of the switching transistor is coupled to an output terminal of the output buffer to provide an output voltage to a data line of a display panel; and A first switching circuit having a common terminal coupled to a substrate of the switching transistor, wherein the first switching circuit electrically connects the substrate of the switching transistor to the substrate of the switching transistor during the driving period The first terminal or the second terminal of the switching transistor, and the first switching circuit electrically connects the base of the switching transistor to a power supply voltage during the high impedance period. 如申請專利範圍第1項所述的輸出緩衝器,其中在該驅動期間中該開關電晶體為導通,以及在該高阻抗期間中該開關電晶體為截止。The output buffer according to claim 1, wherein the switching transistor is on during the driving period, and the switching transistor is off during the high impedance period. 如申請專利範圍第1項所述的輸出緩衝器,其中, 當該開關電晶體為一P通道電晶體時,該電源電壓為高於該輸出電壓的一電壓擺幅的一系統電壓;以及 當該開關電晶體為一N通道電晶體時,該電源電壓為低於該輸出電壓的該電壓擺幅的一參考電壓。 The output buffer as described in item 1 of the scope of patent application, wherein: When the switching transistor is a P-channel transistor, the power supply voltage is a system voltage higher than a voltage swing of the output voltage; and When the switching transistor is an N-channel transistor, the power supply voltage is a reference voltage lower than the voltage swing of the output voltage. 如申請專利範圍第1項所述的輸出緩衝器,其中該第一切換電路包括: 一第一開關,具有一第一端耦接至該開關電晶體的該基體,其中該第一開關的一第二端耦接至該開關電晶體的該第一端或該開關電晶體的該第二端,在該驅動期間中該第一開關為導通,以及在該高阻抗期間中該第一開關為截止;以及 一第二開關,具有一第一端耦接至該開關電晶體的該基體,其中該第二開關的一第二端耦接至該電源電壓,在該驅動期間中該第二開關為截止,以及在該高阻抗期間中該第二開關為導通。 According to the output buffer described in item 1 of the scope of patent application, the first switching circuit includes: A first switch having a first terminal coupled to the base body of the switching transistor, wherein a second terminal of the first switch is coupled to the first terminal of the switching transistor or the switching transistor At the second end, the first switch is turned on during the driving period, and the first switch is turned off during the high impedance period; and A second switch having a first terminal coupled to the base body of the switching transistor, wherein a second terminal of the second switch is coupled to the power supply voltage, and the second switch is turned off during the driving period, And the second switch is turned on during the high impedance period. 如申請專利範圍第1項所述的輸出緩衝器,其中該放大器的該輸出端耦接至該放大器的一第二輸入端。The output buffer according to the first item of the scope of patent application, wherein the output terminal of the amplifier is coupled to a second input terminal of the amplifier. 如申請專利範圍第1項所述的輸出緩衝器,更包括: 一第二切換電路,具有一共同端耦接至該放大器的一第二輸入端,其中在該驅動期間中該第二切換電路將該放大器的該第二輸入端電性連接至該開關電晶體的該第二端或一輸出焊墊,該輸出焊墊經由一靜電放電電阻耦接至該開關電晶體的該第二端,以及在該高阻抗期間中該第二切換電路將該放大器的該第二輸入端電性連接至該放大器的該輸出端。 The output buffer described in item 1 of the scope of patent application further includes: A second switching circuit having a common terminal coupled to a second input terminal of the amplifier, wherein the second switching circuit electrically connects the second input terminal of the amplifier to the switching transistor during the driving period The second end of the output pad or an output pad, the output pad is coupled to the second end of the switching transistor via an electrostatic discharge resistor, and during the high impedance period the second switching circuit of the amplifier The second input terminal is electrically connected to the output terminal of the amplifier. 如申請專利範圍第6項所述的輸出緩衝器,其中該第二切換電路包括: 一第一開關,具有一第一端耦接至該放大器的該第二輸入端,其中該第一開關的一第二端耦接至該開關電晶體的該第二端或該輸出焊墊,在該驅動期間中該第一開關為導通,以及在該高阻抗期間中該第一開關為截止;以及 一第二開關,具有一第一端耦接至該放大器的該第二輸入端,其中該第二開關的一第二端耦接至該放大器的該輸出端,在該驅動期間中該第二開關為截止,以及在該高阻抗期間中該第二開關為導通。 According to the output buffer described in item 6 of the scope of patent application, the second switching circuit includes: A first switch having a first terminal coupled to the second input terminal of the amplifier, wherein a second terminal of the first switch is coupled to the second terminal of the switching transistor or the output pad, The first switch is turned on during the driving period, and the first switch is turned off during the high impedance period; and A second switch having a first terminal coupled to the second input terminal of the amplifier, wherein a second terminal of the second switch is coupled to the output terminal of the amplifier, and during the driving period, the second The switch is off, and the second switch is on during the high impedance period. 一種輸出緩衝器,包括: 一放大器,具有一第一輸入端耦接至該輸出緩衝器的一輸入端以接收一輸入電壓; 一開關電晶體,具有一控制端受控於一控制訊號,其中該控制訊號至少定義一驅動期間與一高阻抗期間,該開關電晶體的一第一端耦接至該放大器的一輸出端,該開關電晶體的一第二端耦接至該輸出緩衝器的一輸出端以提供一輸出電壓給一顯示面板的一資料線;以及 一切換電路,具有一共同端耦接至該放大器的一第二輸入端,其中在該驅動期間中該切換電路將該放大器的該第二輸入端電性連接至該開關電晶體的該第二端或一輸出焊墊,該輸出焊墊經由一靜電放電電阻耦接至該開關電晶體的該第二端,以及在該高阻抗期間中該切換電路將該放大器的該第二輸入端電性連接至該放大器的該輸出端。 An output buffer, including: An amplifier having a first input terminal coupled to an input terminal of the output buffer to receive an input voltage; A switching transistor having a control terminal controlled by a control signal, wherein the control signal defines at least a driving period and a high impedance period, a first terminal of the switching transistor is coupled to an output terminal of the amplifier, A second terminal of the switching transistor is coupled to an output terminal of the output buffer to provide an output voltage to a data line of a display panel; and A switching circuit having a common terminal coupled to a second input terminal of the amplifier, wherein the switching circuit electrically connects the second input terminal of the amplifier to the second input terminal of the switching transistor during the driving period Terminal or an output bonding pad, the output bonding pad is coupled to the second terminal of the switching transistor via an electrostatic discharge resistor, and the switching circuit electrically electrically connects the second input terminal of the amplifier during the high impedance period Connect to the output terminal of the amplifier. 如申請專利範圍第8項所述的輸出緩衝器,其中在該驅動期間中該開關電晶體為導通,以及在該高阻抗期間中該開關電晶體為截止。The output buffer according to item 8 of the scope of patent application, wherein the switching transistor is turned on during the driving period, and the switching transistor is turned off during the high impedance period. 如申請專利範圍第8項所述的輸出緩衝器,其中該切換電路包括: 一第一開關,具有一第一端耦接至該放大器的該第二輸入端,其中該第一開關的一第二端耦接至該開關電晶體的該第二端或該輸出焊墊,在該驅動期間中該第一開關為導通,以及在該高阻抗期間中該第一開關為截止;以及 一第二開關,具有一第一端耦接至該放大器的該第二輸入端,其中該第二開關的一第二端耦接至該放大器的該輸出端,在該驅動期間中該第二開關為截止,以及在該高阻抗期間中該第二開關為導通。 The output buffer according to item 8 of the scope of patent application, wherein the switching circuit includes: A first switch having a first terminal coupled to the second input terminal of the amplifier, wherein a second terminal of the first switch is coupled to the second terminal of the switching transistor or the output pad, The first switch is turned on during the driving period, and the first switch is turned off during the high impedance period; and A second switch having a first terminal coupled to the second input terminal of the amplifier, wherein a second terminal of the second switch is coupled to the output terminal of the amplifier, and during the driving period, the second The switch is off, and the second switch is on during the high impedance period.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200620229A (en) * 2004-12-09 2006-06-16 Samsung Electronics Co Ltd Output buffer of a source driver in a liquid crystal display having a high slew rate and a method of controlling the output buffer
TW201543454A (en) * 2014-05-14 2015-11-16 Himax Tech Ltd Output buffer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200620229A (en) * 2004-12-09 2006-06-16 Samsung Electronics Co Ltd Output buffer of a source driver in a liquid crystal display having a high slew rate and a method of controlling the output buffer
US20110063200A1 (en) * 2004-12-09 2011-03-17 Chang-Ho An Output buffer of a source driver in a liquid crystal display having a high slew rate and a method of controlling the output buffer
TW201543454A (en) * 2014-05-14 2015-11-16 Himax Tech Ltd Output buffer

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