JP6288225B2 - Charge pump - Google Patents

Description

  The present invention relates to a charge pump that performs a boosting operation by transferring charge between capacitors via a field effect transistor.

  ON / OFF of a plurality of transfer metal-oxide-semiconductor field effect transistors (hereinafter referred to as MOSFET; Metal Oxide Semiconductor Field Effect Transistor or simply referred to as a transistor) connected in series between an input node and an output node. By performing OFF switching in synchronization with the clock, various charge pumps are used to transfer charges between a plurality of capacitors using the plurality of transfer transistors and generate an output voltage as a boost result at an output node. Is provided. As a charge pump of this type, when trying to construct a high output voltage, a level shifter that generates a high voltage is used as a means for generating a gate voltage for controlling ON / OFF of the transfer transistor. There is a need to. Therefore, in Patent Document 1, in order to turn off the transfer transistor to which the gate voltage is supplied, the one that outputs the voltage of the node on the output node side as the gate voltage among the nodes on both sides of the transfer transistor is adopted. A charge pump is proposed. In Patent Document 1, the gate voltage output for turning on the transfer transistor to which the gate voltage is supplied is changed according to the clock, and an excessive voltage is applied to the gate oxide film of the transfer transistor. A technique for preventing this is disclosed.

JP 2002-305881 A

  According to the technique disclosed in Patent Document 1 described above, it is possible to prevent an excessive voltage from being applied to the gate oxide film of the transfer transistor. However, since it is necessary to apply a high power supply voltage to the level shifter that supplies the gate voltage to the transfer transistor, a large voltage is applied to the gate oxide film of the transistor that constitutes the level shifter. For this reason, it is necessary to use a high-breakdown-voltage transistor to configure the charge pump, resulting in high costs.

  The present invention has been made in view of the circumstances described above, and an object of the invention is to provide a charge pump that can be configured by a low breakdown voltage transistor.

In order to solve the above-described problem, a charge pump according to the present invention includes an input node to which an input voltage to be boosted is applied, an output node that generates an output voltage that is a boost result, the input node, and the output node. A plurality of transfer MOSFETs connected in series between each other, a first electrode and a second electrode, and a transfer destination node which is a node on the output node side among nodes on both sides of the transfer MOSFET and a capacitor in which the first electrode is electrically connected, are electrically connected to the gate of one of the transfer MOSFET of the prior SL plurality of transfer MOSFET, to switch the one of the transfer MOSFET to oN / OFF A level shifter that outputs a gate voltage to the first transfer MOSFE and an even-numbered transfer MOSFE counted from the input node among the plurality of transfer MOSFETs In the first and second controls, the first control for turning on only the first control and the second control for turning on only the odd-numbered transfer MOSFETs counted from the input node are alternately repeated. The second electrode of the capacitor electrically connected to the node on the output node side of the transfer MOSFET to be turned on among the transfer MOSFETs is electrically connected to the first reference voltage source, and the input node side Switching control means for electrically connecting the second electrode of the capacitor having the first electrode connected to the node of the first reference voltage source to a second reference voltage source that generates a voltage different from the first reference voltage source; The level shifter includes: a first conductivity type first MOSFET whose source is electrically connected to the transfer destination node; a source electrically connected to the transfer destination node; Serial to the drain of the first MOSFET is electrically connected to a first conductivity type second MOSFET of the drain is electrically connected to the gate of said first MOSFET, the source is the first reference voltage A third MOSFET of the second conductivity type electrically connected to the source, and a fourth MOSFET of the second conductivity type electrically connected to the first reference voltage source with the source electrically connected to the first reference voltage source, The third MOSFET and the fourth MOSFET are exclusively turned on, and as a clamp MOSFET, the source is electrically connected to the drain of the first MOSFET, and the first clamp voltage is applied to the gate. A fifth MOSFET of the first conductivity type, and a sixth of the first conductivity type in which the source is electrically connected to the drain of the second MOSFET and the first clamp voltage is applied to the gate. A second conductive layer having a source electrically connected to the drain of the third MOSFET, a drain electrically connected to the drain of the fifth MOSFET, and a second clamp voltage applied to the gate. The seventh MOSFET of the type, the source is electrically connected to the drain of the fourth MOSFET, the drain is electrically connected to the drain of the sixth MOSFET, and the second clamp voltage is applied to the gate second and a conductivity type eighth MOSFET of the first electrode and electrically connected to said first clamp voltage to the voltage of the second electrode of the capacitor to the transfer destination node to be, based on the drain voltage of the first MOSFET or the second MOSFET, this outputs the gate voltage to the gate of the one of the transfer MOSFET The features.

  According to this invention, the voltage applied to each MOSFET constituting the level shifter is suppressed to a predetermined voltage or less by the clamping MOSFET. Therefore, the MOSFET constituting the charge pump including the level shifter is constituted by the low breakdown voltage MOSFET. be able to.

In a preferred aspect, the level shifter uses the voltage of the second reference voltage source as the second clamp voltage.
According to this aspect, the source-drain voltage of the third and fourth MOSFETs can be suppressed to be equal to or lower than the voltage of the second reference voltage source.

  In a preferred embodiment, the first reference voltage source is a low potential voltage source, the second reference voltage source is a high potential voltage source, the first conductivity type is P type, and the second conductivity type is N. It is a type.

  In another preferred embodiment, the first reference voltage source is a high potential voltage source, the second reference voltage source is a low potential voltage source, the first conductivity type is N-type, and the second The conductivity type is P-type.

  In a preferred aspect, the transfer MOSFET is a P-channel MOSFET formed in an N well formed in a P-type semiconductor substrate, and the N well and the source are electrically connected, and the connection point is The transfer destination node on the output node side of the transfer MOSFET is formed.

  In another preferred embodiment, the transfer MOSFET is an N-channel MOSFET formed in a P well formed in an N-type semiconductor substrate, and the P well and the source are electrically connected. The connection point forms a transfer destination node on the output node side of the transfer MOSFET.

1 is a circuit diagram showing a configuration of a charge pump according to a first embodiment of the present invention. It is a time chart which shows the waveform of each part of the charge pump. It is a circuit diagram which shows the state in the phase A of the same charge pump, and the state in the phase B. It is a circuit diagram which shows the structure of the level shifter in the same charge pump. It is a circuit diagram which shows operation | movement of the same level shifter. It is a circuit diagram which shows the structure of the charge pump which is 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the level shifter in the same charge pump. It is a time chart which shows the waveform of each part of the charge pump. 1 is a circuit diagram illustrating a configuration of a printer drive circuit to which a charge pump according to the present invention is applied. FIG.

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a charge pump according to a first embodiment of the present invention. In FIG. 1, P-channel transistors M1, M2, and M3 are transfer MOSFETs for transferring charges between a plurality of capacitors, and are connected in series between an input node N1 and an output node N2. Here, a load and a capacitor Cb are interposed in parallel between the output node N2 and the ground which is the first reference voltage source. The input node N1 is supplied with the output voltage of the high potential voltage source VDD, which is the second reference voltage source, as the input voltage to be boosted. P-channel transistors M1, M2 and M3 are formed in three N wells (low-concentration N-type impurity regions) separately formed on a P-type semiconductor substrate. The drain of the P channel transistor M1 is electrically connected to the input node N1, and the source of the P channel transistor M1 and the N well to which the P channel transistor M1 belongs are electrically connected to the drain of the P channel transistor M2. The source of the P channel transistor M2 and the N well to which the P channel transistor M2 belongs are electrically connected to the drain of the P channel transistor M3. The source of the P channel transistor M3 and the N well to which the P channel transistor M3 belongs are electrically connected to the output node N2.

  A first electrode of the capacitor Cf1 is electrically connected to a node N12 between the P-channel transistors M1 and M2 (more specifically, a connection point between the source and N well of the P-channel transistor M1 and the drain of the P-channel transistor M2). It is connected. The first electrode of the capacitor Cf2 is electrically connected to the node 23 between the P-channel transistors M2 and M3 (more specifically, the connection point between the source and N well of the P-channel transistor M2 and the drain of the P-channel transistor M3). Connected.

  The VDD system circuit 10 and the level shifter unit 20 synchronize with the periodic clock fsw, and the even-numbered transistors (that is, the P-channel transistor M2) counted from the input node N1 among the transfer P-channel transistors M1, M2, and M3. ) That switches only the first transistor (hereinafter referred to as phase A) and the second control (hereinafter referred to as phase B) that turns on only the odd-numbered transistors counted from the input node N1 alternately. It constitutes a control means. In the phases A and B, the switching control means is a partial capacitor of the plurality of capacitors Cf1 and Cf2, and the first node is connected to the node on the output node N2 side among the nodes on both sides of the transfer transistor to be turned on. The second electrode of the capacitor to which the electrode is connected is electrically connected to the ground which is the first reference voltage source, and the second electrode of the capacitor to which the first electrode is connected to the node on the input node N1 side It is electrically connected to a high potential voltage source VDD which is a second reference voltage source.

  Hereinafter, the configuration of the switching control means will be described. The VDD circuit 10 includes a control unit 15, non-inverting buffers 11 and 13, inverters 12 and 14, an inverter including an N-channel transistor ML1 and a P-channel transistor ML2, an N-channel transistor ML3, and a P-channel transistor ML4. And having an inverter. A power supply voltage from the high potential voltage source VDD is supplied to each circuit constituting the VDD system circuit 10.

  The control unit 15 outputs a signal A having the same logic as that of the clock fsw and a signal B obtained by logically inverting the clock fsw. The non-inverting buffer 11 supplies the signal A to the gate of the N-channel transistor ML1 as it is, and the inverter 12 supplies the signal XB obtained by logically inverting the signal B to the gate of the P-channel transistor ML2. The non-inverting buffer 13 supplies the signal B to the gate of the N-channel transistor ML3 as it is, and the inverter 14 supplies the signal XA obtained by logically inverting the signal A to the gate of the P-channel transistor ML4. An inverter including the N-channel transistor ML1 and the P-channel transistor ML2 supplies the output voltage CP3 to the second electrode of the capacitor Cf2. Further, the inverter composed of the N-channel transistor ML3 and the P-channel transistor ML4 supplies the output voltage CP1 to the second electrode of the capacitor Cf1.

  The level shifter unit 20 includes level shifters S1, S2, and S3. Here, the level shifter S1 is a circuit that outputs a gate voltage H_XB1 for the P-channel transistor M1 by performing a level shift of the signal B. The level shifter S2 is a circuit that outputs a gate voltage H_XA for the P-channel transistor M2 by performing a level shift of the signal A. The level shifter S3 is a circuit that outputs a gate voltage H_XB2 for the P-channel transistor M3 by performing a level shift of the signal B.

  These level shifters S1, S2 and S3 are level shifters having the same circuit configuration. These level shifters have a high potential power supply node, a low potential power supply node (ground node), and a clamp voltage node. These level shifters output a voltage applied to the high potential power supply node when the input signal is at the L level (= 0V), and when the input signal is at the H level (= VDD), the voltage at the clamp voltage node. The voltage clamped by is output.

  In FIG. 1, the low-potential power supply nodes of the level shifters S1, S2 and S3 are not shown, but are all electrically grounded to the ground which is the first reference voltage source. In the level shifter S1, the voltage CP2 of the node N12 between the P-channel transistors M1 and M2 is applied to the high potential power supply node, and the ground (= 0 V) is applied to the clamp voltage node. Accordingly, the level shifter S1 supplies the voltage CP2 of the node N12 between the P-channel transistors M1 and M2 to the gate of the P-channel transistor M1 when the input signal B is at the L level. The level shifter S1 supplies the voltage clamped at the voltage 0V at the clamp voltage node to the gate of the P-channel transistor M1 when the input signal B is at the H level.

  In the level shifter S2, the voltage CP4 of the node N23 between the P-channel transistors M2 and M3 is applied to the high potential power supply node, and the voltage CP3 of the second electrode of the capacitor Cf2 is applied to the clamp voltage node. Therefore, the level shifter S2 supplies the voltage CP4 of the node N23 between the P channel transistors M2 and M3 to the gate of the P channel transistor M2 when the input signal A is at the L level. The level shifter S2 supplies the voltage clamped by the voltage CP3 at the clamp voltage node to the gate of the P-channel transistor M2 when the input signal A is at the L level.

In the level shifter S3, the voltage VCP of the output node N2 is applied to the high potential power supply node, and the power supply voltage from the high potential voltage source VDD is applied to the clamp voltage node. Accordingly, the level shifter S3 supplies the voltage VCP of the output node N2 to the gate of the P-channel transistor M3 when the input signal B is at the L level. The level shifter S3 supplies the voltage clamped by the voltage VDD at the clamp voltage node to the gate of the P-channel transistor M3 when the input signal B is at the H level.
The above is the configuration of the charge pump according to the present embodiment.

  FIG. 2 is a time chart showing waveforms of respective parts of the charge pump according to the present embodiment. As shown in FIG. 2, the clock fsw repeats the H level (= VDD) and the L level (= 0V) periodically and alternately. Here, when the clock fsw is at the H level (= VDD), the signal A is at the H level, the signal B is at the L level, the signal XA is at the L level, and the signal XB is at the H level, and the charge pump performs the operation in the phase A. . On the other hand, when the clock fsw is at L level (= 0V), the signal A is at L level, the signal B is at H level, the signal XA is at H level, the signal XB is at L level, and the charge pump operates in phase B.

  FIG. 3A is a circuit diagram showing the state of each part of the charge pump in phase A. FIG. 3B is a circuit diagram showing the state of each part of the charge pump in phase B.

  First, in phase B, since the signal B becomes H level (VDD), the level shifter S1 outputs a voltage clamped by the clamp voltage 0V as the gate voltage H_XB1, and turns on the P-channel transistor M1. Further, since the signal A is at the L level (0 V), the level shifter S3 outputs a voltage clamped by the clamp voltage VDD as the gate voltage H_XB2. Here, in phase B, the voltage 3VDD is output to the output node N2, as will be described later. Therefore, the P-channel transistor M3 is turned on. In phase B, since the signal A is L level and the signal XB is L level, the N-channel transistor ML1 is OFF and the P-channel transistor ML2 is ON, and the voltage CP3 of the second electrode of the capacitor Cf2 becomes VDD. Become. Since the signal A is at the L level, the level shifter S2 outputs the voltage CP4 of the node N23 between the P-channel transistors M2 and M3 as the gate voltage H_XA, and turns off the P-channel transistor M2.

  On the other hand, in phase B, since the signal B becomes H level and the signal XA becomes H level, the N-channel transistor ML3 is turned ON, the P-channel transistor ML4 is turned OFF, and the voltage CP1 of the second electrode of the capacitor Cf1 becomes 0V. Become.

  As a result, in the phase B, as shown in FIG. 3B, a current flows through the path of the input node N1 → P channel transistor M1 → capacitor Cf1 → N channel transistor ML3 → ground, and the voltage VDD is charged in the capacitor Cf1. The In the phase B, a current flows through a path of the high potential voltage source VDD → P channel transistor ML2 → capacitor Cf2 → P channel transistor M3 → output node N2, and the voltage charged in the capacitor Cf2 immediately before the phase B is reached. A voltage obtained by adding the voltage VDD is output to the output node N2.

  Next, in phase A, since the signal B becomes L level, the level shifter S1 outputs the voltage CP2 of the node N12 between the P-channel transistors M1 and M2 as the gate voltage H_XB1, and turns off the P-channel transistor M1. Further, the level shifter S3 outputs the voltage VCP of the output node N2 as the gate voltage H_XB2, and turns off the P-channel transistor M3. In phase A, since the signal A is H level and the signal XB is H level, the N-channel transistor ML1 is ON, the P-channel transistor ML2 is OFF, and the voltage CP3 of the second electrode of the capacitor Cf2 is 0V. Become. Since the signal A is at the H level, the level shifter S2 outputs the gate voltage H_XA clamped with the clamp voltage CP3 = 0V, and turns on the P-channel transistor M2.

  On the other hand, in phase A, since the signal B is L level and the signal XA is L level, the N channel transistor ML3 is OFF, the P channel transistor ML4 is ON, and the voltage CP1 of the second electrode of the capacitor Cf1 is VDD. .

  As a result, in phase A, as shown in FIG. 3A, the current flows through the path of the high potential voltage source VDD → P channel transistor ML4 → capacitor Cf1 → P channel transistor M2 → capacitor Cf2 → N channel transistor ML1 → ground. A voltage obtained by adding the voltage charged to the capacitor Cf1 and the voltage VDD immediately before phase A is output to the node N23 between the P-channel transistors M2 and M3, and this voltage is charged to the capacitor Cf2.

  Here, as described with reference to FIG. 3B, in phase B, the voltage VDD is charged in the capacitor Cf1. Accordingly, in the phase A immediately after the phase B, the voltage of the node N23 between the P-channel transistors M2 and M3 (that is, the voltage CP4 of the first electrode of the capacitor Cf2) is VDD + VDD = 2VDD.

  In phase B after phase A, a voltage obtained by adding the charging voltage of capacitor Cf2 to voltage VDD is output to node N23 between P-channel transistors M2 and M3, and this voltage is output to output node N2. Here, in phase A, the voltage 2VDD is charged in the capacitor Cf2. Therefore, in the phase B, the voltage of the node N23 between the P-channel transistors M2 and M3 (that is, the voltage CP4 of the first electrode of the capacitor Cf2) is VDD + 2VDD = 3VDD.

  FIG. 4 is a circuit diagram showing a configuration example of the level shifter S2 for supplying the gate voltage H_XA to the P-channel transistor M2. As shown in FIG. 4, the level shifter S <b> 2 includes a differential amplification unit 21 and a buffer unit 22.

  In the differential amplifying unit 21, the P-channel transistors M23 and M24 are transfer destination nodes that are nodes on the output node N2 side among the nodes on both sides of the P-channel transistor M2 (that is, the node N23 between the P-channel transistors M2 and M3). The source is electrically connected. The drain of the P-channel transistor M23 is electrically connected to the gate of the P-channel transistor M24. On the other hand, the drain of the P-channel transistor M24 is electrically connected to the gate of the P-channel transistor M23. Here, the drain voltage of the P-channel transistor M24 becomes the output signal of the differential amplifier 21. In the above configuration, the common connection point between the source of the P-channel transistor M23 and the source of the P-channel transistor M24 and the source of the P-channel transistor M30 described later is the high-potential power supply node of the level shifter S2.

  The source of the N-channel transistor M21 and the source of the N-channel transistor M22 are electrically connected to the ground that is the first reference voltage source. This ground is the low potential power supply node of the level shifter S2. A signal A is input to the gate of the N-channel transistor M21, and a signal obtained by inverting the signal A by the inverter 25 is input to the gate of the N-channel transistor M22. Accordingly, when the clock fsw is at the H level, the N-channel transistor M21 is turned on and the N-channel transistor M22 is turned off. When the clock fsw is at the L level, the N-channel transistor M21 is turned off and the N-channel transistor M22 is turned on. As described above, the N-channel transistors M21 and M22 are exclusively turned on in response to the clock fsw.

  The P-channel transistors M27 and M28 are clamping MOSFETs that clamp the level of the output signal of the differential amplifier 21 to the clamp voltage CP3 or higher. More specifically, the P-channel transistor M27 has a source connected to the drain of the P-channel transistor M23, a drain current path of the N-channel transistor M21, specifically, a drain connected to the drain of the N-channel transistor M25. The clamp voltage CP3 is applied to the gate. The P-channel transistor M28 has a source connected to the drain of the P-channel transistor M24, a drain current path of the N-channel transistor M22, specifically, a drain connected to the drain of the N-channel transistor M26, and a clamp voltage CP3. Is given to the gate. A common connection point between the gate of the P-channel transistor M27 and the gate of the N-channel transistor M28 and the source of an N-channel transistor M29 described later is a clamp voltage node of the level shifter S2.

The N-channel transistors M25 and M26 are clamping MOSFETs that clamp the drain voltages of the N-channel transistors M21 and M22 below the voltage VDD. More specifically, in the N-channel transistor M25, the drain is connected to the drain of the P-channel transistor M27, the source is connected to the drain of the N-channel transistor M21, and the voltage VDD is applied to the gate. The N-channel transistor M26 has a drain connected to the drain of the P-channel transistor M28, a source connected to the drain of the N-channel transistor M22, and a voltage VDD applied to the gate.
The above is the configuration of the differential amplifier 21.

The buffer unit 22 is a selection circuit that selects the voltage CP4 applied to the high potential power supply node or the clamp voltage CP3 applied to the clamp voltage node according to the output signal of the differential amplifier unit 21, and outputs the selected voltage CP4 as the gate voltage H_XA. . Specifically, the buffer unit 22 is an inverter that operates using a difference voltage between the voltages CP4 and CP3 as a power supply voltage, and includes a P-channel transistor M30 and an N-channel transistor M29.
The above is the configuration of the level shifter S2. The other level shifters S1 and S3 have the same configuration as the level shifter S2.

  FIG. 5A is a circuit diagram showing a state of each part of the level shifter S2 in the phase A. FIG. 5B is a circuit diagram showing the state of each part of the level shifter S2 in the phase B. Hereinafter, the operation of the level shifter S2 in the present embodiment will be described with reference to FIGS. 5 (A) and 5 (B). In the following, for the sake of simplicity, it is assumed that the threshold voltages of all P-channel transistors and all N-channel transistors constituting the level shifter S3 have the same absolute value Vth.

  As described above, in phase A, the signal A is at the H level (VDD), the voltage CP3 is 0V, and the voltage CP4 is 2VDD. In this case, since the signal A is at the H level, the N-channel transistor M21 is turned on and the N-channel transistor M22 is turned off. Then, as a result of the N channel transistor M21 that has been turned on drawing the drain current, the gate voltage of the P channel transistor M24 becomes lower than the source voltage CP4 = 2VDD, and the P channel transistor M24 is turned on. Further, as a result of the P-channel transistor M24 being turned on, the output voltage of the differential amplifying unit 21 becomes CP4 = 2VDD, and this voltage CP4 = 2VDD is applied as a gate voltage to the P-channel transistor M23, so that the P-channel transistor M23 is turned off. become.

Here, in phase A, clamp voltage CP3 = 0V is applied to the gates of P-channel transistors M27 and M28, and P-channel transistors M27 and M28 are turned on. As a result, the source voltage of the P-channel transistor M27 becomes 0V + Vth.
On the other hand, the N-channel transistors M25 and M26 are turned on because the voltage VDD is applied to the gate. The drain voltage of the N-channel transistor M21 that is ON is 0V, and the drain voltage of the N-channel transistor M22 that is OFF is the voltage VDD−Vth obtained by subtracting the voltage Vth from the gate voltage VDD for the N-channel transistor M26.

As a result of the output voltage of the differential amplifying unit 21 being 2VDD, in the buffer unit 22, the P-channel transistor M30 is turned off and the N-channel transistor M29 is turned on. As a result, the clamp voltage CP3 = 0V is selected by the N-channel transistor M29 and is output to the P-channel transistor M2 as the gate voltage H_XA. As a result, the P-channel transistor M2 is turned ON, and the voltage CP2 at the node between the P-channel transistors M1 and M2 and the voltage CP4 at the node between the P-channel transistors M2 and M3 become 2VDD.
In the phase B, the signal A becomes L level (0 V), the voltage CP3 becomes VDD, and the voltage CP4 becomes 3VDD.

  In this case, since the signal A is at the L level, the N-channel transistor M21 is turned OFF and the N-channel transistor M22 is turned ON. As a result of the N-channel transistor M22 that has been turned on drawing the drain current, the gate voltage of the P-channel transistor M23 becomes lower than the source voltage CP4 = 3VDD, and the P-channel transistor M23 is turned on. Further, as a result of the P-channel transistor M23 being turned on, the voltage CP4 = 3VDD is supplied as a gate voltage to the P-channel transistor M24, and thus the P-channel transistor M24 is turned off.

  In phase B, clamp voltage CP3 = VDD is applied to the gates of P-channel transistors M27 and M28, and P-channel transistors M27 and M28 are turned on. As a result, the source voltage of the P-channel transistor M28, that is, the output voltage of the differential amplifier 21, becomes VDD + Vth.

  On the other hand, the N-channel transistors M25 and M26 are turned on because the voltage VDD is applied to the gate. The drain voltage of the N-channel transistor M22 that is ON is 0V, and the drain voltage of the N-channel transistor M21 that is OFF is the voltage VDD−Vth obtained by subtracting the voltage Vth from the gate voltage VDD for the N-channel transistor M25.

  As a result of the output voltage of the differential amplifying unit 21 becoming VDD + Vth, in the buffer unit 22, the P-channel transistor M30 is turned on and the N-channel transistor M29 is turned off. As a result, the voltage CP4 = 3VDD is selected by the P-channel transistor M30 and is output to the P-channel transistor M2 as the gate voltage H_XA. As a result, the P-channel transistor M2 is turned OFF, the voltage CP2 at the node between the P-channel transistors M1 and M2 is VDD, and the voltage CP4 at the node between the P-channel transistors M2 and M3 is 3VDD.

  In the above operation, the clamping P-channel transistors M27 and M28 and the N-channel transistors M25 and M26 play a role of setting the voltage applied to the gate oxide films of all the transistors of the level shifter S2 to 2 VDD or less.

  If the clamping P-channel transistors M27 and M28 are not provided, the drain voltage of the P-channel transistor M24 becomes 0 V in phase B, so that a voltage of 3VDD is applied to the gate oxide films of the P-channel transistors M23, M24, and M30. Is done.

  However, in this embodiment, clamping P-channel transistors M27 and M28 are provided, and in phase B, the clamp voltage CP3 = VDD is applied to the gates of these transistors, so the drain voltage of the P-channel transistor M24 is VDD + Vth. To be clamped. For this reason, the voltage applied to the gate oxide films of the P-channel transistors M23, M24 and M30 can be 2VDD-Vth.

  If the clamping N-channel transistors M25 and M26 are not provided, the drain voltage of the N-channel transistor M21 becomes 3VDD in the phase B, so that a voltage of 3VDD is applied to the gate oxide film of the N-channel transistor M21. .

  However, in this embodiment, clamping N-channel transistors M25 and M26 are provided, and the clamp voltage VDD is applied to the gates of these transistors, so that the drain voltage of the N-channel transistor M24 is clamped to VDD + Vth. For this reason, the voltage applied to the gate oxide film of the N-channel transistor M24 can be set to VDD + Vth.

  As described above, in this embodiment, the voltage applied to the gate oxide films of all the transistors of the level shifter S2 can be set to 2 VDD or less. Therefore, the charge pump that outputs 3VDD can be configured by a transistor with a withstand voltage of 2VDD. As described above, according to the present embodiment, a process for forming a high breakdown voltage transistor is not required, so that the manufacturing cost of the semiconductor integrated circuit forming the charge pump can be reduced. In addition, according to the present embodiment, it is not necessary to develop a high voltage transistor used for the charge pump when developing the charge pump, so the charge pump development cost can be reduced and the development period can be shortened. .

Second Embodiment
FIG. 6 is a circuit diagram showing a configuration of a charge pump according to the second embodiment of the present invention. In the first embodiment, the voltage is boosted by transferring and adding a positive voltage using a plurality of P-channel transistors. In this embodiment, the voltage is transferred and added by a plurality of N-channel transistors. Boost the voltage. In FIG. 6, N-channel transistors M1 ′, M2 ′ and M3 ′ are transfer MOSFETs connected in series between an input node N1 ′ and an output node N2 ′. Here, a load and a capacitor Cb ′ are interposed in parallel between the output node N2 ′ and the ground which is the first reference voltage source. Further, the output voltage of the low potential voltage source (negative power supply) VSS, which is the second reference voltage source, is applied to the input node N1 ′ as the input voltage to be boosted. N-channel transistors M1 ′, M2 ′ and M3 ′ are formed in three P wells (low-concentration P-type impurity regions) separately formed on the N-type semiconductor substrate. The drain of the N channel transistor M1 ′ is electrically connected to the input node N1 ′, and the source and the P well of the N channel transistor M1 ′ are electrically connected to the drain of the N channel transistor M2 ′. The source and P well of the N channel transistor M2 ′ are electrically connected to the drain of the N channel transistor M3 ′. The source and the P well of the N channel transistor M3 ′ are electrically connected to the output node N2 ′.

  A first electrode of a capacitor Cf1 'is electrically connected to a node N12' between the N-channel transistors M1 'and M2'. A first electrode of a capacitor Cf2 'is electrically connected to a node N23' between the N-channel transistors M2 'and M3'.

  The VSS system circuit 10 ′ and the level shifter unit 20 ′ alternately perform the first control (phase A) and the second control (phase B) similar to those in the first embodiment in synchronization with the periodic clock fsw. The repeating switching control means is constituted. In the phases A and B, the switching control means is a partial capacitor of the plurality of capacitors Cf1 ′ and Cf2 ′, and is connected to a node on the output node N2 ′ side among nodes on both sides of the transfer transistor to be turned on. The second electrode of the capacitor to which the first electrode is connected is electrically connected to the ground which is the first reference voltage source, and the second electrode of the capacitor to which the first electrode is connected to the node on the input node N1 ′ side. The two electrodes are electrically connected to a low potential voltage source VSS which is a second reference voltage source.

  Hereinafter, the configuration of the switching control means will be described. The VSS system circuit 10 ′ includes a control unit 15 ′, non-inverting buffers 12 ′ and 14 ′, inverters 11 ′ and 13 ′, an inverter including an N-channel transistor ML1 ′ and a P-channel transistor ML2 ′, and an N-channel. And an inverter composed of a transistor ML3 ′ and a P-channel transistor ML4 ′. A power supply voltage from the low potential voltage source VSS is supplied to each circuit constituting the VSS system circuit 10 '.

  The control unit 15 ′ outputs a signal A having the same logic as that of the clock fsw and a signal B obtained by logically inverting the clock fsw. The inverter 11 ′ supplies the signal A ′ obtained by logically inverting the signal A to the gate of the N-channel transistor ML1 ′, and the non-inverting buffer 12 ′ uses the signal B as it is as the signal XB ′ as it is as the gate of the P-channel transistor ML2 ′. To supply. The inverter 13 'logically inverts the signal B and supplies it as the signal B' to the gate of the N-channel transistor ML3 '. The non-inverting buffer 14' uses the signal A as it is as the signal XA 'as the signal XA' as the P-channel transistor. Supply to the gate of ML4 ′. An inverter including the N-channel transistor ML1 'and the P-channel transistor ML2' supplies the output voltage CP3 'to the second electrode of the capacitor Cf2'. Further, the inverter composed of the N-channel transistor ML3 'and the P-channel transistor ML4' supplies the output voltage CP1 'to the second electrode of the capacitor Cf1'.

  The level shifter unit 20 'includes level shifters S1', S2 ', and S3'. Here, the level shifter S1 'is a circuit that outputs a gate voltage H_XB1' to the N-channel transistor M1 'by performing a level shift of the signal B. The level shifter S2 'is a circuit that outputs a gate voltage H_XA' to the N-channel transistor M2 'by performing a level shift of the signal A. The level shifter S3 'is a circuit that outputs a gate voltage H_XB2' to the N-channel transistor M3 'by performing a level shift of the signal B.

  These level shifters S1 ', S2' and S3 'are level shifters having the same circuit configuration. These level shifters have a high potential power supply node (ground node), a low potential power supply node, and a clamp voltage node. These level shifters output a voltage applied to the low-potential power supply node when the input signal is at the H level (= 0 V), and the voltage at the clamp voltage node when the input signal is at the L level (= VSS). The voltage clamped by is output.

  In FIG. 6, the high-potential power supply nodes of the level shifters S1 ', S2' and S3 'are not shown, but are all electrically grounded to the ground which is the first reference voltage source. Further, in the level shifter S1 ', the voltage CP2' of the node N12 'between the N-channel transistors M1' and M2 'is supplied to the low potential power supply node, and the ground (= 0V) is supplied to the clamp voltage node. Accordingly, the level shifter S1 'supplies the voltage CP2' of the node N12 'between the N-channel transistors M1' and M2 'to the gate of the N-channel transistor M1' when the input signal B is at the H level. Further, the level shifter S1 'supplies the voltage clamped by the voltage 0V at the clamp voltage node to the gate of the N-channel transistor M1' when the input signal B is at the L level.

  Further, in the level shifter S2 ′, the voltage CP4 ′ of the node N23 ′ between the N-channel transistors M2 ′ and M3 ′ is supplied to the low potential power supply node, and the voltage CP3 ′ of the second electrode of the capacitor Cf2 ′ is used as the clamp voltage node. Given. Therefore, the level shifter S2 'supplies the voltage CP4' of the node N23 'between the N-channel transistors M2' and M3 'to the gate of the N-channel transistor M2' when the input signal A is at the H level. The level shifter S2 'supplies the voltage clamped by the voltage CP3' at the clamp voltage node to the gate of the N-channel transistor M2 'when the input signal A is at the L level.

Further, in the level shifter S3 ′, the voltage VCP ′ at the output node N2 ′ is applied to the low potential power supply node, and the power supply voltage from the low potential voltage source VSS is applied to the clamp voltage node. Accordingly, the level shifter S3 ′ supplies the voltage VCP ′ at the output node N2 ′ to the gate of the N-channel transistor M3 ′ when the input signal B is at the H level. The level shifter S3 ′ supplies the voltage clamped by the voltage VSS at the clamp voltage node to the gate of the N-channel transistor M3 ′ when the input signal B is at the L level.
The above is the configuration of the charge pump according to the present embodiment.

  FIG. 7 is a circuit diagram showing a configuration example of the level shifter S2 'for supplying the gate voltage H_XA' to the N-channel transistor M2 '. As shown in FIG. 7, the level shifter S2 'includes a differential amplifying unit 21' and a buffer unit 22 '.

  In the differential amplifying unit 21 ′, the N-channel transistors M23 ′ and M24 ′ are transfer destination nodes (that is, N-channel transistors M2 ′ and M2 ′) that are nodes on the output node N2 ′ side among the nodes on both sides of the N-channel transistor M2 ′. A source is electrically connected to a node N23 ′) between M3 ′. The drain of the N channel transistor M23 'is electrically connected to the gate of the N channel transistor M24', and the drain of the N channel transistor M24 'is electrically connected to the gate of the N channel transistor M23'. Here, the drain voltage of the N-channel transistor M24 'becomes an output signal of the differential amplifier 21'. A common connection point between the source of the N-channel transistor M23 'and the source of the N-channel transistor M24' and the source of an N-channel transistor M30 'to be described later is a low potential power supply node of the level shifter S2'.

  The source of the P-channel transistor M21 'and the source of the P-channel transistor M22' are electrically connected to the ground that is the first reference voltage source. A signal A is input to the gate of the P-channel transistor M21 ', and a signal obtained by inverting the signal A by the inverter 29' is input to the gate of the P-channel transistor M22 '. Accordingly, when the clock fsw is at the L level, the P channel transistor M21 ′ is turned on and the P channel transistor M22 ′ is turned off. When the clock fsw is at the L level, the P channel transistor M21 ′ is turned off and the P channel transistor M22 ′ is turned on. It becomes. In this way, the P-channel transistors M21 'and M22' are exclusively turned on in response to the clock fsw.

  The N-channel transistors M27 'and M28' are clamping MOSFETs that clamp the level of the output signal of the differential amplifier 21 'to a clamp voltage CP3' or less. The source of the N-channel transistor M27 'is connected to the drain of the N-channel transistor M23', and the source of the N-channel transistor M28 'is connected to the drain of the N-channel transistor M24'. The clamp voltage CP3 'is applied to the gates of the N-channel transistors M27' and M28 '. A common connection point between the gate of the N-channel transistor M27 'and the gate of the N-channel transistor M28' and the source of a P-channel transistor M29 'described later is a clamp voltage node of the level shifter S2'.

  P-channel transistors M25 'and M26' are clamping MOSFETs that clamp the drain voltages of P-channel transistors M21 'and M22' to voltage VSS or higher. The source of the P-channel transistor M25 'is connected to the drain of the P-channel transistor M21', and the source of the P-channel transistor M26 'is connected to the drain of the P-channel transistor M22'. The drain of the P-channel transistor M25 'is connected to the drain of the N-channel transistor M27', and the drain of the P-channel transistor M26 'is connected to the drain of the N-channel transistor M28'. The voltage VSS is applied to the gate of the P-channel transistor M25 'and the gate of the P-channel transistor M26'. The above is the configuration of the differential amplifier 21.

  The buffer unit 22 ′ selects the voltage CP4 ′ applied to the low potential power supply node or the clamp voltage CP3 ′ applied to the clamp voltage node according to the output signal of the differential amplifier unit 21 ′, and outputs it as the gate voltage H_XA ′. This is a selection circuit. Specifically, the buffer unit 22 ′ is an inverter that operates using a voltage difference between the voltages CP 4 ′ and CP 3 ′ as a power supply voltage, and includes a P-channel transistor M 29 ′ and an N-channel transistor M 30 ′.

  The above is the configuration of the level shifter S2 '. The other level shifters S1 'and S3' have the same configuration as that of the level shifter S2 '.

  FIG. 8 is a time chart showing waveforms of respective parts of the charge pump according to the present embodiment. As shown in FIG. 8, the clock fsw repeats the H level (= 0V) and the L level (= VSS) periodically and alternately. Here, when the clock fsw is at the H level, the signal A is at the H level, the signal B is at the L level, the signal A ′ is at the L level, and the signal B ′ is at the H level, and the charge pump performs the operation in the phase B. That is, the N-channel transistor M2 'is OFF, the N-channel transistors M1' and M3 'are ON, the voltage CP1' is 0V, and the voltage CP3 'is VSS. As a result, a current flows through a path of ground → P-channel transistor ML2 ′ → capacitor Cf1 ′ → N-channel transistor M1 ′ → VSS, and the voltage VSS is charged in the capacitor Cf1 ′. Further, a current flows through the path of the output node N2 ′ → N channel transistor M3 ′ → capacitor Cf2 ′ → N channel transistor ML3 ′ → VSS, and a voltage obtained by adding the voltage VSS to the charge voltage of the capacitor Cf2 ′ is output to the output node N2 ′. Is output.

  Next, when the clock fsw is at the L level, the signal A is at the L level, the signal B is at the H level, the signal A 'is at the H level, the signal B' is at the L level, and the charge pump performs the operation in the phase A. That is, the N-channel transistor M2 'is turned on, the N-channel transistors M1' and M3 'are turned off, the voltage CP1' is VSS, and the voltage CP3 'is 0V. As a result, current flows through the path of ground → P channel transistor ML4 ′ → capacitor Cf2 ′ → N channel transistor M2 ′ → capacitor Cf1 ′ → N channel transistor ML1 ′ → VSS, and the voltage VSS is added to the charging voltage of the capacitor Cf1 ′. A voltage, that is, VSS + VSS = 2VSS is output to the node N23 ′ between the N-channel transistors M2 ′ and M3 ′, and this voltage is charged in the capacitor Cf2 ′.

  Thus, in phase A, the voltage 2VSS is charged in the capacitor Cf2 '. Therefore, in phase B after phase A, voltage 3VSS obtained by adding voltage VSS to charging voltage 2VSS of capacitor Cf2 'is output to output node N2'.

As in the first embodiment, the voltages CP3 ′ and CP4 ′ are interlocked with the voltages CP1 ′ and CP2 ′. That is, since the charging voltage of the capacitor Cf1 ′ is VSS, the voltage CP3 ′ is lower than the voltage CP1 ′ by VSS. Further, since the charging voltage of the capacitor Cf2 ′ is 2 VSS, the voltage CP4 ′ is lower than the voltage CP2 ′ by 2 VSS.
The above is the outline of the operation of the charge pump in the present embodiment.

  Next, the operation of the level shifter S2 'will be described. In the phase A, the signal A becomes L level, the voltage CP3 'becomes 0V, and the voltage CP4' becomes 2VSS. In this case, since the signal A is at the L level, the P-channel transistor M21 'is turned on and the P-channel transistor M22' is turned off. Then, as a result of the drain of the P-channel transistor M21 'that has been turned ON, the gate voltage of the N-channel transistor M24' becomes higher than the source voltage CP4 '= 2VSS, and the N-channel transistor M24' is turned ON. Further, as a result of the N-channel transistor M24 ′ being turned on, the output voltage of the differential amplifier 21 ′ becomes CP4 ′ = 2VSS, and this voltage CP4 ′ = 2VSS is applied as a gate voltage to the N-channel transistor M23 ′. The channel transistor M23 ′ is turned off.

  Here, in phase A, the clamp voltage CP3 '= 0V is applied to the gates of the N-channel transistors M27' and M28 ', and the N-channel transistors M27' and M28 'are turned ON. As a result, the source voltage of the N-channel transistor M27 'becomes 0V-Vth.

  On the other hand, the P-channel transistors M25 'and M26' are turned on because the voltage VSS is applied to the gate. The drain voltage of the P-channel transistor M21 'that is ON is 0V, and the drain voltage of the P-channel transistor M22' that is OFF is the voltage VSS + Vth obtained by adding the voltage Vth to the gate voltage VSS for the P-channel transistor M26 '.

  As a result of the output voltage of the differential amplifier 21 'being 2 VSS, in the buffer 22', the N-channel transistor M30 'is turned off and the P-channel transistor M29' is turned on. As a result, the clamp voltage CP3 '= 0V is selected by the P-channel transistor M29' and is output to the N-channel transistor M2 'as the gate voltage H_XA. As a result, the N-channel transistor M2 ′ is turned ON, and the voltage CP2 ′ of the node N12 ′ between the N-channel transistors M1 ′ and M2 ′ and the voltage CP4 ′ of the node N23 ′ between the N-channel transistors M2 ′ and M3 ′ are 2 VSS. Become.

  In the phase B, the signal A becomes H level (0 V), the voltage CP3 'becomes VSS, and the voltage CP4' becomes 3VSS. In this case, since the signal A is at the H level, the P-channel transistor M21 'is OFF and the P-channel transistor M22' is ON. Then, as a result of the P channel transistor M22 'turned on outputting the drain current, the gate voltage of the N channel transistor M23' becomes higher than the source voltage CP4 '= 3 VSS, and the N channel transistor M23' is turned on. Further, as a result of the N-channel transistor M23 'being turned on, the voltage CP4' = 3VSS is applied as a gate voltage to the N-channel transistor M24 ', so that the N-channel transistor M24' is turned off.

  In phase B, the clamp voltage CP3 '= VSS is applied to the gates of the N-channel transistors M27' and M28 ', and the N-channel transistors M27' and M28 'are turned on. As a result, the source voltage of the N-channel transistor M28 ', that is, the output voltage of the differential amplifier 21' becomes VSS-Vth.

  On the other hand, the P-channel transistors M25 'and M26' are turned on because the voltage VSS is applied to the gate. The drain voltage of the P-channel transistor M22 'that is ON is 0V, and the drain voltage of the P-channel transistor M21' that is OFF is the voltage VSS + Vth obtained by adding the voltage Vth to the gate voltage VSS for the P-channel transistor M25 '.

  As a result of the output voltage of the differential amplifier 21 'being VSS-Vth, in the buffer 22', the P-channel transistor M29 'is substantially OFF and the N-channel transistor M29' is ON. As a result, the voltage CP4 '= 3VSS is selected by the N-channel transistor M30', and is output to the N-channel transistor M2 'as the gate voltage H_XA'. As a result, the N-channel transistor M2 'is turned OFF, the voltage CP2 at the node N12' between the N-channel transistors M1 'and M2' becomes VSS, and the voltage CP4 'at the node between the N-channel transistors M2' and M3 'becomes 3VSS.

  In the above operation, the clamping N-channel transistors M27 ′ and M28 ′ and the P-channel transistors M25 ′ and M26 ′ serve to suppress the voltage applied to the gate oxide films of all the transistors of the level shifter S2 ′ within 2 VSS. Fulfill.

  If the N-channel transistors M27 ′ and M28 ′ for clamping are not provided, the drain voltage of the N-channel transistor M24 ′ becomes 0 V in the phase B. Therefore, the gate oxide films of the N-channel transistors M23 ′, M24 ′ and M30 ′ A voltage of 3 VSS is applied.

  However, in this embodiment, clamping N-channel transistors M27 ′ and M28 ′ are provided, and in phase B, the clamp voltage CP3 ′ = VSS is applied to the gates of these transistors, so that the N-channel transistor M24 ′ The drain voltage is clamped to VSS-Vth. Therefore, the voltage applied to the gate oxide films of the N-channel transistors M23 ', M24' and M30 'can be 2VSS + Vth.

  Further, if the clamping P-channel transistors M25 ′ and M26 ′ are not provided, the drain voltage of the P-channel transistor M21 ′ becomes 3 VSS in the phase B, so that the voltage of 3 VSS is applied to the gate oxide film of the P-channel transistor M21 ′. Is applied.

However, in this embodiment, clamping P-channel transistors M25 ′ and M26 ′ are provided, and the clamp voltage VSS is applied to the gates of these transistors, so that the drain voltage of the P-channel transistor M24 ′ is VSS−Vth. To be clamped. For this reason, the voltage applied to the gate oxide film of the P-channel transistor M24 ′ can be set to VSS−Vth.
As described above, the present embodiment can provide the same effects as those of the first embodiment.

<Application example>
FIG. 9 is a circuit diagram showing a configuration example of a printer driving circuit which is an application example of the charge pump according to the present invention. As shown in FIG. 9, this printer drive circuit is a gate drive comprising a control circuit 31, a power supply circuit 32, LIFs (level interfaces) 361 and 363, LSD (low side driver) 362, and HSD (high side driver) 364. The circuit 36 includes an output circuit that includes an N-channel transistor M33 and a P-channel transistor M34, and drives the printer head 35. Here, the power supply circuit 32 is a circuit that generates the power supply voltage GVDD for the gate drive circuit 36 by boosting the power supply voltage LVDD. The gate drive circuit 36 is a circuit that drives the N-channel transistor M33 and the P-channel transistor M34 in accordance with a command from the control circuit 31, and consumes a current of about 100 mA. Therefore, since the power supply circuit 32 needs to supply a current of about 100 mA to the gate drive circuit 36, it is necessary to make the output impedance as low as possible. The charge pump according to the present invention is suitable for such a power supply circuit 32 because it can boost the voltage with high efficiency and keep the output impedance low. Moreover, since the charge pump according to the present invention can be constituted by a low breakdown voltage transistor, the manufacturing cost can be reduced. Therefore, by using the charge pump according to the present invention as the power supply circuit 32, the cost of the printer drive circuit can be reduced.

<Other embodiments>
Although the first and second embodiments of the present invention have been described above, other embodiments are conceivable for the present invention. For example:

(1) In the first and second embodiments, all the level shifters S1 to S3 (S1 ′ to S3 ′) are configured by the level shifters including the clamp MOSFET, but a high voltage is applied to the gate oxide film of the transistor. Some of the level shifters (for example, the level shifter S1 or S1 ′) that are not particularly preferable may be level shifters that do not include the clamping MOSFET.

(2) In the first embodiment, the buffer unit 22 is provided in the level shifters S1 to S3. However, the buffer unit 22 is not provided, and the drain voltage of, for example, the P-channel transistor M23 of the differential amplifier 21 is set to the level shifters S1 to S3. An output signal may be used (see FIG. 4). Alternatively, the buffer unit 22 may be configured by a two-stage inverter, and the drain voltage of the P-channel transistor M23 may be supplied to the first-stage inverter. The same applies to the second embodiment.

(3) In the first embodiment, the clamp voltage CP3 is applied to the gates of the P-channel transistors M23 and M24. However, the voltage VDD may be applied to the gates of the P-channel transistors M23 and M24 (see FIG. 4). In the second embodiment, the clamp voltage CP3 ′ is applied to the gates of the N-channel transistors M23 ′ and M24 ′. However, the voltage VSS may be applied to the gates of the N-channel transistors M23 ′ and M24 ′ (FIG. 7). reference).

Cf1, Cf2, Cf3, Cf1 ', Cf2', Cf3 '... Capacitor, N1, N1' ... Input node, N2 ', N2' ... Output node, M1, M2, M3 ... P-channel transistors (for transfer) MOSFET), M1 ′, M2 ′, M3 ′... N channel transistor (transfer MOSFET), 10... VDD system circuit, 10 ′... VSS system circuit, 20, 20 ′. S1 ′ to S3 ′... Level shifter, M21, M22, M25, M26, M29, M23 ′, M24 ′, M27 ′, M28 ′, M30 ′... N-channel transistors, M21 ′, M22 ′, M25 ′, M26 ′ , M29 ′, M23, M24, M27, M28, M30... P-channel transistors.

Claims (6)

An input node to which an input voltage to be boosted is applied;
An output node that generates an output voltage that is a boost result; and
A plurality of transfer MOSFETs connected in series between the input node and the output node;
A capacitor comprising a first electrode and a second electrode, wherein the first electrode is electrically connected to a transfer destination node which is a node on the output node side among nodes on both sides of the transfer MOSFET;
A level shifter that is electrically connected to the gate of one transfer MOSFET among the plurality of transfer MOSFETs and outputs a gate voltage so as to switch the one transfer MOSFET ON / OFF;
First control for turning on only even-numbered transfer MOSFETs counted from the input node among the plurality of transfer MOSFETs, and second for turning on only odd-numbered transfer MOSFETs counted from the input node Of the capacitor electrically connected to the node on the output node side of the transfer MOSFET that is turned ON among the plurality of transfer MOSFETs in the first and second controls. The first electrode is electrically connected to the first reference voltage source, and the second electrode of the capacitor having the first electrode connected to the node on the input node side generates a voltage different from that of the first reference voltage source. Switching control means electrically connected to the second reference voltage source
The level shifter is
A first MOSFET of a first conductivity type having a source electrically connected to the transfer destination node;
A first conductivity type having a source electrically connected to the transfer destination node, a gate electrically connected to a drain of the first MOSFET, and a drain electrically connected to a gate of the first MOSFET; A second MOSFET of
Source electrically connected to said first reference voltage source, a third MOSFET of the second conductivity type,
A source electrically connected to the first reference voltage source; a fourth MOSFET of a second conductivity type;
The third MOSFET and the fourth MOSFET are exclusively turned on, and as a clamp MOSFET, the source is electrically connected to the drain of the first MOSFET, and the first clamp voltage is applied to the gate. A fifth MOSFET of the first conductivity type;
A sixth MOSFET of a first conductivity type, the source of which is electrically connected to the drain of the second MOSFET and the first clamp voltage applied to the gate;
A seventh conductivity type seventh element having a source electrically connected to the drain of the third MOSFET, a drain electrically connected to the drain of the fifth MOSFET, and a second clamp voltage applied to the gate. MOSFET of
The second conductivity type second source is electrically connected to the drain of the fourth MOSFET, the drain is electrically connected to the drain of the sixth MOSFET, and the second clamp voltage is applied to the gate. 8 MOSFETs,
The voltage of the second electrode of the capacitor in which the first electrode is electrically connected to the transfer destination node and said first clamp voltage,
Based on the drain voltage of the first MOSFET or the second MOSFET, the gate voltage is output to the gate of the one transfer MOSFET.
A charge pump characterized by that.   2. The charge pump according to claim 1, wherein the level shifter uses the voltage of the second reference voltage source as the second clamp voltage. 3.   The first reference voltage source is a low potential voltage source, the second reference voltage source is a high potential voltage source, the first conductivity type is P-type, and the second conductivity type is N-type. The charge pump according to claim 1 or 2. The first reference voltage source is a high potential voltage source, the second reference voltage source is a low potential voltage source, the first conductivity type is N-type, and the second conductivity type is P-type. The charge pump according to claim 1 or 2 .   The transfer MOSFET is a P-channel MOSFET formed in an N well formed on a P-type semiconductor substrate, and the N well and the source are electrically connected, and this connection point is the transfer MOSFET. The charge pump according to any one of claims 1 to 4, wherein the charge pump is the transfer destination node on the output node side.   The transfer MOSFET is an N-channel MOSFET formed in a P well formed in an N-type semiconductor substrate, and the P well and the source are electrically connected, and this connection point is the transfer MOSFET. The charge pump according to any one of claims 1 to 4, wherein the charge pump is a transfer destination node on the output node side.

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