JP7134255B2 - Charge pump circuit and semiconductor device - Google Patents

Description

The present invention relates to a charge pump circuit and a semiconductor device having the charge pump circuit.

Charge pumps described in Japanese Patent Application Laid-Open Nos. 2003-33006 (Patent Document 1) and 2006-67764 (Patent Document 2), etc., as circuits for obtaining an output voltage obtained by boosting the input voltage of the input terminal at the output terminal. circuits are known. A charge pump circuit boosts an input voltage and outputs an output voltage by charging and discharging a capacitor by switching on and off of a plurality of switching elements connected in series between an input terminal and an output terminal according to a clock signal. generated at the terminal.

In these charge pump circuits, when the operation is stopped, current is supplied from the input terminal to the output terminal through the parasitic diodes of the plurality of switch elements, thereby reducing the output voltage to 0 V (ground voltage). Have difficulty. As a result, in a circuit group that uses the output voltage of the charge pump circuit as a power supply, a leak current is generated due to the application of the voltage.

As the miniaturization of semiconductor elements progresses, the leakage current increases, so the problem with the charge pump circuit described above greatly affects current consumption (in other words, standby power) when the electronic device stops operating.

In Patent Document 1, in the charge pump circuit, a transistor for cutting off the supply of the input voltage and a transistor for forcibly fixing the output voltage to the ground voltage are additionally arranged, and both transistors respond to the reset signal. Disclosed is a configuration for operating with As a result, when the charge pump circuit stops operating, the current from the input terminal to the output terminal is cut off and the output voltage is fixed at the ground voltage.

In Patent Document 2, a mechanism is provided for switching the connection destination of the back gate of the switch element connected between the input terminal and the connection terminal, and the polarity of the parasitic diode is changed between operating and stopping the charge pump circuit. It is described that the inversion reduces the current consumption when the operation is stopped.

Japanese Patent Application Laid-Open No. 2003-33006 JP 2006-67764 A

However, in the configuration of Patent Document 1, the supply current to the output terminal passes through the transistor for cutting off the supply of the input voltage when the charge pump circuit operates. Therefore, in order to ensure the current capability of the charge pump circuit, the element size of the transistor added for blocking must be increased. Therefore, there is concern about an increase in circuit size.

In Patent Document 2, a plurality of switch elements connected in series between an input terminal and an output terminal are composed of N-channel transistors. Therefore, when the charge pump circuit stops operating, the polarity of the parasitic diode is reversed to cut off the current path through the back gate when the N-channel transistor is turned off in response to a drop in the gate voltage. It can cut off the current from the terminal to the output terminal.

However, when the plurality of switch elements are composed of P-channel transistors, it is necessary to set the gate voltage to the output voltage level in order to turn off the P-channel transistors during the operation of the charge pump circuit. When the operation is stopped, if the output voltage is lowered to the ground voltage, the P-channel transistor cannot be turned off, so there is a concern that the current from the input terminal to the output terminal cannot be interrupted.

That is, when a plurality of switch elements composed of P-channel transistors are combined with Patent Document 2, the output voltage is discharged to 0 V, and the gates of the P-channel transistors constituting the plurality of switch elements are discharged. Since the supplied voltage is also 0 V, each switch element cannot be turned off, and there is concern that current will be supplied from the input terminal to the output terminal via a plurality of switch elements.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and its main object is to cut off the current supply from the input terminal to the output terminal and discharge the output terminal when the operation is stopped. Another object of the present invention is to provide a configuration of a charge pump circuit.

In one aspect of the present invention, a charge pump circuit that boosts an input voltage to generate an output voltage includes an input terminal to which the input voltage is input, an output terminal to output the output voltage, and a plurality of first P-type transistors. , a plurality of switch drive circuits, a capacitor having first and second terminals, a voltage selection circuit, a backgate disconnect switch element, a backgate disconnect switch drive circuit, and a discharge element. The discharge element discharges the output terminal by being turned on when the charge pump circuit is in an inoperative state. A plurality of first P-type transistors are connected in series between the input terminal and the output terminal, and constitute a plurality of switch elements, respectively. The plurality of switch drive circuits selectively apply one of the reference voltage and the output voltage to the control electrode of each of the plurality of first P-type transistors according to one of complementary first and second clocks. output to control on/off of a plurality of switch elements. A first terminal of the capacitor is connected to a connection point of two adjacent switch elements among the plurality of switch elements. The voltage selection circuit selectively outputs one of the reference voltage and the input voltage to the second terminal of the capacitor according to the first or second clock. The backgate disconnecting switch element includes a backgate of at least one first P-type transistor among the plurality of first P-type transistors and an output terminal of the two main electrodes of the first P-type transistor. connected between the main electrodes on the side. The back gate disconnect switch drive circuit turns on the back gate disconnect switch element in the boost operation state, and turns off the back gate disconnect switch element in the operation stop state. The second P-type transistor constituting the backgate disconnecting switch element has a first main electrode connected to the backgate of the first P-type transistor and a main electrode on the output terminal side of the first P-type transistor. and a connected second main electrode. A back gate of the second P-type transistor is connected to the first main electrode. Of the plurality of switch drive circuits, at least one first switch drive circuit corresponding to at least one first P-type transistor to which the back gate disconnecting switch element is connected is operated in a state where the charge pump circuit is stopped. , outputs the input voltage to the control electrode of the first P-type transistor.

According to the above charge pump circuit, when the operation is stopped, the input voltage is supplied to the gate of the first P-type transistor by the first switch driving circuit, and the parasitic diode formed in the second P-type transistor causes A current can be cut off from the input terminal to the output terminal. At the same time, the output terminal can be discharged and the output voltage can be lowered to the ground voltage.

FIG. 3 is a circuit diagram illustrating the configuration of a charge pump circuit according to a comparative example; 4 is a waveform diagram of a clock signal input to the charge pump circuit; FIG. 2 is a chart for explaining the boosting operation of the charge pump circuit shown in FIG. 1; FIG. 2 is a circuit diagram illustrating a configuration example of a charge pump circuit according to Embodiment 1; FIG. 5 is a conceptual cross-sectional view for explaining a current blocking structure of a switch element in the charge pump shown in FIG. 4; FIG. 4A and 4B are charts for explaining the behavior of the charge pump circuit according to the first embodiment in an operation stop state and a boosting operation state; 5 is a flowchart for explaining control processing at the start of boosting operation of the charge pump circuit according to the first embodiment; FIG. 4 is a circuit diagram illustrating the configuration of a charge pump circuit according to a first modification of the first embodiment; FIG. 8 is a circuit diagram illustrating the configuration of a charge pump circuit according to a second modification of the first embodiment; FIG. 11 is a circuit diagram illustrating a configuration example of a charge pump circuit according to a second embodiment; 11 is a waveform diagram of a clock signal input to the charge pump circuit shown in FIG. 10; FIG. 11 is a chart for explaining the operation of the charge pump circuit shown in FIG. 10; FIG. 1 is a schematic block diagram of a semiconductor device including a charge pump circuit according to an embodiment; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Below, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same reference numerals are given to the same or corresponding parts in the drawings, and the description thereof will not be repeated in principle.

Embodiment 1.
(Description of Comparative Example)
First, the configuration of a general charge pump circuit will be described as a comparative example of this embodiment.

FIG. 1 is a circuit diagram illustrating the configuration of a charge pump circuit according to a comparative example. As will be clear from the following description, the basic circuit operation (boosting operation) of the charge pump circuit 100 according to the comparative example is the same as that of the charge pump circuit according to the present embodiment, which will be described later. The charge pump circuit 100 has the same problem as that of Japanese Patent Laid-Open No. 2002-100019 regarding the function of interrupting the short-circuit current when the output terminal is grounded.

Referring to FIG. 1, a charge pump circuit 100 according to the comparative example includes an input terminal 5, an output terminal 10, and "a plurality of switch elements" connected in series between the input terminal 5 and the output terminal 10. It includes P-channel type (also simply referred to as P-type) transistors PMOS5 and PMOS6, switch drive circuits 11 and 12, an inverter 20, inverter drive circuits 13 and 14, and a capacitor C1. Hereinafter, the voltage at the input terminal 5 will be referred to as the input voltage VIN, and the voltage at the output terminal 10 will be referred to as the output voltage VOUT.

Each of clock signals CLK1-CLK4 shown in FIG. ”) is repeated at regular intervals.

Transistor PMOS5 is electrically connected between node Np0 connected to input terminal 5 and node Np1. The gate of transistor PMOS5 is connected to output node N3 of switch drive circuit 11 . Transistor PMOS5 has a parasitic diode D9 of the polarity shown in FIG. 1 by connecting its backgate to node Np1.

Transistor PMOS6 is electrically connected between node Np1 and node Np2 connected to output terminal . The gate of transistor PMOS6 is connected to output node N4 of switch drive circuit 12 . Transistor PMOS6 has a parasitic diode D10 of the polarity shown in FIG. 1 by connecting its backgate to node Np2.

The switch drive circuit 11 has a P-type transistor PMOS1 and an N-channel (also simply referred to as N-type) transistor NMOS1 connected in series via a node N3 between a node Np2 and a ground node Ng. A clock signal CLK1 is commonly input to the gates of the transistors PMOS1 and NMOS1. Ground node Ng supplies a reference voltage (typically ground voltage GND).

Similarly, the switch driving circuit 12 has a P-type transistor PMOS2 and an N-type transistor NMOS2 connected in series via a node N4 between the node Np2 and the ground node Ng. A clock signal CLK2 is commonly input to the gates of the transistors PMOS2 and NMOS2.

The switch drive circuits 11 and 12 constitute inverters that use the output voltage VOUT and the ground voltage GND as power sources and receive the clock signals CLK1 and CLK2 as inputs. Transistors PMOS1 and NMOS1 have parasitic diodes D1 and D2 of the polarities shown in FIG. 1 by connecting their backgates to node Np2 and ground node Ng, respectively. Similarly, transistors PMOS2 and NMOS2 have parasitic diodes D3 and D4 of the polarities shown in FIG. 1 by connecting their back gates to node Np2 and ground node Ng, respectively.

The inverter 20 has a P-type transistor PMOS7 and an N-type transistor NMOS5 connected in series via a node N2 between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND). Node N2 is connected to node Np1 via capacitor C1.

The gate of transistor PMOS7 is connected to the output node of inverter drive circuit 13 to which clock signal CLK3 is input. The gate of transistor NMOS5 is connected to the output node of inverter drive circuit 14 to which clock signal CLK4 is input. Transistors PMOS7 and NMOS5 have parasitic diodes D11 and D12 of the polarities shown in FIG. 1 by connecting their back gates to node Np0 and ground node Ng, respectively.

The inverter drive circuit 13 includes P-type transistors PMOS3 and PMOS3 connected in series between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor PMOS7. It has an N-type transistor NMOS3. A clock signal CLK3 is commonly input to the gates of the transistors PMOS3 and NMOS3.

Similarly, the inverter drive circuit 14 is a P-type inverter connected in series between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor NMOS5. It has a transistor PMOS4 and an N-type transistor NMOS4. A clock signal CLK4 is commonly input to gates of the transistors PMOS4 and NMOS4.

The inverter drive circuits 13 and 14 constitute inverters that use the input voltage VIN and the ground voltage GND as power sources and receive the clock signals CLK3 and CLK4 as inputs. Transistors PMOS3 and NMOS3 have parasitic diodes D5 and D6 of the polarities shown in FIG. 1 by connecting their backgates to node Np0 and ground node Ng, respectively. Similarly, transistors PMOS4 and NMOS4 have parasitic diodes D7 and D8 of the polarities shown in FIG. 1 by connecting their backgates to node Np0 and ground node Ng, respectively.

FIG. 2 is a waveform diagram of clock signals CLK1 to CLK4 input to the charge pump circuit 100. As shown in FIG.

Referring to FIG. 2, clock signal CLK1 and clock signals CLK2-CLK4 are in opposite phase, and clock signals CLK2-CLK4 are in phase. However, between the edges of the clock signals CLK1 to CLK4, a time difference (so-called dead time equivalent) is provided to prevent through current due to simultaneous conduction of a plurality of transistors.

For example, the clock signals CLK1 to CLK4 can be generated by not giving the dead time to the reference clocks CLKa and CLKb having phases opposite to each other. Although the dead time is usually several (ns) to several tens (ns), it is exaggerated with respect to the clock period in FIG.

FIG. 3 shows a chart for explaining the boosting operation of the charge pump circuit 100. As shown in FIG. The charge pump circuit 100 alternately repeats state 1 and state 2 shown in FIG. 3 according to clock signals CLK1-CLK4 based on complementary reference clocks CLKa and CLKb.

3 and 1, in state 1, reference clock CLKa (clock signal CLK1) is at H level, while reference clock CLKb (clock signals CLK2 to CLK4) is at L level. Therefore, the switch drive circuit 11 outputs an L level voltage (ground voltage GND) to the node N3. On the other hand, switch driving circuit 12 outputs an H level voltage (output voltage VOUT) to node N4. As a result, regarding the plurality of switch elements, the transistor PMOS6 is turned off while the transistor PMOS5 is turned on.

Further, since the inverter drive circuits 13 and 14 output the input voltage VIN, the transistor PMOS7 is turned off and the transistor NMOS5 is turned on. Therefore, inverter 20 connects node N2 to ground node Ng. As a result, in state 1, the node Np1 is connected to the input terminal 5 (input voltage VIN) and disconnected from the output terminal 10. FIG. Furthermore, the capacitor C1 is charged by the input voltage VIN by being connected between the node Np1 and the ground node Ng. Therefore, the capacitor voltage V(C1)=VIN.

In contrast, in state 2, clock signal CLK1 (reference clock CLKa) is at L level, while clock signals CLK2 to CLK4 (reference clock CLKb) are at H level. Therefore, the node N3, that is, the gate voltage of the transistor PMOS5 becomes the output voltage VOUT, and the node N4, that is, the gate voltage of the transistor PMOS6 becomes the ground voltage GND. As a result, in the plurality of switch elements, the transistor PMOS6 is turned on, while the transistor PMOS5 is turned off.

Further, since the inverter drive circuits 13 and 14 output the ground voltage GND, the transistor PMOS7 is turned on and the transistor NMOS5 is turned off. Therefore, inverter 20 connects node N2 to node Np0. As a result, in state 2, node Np1 is connected to output terminal 10 while being disconnected from input terminal 5 (input voltage VIN). Further, capacitor C1 is connected between input terminal 5 (node Np0) and node Np1. Therefore, the output voltage VOUT at the output terminal 10 is the sum of the input voltage VIN and the capacitor voltage V(C1), ie twice the input voltage VIN.

The charge pump circuit 100 alternately repeats State 1 and State 2 according to the clock signals CLK1 to CLK4, thereby performing a boosting operation that outputs an output voltage VOUT that is twice the input voltage VIN.

In the charge pump circuit 100 shown in FIG. 1, when the boosting operation is stopped, the oscillation of the reference clocks CLKa and CLKb is stopped, and the clock signals CLK1 to CLK4 are stopped at H level or L level.

In the non-operating state, fixed at state 1 in FIG. 3, the transistor PMOS6 is turned off while the transistor PMOS5 is turned on. However, a current path from the input terminal 5 to the output terminal 10 is formed by the on-state transistor PMOS5 and the parasitic diode D10 of the off-state transistor PMOS6. At this time, the output voltage VOUT is lower than the input voltage VIN by the amount of forward voltage drop due to the parasitic diode D10.

On the other hand, when fixed to state 1 in FIG. 3, transistor PMOS6 is turned on while transistor PMOS5 is turned off. However, a current path from the input terminal 5 to the output terminal 10 is formed by the on-state transistor PMOS6 and the parasitic diode D9 of the off-state transistor PMOS5. At this time, the output voltage VOUT is lower than the input voltage VIN by the amount of forward voltage drop due to the parasitic diode D9.

When the output terminal 10 is discharged when the operation is stopped and the output voltage VOUT drops, the voltage output from the switch drive circuits 11 and 12 to the nodes N3 and N4, that is, the gates of the transistors PMOS5 and PMOS6 also drops. Therefore, it becomes difficult to secure a gate voltage higher than the input voltage VIN to turn off the transistors PMOS5 and PMOS6.

Even if both the transistors PMOS5 and PMOS6 can be turned off, a current path from the input terminal 5 to the output terminal 10 is formed by the parasitic diodes D) and D10. At this time, the output voltage VOUT is lower than the input voltage VIN by the sum of forward voltage drops due to the parasitic diodes D9 and D10.

Thus, in the charge pump circuit 100 of the comparative example, it is difficult to cut off the current from the input terminal to the output terminal and reduce the voltage of the output terminal when the operation is stopped.

(Description of Embodiment 1)
FIG. 4 is a circuit diagram illustrating a configuration example of the charge pump circuit according to the first embodiment.

Referring to FIG. 4, charge pump circuit 101 according to the first embodiment performs the same boosting operation as charge pump circuit 100 according to the comparative example, and also performs a voltage boosting operation from input terminal 5 to output terminal 10 in the operation stopped state. current interrupting function.

Compared to the charge pump circuit 100 of the comparative example, the charge pump circuit 101 according to the first embodiment has a transistor PMOS13 connected to the back gate of the transistor PMOS5, which is a switch element, and a switch drive for controlling on/off of the transistor PMOS13. It further comprises a circuit 30 and an N-type transistor NMOS7 corresponding to one embodiment of a "discharge element".

Further, the charge pump circuit 101 according to the first embodiment includes a switch drive circuit 21 instead of the switch drive circuit 12 in the charge pump circuit 100 of the comparative example. The switch drive circuit 21 controls on/off of the transistor PMOS6, which is a switch element to which the transistor PMOS13 is connected.

Since the configuration of other portions of charge pump circuit 101 according to the first embodiment is similar to that of charge pump circuit 100 (FIG. 1) according to the comparative example, detailed description thereof will not be repeated. In the configuration example of FIG. 4, the transistors PMOS5 and PMOS6 correspond to an example of a "first P-type transistor" constituting "a plurality of switch elements", and the transistor PMOS13 serves as a "back gate disconnect switch element". This corresponds to an embodiment of the "second P-type transistor" to be constructed. Also, the switch drive circuit 30 corresponds to an embodiment of the "back gate disconnection switch element drive circuit". Furthermore, the node Np1 corresponds to a "connection point" between two adjacent switch elements, and the inverter drive circuits 13 and 14 and the inverter 20 constitute an example of a "voltage selection circuit".

The transistor PMOS13 is connected between the back gate of the transistor PMOS6 and the main electrode (source in FIG. 4) on the output terminal 10 side of the two main electrodes (source and drain) of the transistor PMOS6.

FIG. 5 shows a conceptual cross-sectional view of the transistors PMOS6 and PMOS13 for explaining the current blocking structure of the charge pump circuit 101. As shown in FIG.

Referring to FIG. 5, N-well 61 and N-well 71 are formed in P-type substrate 60 . Transistor PMOS 6 has P+ regions 62 and 63 and an N+ region 65 formed in N-well 61 . P+ regions 62 and 63 correspond to the first and second main electrodes (source and drain, respectively) of transistor PMOS6. N+ region 65 corresponds to the back gate of transistor PMOS6. The transistor PMOS6 further has a gate 64 corresponding to a control electrode formed directly above the channel region between the P+ regions 62 and 63 with an insulating film interposed therebetween.

Similarly, transistor PMOS13 has P+ regions 72 and 73, gate 74, and N+ region 75 formed in N-well 71. FIG. P+ regions 72 and 73 correspond to the first and second main electrodes (one of the source and drain, respectively) of transistor PMOS13, and N+ region 75 corresponds to the back gate of transistor PMOS13. Gate 64 corresponds to the control electrode of transistor PMOS13.

In transistor PMOS6, P+ region 63 is connected to node Np2 (that is, output terminal 10), and P+ region 62 is connected to node Np1 connected to capacitor C1. Gate 64 is connected to node N4 receiving the output of switch driving circuit 21. FIG. In transistor PMOS 6, P+ region 62 and P+ region 63 correspond to one embodiment of a "main electrode", in particular P+ region 63 corresponds to the "main electrode" on the output terminal 10 side.

In transistor PMOS13, P+ region 73 is connected to node Np2 (that is, P+ region 63 of transistor PMOS6), and gate 74 is connected to node N5 which receives the output of switch drive circuit 30. FIG. P+ region 72 is connected to N+ region 75 and N+ region 65 of transistor PMOS6. As a result, in the transistor PMOS13, a PN junction between the P+ region 73 connected to the output terminal 10 and the N well 71 forms a parasitic diode. Similarly, in transistor PMOS13, a PN junction between P+ region 62 connected to node Np1 and N well 61 forms a parasitic diode. Also, the bodies (back gates) of the PMOS 6 and PMOS 13 are electrically connected to each other. That is, in the transistor PMOS13, which is an embodiment of the "second P-type transistor," the P+ region 72 corresponds to an embodiment of the "first main electrode," and the P+ region 73 is the "second main electrode." , and N+ region 75 corresponds to an embodiment of "backgate."

Referring to FIG. 4 again, a path is formed between the main electrodes of the transistor PMOS6 by the parasitic diode D10 of PMOS6, the body (backgate) of PMOS6 and PMOS13, and the parasitic diode D23 of PMOS13. By establishing the connection relationship described in FIG. 5 on the path including the back gate, the parasitic diodes D10 and D23 are connected in series with opposite polarities.

The switch drive circuit 30 has a P-type transistor PMOS14 and an N-type transistor NMOS11 connected in series via a node N5 between a node Np0 and a ground node Ng. A control signal EN is commonly input to the gates of the transistors PMOS14 and NMOS11. Control signal EN is set to H level when the charge pump circuit is in the boosting operation state, and is set to L level when the operation is stopped.

The switch drive circuit 30 constitutes an inverter that uses the input voltage VIN and the ground voltage GND as power sources and receives the control signal EN as an input. Transistors PMOS14 and NMOS11 have parasitic diodes D24 and D25 of the polarities shown in FIG. 1 by connecting their backgates to node Np1 and ground node Ng, respectively. As described above, the output node N5 of the switch drive circuit 30 is connected to the gate of the transistor PMOS13.

The switch drive circuit 21 further includes transistors PMOS11 and PMOS12 in addition to the inverter-connected transistors PMOS2 and NMOS2 as in the switch drive circuit 12 of FIG. The transistor PMOS11 is connected between a node Np0 (input voltage VIN) and a node Ns corresponding to the source of the transistor PMOS2. The transistor PMOS12 is connected between the node Np2 (output voltage VOUT) and the node Ns (transistor PMOS2).

A control signal EN is input to the gate of the transistor PMOS11. On the other hand, the gate of the transistor PMOS12 receives the control signal ENB, which is the logic level inversion of the control signal EN. That is, the control signal ENB is set to H level when the operation is stopped, and is set to L level when the charge pump circuit is in the boosting operation state. The transistors PMOS11 and NMOS12 have the parasitic diodes D21 and D22 of the polarities shown in FIG. 1 by connecting their backgates in common with the node Ns.

Therefore, in the boosting operation state of the charge pump circuit 101, the switch drive circuit 21 operates as an inverter using the output voltage VOUT as the power supply voltage by turning on the transistor PMOS12. On the other hand, when the charge pump circuit 101 is stopped, the switch drive circuit 21 operates as an inverter using the input voltage VIN as the power supply voltage. An output node N4 of the inverter is connected to the gate of transistor PMOS6.

Clock signals CLK1 to CLK4 (FIG. 2) similar to those of the charge pump circuit 100 of the comparative example are input to the switch drive circuits 11 and 21 and the inverter drive circuits 13 and 14 of the charge pump circuit 101, respectively.

Transistor NMOS7 is connected between output terminal 10 (node Np2) and ground node Ng. An output signal of the logic gate 80 is input to the gate of the transistor NMOS7. Logic gate 80 outputs a logical product (AND) operation result of control signal ENB and an inverted signal of precharge signal PR. The precharge signal PR defaults to L level and is set to H level during a precharge period, which will be described later.

Next, behavior of the charge pump circuit 101 will be described with reference to FIG.
Referring to FIG. 6, EN is set to L level and ENB is set to H level in the operation stopped state. Therefore, if the precharge signal PR is at L level, that is, during periods other than the precharge period, the output terminal 10 is discharged by turning on the transistor NMOS7, whereby the output voltage VOUT can be lowered to the ground voltage GND.

In the switch drive circuit 21, the transistor PMOS11 is turned on, while the transistor PMOS12 is turned off. As a result, the input voltage VIN is supplied to the node Ns by the transistor PMOS11. Therefore, by fixing the clock signal CLK2 to L level, the input voltage VIN can be output to the node N4, that is, the gate of the transistor PMOS6 via the transistor PMOS2. As a result, the transistor PMOS6 can be turned off by applying a high voltage to the gate with respect to the source connected to the node Np2 (output terminal 10).

Thus, among the plurality of switch drive circuits 11 and 21, the switch drive circuit 21 realizes the function of the "first switch drive circuit". In the switch drive circuit 21, the transistors PMOS11 and PMOS12 form an embodiment of a "voltage switching circuit", and the inverters of the transistors PMOS2 and NMOS2 form an embodiment of a "signal transmission circuit". Also, the node Ns corresponds to an example of a "power supply node", and the ground node Ng corresponds to an example of a "reference voltage node".

The switch driving circuit 30 outputs the input voltage VIN to the node N5 by turning on the transistor PMOS14. This keeps the transistor PMOS13 off as well as the transistor PMOS6. At this time, the current path through the body (backgate) of the transistor PMOS6 is cut off by the reverse voltage blocking by the parasitic diode D23 of the transistor PMOS13, which is the "backgate disconnection switch element". As a result, the current path from the input terminal 5 to the output terminal 10 can be cut off even when the transistor PMOS5 is turned on.

As described above, according to the charge pump circuit 101 according to the first embodiment, when the operation is stopped (ENB=H, EN=L), the current from the input terminal 5 to the output terminal 10 is cut off, and the output terminal 10 can be discharged to reduce the output voltage VOUT to the ground voltage GND. As a result, the leakage current generated in the element group (not shown) supplied with the output voltage VOUT of the charge pump circuit 101 can be reduced, and the standby power can be suppressed.

Next, the control at the time of starting the boosting operation of the charge pump circuit 101 according to the first embodiment, that is, at the time of transition from the operation stop state to the boosting operation state will be described.

FIG. 7 is a flowchart for explaining control processing at the start of the boosting operation of charge pump circuit 101 according to the first embodiment. The control process shown in FIG. 7 can be executed by a control circuit (not shown) that outputs clock signals CLK1 to CLK4 and control signals EN and ENB. The control circuit can be provided outside the charge pump circuit 101 . Alternatively, the control circuit can be arranged inside the charge pump circuit 101 . In this case, for example, by inputting the operation and stop instructions of the charge pump circuit 101 and the reference clocks CLKa and CLKb to the control circuit, the control circuit outputs the clock signals CLK1 to CLK4 and the control signals EN and ENB. It is possible to have a configuration that

Referring to FIG. 7, at step (hereinafter also simply referred to as "S") 100, clock signal CLK2 is changed from L level to H level under the conditions of EN=L and ENB=H. Furthermore, the precharge signal PR is set to H level.

As a result, the output terminal 10 is disconnected from the ground node Ng by turning off the transistor NMOS7. Further, the transistor PMOS6 is turned on by the switch driving circuit 21 outputting the ground voltage GND to the node N4. Since the output voltage VOUT has dropped to the ground voltage GND before precharging, the transistor PMOS5 is turned on regardless of the clock signal CLK1. Therefore, when the transistor PMOS6 is turned on, the output terminal 10 is precharged with the input voltage VIN.

Through S110, the completion determination of precharge through S100 is executed. For example, precharging in S100 continues until a predetermined time Txp elapses from the start of charging in S100 (NO determination in S110). After the time Txp has elapsed, it is determined that precharging has been completed (YES in S110), and the process proceeds to S120.

In S120, the transistor PMOS is turned off by changing the clock signal CLK2 to L level again. Furthermore, according to the rise of the output voltage VOUT, the transistor PMOS6 is also turned off under the clock signal CLK1=L, so the precharge is completed. At the end of precharging, the transistor NMOS7 is also turned off by returning the precharge signal PR to the L level.

The determination in S120 can be realized by measuring the elapsed time using a timer or the like. may

When the precharging is completed in S120, the control signal EN changes from L level to H level and the control signal ENB changes from H level to L level in S130, thereby precharging the charge pump circuit. 101 transitions to the boost operation state.

Referring to FIG. 6 again, EN=H level and ENB=L level are set in the boosting operation state. As a result, the transistor NMOS7 is kept off after precharging.

In the switch drive circuit 21, the transistor PMOS11 is turned off while the transistor PMOS12 is turned on. As a result, the output voltage VOUT is supplied to the node Ns by turning on the transistor PMOS12, so the switch drive circuit 21 operates in the same manner as the switch drive circuit 12 in FIG. As a result, the voltage of the node Ns also rises in accordance with the rise of the output voltage VOUT, so even if the output voltage VOUT becomes higher than the input voltage VIN, the transistor PMOS6 can be turned off during the L level period of the clock signal CLK2. can.

Also, the switch drive circuit 30 outputs the ground voltage GND to the node N5 by turning on the transistor NMOS14. As a result, the transistor PMOS13 is turned on, and the body (back gate) of the transistor PMOS6 is connected to the source (that is, the main electrode on the output terminal 10 side) as in FIG.

Thus, the charge pump circuit 101 can operate in the same manner as the charge pump circuit 100 in FIG. 1 in the boosting operation state. Therefore, in S140, by inputting the clock signals CLK1 to CLK4 (FIG. 2) based on the reference clocks CLKa and CLKb, the charge pump circuit 101 repeats states 1 and 2 shown in FIG. A boosting operation is performed in which the voltage VOUT rises to twice the input voltage VIN. That is, the reference clock CLKa (or clock signal CLK1) and CLKb (or clock signals CLK2 to CLK4) correspond to an example of "mutually complementary first and second clocks".

By starting the boosting operation according to the control process shown in FIG. 7, the output terminal 10 can be precharged without causing a current to flow through the parasitic diodes D9 and D10. As a result, latch-up in the parasitic diodes D9 and D10 can be prevented during precharging, and the boosting operation can be started stably.

Modification 1 of the first embodiment.
FIG. 8 is a circuit diagram illustrating the configuration of the charge pump circuit according to the first modification of the first embodiment.

Referring to FIG. 8, charge pump circuit 102 according to the first modification of the first embodiment is connected to the back gate of transistor PMOS6 which is a switch element, unlike charge pump circuit 100 according to the comparative example. a transistor PMOS17, a switch drive circuit 30 for controlling on/off of the transistor PMOS17, and a transistor NMOS7 similar to that in FIG. Further, the charge pump circuit 102 includes a switch drive circuit 23 instead of the switch drive circuit 11 in the charge pump circuit 100 of the comparative example. The switch drive circuit 23 controls on/off of the transistor PMOS5, which is a switch element to which the transistor PMOS17 is connected.

The transistor PMOS17 is connected between the back gate of the transistor PMOS5 and the main electrode (the source in FIG. 8) on the output terminal 10 side of the two main electrodes of the transistor PMOS5. The connection relationship between the transistors PMOS17 and PMOS5 is the same as the connection relationship between the transistors PMOS13 and PMOS6 in FIGS. Therefore, the parasitic diode D9 of the transistor PMOS5 and the parasitic diode D28 of the transistor PMOS17 are connected in series with opposite polarities on the path through the body (backgate) between the main electrodes of the transistor PMOS6.

The configuration and operation of switch drive circuit 30 are the same as those in FIG. 4, and detailed description thereof will not be repeated. The output node N5 of the switch drive circuit 30 is connected to the gate of the transistor PMOS17.

The switch drive circuit 23 further includes transistors PMOS15 and PMOS16 in addition to the inverter-connected transistors PMOS1 and NMOS1 as in the switch drive circuit 12 of FIG. The transistor PMOS15 is connected between the node Np0 (input voltage VIN) and the node Ns corresponding to the source of the transistor PMOS1, like the transistor PMOS11 in FIG. Transistor PMOS16 is connected between node Np2 (output voltage VOUT) and node Ns (transistor PMOS1). A control signal EN is input to the gate of the transistor PMOS15. A control signal ENB is input to the gate of the transistor PMOS16. The transistors PMOS15 and NMOS16 have the parasitic diodes D26 and D27 of the polarities shown in FIG. 8 by connecting their backgates in common with the node Ns.

Therefore, like the switch drive circuit 21 in FIG. 4, the switch drive circuit 23 operates as an inverter using the input voltage VIN as the power supply voltage when the transistor PMOS15 is on, while the output voltage VOUT is used when the transistor PMOS16 is on. It operates as an inverter with power supply voltage. An output node N3 of the inverter is connected to the gate of transistor PMOS5. That is, in the configuration of FIG. 8, the function of the "first switch drive circuit" is realized by the switch drive circuit 23 among the plurality of switch drive circuits 23 and 12. FIG. In the switch drive circuit 23, the transistors PMOS15 and PMOS16 form an embodiment of a "voltage switching circuit", and the inverters of the transistors PMOS1 and NMOS1 form an embodiment of a "signal transmission circuit".

Since the configuration of other portions of charge pump circuit 102 according to the first modification of the first embodiment is the same as that of charge pump circuit 100 (FIG. 1) according to the comparative example, detailed description thereof will not be repeated. Also in the configuration example of FIG. 8, the transistors PMOS5 and PMOS6 constituting a plurality of switch elements correspond to an embodiment of the "first P-type transistor", and the transistor PMOS17 constitutes the "back gate disconnection switch element". corresponds to an embodiment of the "second P-type transistor".

In the charge pump circuit 102 of FIG. 8, the switch drive circuits 23 and 30 and the transistor PMOS17 operate similarly to the switch drive circuits 21 and 30 and the transistor PMOS13 in FIG. 4 (charge pump circuit 101). Therefore, the behavior of the charge pump circuit 102 according to the first modification of the first embodiment in the operation stop state and the boosting operation state is the same as that of the charge pump circuit 101 according to the first embodiment.

As a result, when the control signal ENB is set to H level (EN=L level) and the operation is stopped, if the precharge signal PR is at L level, i.e., except during the precharge period, the transistor NMOS7 is turned on to turn on the output terminal. By discharging 10, the output voltage VOUT can be lowered to the ground voltage GND.

In the switch drive circuit 23, the transistor PMOS15 is turned on, while the transistor PMOS16 is turned off. As a result, the input voltage VIN is supplied to the node Ns by the transistor PMOS15. Therefore, by fixing the clock signal CLK1 to L level, the input voltage VIN can be output to the node N3, that is, the gate of the transistor PMOS5 via the transistor PMOS1. As a result, the transistor PMOS5 can be turned off by applying a high voltage to the gate with respect to the source connected to the node Np1 (output terminal 10).

Further, when the transistor PMOS17 is kept off by the switch drive circuit 30, the current path through the body (backgate) of the transistor PMOS5 is a reverse voltage due to the parasitic diode D28 of the transistor PMOS17, which is the "backgate cutoff switch element". Blocked by blocking. As a result, the current path from the input terminal 5 to the output terminal 10 can be cut off even when the transistor PMOS5 is turned on.

As a result, in the modification of the first embodiment, the transistor PMOS17 is connected as a "back gate disconnecting switch element" to the transistor PMOS5 among the plurality of switch elements. In the operation stop state (ENB=H, EN=L), the current from the input terminal 5 to the output terminal 10 is cut off, and the output terminal 10 is discharged, so that the output voltage VOUT can be lowered to the ground voltage GND. .

Further, when the charge pump circuit 101 starts the boosting operation, in the control process of FIG. 7, the clock signal CLK1 is changed from L level to H level in S100, and the clock signal CLK1 is changed from H level to L level in S120. , the output terminal 10 can be precharged by turning on the transistor PMOS5 without passing current through the parasitic diodes D9 and D10. After precharging is completed, a boosting operation similar to that of charge pump circuits 100 and 101 can be performed according to clock signals CLK1-CLK4 (FIG. 2).

Modified example 2 of the first embodiment.
FIG. 9 is a circuit diagram illustrating the configuration of a charge pump circuit according to a second modification of the first embodiment.

Referring to FIG. 9, in a charge pump circuit 103 according to the second modification of the first embodiment, compared with the charge pump circuit 100 according to the comparative example, the back gates of transistors PMOS5 and PMOS6 which are switch elements have It further comprises transistors PMOS13 and PMOS17 which are respectively connected, and a switch drive circuit 30 which controls on/off of the transistors PMOS13 and PMOS17. Further, the charge pump circuit 103 has the switch drive circuit 23 of FIG. 4 in place of the switch drive circuit 11 (FIG. 1) and the switch drive circuit 12 (FIG. ), the switch drive circuit 21 of FIG. 8 is provided.

The connection relationship between the transistors PMOS13 and PMOS6 is the same as that described in the first embodiment (FIGS. 4 and 5), and the connection relationship between the transistors PMOS17 and PMOS5 is the same as that described in the first embodiment. It is the same as the modified example (FIG. 8). The configuration and operation of the switch drive circuit 30 are the same as those described with reference to FIGS. be.

The switch drive circuit 21 controls on/off of the transistor PMOS6 with the same configuration and operation as in FIG. Similarly, the switch drive circuit 23 controls on/off of the transistor PMOS5 with the same configuration and operation as in FIG.

Since the configuration of other portions of charge pump circuit 103 according to the second modification of the first embodiment is the same as that of charge pump circuit 100 (FIG. 1) according to the comparative example, detailed description thereof will not be repeated. Also in the configuration example of FIG. 6, the transistors PMOS5 and PMOS6 correspond to an embodiment of the "first P-type transistor" constituting the "plurality of switch elements", and the transistors PMOS13 and PMOS17 correspond to the "back gate disconnect switch". This corresponds to an example of the "second P-type transistor" that constitutes the "element". Further, each of the plurality of switch drive circuits 21 and 23 has the function of "first switch drive circuit".

In the charge pump circuit 103, when the control signal ENB is set to H level (EN=L level) and the boosting operation is stopped, if the precharge signal PR is at L level, that is, during periods other than the precharge period, the transistor NMOS7 is turned on. By discharging the output terminal 10 by turning it on, the output voltage VOUT can be lowered to the ground voltage GND. Furthermore, by fixing the clock signals CLK1 and CLK2 to L level, the transistors PMOS5 and PMOS6 are turned off by the switch drive circuits 21 and 23, and the reverse voltage blocking by the parasitic diodes D28 and D23 of the transistors PMOS17 and PMOS15 A current path from the input terminal 5 to the output terminal 10 can be cut off.

In this way, even if the transistors PMOS13 and PMOS17 are connected as "back gate disconnecting switch elements" to both the transistors PMOS5 and PMOS6 among the plurality of switch elements, the operation is stopped in the same manner as in the first embodiment. In the state (ENB=H, EN=L), the current from the input terminal 5 to the output terminal 10 can be cut off and the output terminal 10 can be discharged to reduce the output voltage VOUT to the ground voltage GND.

Further, when the charge pump circuit 103 starts the boosting operation, the clock signals CLK1 and CLK2 are changed from L level to H level in S100 in the control process of FIG. By transforming it to a level change, the turn-on of transistors PMOS5 and PMOS6 allows the output terminal 10 to be precharged without passing current through the parasitic diodes D9 and D10. After precharging is completed, a boosting operation similar to that of charge pump circuits 100 and 101 can be performed according to clock signals CLK1-CLK4 (FIG. 2).

For at least one of the plurality of switch elements (transistors PMOS5 and PMOS6) connected between the input terminal 5 and the output terminal 10 from the charge pump circuits 101 to 103 of FIGS. 4, 8 and 9 described above, By connecting at least one of the transistors PMOS13 and PMOS17 as the "back gate disconnecting switch element" and by arranging at least one of the switch driving circuits 23 and 21 as the "first switch driving circuit", , it is possible to provide a function of interrupting the current from the input terminal 5 to the output terminal 10 in the operation stop state.

Embodiment 2.
In the first embodiment and its modification, the function of interrupting the current from the input terminal 5 to the output terminal 10 in the operation stop state in the charge pump circuit with the boost ratio (VOUT/VIN) of 2 has been described. A similar overcurrent protection function can be applied to different charge pump circuits. In the second embodiment, addition of an overcurrent prevention function to a charge pump circuit having a step-up ratio (VOUT/VIN) of 3 will be described as an example.

FIG. 10 is a circuit diagram illustrating a configuration example of a charge pump circuit according to the second embodiment.
Referring to FIG. 10, charge pump circuit 105 according to the second embodiment differs from charge pump circuit 101 (FIG. 4) according to the first embodiment in that transistor PMOS18 as a switch element and ON/OFF state of transistor PMOS18 are different. , a capacitor C2, an inverter 32, and inverter drive circuits 26 and 27.

The transistor PMOS18 is connected between the node Np0 connected to the input terminal 5 and the transistor PMOS5. That is, in the configuration of FIG. 10, the transistors PMOS5, PMOS6, and PMPOS18 connected in series between the input terminal 5 and the output terminal 10 constitute a "first P-type transistor" forming a "plurality of switch elements." corresponds to an embodiment of

A capacitor C2 is connected between a node Np3 corresponding to a connection point of the transistors PMOS5 and PMOS18 and a node N8. The voltage of node N 8 is controlled by inverter 32 .

The switch drive circuit 25 has a P-type transistor PMOS19 and an N-type transistor NMOS12 connected in series via a node N6 between a node Np2 and a ground node Ng. A clock signal CLK5 is commonly input to the gates of the transistors PMOS19 and NMOS12. The switch drive circuit 25 constitutes an inverter that uses the output voltage VOUT and the ground voltage GND as power sources and receives the clock signal CLK5 as an input. Transistors PMOS19 and NMOS12 have parasitic diodes D29 and D30 of the polarities shown in FIG. 10 by connecting their back gates to node Np2 and ground node Ng, respectively.

The inverter 32 has a P-type transistor PMOS22 and an N-type transistor NMOS14 connected in series via a node N8 between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND). Node N8 is connected to node Np3 via capacitor C2.

The gate of transistor PMOS22 is connected to the output node of inverter drive circuit 26 to which clock signal CLK6 is input. The gate of transistor NMOS14 is connected to the output node of inverter drive circuit 27 to which clock signal CLK7 is input. Transistors PMOS22 and NMOS14 have parasitic diodes D36 and D37 of the polarities shown in FIG. 12 by connecting their backgates to node Np0 and ground node Ng, respectively.

The inverter drive circuit 26 includes a P-type transistor PMOS20 and a P-type transistor PMOS20 connected in series between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor PMOS22. It has an N-type transistor NMOS15. A clock signal CLK6 is commonly input to the gates of the transistors PMOS20 and NMOS15.

Similarly, the inverter drive circuit 27 is a P-type inverter connected in series between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor NMOS14. It has a transistor PMOS21 and an N-type transistor NMOS13. A clock signal CLK7 is commonly input to the gates of the transistors PMOS21 and NMOS13.

The inverter drive circuits 26 and 27 constitute inverters that use the input voltage VIN and the ground voltage GND as power sources and receive the clock signals CLK6 and CLK7 as inputs. Transistors PMOS20 and NMOS15 have parasitic diodes D31 and D32 of the polarities shown in FIG. 12 by connecting their backgates to node Np0 and ground node Ng, respectively. Similarly, transistors PMOS21 and NMOS13 have parasitic diodes D33 and D34 of the polarities shown in FIG. 12 by connecting their backgates to node Np0 and ground node Ng, respectively.

The configuration of charge pump circuit 105 according to the second embodiment other than that described above is similar to that of charge pump circuit 101 according to the first embodiment, and therefore detailed description thereof will not be repeated. That is, as in FIG. 4, among the transistors PMOS5, PMOS6, and PMPOS18, which are a plurality of switch elements, for the transistor PMOS6, the "second P-type transistor" constituting the "back gate disconnecting switch" is used. A corresponding transistor PMOS13 is arranged. As in the first embodiment, the transistor PMOS13 is turned off in normal boosting operation. Further, in the charge pump circuit 105, in addition to the "voltage selection circuit" formed by the inverter drive circuits 13 and 14 and the inverter 20, the inverter drive circuits 26 and 27 and the inverter 32 also constitute a "voltage selection circuit". Configured. Furthermore, transistor NMOS7 constitutes an embodiment of a "discharge element".

FIG. 11 is a waveform diagram of clock signals CLK1 to CLK7 input to the charge pump circuit 105. As shown in FIG.

Referring to FIG. 11, clock signals CLK1-CLK4 are the same as those in FIG. 2, and clock signal CLK1 based on reference clock CLKa and clock signals CLK2-CLK4 based on reference clock CLKb have opposite phases.

As described above, clock signals CLK5 to CLK7 are added in the second embodiment. Clock signal CLK5 is in phase with clock signals CLK2-CLK4, and clock signals CLK6 and CLK7 are in phase with clock signal CLK1. Similarly to clock signals CLK1 to CLK4, dead times are appropriately provided for clock signals CLK5 to CLK7.

FIG. 12 shows a diagram for explaining the boosting operation of the charge pump circuit 105. As shown in FIG. The charge pump circuit 105 alternately repeats state X and state Y shown in FIG. 12 according to clock signals CLK1 to CLK7 based on complementary reference clocks CLKa and CLKb.

12 and 10, in state X, reference clock CLKb (clock signals CLK2 to CLK5) is at H level, while reference clock CLKa (clock signals CLK1, CLK6 and CLK7) is at L level. Therefore, switch drive circuits 21 and 25 output an L level voltage (ground voltage GND) to nodes N4 and N6, while switch drive circuit 11 outputs an H level voltage (output voltage VOUT) to node N3. . As a result, regarding the plurality of switch elements, the transistors PMOS18 and PMOS6 are turned on, while the transistor PMOS5 is turned off.

On the other hand, since the inverter drive circuits 26 and 27 output the H level voltage (input voltage VIN), the inverter 32 connects the node N8 to the ground node Ng (ground voltage GND) by turning on the transistor NMOS14. On the other hand, since the inverter drive circuits 13 and 14 output the L level voltage (input voltage VIN), the inverter 20 connects the node N2 to the node Np0 (input voltage VIN) by turning on the transistor PMOS7.

Therefore, in state X, node Np3 is connected to input terminal 5 (input voltage VIN), while being disconnected from output terminal 10 and node Np1. Furthermore, the capacitor C1 is charged by the input voltage VIN by being connected between the node Np3 and the ground node Ng. Therefore, the capacitor voltage V(C1)=VIN. Capacitor C2 is connected between node Np1, which is connected to output terminal 10 by transistor PMOS6, and node Np0. Therefore, using the voltage V(C2) of capacitor C1 at that time, VOUT=VIN+V(C2) is shown.

In contrast, in state Y, reference clock CLKb (clock signals CLK2 to CLK5) is at L level, while reference clock CLKa (clock signals CLK1, CLK6 and CLK7) is at H level. Therefore, switch drive circuits 21 and 25 output an H level (output voltage VOUT) to nodes N4 and N6, while switch drive circuit 11 outputs an L level voltage (ground voltage GND) to node N3. As a result, regarding the plurality of switch elements, the transistors PMOS18 and PMOS6 are turned off, while the transistor PMOS5 is turned on.

On the other hand, since the inverter drive circuits 26 and 27 output the L level voltage (ground voltage GND), the inverter 32 connects the node N8 to the node Np0 (input voltage VIN) by turning on the transistor PMOS22. On the other hand, since the inverter drive circuits 13 and 14 output the H level voltage (ground voltage GND), the inverter 20 connects the node N2 to the ground node Ng (ground voltage GND) by turning on the transistor NMOS5.

In state Y, nodes Np1 and Np3 connected by transistor PMOS5 are disconnected from input terminal 5 (input voltage VIN) and output terminal 10 (output voltage VOUT), respectively. Furthermore, capacitor C1 is connected between node Np0 (input terminal 5) and node Np3. Therefore, the voltage of node Np3 becomes VIN+V(C1). In the immediately preceding state X, the node Np3 is charged to V(C1)=VIN, so the voltage of the node Np3 is twice the input voltage VIN.

On the other hand, capacitor C2 is charged to a voltage equivalent to that of node Np3 by being connected between node Np1 and ground node Ng. Therefore, in state Y, V(C2)=V(C1)=2.VIN.

Next, in state X again, the capacitor C1 is charged to the input voltage VIN, and the output voltage VOUT becomes the sum of the input voltage VIN and the voltage V(C2) of the capacitor C2 at that time. In the previous state Y, since it is charged to V(C2)=2.VIN, it is understood that VOUT=VIN+V(C2)=3.VIN and the step-up ratio (VOUT/VIN) is 3. .

As described above, the charge pump circuit 105 according to the second embodiment alternately repeats the state X and the state Y according to the clock signals CLK1 to CLK7 based on the complementary reference clocks CLKa and CLKb, thereby reducing the input voltage VIN to 3 It is possible to execute a boosting operation that outputs double the output voltage VOUT.

In the charge pump circuit 105 according to the second embodiment, when the control signal ENB is set to H level (EN=L level) and the operation is stopped, if the precharge signal PR is at L level, that is, during a period other than the precharge period. Now, by turning on the transistor NMOS7, the output voltage VOUT can be lowered to the ground voltage GND.

Further, in the switch drive circuit 21, the transistor PMOS11 is turned off while the transistor PMOS12 is turned on. As a result, the input voltage VIN is supplied to the node Ns by the transistor PMOS11. Therefore, by fixing the clock signal CLK2 to L level, the input voltage VIN can be output to the node N4, that is, the gate of the transistor PMOS6 via the transistor PMOS2. As a result, the transistor PMOS5 can be turned off as in the first embodiment.

In addition, since the transistor PMOS13 is turned off by the switch drive circuit 30, the current path via the body (backgate) of the transistor PMOS5 is blocked by the reverse voltage blocking by the parasitic diode D23 of the transistor PMOS13, which is the "backgate cutoff switch element". blocked. As a result, the current path from the input terminal 5 to the output terminal 10 can be cut off, as in the first embodiment.

As a result, in the charge pump circuit 105 according to the second embodiment, as in the first embodiment, the current from the input terminal 5 to the output terminal 10 is cut off when the operation is stopped (ENB=H, EN=L). At the same time, the output terminal 10 can be discharged to lower the output voltage VOUT to the ground voltage GND.

Also in the charge pump circuit 105 according to the second embodiment, as described in the first and second modifications of the first embodiment, among the plurality of switch elements, the transistors PMOS18, PMOS5, and PMOS6, A switch drive circuit configured to use the input voltage VIN as an inverter power supply when the output voltage VOUT drops, like the switch drive circuit 21 (i.e., a "first switch drive circuit") for at least one of , and a transistor (PMOS 13 in FIG. 12) serving as a “back gate disconnecting switch element” and its drive circuit (switch drive circuit 30) can be arranged.

Furthermore, in the second embodiment, the charge pump circuit with a step-up ratio of 3 has been described, but the first embodiment and its modifications can be similarly applied to a charge pump circuit with a higher step-up ratio. be. For such a charge pump circuit as well, for at least one of the plurality of switch elements connected in series between the input terminal 5 and the output terminal 10, the above-described "first switch drive circuit" and By arranging the "back gate disconnect switch element", the "back gate disconnect switch drive circuit", and the "discharge element", it is possible to prevent the occurrence of overcurrent when the output voltage VOUT drops due to the occurrence of a ground fault or the like. It is possible.

The charge pump circuits 101 to 105 according to the first embodiment, its modification, and the second embodiment described above can be applied to a semiconductor device. For example, as shown in FIG. 13, a semiconductor device 200 includes a power supply circuit 202, a semiconductor circuit 210 including a semiconductor element 215, and a charge pump circuit according to any one of the first to fourth embodiments. Semiconductor element 215 is typically composed of a transistor or a diode. The power supply circuit 202 can generate a stable voltage VDD from the power supply voltage Vp externally supplied to the semiconductor device 200 . The charge pump circuits 101 to 105 output the voltage VBB as the output voltage VOUT by performing a boosting operation using the voltage VDD from the power supply circuit 202 as the input voltage VIN. Since both the voltage VDD and the voltage VBB are supplied to the semiconductor circuit 210 as power supply voltages, the semiconductor element 215 can operate by receiving the boosted voltage VBB, which is the output voltage of the charge pump circuits 101-105.

It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

5 input terminals, 10 output terminals, 11, 12, 21, 23, 25, 30 switch drive circuit, 13, 14, 26, 27 inverter drive circuit, 20, 32 inverter, 60 P-type substrate, 61, 71 N well, 62, 63, 72, 73 P+ region, 64, 74 gate, 65, 75 N+ region, 100, 101 to 105 charge pump circuit, 200 semiconductor device, 202 power supply circuit, 210 semiconductor circuit, 215 semiconductor element, C1, C2 capacitor , CLK1 to CLK7 clock signal, CLKa, CLKb reference clock, D1 to D12, D21 to D37 parasitic diode, GND ground voltage, N2 to N6, N8, Np0 to Np3, Ns node, NMOS1 to NMOS5, NMOS11 to NMOS22 N-channel type Transistors, PMOS1 to PMOS7, PMOS11 to PMOS22 P-channel transistors, Ng ground node, VBB, VDD voltages, VIN input voltage, VOUT output voltage.

Claims (6)

A charge pump circuit that generates an output voltage by boosting an input voltage,
an input terminal to which the input voltage is input;
an output terminal for outputting the output voltage;
a plurality of first P-type transistors connected in series between the input terminal and the output terminal and constituting a plurality of switch elements, respectively;
a capacitor connected to each connection point of two adjacent switch elements among the plurality of switch elements;
a discharge element that discharges the output terminal by being turned on when the charge pump circuit is in an operation stop state;
In at least one first P-type transistor among the plurality of first P-type transistors, a back gate and a main electrode on the output terminal side of two main electrodes of the first P-type transistor a backgate disconnect switch element connected between
a back gate disconnect switch drive circuit that turns on the back gate disconnect switch element in a boost operation state of the charge pump circuit, and turns off the back gate disconnect switch element in the operation stop state ,
In the second P-type transistor constituting the back gate disconnecting switch element, the parasitic diode of the second P-type transistor has a polarity opposite to the parasitic diode of the first P-type transistor to which it is connected. and a charge pump circuit configured to be connected in series. the capacitor has a first terminal connected to the connection point and a second terminal facing the first terminal;
The charge pump circuit is
In the boosting operation state, according to one of first and second clocks which are set to logic levels complementary to each other, the reference voltage and the output are applied to the control electrodes of the plurality of first P-type transistors. a plurality of switch drive circuits that selectively output one of the voltages to control on/off of the plurality of switch elements;
a voltage selection circuit that selectively outputs one of the reference voltage and the input voltage to the second terminal of the capacitor according to the first or second clock;
The second P-type transistor is
a first main electrode connected to the back gate of the first P-type transistor;
a second main electrode connected to the main electrode on the output terminal side of the first P-type transistor;
a back gate of the second P-type transistor is connected to the first main electrode;
Of the plurality of switch drive circuits, at least one first switch drive circuit corresponding to the at least one first P-type transistor to which the back gate disconnecting switch element is connected is connected to the first P-type transistor. In the boost operation state, one of the reference voltage and the output voltage is selectively input to the control electrode of the type transistor according to the logic level of the one clock, while in the operation stop state, the reference voltage and the output voltage are selectively input. 2. The charge pump circuit according to claim 1 , selectively inputting one of said input voltages . The first switch drive circuit includes:
said control electrode of said first P-type transistor connected between a power supply node and a reference voltage node transmitting said reference voltage and constituting a corresponding switch element according to said first or second clock; a signal transmission circuit selectively connecting one of the power supply node and the reference voltage node to an output node connected to
is connected between the power supply node and the input terminal and the output terminal, and connects the output terminal and the power supply node in the boost operation state, and connects the input terminal and the input terminal in the operation stop state. a voltage switching circuit connected to the power supply node,
wherein said first or second clock input to said first switch drive circuit is fixed to a logic level at which said signal transmission circuit connects said output node with said power supply node in said operation stop state. 3. A charge pump circuit according to item 2. A precharge period is provided for charging the output terminal with the input voltage of the input terminal when the charge pump circuit transitions from the operation stop state to the boost operation state,
During the precharge period, the discharge element is turned off, and the first switch drive circuit applies the reference voltage to turn on the first P-type transistor constituting each of the plurality of switch elements. 4. The charge pump circuit according to claim 2, which outputs. the backgate disconnect switch element is connected to each of two or more switch elements among the plurality of switch elements;
Each of the back gate disconnecting switch elements is turned on in the boosting operation state by supplying an output voltage from the common back gate disconnecting switch driving circuit to the control electrode of the second P-type transistor. 5. The charge pump circuit according to claim 2, wherein said charge pump circuit is turned off in said operation stop state . a charge pump circuit according to any one of claims 1 to 5;
and a semiconductor element that operates upon receiving the output voltage of the charge pump circuit.

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