JP7191124B2 - Charge pump circuit and semiconductor device - Google Patents

Description

The present invention relates to a charge pump circuit and a semiconductor device having the same.

A charge pump circuit described in Japanese Patent Application Laid-Open No. 2009-183111 (Patent Document 1) is known as a circuit that obtains an output voltage obtained by boosting an input voltage of an input terminal at an output terminal. The charge pump circuit connects a plurality of switch elements (drive transistors T1 and T4 in Patent Document 1) in series between an input terminal and an output terminal, and repeats on/off switching of the plurality of switch elements. Specifically, the capacitor is charged with the input voltage in the first period in which some of the switch elements are turned on while the remaining switch elements are turned off, and the on/off state of the plurality of switch elements is switched in the second period. , the boosting operation is realized by applying the sum of the input voltage and the capacitor voltage to the output voltage.

In such a charge pump circuit, when the output terminal is grounded, a plurality of switch elements in the path from the input terminal to the output terminal are turned on, causing an overcurrent. In order to prevent such an overcurrent, in Patent Document 1, when an output terminal is grounded, an output current is applied to the gates of a plurality of switching elements (P-type transistors) connected from the input terminal to the output terminal. A circuit configuration for forcibly inputting an off voltage (power supply voltage Vdd) by a protection transistor that is turned on according to a voltage drop is described.

Japanese Patent Application Laid-Open No. 2009-183111

However, in Patent Document 1, even if a plurality of switch elements are forcibly turned off, a current path is formed between the input terminal and the output terminal via the parasitic diode of each switch element (P-type transistor). , it is difficult to prevent overcurrent from flowing from the input terminal to the output terminal. In Patent Document 1, by connecting a protective resistor to the back gate of each switch element, the amount of current in the current path via the parasitic diode is suppressed, but the current path may be continuously formed. Concerned.

Further, in Patent Document 1, the OFF voltage supplied to each gate of the plurality of switch elements via the protection transistor is common to the power supply voltage applied to the input terminal. Therefore, when a ground fault occurs in the output terminal, there is concern that the gate voltages of the switch elements may drop due to the power supply voltage dropping due to the current flowing through the parasitic diodes of the switch elements. Normally, the size of a plurality of switching elements between an input terminal and an output terminal is designed to be large in order to ensure current driving capability, so the voltage drop due to parasitic diodes tends to increase. For this reason, there is a concern that a decrease in the gate voltage supplied by the protection transistor may result in insufficient cutoff of the current path by the plurality of switch elements.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and an object of the present invention is to prevent an overcurrent from flowing from an input terminal to an output terminal when the output terminal is grounded. It is another object of the present invention to provide a configuration of a charge pump circuit capable of

In one aspect of the present invention, a charge pump circuit that boosts an input voltage to generate an output voltage includes an input terminal to which the input voltage is input, an output terminal to output the output voltage, and a plurality of first P-type transistors. , a plurality of switch drive circuits, a capacitor, a voltage selection circuit, a backgate disconnect switch element, and a backgate disconnect switch drive circuit. A plurality of first P-type transistors are connected in series between the input terminal and the output terminal, and constitute a plurality of switch elements, respectively. The plurality of switch drive circuits selectively apply one of the reference voltage and the output voltage to the control electrode of each of the plurality of first P-type transistors according to one of complementary first and second clocks. output to control on/off of a plurality of switch elements. The capacitor has first and second terminals, and the first terminal is connected to a connection point between two adjacent switch elements among the plurality of switch elements. The voltage selection circuit selectively outputs one of the reference voltage and the input voltage to the second terminal of the capacitor according to the first or second clock. The backgate disconnecting switch element includes a backgate of at least one first P-type transistor among the plurality of first P-type transistors and an output terminal of the two main electrodes of the first P-type transistor. connected between the main electrodes on the side. The back gate disconnect switch drive circuit changes the back gate disconnect switch element from on to off when the output voltage drops. The second P-type transistor constituting the backgate disconnecting switch element has a first main electrode connected to the backgate of the first P-type transistor and a main electrode on the output terminal side of the first P-type transistor. and a connected second main electrode. A back gate of the second P-type transistor is connected to the first main electrode. Of the plurality of switch drive circuits, at least one first switch drive circuit corresponding to at least the first P-type transistor to which the back gate disconnecting switch element is connected is configured to reduce the output voltage when the output voltage drops. instead of selectively outputting the input voltage to the control electrode of the first P-type transistor.

According to the above charge pump circuit, even when the output terminal is grounded and the output voltage drops, the input voltage is supplied to the gate of the first P-type transistor by the first switch driving circuit, and the second Since the parasitic diode formed in the P-type transistor can avoid the continuous formation of a current path from the input terminal to the output terminal, the occurrence of overcurrent can be prevented.

FIG. 3 is a circuit diagram illustrating the configuration of a charge pump circuit according to a comparative example; 4 is a waveform diagram of a clock signal input to the charge pump circuit; FIG. 2 is a chart for explaining the boosting operation of the charge pump circuit shown in FIG. 1; FIG. 2 is a circuit diagram illustrating a configuration example of a charge pump circuit according to Embodiment 1; FIG. 5 is a conceptual cross-sectional view for explaining a current blocking structure of a switch element in the charge pump shown in FIG. 4; FIG. FIG. 4 is a circuit diagram illustrating the configuration of a charge pump circuit according to a first modification of the first embodiment; FIG. 8 is a circuit diagram illustrating the configuration of a charge pump circuit according to a second modification of the first embodiment; FIG. 11 is a circuit diagram illustrating a configuration example of a charge pump circuit according to a second embodiment; FIG. 11 is a circuit diagram illustrating a configuration example of a charge pump circuit according to a third embodiment; 10 is a block diagram illustrating a configuration example of an output ground fault detection circuit shown in FIG. 9; FIG. FIG. 10 is a circuit diagram illustrating a configuration example of a charge pump circuit in which the second embodiment and the third embodiment are combined; FIG. 11 is a circuit diagram illustrating a configuration example of a charge pump circuit according to a fourth embodiment; 13 is a waveform diagram of a clock signal input to the charge pump circuit shown in FIG. 12; FIG. 13 is a chart for explaining the operation of the charge pump circuit shown in FIG. 12; FIG. 1 is a schematic block diagram of a semiconductor device including a charge pump circuit according to an embodiment; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Below, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same reference numerals are given to the same or corresponding parts in the drawings, and the description thereof will not be repeated in principle.

Embodiment 1.
(Description of Comparative Example)
First, the configuration of a general charge pump circuit will be described as a comparative example of this embodiment.

FIG. 1 is a circuit diagram illustrating the configuration of a charge pump circuit according to a comparative example. As will be clear from the following description, the basic circuit operation (boosting operation) of the charge pump circuit 100 according to the comparative example is the same as that of the charge pump circuit according to the present embodiment, which will be described later. The charge pump circuit 100 has the same problem as that of Japanese Patent Laid-Open No. 2002-100019 regarding the function of interrupting the short-circuit current when the output terminal is grounded.

Referring to FIG. 1, a charge pump circuit 100 according to the comparative example includes an input terminal 5, an output terminal 10, and "a plurality of switch elements" connected in series between the input terminal 5 and the output terminal 10. It includes P-channel type (also simply referred to as P-type) transistors PMOS5 and PMOS6, switch drive circuits 11 and 12, an inverter 20, inverter drive circuits 13 and 14, and a capacitor C1. Hereinafter, the voltage at the input terminal 5 will be referred to as the input voltage VIN, and the voltage at the output terminal 10 will be referred to as the output voltage VOUT.

Each of clock signals CLK1-CLK4 shown in FIG. ”) is repeated at regular intervals.

Transistor PMOS5 is electrically connected between node Np0 connected to input terminal 5 and node Np1. The gate of transistor PMOS5 is connected to output node N3 of switch drive circuit 11 . Transistor PMOS5 has a parasitic diode D9 of the polarity shown in FIG. 1 by connecting its backgate to node Np1.

Transistor PMOS6 is electrically connected between node Np1 and node Np2 connected to output terminal . The gate of transistor PMOS6 is connected to output node N4 of switch drive circuit 12 . Transistor PMOS6 has a parasitic diode D10 of the polarity shown in FIG. 1 by connecting its backgate to node Np2.

The switch drive circuit 11 has a P-type transistor PMOS1 and an N-channel (also simply referred to as N-type) transistor NMOS1 connected in series via a node N3 between a node Np2 and a ground node Ng. A clock signal CLK1 is commonly input to the gates of the transistors PMOS1 and NMOS1. Ground node Ng supplies a reference voltage (typically ground voltage GND).

Similarly, the switch driving circuit 12 has a P-type transistor PMOS2 and an N-type transistor NMOS2 connected in series via a node N4 between the node Np2 and the ground node Ng. A clock signal CLK2 is commonly input to the gates of the transistors PMOS2 and NMOS2.

The switch drive circuits 11 and 12 constitute inverters that use the output voltage VOUT and the ground voltage GND as power sources and receive the clock signals CLK1 and CLK2 as inputs. Transistors PMOS1 and NMOS1 have parasitic diodes D1 and D2 of the polarities shown in FIG. 1 by connecting their backgates to node Np2 and ground node Ng, respectively. Similarly, transistors PMOS2 and NMOS2 have parasitic diodes D3 and D4 of the polarities shown in FIG. 1 by connecting their back gates to node Np2 and ground node Ng, respectively.

The inverter 20 has a P-type transistor PMOS7 and an N-type transistor NMOS5 connected in series via a node N2 between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND). Node N2 is connected to node Np1 via capacitor C1.

The gate of transistor PMOS7 is connected to the output node of inverter drive circuit 13 to which clock signal CLK3 is input. The gate of transistor NMOS5 is connected to the output node of inverter drive circuit 14 to which clock signal CLK4 is input. Transistors PMOS7 and NMOS5 have parasitic diodes D11 and D12 of the polarities shown in FIG. 1 by connecting their back gates to node Np0 and ground node Ng, respectively.

The inverter drive circuit 13 includes P-type transistors PMOS3 and PMOS3 connected in series between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor PMOS7. It has an N-type transistor NMOS3. A clock signal CLK3 is commonly input to the gates of the transistors PMOS3 and NMOS3.

Similarly, the inverter drive circuit 14 is a P-type inverter connected in series between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor NMOS5. It has a transistor PMOS4 and an N-type transistor NMOS4. A clock signal CLK4 is commonly input to gates of the transistors PMOS4 and NMOS4.

The inverter drive circuits 13 and 14 constitute inverters that use the input voltage VIN and the ground voltage GND as power sources and receive the clock signals CLK3 and CLK4 as inputs. Transistors PMOS3 and NMOS3 have parasitic diodes D5 and D6 of the polarities shown in FIG. 1 by connecting their backgates to node Np0 and ground node Ng, respectively. Similarly, transistors PMOS4 and NMOS4 have parasitic diodes D7 and D8 of the polarities shown in FIG. 1 by connecting their backgates to node Np0 and ground node Ng, respectively.

FIG. 2 is a waveform diagram of clock signals CLK1 to CLK4 input to the charge pump circuit 100. As shown in FIG.

Referring to FIG. 2, clock signal CLK1 and clock signals CLK2-CLK4 are in opposite phase, and clock signals CLK2-CLK4 are in phase. However, between the edges of the clock signals CLK1 to CLK4, a time difference (so-called dead time equivalent) is provided to prevent through current due to simultaneous conduction of a plurality of transistors.

For example, the clock signals CLK1 to CLK4 can be generated by not giving the dead time to the reference clocks CLKa and CLKb having phases opposite to each other. Although the dead time is usually several (ns) to several tens (ns), it is exaggerated with respect to the clock period in FIG.

FIG. 3 shows a chart for explaining the boosting operation of the charge pump circuit 100. As shown in FIG. The charge pump circuit 100 alternately repeats state 1 and state 2 shown in FIG. 3 according to clock signals CLK1-CLK4 based on complementary reference clocks CLKa and CLKb.

3 and 1, in state 1, reference clock CLKa (clock signal CLK1) is at H level, while reference clock CLKb (clock signals CLK2 to CLK4) is at L level. Therefore, the switch drive circuit 11 outputs an L level voltage (ground voltage GND) to the node N3. On the other hand, switch driving circuit 12 outputs an H level voltage (output voltage VOUT) to node N4. As a result, regarding the plurality of switch elements, the transistor PMOS6 is turned off while the transistor PMOS5 is turned on.

Further, since the inverter drive circuits 13 and 14 output the input voltage VIN, the transistor PMOS7 is turned off and the transistor NMOS5 is turned on. Therefore, inverter 20 connects node N2 to ground node Ng. As a result, in state 1, the node Np1 is connected to the input terminal 5 (input voltage VIN) and disconnected from the output terminal 10. FIG. Furthermore, the capacitor C1 is charged by the input voltage VIN by being connected between the node Np1 and the ground node Ng. Therefore, the capacitor voltage V(C1)=VIN.

In contrast, in state 2, clock signal CLK1 (reference clock CLKa) is at L level, while clock signals CLK2 to CLK4 (reference clock CLKb) are at H level. Therefore, the node N3, that is, the gate voltage of the transistor PMOS5 becomes the output voltage VOUT, and the node N4, that is, the gate voltage of the transistor PMOS6 becomes the ground voltage GND. As a result, in the plurality of switch elements, the transistor PMOS6 is turned on, while the transistor PMOS5 is turned off.

Further, since the inverter drive circuits 13 and 14 output the ground voltage GND, the transistor PMOS7 is turned on and the transistor NMOS5 is turned off. Therefore, inverter 20 connects node N2 to node Np0. As a result, in state 2, node Np1 is connected to output terminal 10 while being disconnected from input terminal 5 (input voltage VIN). Further, capacitor C1 is connected between input terminal 5 (node Np0) and node Np1. Therefore, the output voltage VOUT at the output terminal 10 is the sum of the input voltage VIN and the capacitor voltage V(C1), ie twice the input voltage VIN.

The charge pump circuit 100 alternately repeats State 1 and State 2 according to the clock signals CLK1 to CLK4, thereby performing a boosting operation that outputs an output voltage VOUT that is twice the input voltage VIN.

Next, the operation of the charge pump circuit 100 according to the comparative example when the output terminal 10 is grounded and the output voltage VOUT drops to near the ground voltage GND will be described.

When the output voltage VOUT of the node Np2 drops, the switch drive circuits 11 and 12 can only supply voltages lower than the input voltage VIN to the gates of the transistors PMOS5 and PMOS6. Therefore, the transistors PMOS5 and PMOS6 cannot be turned off, and the transistors PMOS5 and PMOS6, which are a plurality of switch elements connected between the input terminal 5 and the output terminal 10, are both turned on.

Since the element size of the transistors PMOS5 and PMOS6, which constitute a plurality of switch elements, is directly related to the current capability of the charge pump circuit 100, it is generally designed to be large so that a large current can flow. Therefore, if both the transistors PMOS5 and PMOS6 are turned on, there is concern that overcurrent will occur in the path from the input terminal 5 to the output terminal 10 .

Further, since the element sizes of the parasitic diodes D9 and D10 increase in conjunction with the element sizes of the transistors PMOS5 and PMOS6, the amount of current that can flow through the parasitic diodes D9 and D10 also increases. Therefore, when a ground fault occurs at the output terminal 10, there is concern that an overcurrent may flow from the input terminal 5 to the output terminal 10 also through the path through the parasitic diodes D9 and D10.

(Description of Embodiment 1)
FIG. 4 is a circuit diagram illustrating a configuration example of the charge pump circuit according to the first embodiment.

Referring to FIG. 4, charge pump circuit 101 according to the first embodiment performs the same boosting operation as charge pump circuit 100 according to the comparative example, and at the same time, the output voltage is reduced due to the occurrence of a ground fault at output terminal 10 or the like. It has an overcurrent prevention function when the voltage VOUT drops.

Compared to the charge pump circuit 100 of the comparative example, the charge pump circuit 101 according to the first embodiment has a transistor PMOS13 connected to the back gate of the transistor PMOS5, which is a switch element, and a switch drive for controlling on/off of the transistor PMOS13. and circuit 30 . Further, the charge pump circuit 101 according to the first embodiment includes a switch drive circuit 21 instead of the switch drive circuit 12 in the charge pump circuit 100 of the comparative example. The switch drive circuit 21 controls on/off of the transistor PMOS6, which is a switch element to which the transistor PMOS13 is connected.

Since the configuration of other portions of charge pump circuit 101 according to the first embodiment is similar to that of charge pump circuit 100 (FIG. 1) according to the comparative example, detailed description thereof will not be repeated. In the configuration example of FIG. 4, the transistors PMOS5 and PMOS6 correspond to an example of a "first P-type transistor" constituting "a plurality of switch elements", and the transistor PMOS13 serves as a "back gate disconnect switch element". This corresponds to an embodiment of the "second P-type transistor" to be constructed. Also, the switch drive circuit 30 corresponds to an embodiment of the "back gate disconnection switch element drive circuit". Furthermore, the node Np1 corresponds to a "connection point" between two adjacent switch elements, and the inverter drive circuits 13 and 14 and the inverter 20 constitute an example of a "voltage selection circuit".

The transistor PMOS13 is connected between the back gate of the transistor PMOS6 and the main electrode (source in FIG. 4) on the output terminal 10 side of the two main electrodes (source and drain) of the transistor PMOS6.

FIG. 5 shows a conceptual cross-sectional view of the transistors PMOS6 and PMOS13 for explaining the current blocking structure of the charge pump circuit 101. As shown in FIG.

Referring to FIG. 5, N-well 61 and N-well 71 are formed in P-type substrate 60 . Transistor PMOS 6 has P+ regions 62 and 63 and an N+ region 65 formed in N-well 61 . P+ regions 62 and 63 correspond to the first and second main electrodes (source and drain, respectively) of transistor PMOS6. N+ region 65 corresponds to the back gate of transistor PMOS6. The transistor PMOS6 further has a gate 64 corresponding to a control electrode formed directly above the channel region between the P+ regions 62 and 63 with an insulating film interposed therebetween.

Similarly, transistor PMOS13 has P+ regions 72 and 73, gate 74, and N+ region 75 formed in N-well 71. FIG. P+ regions 72 and 73 correspond to the first and second main electrodes (one of the source and drain, respectively) of transistor PMOS13, and N+ region 75 corresponds to the back gate of transistor PMOS13. Gate 64 corresponds to the control electrode of transistor PMOS13.

In transistor PMOS6, P+ region 63 is connected to node Np2 (that is, output terminal 10), and P+ region 62 is connected to node Np1 connected to capacitor C1. Gate 64 is connected to node N4 receiving the output of switch driving circuit 21. FIG. In transistor PMOS 6, P+ region 62 and P+ region 63 correspond to one embodiment of a "main electrode", in particular P+ region 63 corresponds to the "main electrode" on the output terminal 10 side.

In transistor PMOS13, P+ region 73 is connected to node Np2 (that is, P+ region 63 of transistor PMOS6), and gate 74 is connected to node N5 which receives the output of switch drive circuit 30. FIG. P+ region 72 is connected to N+ region 75 and N+ region 65 of transistor PMOS6. As a result, in the transistor PMOS13, a PN junction between the P+ region 73 connected to the output terminal 10 and the N well 71 forms a parasitic diode. Similarly, in transistor PMOS13, a PN junction between P+ region 62 connected to node Np1 and N well 61 forms a parasitic diode. Also, the bodies (back gates) of the PMOS 6 and PMOS 13 are electrically connected to each other. That is, in the transistor PMOS13, which is an embodiment of the "second P-type transistor," the P+ region 72 corresponds to an embodiment of the "first main electrode," and the P+ region 73 is the "second main electrode." , and N+ region 75 corresponds to an embodiment of "backgate."

Referring to FIG. 4 again, a path is formed between the main electrodes of the transistor PMOS6 by the parasitic diode D10 of PMOS6, the body (backgate) of PMOS6 and PMOS13, and the parasitic diode D23 of PMOS13. By establishing the connection relationship described in FIG. 5 on the path including the back gate, the parasitic diodes D10 and D23 are connected in series with opposite polarities.

The switch drive circuit 30 has a P-type transistor PMOS14 and an N-type transistor NMOS11 connected in series via a node N5 between a node Np0 and a ground node Ng. The gates of the transistors PMOS14 and NMOS11 are commonly connected to the node Np2 (output terminal 10).

The switch drive circuit 30 constitutes an inverter that uses the input voltage VIN and the ground voltage GND as power sources and receives the output voltage VOUT as an input. Transistors PMOS14 and NMOS11 have parasitic diodes D24 and D25 of the polarities shown in FIG. 4 by connecting their backgates to node Np1 and ground node Ng, respectively. As described above, the output node N5 of the switch drive circuit 30 is connected to the gate of the transistor PMOS13.

The switch drive circuit 21 further includes transistors PMOS11 and PMOS12 in addition to the inverter-connected transistors PMOS2 and NMOS2 as in the switch drive circuit 12 of FIG. The transistor PMOS11 is connected between a node Np0 (input voltage VIN) and a node Ns corresponding to the source of the transistor PMOS2. The transistor PMOS12 is connected between the node Np2 (output voltage VOUT) and the node Ns (transistor PMOS2). The gate of transistor PMOS11 is connected to node Np2 (output voltage VOUT). The gate of transistor PMOS12 is connected to node Np0 (input voltage VIN). The transistors PMOS11 and NMOS12 have the parasitic diodes D21 and D22 of the polarities shown in FIG. 4 by connecting their backgates in common with the node Ns.

Therefore, the switch drive circuit 21 operates as an inverter using the input voltage VIN as the power supply voltage when the transistor PMOS11 is on, and operates as an inverter using the output voltage VOUT as the power supply voltage when the transistor PMOS12 is on. An output node N4 of the inverter is connected to the gate of transistor PMOS6.

Clock signals CLK1 to CLK4 (FIG. 2) similar to those of the charge pump circuit 100 of the comparative example are input to the switch drive circuits 11 and 21 and the inverter drive circuits 13 and 14 of the charge pump circuit 101, respectively.

In the charge pump circuit 101, before the boost operation starts, the output voltage VOUT is lower than the input voltage VIN by the amount of forward voltage drop caused by the parasitic diodes D9 and D10. Therefore, the transistors PMOS11 and PMOS12 are off, and the voltage of the source (node Ns) of the transistor PMOS2 is supplied via the parasitic diode D21 of the transistor PMOS11.

Since the transistor PMOS13 is kept on during the boosting operation, the body (backgate) of the transistor PMOS6 is connected to the source (that is, the main electrode on the output terminal 10 side) as in FIG. Furthermore, in the switch driving circuit 21, the gate-source voltage of the transistor PMOS12 increases as the output voltage VOUT rises, thereby turning on the transistor PMOS12. As a result, the output voltage VOUT is supplied to the source (node Ns) of the transistor PMOS2 via the transistor PMOS12, so that the switch drive circuit 21 operates in the same manner as the switch drive circuit 12 in FIG.

Therefore, in the charge pump circuit 101 as well, states 1 and 2 shown in FIG. 3 are repeated in response to the clock signals CLK1 to CLK4 (FIG. 2) based on the reference clocks CLKa and CLKb. A boosting operation is performed to raise the voltage up to twice the input voltage VIN. That is, the reference clocks CLKa and CLKb correspond to an example of "mutually complementary first and second clocks".

When the output terminal 10 of the charge pump circuit 101 is grounded, the output voltage VOUT drops to near the ground voltage GND and becomes lower than the input voltage VIN. As a result, the transistor PMOS12 is turned off while the transistor PMOS11 is turned on, so that the input voltage VIN is supplied to the source (node Ns) of the transistor PMOS2 via the transistor PMOS11.

Since the source voltage of the transistor PMOS11 is not the output voltage VOUT but the input voltage VIN, the inverter composed of the transistors PMOS2 and NMOS2 supplies H to the gate of the transistor PMOS6 from the node N4 during the L level period of the clock signal CLK2. The input voltage VIN can be output as the level voltage. As a result, even the transistor PMOS6 whose source voltage has dropped to near the ground voltage GND due to the ground fault can be turned off by inputting the input voltage VIN to the gate. Thereby, an OFF period of the transistor PMOS6 can be provided. Thus, among the plurality of switch drive circuits 11 and 21, the switch drive circuit 21 realizes the function of the "first switch drive circuit". In the switch drive circuit 21, the transistors PMOS11 and PMOS12 form an embodiment of a "voltage switching circuit", and the inverters of the transistors PMOS2 and NMOS2 form an embodiment of a "signal transmission circuit".

Furthermore, in the switch drive circuit 21, when the output terminal 10 is grounded, the current between the node Ns to which the input voltage VIN is supplied via the transistor PMOS11 and the grounded output terminal 10 (node Np2) The path is blocked by the parasitic diode D22 of transistor PMOS12. Also, in the switch drive circuit 11, there is no configuration for forcibly supplying the off voltage to the node N3. Therefore, in each of the switch drive circuits 11 and 21, even if the output terminal 10 is grounded, a current path toward the output terminal 10 is not formed inside.

On the other hand, in Patent Document 1, when a ground fault occurs in the output terminal, the off voltage of the drive transistor is supplied to the gate of the drive transistor via the protection transistor. Therefore, inside the drive circuit of the drive transistor, a current path is formed from the gate of the drive transistor (that is, the output node of the drive circuit) toward the output terminal (ground fault occurrence) that is also connected to the drive circuit. There is fear. Typically, the drive circuit is composed of an inverter like the switch drive circuit 11 in FIG. 4, so there is a possibility that the current path is formed by the parasitic diode D1 of the transistor PMOS1 in FIG. Therefore, the charge pump circuit 101 according to the first embodiment is also advantageous in that a current path leading to the output terminal 10 is not formed in each of the switch driving circuits 11 and 21 when the output terminal 10 is grounded. be.

Furthermore, in the switch drive circuit 30, when a ground fault occurs at the output terminal 10, the transistor PMOS14 is kept on, so that the input voltage VIN is output from the node N5 to the gate of the transistor PMOS13. This keeps the transistor PMOS13 off. At this time, the current path through the body (backgate) of the transistor PMOS6 is cut off by the reverse voltage blocking by the parasitic diode D23 of the transistor PMOS13, which is the "backgate disconnection switch element".

When the output voltage VOUT drops to near the ground voltage GND, there is concern that the L level voltage (ground voltage GND) will be fixedly output from the switch drive circuit 11 to the node N3 and the transistor PMOS5 will be kept on. be. However, the switch driving circuit 21 and the transistor PMOS 6 in which the transistor PMOS 13 is arranged can prevent the continuous formation of a current path from the input terminal 5 to the output terminal 10, thereby preventing the occurrence of overcurrent.

As a result, according to the charge pump circuit 101 according to the first embodiment, it is possible to perform the same boosting operation as the charge pump circuit 100 of the comparative example during normal operation (when no ground fault occurs at the output terminal 10). , it is possible to prevent the occurrence of overcurrent when the output voltage VOUT drops due to the occurrence of a ground fault at the output terminal 10 or the like.

Modification 1 of the first embodiment.
FIG. 6 is a circuit diagram illustrating the configuration of the charge pump circuit according to the first modification of the first embodiment.

Referring to FIG. 6, charge pump circuit 102 according to the first modification of the first embodiment is connected to the back gate of transistor PMOS6 which is a switch element, unlike charge pump circuit 100 according to the comparative example. and a switch drive circuit 30 for controlling on/off of the transistor PMOS17. Further, the charge pump circuit 102 includes a switch drive circuit 23 instead of the switch drive circuit 11 in the charge pump circuit 100 of the comparative example. The switch drive circuit 23 controls on/off of the transistor PMOS5, which is a switch element to which the transistor PMOS17 is connected.

The transistor PMOS17 is connected between the back gate of the transistor PMOS5 and the main electrode (the source in FIG. 6) on the output terminal 10 side of the two main electrodes of the transistor PMOS5. The connection relationship between the transistors PMOS17 and PMOS5 is the same as the connection relationship between the transistors PMOS13 and PMOS6 in FIGS. Therefore, the parasitic diode D9 of the transistor PMOS5 and the parasitic diode D28 of the transistor PMOS17 are connected in series with opposite polarities on the path through the body (backgate) between the main electrodes of the transistor PMOS6.

The configuration and operation of switch drive circuit 30 are the same as those in FIG. 4, and detailed description thereof will not be repeated. The output node N5 of the switch drive circuit 30 is connected to the gate of the transistor PMOS17.

The switch drive circuit 23 further includes transistors PMOS15 and PMOS16 in addition to the inverter-connected transistors PMOS1 and NMOS1 as in the switch drive circuit 12 of FIG. The transistor PMOS15 is connected between the node Np0 (input voltage VIN) and the node Ns corresponding to the source of the transistor PMOS1, like the transistor PMOS11 in FIG. Transistor PMOS16 is connected between node Np2 (output voltage VOUT) and node Ns (transistor PMOS1). The gate of transistor PMOS15 is connected to node Np2 (output voltage VOUT). The gate of transistor PMOS16 is connected to node Np0 (input voltage VIN). Transistors PMOS15 and NMOS16 have parasitic diodes D26 and D27 of the polarities shown in FIG. 6 by connecting their backgates in common with node Ns.

Therefore, like the switch drive circuit 21 in FIG. 4, the switch drive circuit 23 operates as an inverter using the input voltage VIN as the power supply voltage when the transistor PMOS15 is on, while the output voltage VOUT is used when the transistor PMOS16 is on. It operates as an inverter with power supply voltage. An output node N3 of the inverter is connected to the gate of transistor PMOS5. That is, in the configuration of FIG. 6, the function of the "first switch drive circuit" is realized by the switch drive circuit 23 among the plurality of switch drive circuits 23 and 12. In FIG. In the switch driving circuit 23, the transistors PMOS15 and PMOS16 form an embodiment of a "voltage switching circuit", and the inverters of the transistors PMOS1 and NMOS1 form an embodiment of a "signal transmission circuit". That is, the node Ns corresponds to an example of a "power supply node", and the ground node Ng corresponds to an example of a "reference voltage node".

Since the configuration of other portions of charge pump circuit 102 according to the first modification of the first embodiment is the same as that of charge pump circuit 100 (FIG. 1) according to the comparative example, detailed description thereof will not be repeated. Also in the configuration example of FIG. 6, the transistors PMOS5 and PMOS6 constituting a plurality of switch elements correspond to an embodiment of the "first P-type transistor", and the transistor PMOS17 constitutes the "back gate disconnection switch element". corresponds to an embodiment of the "second P-type transistor".

In the charge pump circuit 102 of FIG. 6, the switch drive circuits 23 and 30 and the transistor PMOS17 operate similarly to the switch drive circuits 21 and 30 and the transistor PMOS13 in FIG. 4 (charge pump circuit 101). As a result, the charge pump circuit 102 according to the first modification of the first embodiment, like the charge pump circuit 101 according to the first embodiment, performs a boosting operation similar to that of the charge pump circuit 100 of the comparative example. be able to.

In the charge pump circuit 102 of FIG. 6, when the output voltage VOUT drops due to the occurrence of a ground fault at the output terminal 10 or the like, the L level voltage (ground voltage GND) is fixedly output from the switch drive circuit 12 to the node N4, and the transistor There is concern that the PMOS 6 will remain on.

However, since the switch drive circuit 23 can supply the input voltage VIN to the node N4, that is, the gate of the transistor PMOS5, via the transistors PMOS15 and PMOS1, the input voltage VIN corresponds to the L level period of the clock signal CLK1. , an OFF period of the transistor PMOS5 can be provided. Further, when the transistor PMOS17 is kept off by the switch drive circuit 30, the current path through the body (backgate) of the transistor PMOS5 is a reverse voltage due to the parasitic diode D28 of the transistor PMOS17, which is the "backgate cutoff switch element". Blocked by blocking.

As described above, in the charge pump circuit 102 of FIG. 6, when the output voltage VOUT drops due to the occurrence of a ground fault at the output terminal 10 or the like, the switch driving circuit 23 and the transistor PMOS5 in which the transistor PMOS17 is arranged cause the input terminal 5 to the output terminal to Since it is possible to avoid the continuous formation of a current path to 10, the occurrence of overcurrent can be prevented.

As a result, in the modification of the first embodiment, the transistor PMOS17 is connected as a "back gate disconnecting switch element" to the transistor PMOS5 among the plurality of switch elements. It is possible to prevent the occurrence of overcurrent when the output voltage VOUT drops due to the occurrence of a ground fault at the output terminal 10 or the like.

Modified example 2 of the first embodiment.
FIG. 7 is a circuit diagram illustrating the configuration of a charge pump circuit according to a second modification of the first embodiment.

Referring to FIG. 7, in a charge pump circuit 103 according to the second modification of the first embodiment, compared with the charge pump circuit 100 according to the comparative example, the back gates of transistors PMOS5 and PMOS6 which are switch elements have It further comprises transistors PMOS13 and PMOS17 which are respectively connected, and a switch drive circuit 30 which controls on/off of the transistors PMOS13 and PMOS17. Further, the charge pump circuit 103 has the switch drive circuit 23 of FIG. 4 in place of the switch drive circuit 11 (FIG. 1) and the switch drive circuit 12 (FIG. ), it has the switch driving circuit 21 of FIG.

The connection relationship between the transistors PMOS13 and PMOS6 is the same as that described in the first embodiment (FIGS. 4 and 5), and the connection relationship between the transistors PMOS17 and PMOS5 is the same as that described in the first embodiment. It is the same as the modified example (FIG. 6). 4 and 6, the transistors PMOS13 and PMOS17 are turned on and off in common according to the voltage of the output node N5 of the switch drive circuit 30. be.

The switch drive circuit 21 controls on/off of the transistor PMOS6 with the same configuration and operation as in FIG. Similarly, the switch driving circuit 23 controls on/off of the transistor PMOS5 with the same configuration and operation as in FIG.

Since the configuration of other portions of charge pump circuit 103 according to the second modification of the first embodiment is the same as that of charge pump circuit 100 (FIG. 1) according to the comparative example, detailed description thereof will not be repeated. Also in the configuration example of FIG. 6, the transistors PMOS5 and PMOS6 correspond to an embodiment of the "first P-type transistor" constituting the "plurality of switch elements", and the transistors PMOS13 and PMOS17 correspond to the "back gate disconnect switch". This corresponds to an example of the "second P-type transistor" that constitutes the "element". Further, each of the plurality of switch drive circuits 21 and 23 has the function of "first switch drive circuit".

In the charge pump circuit 103 of FIG. 7, the switch drive circuits 21, 23, 30 and the transistors PMOS13 and PMOS17 operate in the same manner as described with reference to FIGS. As a result, the charge pump circuit 103 according to the second modification of the first embodiment, like the charge pump circuit 101 according to the first embodiment, performs the boosting operation similar to that of the charge pump circuit 100 of the comparative example. be able to.

Furthermore, when the output voltage VOUT drops due to the occurrence of a ground fault at the output terminal 10 or the like, the switch drive circuits 21 and 23 ensure the OFF period of the transistors PMOS5 and PMOS6 corresponding to the L level period of the clock signals CLK1 and CLK2. The reverse voltage blocking by the parasitic diodes D28 and D23 of the transistors PMOS17 and PMOS15 prevents the continuous formation of a current path from the input terminal 5 to the output terminal 10, thereby preventing overcurrent.

Thus, even with the configuration in which the transistors PMOS13 and PMOS17 are connected as "back gate disconnecting switch elements" to both the transistors PMOS5 and PMOS6 among the plurality of switch elements, the overcurrent when the output voltage VOUT drops can be avoided. It is possible to prevent it from occurring.

The charge pump circuits 101 to 103 shown in FIGS. 4, 6 and 7 apply a "back gate By connecting at least one of the transistors PMOS13 and PMOS17 as the "disconnecting switch element" and arranging at least one of the switch driving circuits 23 and 21 as the "first switch driving circuit", the output terminal It is understood that it is possible to provide an overcurrent prevention function when the output voltage VOUT drops due to the occurrence of a ground fault at 10 or the like.

Embodiment 2.
FIG. 8 is a circuit diagram illustrating a configuration example of a charge pump circuit according to the second embodiment.

Referring to FIG. 8, charge pump circuit 104 according to the second embodiment differs from charge pump circuit 101 (FIG. 4) according to the first embodiment in that clock control circuits 81 to 83 formed of logic gates are provided. is further provided.

The clock control circuit 81 is composed of an AND gate, and outputs the logical AND operation result of the clock signal CLK2 and the output voltage VOUT. The clock control circuit 82 is composed of a NAND gate and outputs the result of the NAND operation of the inverted signal of the clock signal CLK3 and the output voltage VOUT. Similarly, the clock control circuit 84 is composed of a NAND gate and outputs the result of the NAND operation of the inverted signal of the clock signal CLK4 and the output voltage VOUT.

The clock signal CLK2 processed by the clock control circuit 81 is input to the inverter configured by the transistors PMOS2 and NMOS2 in the switch drive circuit 21 . Similarly, the clock signal CLK3 processed by the clock control circuit 82 is input to the inverter configured by the transistors PMOS3 and NMOS3 in the inverter drive circuit 13 . Further, the clock signal CLK4 processed by the clock control circuit 83 is input to the inverter configured by the transistors PMOS4 and NMOS4 in the inverter drive circuit 14 . That is, the clock control circuit 81 corresponds to one embodiment of the "first clock control circuit", and the clock control circuits 82 and 83 correspond to one embodiment of the "second clock control circuit".

When the output voltage VOUT is normal (when no ground fault occurs at the output terminal 10), the terminals to which the output voltage VOUT of the logic gates forming the clock control circuits 81 to 83 are input are fixed at H level. Therefore, the clock control circuits 81 to 83 output signals having the same logic level as the clock signals CLK2 to CLK4. Therefore, the charge pump circuit 104 according to the second embodiment can perform the same boosting operation as the charge pump circuit 101 according to the first embodiment.

On the other hand, when the output voltage VOUT drops to near the ground voltage GND due to the occurrence of a ground fault at the output terminal 10 or the like, the output of the clock control circuit 81 (AND gate) is fixed at the L level voltage (ground voltage GND). . On the other hand, the outputs of the clock control circuits 82 and 83 (NAND gate) are fixed at the H level voltage (input voltage VIN).

As a result, the node N4 is maintained at the H level (input voltage VIN) by the switch drive circuit 21, so the transistor PMOS6 is fixed off. Similarly, the gate voltages of the transistors PMOS7 and NMOS5 are maintained at L level (ground voltage GND) by the inverter drive circuits 13 and 14, respectively. As a result, in the inverter 20, the transistor PMOS7 is fixedly turned on and the transistor NMOS5 is fixedly turned off, so that the node N2 is fixed at the input voltage VIN. As a result, even if the transistor PMOS5 is kept on due to a decrease in the output voltage VOUT, no voltage difference occurs between the terminals of the capacitor C1, so that the capacitor C1 can be prevented from being charged when a ground fault occurs.

Therefore, when the output voltage VOUT drops to near the ground voltage GND, even if the transistor PMOS5, whose L level voltage (ground voltage GND) is fixedly output from the switch drive circuit 11 to the node N3, is kept on, Clock control circuit 81 keeps transistor PMOS6 off. Furthermore, by turning off the transistor PMOS 13 as in the first embodiment, the current path from the input terminal 5 to the output terminal 10 can be cut off in the same manner as in the first embodiment. Further, by fixing the voltage of node N2, it is possible to more reliably prevent current from being generated inside charge pump circuit 104. FIG.

As described above, in the charge pump circuit 104 according to the second embodiment, when the output voltage VOUT drops to near the ground voltage GND due to the occurrence of a ground fault at the output terminal 10 or the like, the outputs of the clock control circuits 81 to 83 is fixed, it is possible to completely stop the boosting operation and reliably prevent the occurrence of overcurrent.

The charge pump circuit according to the second embodiment can be combined with the first modification (FIG. 6) and the second modification (FIG. 7) of the first embodiment. Specifically, when combined with the first modification of the first embodiment, in the configuration of FIG. 6, a logic gate (AND gate) similar to that of FIG. , the AND operation of the clock signal CLK1 and the output voltage VOUT can be commonly input to the gates of the transistors PMOS1 and NMOS1.

Similarly, in the configuration of FIG. 7, logic gates (AND gates) similar to those in FIG. The calculation can be configured to be input to the switch drive circuits 21 and 23 .

Embodiment 3.
FIG. 9 is a circuit diagram illustrating a configuration example of a charge pump circuit according to the third embodiment.

9, charge pump circuit 105 according to the third embodiment differs from charge pump circuit 101 (FIG. 4) according to the first embodiment in that an output ground fault detection circuit 50 is further provided. .

FIG. 10 is a block diagram illustrating a configuration example of output ground fault detection circuit 50 shown in FIG.

Referring to FIG. 10, output ground fault detection circuit 50 has voltage comparator 51 and level shifter 55 .

Voltage comparator 51 compares output voltage VOUT of output terminal 10 with a predetermined ground fault determination voltage VR. In the normal state where no ground fault occurs at the output terminal 10, the lower limit value of the output voltage VOUT is the sum of forward voltage drops from the input voltage VIN due to the parasitic diode D9 (PMOS5) and the parasitic diode D10 (PMOS6). It is a voltage (VIN-Vf) lower by Vf. Therefore, when the output voltage VOUT drops below the voltage (VIN-Vf), it can be detected that a ground fault has occurred at the output terminal 10. FIG. That is, the ground fault determination voltage VR can be determined corresponding to the voltage (VIN-Vf).

Voltage comparator 51 operates upon receiving input voltage VIN and ground voltage GND. Therefore, the output voltage of the voltage comparator 51 becomes the input voltage VIN (H level) when VOUT>VR, and becomes the ground voltage GND (L level) when VOUT<VR.

The level shifter 55 level-converts the output voltage of the voltage comparator 51 and outputs a voltage signal Vdet. The level shifter 55 sets the voltage signal Vdet to the output voltage VOUT of the output terminal 10 when the output of the voltage comparator 51 is at H level. On the other hand, level shifter 55 sets voltage signal Vdet to ground voltage GND when the output of voltage comparator 51 is at L level.

Therefore, the output ground fault detection circuit 50 sets the voltage signal Vdet to VOUT when the output terminal 10 is not grounded, that is, when VOUT>VR. That is, when VOUT<VR, the voltage signal Vdet is set to GND.

Referring to FIG. 9 again, voltage signal Vdet from output ground fault detection circuit 50 is input to the gates of transistors PMOS14 and NMOS11 of switch drive circuit 30 and the gate of transistor PMOS11 of switch drive circuit 21 . Since the configuration of other portions of charge pump circuit 105 according to the third embodiment is similar to that of charge pump circuit 100 (FIG. 4) according to the first embodiment, detailed description thereof will not be repeated.

As described in the first embodiment, when the ground fault occurs and the output voltage VOUT drops to near the ground voltage GND, the transistor PMOS14 is turned on in the switch drive circuit 30, thereby turning off the transistor PMOS13 and turning off the switch drive circuit. By turning on the transistor PMOS11 at 21 and turning off the transistor PMOS6, the current path from the input terminal 5 to the output terminal 10 can be cut off.

On the other hand, in the configuration of the first embodiment (FIG. 4), if the amount of drop in the output voltage VOUT due to the ground fault at the output terminal 10 is small and the output voltage VOUT does not drop to near the ground voltage GND, the transistor PMOS 14 and Since the PMOS 11 cannot be turned on, the overcurrent prevention function may not be exhibited.

In contrast, in the charge pump circuit 105 according to the third embodiment, when the output voltage VOUT drops below the ground fault determination voltage VR, the voltage signal Vdet from the output ground fault detection circuit 50 is set to the ground voltage GND. Therefore, the transistors PMOS14 and PMOS11 are reliably turned on.As a result, the current path from the input terminal 5 to the output terminal 10 can be cut off by reliably turning off the transistors PMOS6 and PMOS13. That is, even when the output voltage VOUT does not drop to near the ground voltage GND, the overcurrent prevention function described in the first embodiment is exhibited.

In addition, when the output terminal 10 is not grounded, the voltage signal Vdet is equal to VOUT, and the output voltage VOUT is input to the transistors PMOS14 and PMOS11. This is the same as the charge pump circuit 100 according to the first embodiment, and can perform the boosting operation for making the output voltage VOUT twice the input voltage VIN in the same manner as in the first embodiment.

The charge pump circuit according to the third embodiment can be combined with the first modification (FIG. 6) and the second modification (FIG. 7) of the first embodiment. Specifically, when combined with the first modification of the first embodiment, an output ground fault detection circuit 50 similar to that in FIG. can be commonly input to the gates of the transistors PMOS14 and NMOS14 of the switch drive circuit 30 and the gate of the transistor PMOS15 of the switch drive circuit 23 .

Similarly, in the configuration of FIG. 7, an output ground fault detection circuit 50 similar to that of FIG. , the gate of the transistor PMOS15 of the switch drive circuit 23 and the gate of the transistor PMOS11 of the switch drive circuit 21 can be commonly input.

Alternatively, as shown in FIG. 11, it is possible to configure a charge pump circuit by combining the second and third embodiments. In charge pump circuit 106 shown in FIG. 11, an output ground fault detection circuit 50 similar to that in FIG. 9 is additionally arranged in the configuration of FIG. Further, for the input to the switch drive circuit 30, the input to the gate of the transistor PMOS11 of the switch drive circuit 21, and the inputs to the clock control circuits 81 to 83, the output voltage VOUT is the voltage signal from the output ground fault detection circuit 50. By replacing with Vdet, it is possible to enjoy both the effects of the second and third embodiments.

Embodiment 4.
In the first to third embodiments, the overcurrent prevention function when a ground fault occurs at the output terminal 10 in the charge pump circuit having a voltage step-up ratio (VOUT/VIN) of 2 has been described. A similar overcurrent protection function can also be applied to In the fourth embodiment, addition of an overcurrent prevention function to a charge pump circuit having a step-up ratio (VOUT/VIN) of 3 will be described as an example.

FIG. 12 is a circuit diagram illustrating a configuration example of a charge pump circuit according to the fourth embodiment.
Referring to FIG. 12, charge pump circuit 107 according to the fourth embodiment differs from charge pump circuit 101 (FIG. 4) according to the first embodiment in that transistor PMOS18 as a switch element and ON/OFF state of transistor PMOS18 are different. , a capacitor C2, an inverter 32, and inverter drive circuits 26 and 27.

The transistor PMOS18 is connected between the node Np0 connected to the input terminal 5 and the transistor PMOS5. That is, in the configuration of FIG. 12, the transistors PMOS5, PMOS6, and PMPOS18 connected in series between the input terminal 5 and the output terminal 10 are the "first P-type transistors" that constitute the "plurality of switch elements." corresponds to an embodiment of

A capacitor C2 is connected between a node Np3 corresponding to a connection point of the transistors PMOS5 and PMOS18 and a node N8. The voltage of node N 8 is controlled by inverter 32 .

The switch drive circuit 25 has a P-type transistor PMOS19 and an N-type transistor NMOS12 connected in series via a node N6 between a node Np2 and a ground node Ng. A clock signal CLK5 is commonly input to the gates of the transistors PMOS19 and NMOS12. The switch drive circuit 25 constitutes an inverter that uses the output voltage VOUT and the ground voltage GND as power sources and receives the clock signal CLK5 as an input. Transistors PMOS19 and NMOS12 have parasitic diodes D29 and D30 of the polarities shown in FIG. 12 by connecting their backgates to node Np2 and ground node Ng, respectively.

The inverter 32 has a P-type transistor PMOS22 and an N-type transistor NMOS14 connected in series via a node N8 between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND). Node N8 is connected to node Np3 via capacitor C2.

The gate of transistor PMOS22 is connected to the output node of inverter drive circuit 26 to which clock signal CLK6 is input. The gate of transistor NMOS14 is connected to the output node of inverter drive circuit 27 to which clock signal CLK7 is input. Transistors PMOS22 and NMOS14 have parasitic diodes D36 and D37 of the polarities shown in FIG. 12 by connecting their backgates to node Np0 and ground node Ng, respectively.

The inverter drive circuit 26 includes a P-type transistor PMOS20 and a P-type transistor PMOS20 connected in series between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor PMOS22. It has an N-type transistor NMOS15. A clock signal CLK6 is commonly input to the gates of the transistors PMOS20 and NMOS15.

Similarly, the inverter drive circuit 27 is a P-type inverter connected in series between a node Np0 (input voltage VIN) and a ground node Ng (ground voltage GND) via an output node connected to the gate of the transistor NMOS14. It has a transistor PMOS21 and an N-type transistor NMOS13. A clock signal CLK7 is commonly input to the gates of the transistors PMOS21 and NMOS13.

The inverter drive circuits 26 and 27 constitute inverters that use the input voltage VIN and the ground voltage GND as power sources and receive the clock signals CLK6 and CLK7 as inputs. Transistors PMOS20 and NMOS15 have parasitic diodes D31 and D32 of the polarities shown in FIG. 12 by connecting their backgates to node Np0 and ground node Ng, respectively. Similarly, transistors PMOS21 and NMOS13 have parasitic diodes D33 and D34 of the polarities shown in FIG. 12 by connecting their backgates to node Np0 and ground node Ng, respectively.

The configuration of charge pump circuit 107 according to the fourth embodiment other than that described above is similar to that of charge pump circuit 101 according to the first embodiment, and therefore detailed description thereof will not be repeated. That is, as in FIG. 4, among the transistors PMOS5, PMOS6, and PMPOS18, which are a plurality of switch elements, for the transistor PMOS6, the "second P-type transistor" constituting the "back gate disconnecting switch" is used. A corresponding transistor PMOS13 is arranged. As in the first embodiment, the transistor PMOS13 is turned off during normal boosting operation. Further, in the charge pump circuit 107, in addition to the "voltage selection circuit" formed by the inverter drive circuits 13 and 14 and the inverter 20, the inverter drive circuits 26 and 27 and the inverter 32 also form a "voltage selection circuit". Configured.

FIG. 13 is a waveform diagram of clock signals CLK1 to CLK7 input to the charge pump circuit 107. As shown in FIG.

Referring to FIG. 13, clock signals CLK1-CLK4 are the same as those in FIG. 2, and clock signal CLK1 based on reference clock CLKa and clock signals CLK2-CLK4 based on reference clock CLKb have opposite phases.

As described above, clock signals CLK5 to CLK7 are added in the fourth embodiment. Clock signal CLK5 is in phase with clock signals CLK2-CLK4, and clock signals CLK6 and CLK7 are in phase with clock signal CLK1. Similarly to clock signals CLK1 to CLK4, dead times are appropriately provided for clock signals CLK5 to CLK7.

FIG. 14 shows a chart for explaining the boosting operation of the charge pump circuit 107. As shown in FIG. The charge pump circuit 107 alternately repeats state X and state Y shown in FIG. 14 according to clock signals CLK1 to CLK7 based on complementary reference clocks CLKa and CLKb.

14 and 12, in state X, reference clock CLKb (clock signals CLK2 to CLK5) is at H level, while reference clock CLKa (clock signals CLK1, CLK6 and CLK7) is at L level. Therefore, switch drive circuits 21 and 25 output an L level voltage (ground voltage GND) to nodes N4 and N6, while switch drive circuit 11 outputs an H level voltage (output voltage VOUT) to node N3. . As a result, regarding the plurality of switch elements, the transistors PMOS18 and PMOS6 are turned on, while the transistor PMOS5 is turned off.

On the other hand, since the inverter drive circuits 26 and 27 output the H level voltage (input voltage VIN), the inverter 32 connects the node N8 to the ground node Ng (ground voltage GND) by turning on the transistor NMOS14. On the other hand, since the inverter drive circuits 13 and 14 output the L level voltage (input voltage VIN), the inverter 20 connects the node N2 to the node Np0 (input voltage VIN) by turning on the transistor PMOS7.

Therefore, in state X, node Np3 is connected to input terminal 5 (input voltage VIN), while being disconnected from output terminal 10 and node Np1. Furthermore, the capacitor C1 is charged by the input voltage VIN by being connected between the node Np3 and the ground node Ng. Therefore, the capacitor voltage V(C1)=VIN. Capacitor C2 is connected between node Np1, which is connected to output terminal 10 by transistor PMOS6, and node Np0. Therefore, using the voltage V(C2) of capacitor C1 at that time, VOUT=VIN+V(C2) is shown.

In contrast, in state Y, reference clock CLKb (clock signals CLK2 to CLK5) is at L level, while reference clock CLKa (clock signals CLK1, CLK6 and CLK7) is at H level. Therefore, switch drive circuits 21 and 25 output an H level (output voltage VOUT) to nodes N4 and N6, while switch drive circuit 11 outputs an L level voltage (ground voltage GND) to node N3. As a result, regarding the plurality of switch elements, the transistors PMOS18 and PMOS6 are turned off, while the transistor PMOS5 is turned on.

On the other hand, since the inverter drive circuits 26 and 27 output the L level voltage (ground voltage GND), the inverter 32 connects the node N8 to the node Np0 (input voltage VIN) by turning on the transistor PMOS22. On the other hand, since the inverter drive circuits 13 and 14 output the H level voltage (ground voltage GND), the inverter 20 connects the node N2 to the ground node Ng (ground voltage GND) by turning on the transistor NMOS5.

In state Y, nodes Np1 and Np3 connected by transistor PMOS5 are disconnected from input terminal 5 (input voltage VIN) and output terminal 10 (output voltage VOUT), respectively. Furthermore, capacitor C1 is connected between node Np0 (input terminal 5) and node Np3. Therefore, the voltage of node Np3 becomes VIN+V(C1). In the immediately preceding state X, the node Np3 is charged to V(C1)=VIN, so the voltage of the node Np3 is twice the input voltage VIN.

On the other hand, capacitor C2 is charged to a voltage equivalent to that of node Np3 by being connected between node Np1 and ground node Ng. Therefore, in state Y, V(C2)=V(C1)=2.VIN.

Next, in state X again, the capacitor C1 is charged to the input voltage VIN, and the output voltage VOUT becomes the sum of the input voltage VIN and the voltage V(C2) of the capacitor C2 at that time. In the immediately preceding state Y, since it is charged to V(C2)=2.VIN, it is understood that VOUT=VIN+V(C2)=3.VIN and the step-up ratio (VOUT/VIN) is 3. .

As described above, the charge pump circuit 107 according to the fourth embodiment alternately repeats the state X and the state Y in accordance with the clock signals CLK1 to CLK7 based on the complementary reference clocks CLKa and CLKb, thereby reducing the input voltage VIN by 3. It is possible to execute a boosting operation that outputs double the output voltage VOUT.

In the charge pump circuit 107 according to the fourth embodiment, when the output terminal 10 is grounded and the output voltage VOUT drops to the vicinity of the ground voltage GND, the output of the switch driving circuit 30 (node N5) changes from the L level voltage (ground voltage GND) to the H level voltage (input voltage VIN). As a result, the transistor PMOS13, which is normally on, is turned off by the voltage difference between the output terminal 10 (lowered output voltage VOUT) and the node N5 (the gate of the PMOS15).

On the other hand, in the switch drive circuit 21, the switch drive circuit 21 can output the input voltage VIN to the node N4 during the L level period of the clock signal CLK2 by turning on the transistor PMOS11 as the output voltage VOUT drops. Thereby, an OFF period of the transistor PMOS6 can be provided. Also, as in the first embodiment, the current path through the body (backgate) of the transistor PMOS6 is cut off by reverse voltage blocking by the parasitic diode D23 of the transistor PMOS13, which is the "backgate disconnection switch element".

As a result, in the charge pump circuit 107 according to the fourth embodiment as well, when the output voltage VOUT drops due to the occurrence of a ground fault at the output terminal 10 or the like, the input terminal 5 is to the output terminal 10 can be avoided. As a result, even in charge pump circuit 107 having a step-up ratio of 3, it is possible to prevent overcurrent from occurring when output terminal 10 is grounded.

Also in the charge pump circuit 107 according to the fourth embodiment, as described in the first and second modifications of the first embodiment, among the plurality of switch elements, the transistors PMOS18, PMOS5, and PMOS6, A switch drive circuit configured to use the input voltage VIN as an inverter power supply when the output voltage VOUT drops, like the switch drive circuit 21 (i.e., a "first switch drive circuit") for at least one of , and a transistor (PMOS 13 in FIG. 12) serving as a “back gate disconnecting switch element” and its drive circuit (switch drive circuit 30) can be arranged.

Further, in the charge pump circuit 107 according to the fourth embodiment, at least one of the clock control circuits 81 to 83 in FIG. 8 and the output ground fault detection circuit 50 in FIG. It is also possible to control in the same way as

Furthermore, in the fourth embodiment, the charge pump circuit with the step-up ratio of 3 has been described, but the first to third embodiments can be similarly applied to a charge pump circuit with a higher step-up ratio. For such a charge pump circuit as well, for at least one of the plurality of switch elements connected in series between the input terminal 5 and the output terminal 10, the above-described "first switch drive circuit" and By arranging the "back gate disconnecting switch element" and the "back gate disconnecting switch drive circuit", it is possible to prevent the occurrence of overcurrent when the output voltage VOUT drops due to the occurrence of a ground fault or the like.

The charge pump circuits 101 to 107 according to the first to fourth embodiments described above can be applied to semiconductor devices. For example, as shown in FIG. 15, a semiconductor device 200 includes a power supply circuit 202, a semiconductor circuit 210 including a semiconductor element 215, and a charge pump circuit according to any one of the first to fourth embodiments. Semiconductor element 215 is typically composed of a transistor or a diode. The power supply circuit 202 can generate a stable voltage VDD from the power supply voltage Vp externally supplied to the semiconductor device 200 . The charge pump circuits 101 to 107 output a boosted voltage VBB as an output voltage VOUT by performing a boosting operation using the voltage VDD from the power supply circuit 202 as the input voltage VIN. Since both the voltage VDD and the voltage VBB are supplied to the semiconductor circuit 210 as power supply voltages, the semiconductor element 215 can operate by receiving the boosted voltage VBB, which is the output voltage of the charge pump circuits 101-107.

It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

5 input terminals 10 output terminals 11, 12, 21, 23, 25, 30 switch drive circuit 13, 14, 26, 27 inverter drive circuit 20, 32 inverter 50 output ground fault detection circuit 51 voltage comparator , 55 level shifter, 60 P-type substrate, 61, 71 N well, 62, 63, 72, 73 P+ region, 64, 74 gate, 65, 75 N+ region, 81 to 84 clock control circuit, 100, 101, 102, 103 , 104, 105, 106, 107 charge pump circuit 200 semiconductor device 202 power supply circuit 210 semiconductor circuit 215 semiconductor element C1, C2 capacitors CLK1 to CLK7 clock signals CLKa, CLKb reference clocks D1 to D12, D21 ~D37 parasitic diode, GND, VIN ground voltage, N2~N6, N8, Np0~Np3, Ns nodes, NMOS1~NMOS5, NMOS11~NMOS22 N-channel transistors, PMOS1~PMOS7, PMOS11~PMOS22 P-channel transistors, Ng ground Node, VBB, VDD voltage, VBB boosted voltage, VIN input voltage, VOUT output voltage, VR ground fault determination voltage, Vdet voltage signal (output ground fault detection circuit).

Claims (12)

A charge pump circuit that generates an output voltage by boosting an input voltage,
an input terminal to which the input voltage is input;
an output terminal for outputting the output voltage;
a plurality of first P-type transistors connected in series between the input terminal and the output terminal and constituting a plurality of switch elements, respectively;
In the boosting operation state of the charge pump circuit, according to the logic level of one of the first and second clocks complementary to each other, the reference voltage and the a plurality of switch drive circuits that selectively output one of the output voltages to control on/off of the plurality of switch elements;
a capacitor connected to each connection point of two adjacent switch elements among the plurality of switch elements;
In at least one first P-type transistor among the plurality of first P-type transistors, a back gate and a main electrode on the output terminal side of two main electrodes of the first P-type transistor a backgate disconnect switch element connected between
a back gate disconnect switch drive circuit that changes the back gate disconnect switch element from on to off when the output voltage drops,
In the second P-type transistor constituting the back gate disconnecting switch element, the parasitic diode of the second P-type transistor has a polarity opposite to the parasitic diode of the first P-type transistor to which it is connected. and configured to be connected in series,
Of the plurality of switch drive circuits, at least one first switch drive circuit corresponding to the at least one first P-type transistor to which the back gate disconnecting switch element is connected is connected to the first P-type transistor. One of the reference voltage and the output voltage is selectively input to the control electrode of the type transistor according to the logic level of the one clock when the back gate disconnect switch element is on, while the back gate disconnect is performed. A charge pump circuit that selectively inputs one of the reference voltage and the input voltage when a switch element is turned off. the capacitor has a first terminal connected to the connection point and a second terminal facing the first terminal;
The charge pump circuit is
2. The charge pump circuit according to claim 1, further comprising a voltage selection circuit for selectively outputting one of said reference voltage and said input voltage to said second terminal of said capacitor according to said first or second clock. . The first switch drive circuit and the backgate cutoff in the case where the first P-type transistor to which the backgate cutoff switch element is connected and the first switch drive circuit are provided one by one. When a plurality of first P-type transistors to which switch elements are connected and a plurality of the first switch driving circuits are provided, each of the first switch driving circuits includes:
said control electrode of said first P-type transistor connected between a power supply node and a reference voltage node transmitting said reference voltage and constituting a corresponding switch element according to said first or second clock; a signal transmission circuit selectively connecting one of the power supply node and the reference voltage node to an output node connected to
is connected between the power supply node and the input terminal and the output terminal, and connects the input terminal and the power supply node when the output voltage drops, and connects the output terminal when the output voltage does not drop. 3. The charge pump circuit according to claim 2, further comprising a voltage switching circuit connecting said power supply node with said power supply node. the backgate disconnect switch element is connected to each of two or more switch elements among the plurality of switch elements;
Each of the back gate disconnecting switch elements is turned off when the output voltage drops by supplying an output voltage from the common back gate disconnecting switch driving circuit to the control electrode of the second P-type transistor. 4. The charge pump circuit according to claim 2, wherein the charge pump circuit changes to . one first P-type transistor to which the backgate disconnecting switch element is connected and one first switch drive circuit;
The charge pump circuit is
a first clock control circuit provided corresponding to the first switch drive circuit;
a second clock control circuit provided corresponding to the voltage selection circuit,
The first clock control circuit controls the one clock so that the input voltage is fixedly output to the control electrode of the first P-type transistor when the output voltage drops. processed and input to the first switch drive circuit;
The second clock control circuit controls the second clock control circuit so that one of the reference voltage and the input voltage is fixedly output to the second terminal of the capacitor when the output voltage drops. 5. The charge pump circuit according to claim 2, wherein the first or second clock is processed and input to said voltage selection circuit. a plurality of first P-type transistors to which the back gate disconnecting switch element is connected and a plurality of the first switch driving circuits are provided;
The charge pump circuit is
a first clock control circuit provided corresponding to each of the plurality of first switch drive circuits;
a second clock control circuit provided corresponding to the voltage selection circuit,
The first clock control circuit, when the output voltage drops , the first switch drive circuit among the plurality of first switch drive circuits corresponding to the first clock control circuit. processing the one clock and inputting it to the first switch drive circuit so that the input voltage is fixedly output to the control electrode of the associated first P-type transistor;
The second clock control circuit controls the second clock control circuit so that one of the reference voltage and the input voltage is fixedly output to the second terminal of the capacitor when the output voltage drops. 5. The charge pump circuit according to claim 2, wherein the first or second clock is processed and input to said voltage selection circuit. further comprising an output ground fault detection circuit that detects that a ground fault has occurred at the output terminal based on the output voltage;
5. The backgate disconnect switch drive circuit according to claim 2, wherein the backgate disconnect switch drive circuit changes the backgate disconnect switch element from on to off in response to detection of the ground fault by the output ground fault detection circuit. Charge pump circuit as described. one first P-type transistor to which the backgate disconnecting switch element is connected and one first switch drive circuit;
The charge pump circuit is
a first clock control circuit provided corresponding to the first switch drive circuit;
a second clock control circuit provided corresponding to the voltage selection circuit,
The first clock control circuit outputs the input voltage fixedly to the control electrode of the first P-type transistor in response to detection of the ground fault by the output ground fault detection circuit. and processing the one clock and inputting it to the first switch drive circuit,
The second clock control circuit fixedly outputs one of the reference voltage and the input voltage to the second terminal of the capacitor in response to detection of the ground fault by the output ground fault detection circuit. 8. The charge pump circuit according to claim 7 , wherein said first or second clock is processed to be input to said voltage selection circuit. a plurality of first P-type transistors to which the back gate disconnecting switch element is connected and a plurality of the first switch driving circuits are provided;
The charge pump circuit is
a first clock control circuit provided corresponding to each of the plurality of first switch drive circuits;
a second clock control circuit provided corresponding to the voltage selection circuit,
The first clock control circuit, in response to detection of the ground fault by the output ground fault detection circuit, controls the clock control circuit corresponding to the first clock control circuit among the plurality of first switch drive circuits. The one clock is processed to operate the first switch so that the input voltage is fixedly output to the control electrode of the first P-type transistor associated with the first switch drive circuit. input to the drive circuit,
The second clock control circuit fixedly outputs one of the reference voltage and the input voltage to the second terminal of the capacitor in response to detection of the ground fault by the output ground fault detection circuit. 8. The charge pump circuit according to claim 7 , wherein said first or second clock is processed to be input to said voltage selection circuit. The output ground fault detection circuit detects that the ground fault has occurred at the output terminal when the output voltage drops below a short circuit determination voltage, and outputs the output voltage when the ground fault is not detected,
The short-circuit determination voltage is predetermined corresponding to a voltage obtained by subtracting, from the input voltage, a sum of forward voltage drops due to the parasitic diodes of the first P-type transistors constituting the plurality of switch elements. The charge pump circuit according to any one of claims 7-9. further comprising an output ground fault detection circuit that detects that a ground fault has occurred at the output terminal based on the output voltage;
2. The charge pump circuit according to claim 1, wherein said backgate disconnect switch drive circuit changes said backgate disconnect switch element from on to off in response to detection of said ground fault by said output ground fault detection circuit. a charge pump circuit according to any one of claims 1 to 11 ;
and a semiconductor element that operates upon receiving the output voltage of the charge pump circuit.

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