TW201542885A - Substrate treatment method and substrate treatment jig - Google Patents

Substrate treatment method and substrate treatment jig Download PDF

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TW201542885A
TW201542885A TW104108212A TW104108212A TW201542885A TW 201542885 A TW201542885 A TW 201542885A TW 104108212 A TW104108212 A TW 104108212A TW 104108212 A TW104108212 A TW 104108212A TW 201542885 A TW201542885 A TW 201542885A
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substrate
liquid
alignment
alignment liquid
liquid discharge
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Haruo Iwatsu
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Tokyo Electron Ltd
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/02Tanks; Installations therefor
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/10Electrodes, e.g. composition, counter electrode
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/003Electroplating using gases, e.g. pressure influence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

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  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
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Abstract

In the present invention, a substrate treatment method includes: supplying an alignment solution to the entire surface of a substrate on which a plurality of semiconductor chips have been formed; arranging a counter substrate, in which alignment solution discharge holes penetrating through the thickness direction have been formed, over the substrate with the alignment solution therebetween; discharging the alignment solution by capillary action to the upper surface side of the counter substrate via the alignment solution discharge holes from scribe lines between the semiconductor chips, and in the area between the counter substrate and the substrate, supplying air to spaces formed on the scribe lines to form a gas-liquid interface between margins of the semiconductor chips and the counter substrate; and adjusting the position of the counter substrate relative to the substrate, by the surface tension of the alignment solution at the gas-liquid interface.

Description

基板處理方法及基板處理治具 Substrate processing method and substrate processing fixture (相關申請案之相互參照) (Reciprocal reference of related applications)

本申請案係基於在2014年3月24日於日本提出申請之日本專利特願2014-051115號並主張優先權,且將其內容引用於本文中。 The present application is based on Japanese Patent Application No. 2014-051115, filed on Jun.

本發明係關於一種對形成有複數個半導體晶片之基板進行特定之處理之基板處理方法、及該基板處理方法中所使用之基板處理治具。 The present invention relates to a substrate processing method for performing specific processing on a substrate on which a plurality of semiconductor wafers are formed, and a substrate processing jig used in the substrate processing method.

近年來,要求半導體裝置之高性能化,而進行半導體元件之高積體化。於該狀況下,在將經高積體化之半導體元件於水平面內配置複數個,並利用配線將該等半導體元件連接而製造半導體裝置之情形時,有配線長度增大,由此導致配線之電阻變大且配線延遲增大之虞。 In recent years, high performance of semiconductor devices has been demanded, and semiconductor elements have been highly integrated. In this case, when a plurality of highly integrated semiconductor elements are arranged in a horizontal plane and the semiconductor elements are connected by wiring to manufacture a semiconductor device, the wiring length is increased, thereby causing wiring. The resistance becomes large and the wiring delay increases.

因此,提出有將半導體元件三維地積層之三維積體技術。於該三維積體技術中,以貫通藉由對背面進行研磨而薄化且於正面形成有複數個電子電路之半導體晶圓(以下,稱為「晶圓」)之方式,形成複數個例如具有100μm以下之微細直徑之電極、所謂的貫通電極(TSV:Through Silicon Via,矽通孔)。而且,經由該貫通電極,將上下積層之晶圓電性連接。 Therefore, a three-dimensional integrated technique in which a semiconductor element is three-dimensionally laminated has been proposed. In the three-dimensional integrated technique, a plurality of semiconductor wafers (hereinafter referred to as "wafers") having a plurality of electronic circuits formed on the front surface by thinning the back surface are formed, for example, An electrode having a fine diameter of 100 μm or less, a so-called through electrode (TSV: Through Silicon Via). Further, the stacked wafers are electrically connected via the through electrodes.

針對形成上述貫通電極之方式研究出各種。例如於專利文獻1中,提出有使用具備鍍敷液等之流通路徑之模板,於例如晶圓之貫通孔內進行電解鍍敷而形成貫通電極。具體而言,首先,向晶圓表面之對準區域供給對準液(純水)之後,將模板與晶圓對向地配置,藉由該 對準液之表面張力使恢復力作用於模板,而進行模板與晶圓之位置調整。其後,利用毛細管現象自模板之流通路徑向晶圓之貫通孔內供給鍍敷液,進而以模板側之電極為陽極、以晶圓側之對向電極為陰極而施加電壓,於貫通孔內進行鍍敷處理而於該貫通孔內形成貫通電極。 Various types of research have been made on the formation of the above-mentioned through electrodes. For example, in Patent Document 1, it is proposed to form a through electrode by performing electrolytic plating in a through hole of a wafer, for example, using a template having a flow path such as a plating solution. Specifically, first, after supplying an alignment liquid (pure water) to an alignment region of the wafer surface, the template is placed opposite to the wafer, by the The surface tension of the alignment liquid causes the restoring force to act on the template to perform positional adjustment of the template and the wafer. Thereafter, the plating solution is supplied from the flow path of the template to the through hole of the wafer by capillary action, and the electrode on the template side is used as the anode, and the counter electrode on the wafer side is used as the cathode, and a voltage is applied to the through hole. A plating treatment is performed to form a through electrode in the through hole.

於如此般使用模板對晶圓進行特定之處理之情形時,需要進行模板與晶圓之位置調整。作為該位置調整之方法,例如於專利文獻2中亦提出有如下方法:將模板與晶圓對向地配置之後,自模板之流通路徑向晶圓表面之對準用圖案供給對準液(純水)。於此情形時,亦會藉由對準液之表面張力使恢復力作用於模板,而進行模板與晶圓之位置調整。 When the stencil is used to perform specific processing on the wafer in this way, the position adjustment of the stencil and the wafer is required. As a method of adjusting the position, for example, Patent Document 2 proposes a method of supplying an alignment liquid (pure water) from a pattern of alignment of a flow path of a template to a surface of a wafer after the template is placed opposite to the wafer. ). In this case, the positional adjustment of the template and the wafer is also performed by applying the restoring force to the template by the surface tension of the alignment liquid.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本專利特開2013-108111號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2013-108111

[專利文獻2]日本專利特開2013-138123號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2013-138123

然而,於使用專利文獻1所記載之位置調整方法之情形時,需要向晶圓表面之複數個且微小之對準區域供給對準液。因此,難以向各對準區域適當地供給對準液。 However, in the case of using the position adjustment method described in Patent Document 1, it is necessary to supply the alignment liquid to a plurality of minute alignment regions on the wafer surface. Therefore, it is difficult to appropriately supply the alignment liquid to each of the alignment regions.

又,於使用專利文獻2所記載之位置調整方法之情形時,需要自模板之具有微小直徑之流通路徑向對準用圖案供給對準液。於該微小直徑之流通路徑內,對準液難以流通。而且,於流通路徑之晶圓側之開口部,表面張力作用於對準液,而難以使該對準液與晶圓接觸。 Further, in the case of using the position adjustment method described in Patent Document 2, it is necessary to supply the alignment liquid to the alignment pattern from the flow path having the minute diameter of the template. It is difficult for the alignment liquid to flow in the flow path of the minute diameter. Further, in the opening portion on the wafer side of the flow path, surface tension acts on the alignment liquid, and it is difficult to bring the alignment liquid into contact with the wafer.

如以上般,使用模板對晶圓進行特定之處理時,模板與晶圓之位置調整存在改善之餘地。 As described above, there is room for improvement in the positional adjustment of the template and the wafer when the wafer is specifically processed using the template.

本發明係鑒於上述情況而完成者,其目的在於適當地進行基板處 理治具與基板之位置調整、適當地進行使用該基板處理治具之基板處理。 The present invention has been made in view of the above circumstances, and an object thereof is to appropriately perform a substrate The position of the fixture and the substrate is adjusted, and the substrate processing using the substrate processing jig is appropriately performed.

為達成上述目的,本發明係一種基板處理方法,其係對形成有複數個半導體晶片之基板進行特定之處理者,且包括:第1步驟,其係對上述形成有複數個半導體晶片之基板之整個表面供給對準液;第2步驟,其係將形成有於厚度方向貫通之對準液排出孔之對向基板隔著上述對準液而配置於基板上;第3步驟,其係利用毛細管現象將上述對準液自上述半導體晶片間之切割道經由上述對準液排出孔而朝上述對向基板之上表面側排出,並且於上述對向基板與基板之間形成於上述切割道上之空間供給空氣,而於上述半導體晶片之周緣部與上述對向基板之間形成氣液界面;及第4步驟,其係藉由上述氣液界面中之上述對準液之表面張力,進行上述對向基板相對於基板之位置調整。 In order to achieve the above object, the present invention is a substrate processing method for performing specific processing on a substrate on which a plurality of semiconductor wafers are formed, and includes: a first step of the substrate on which the plurality of semiconductor wafers are formed The alignment liquid is supplied to the entire surface; in the second step, the opposite substrate on which the alignment liquid discharge hole penetrating in the thickness direction is formed is placed on the substrate via the alignment liquid; and the third step is to use the capillary tube a phenomenon in which the alignment liquid is discharged from the scribe line between the semiconductor wafers toward the upper surface side of the opposite substrate via the alignment liquid discharge hole, and a space formed on the scribe line between the opposite substrate and the substrate Supplying air to form a gas-liquid interface between the peripheral portion of the semiconductor wafer and the opposite substrate; and a fourth step of performing the above-described alignment by the surface tension of the alignment liquid in the gas-liquid interface The position of the substrate relative to the substrate is adjusted.

根據本發明,向基板之整個表面供給對準液之後,僅存在於切割道上之對準液利用毛細管現象經由對準液排出孔而向對向基板之上表面側排出。同時,於對向基板與基板之間,向形成於切割道上之空間供給空氣,藉此於半導體晶片之周緣部與對向基板之間形成氣液界面。而且,藉由氣液界面中之對準液之表面張力,使對向基板移動之恢復力會發生作用,而高精度地進行對向基板相對於基板之位置調整。如此,於本發明中,由於向基板之整個表面供給對準液,故而消除先前之對準液供給之困難性,可適當且容易地進行對向基板與基板之位置調整。又,由於如此般適當地進行對向基板與基板之位置調整,故而可適當地進行後續進行之基板處理。 According to the invention, after the alignment liquid is supplied to the entire surface of the substrate, only the alignment liquid existing on the scribe line is discharged to the upper surface side of the counter substrate via the alignment liquid discharge hole by the capillary phenomenon. At the same time, air is supplied between the opposite substrate and the substrate to the space formed on the scribe line, thereby forming a gas-liquid interface between the peripheral portion of the semiconductor wafer and the opposite substrate. Further, by the surface tension of the alignment liquid in the gas-liquid interface, the restoring force for moving the counter substrate acts, and the positional adjustment of the counter substrate with respect to the substrate is performed with high precision. As described above, in the present invention, since the alignment liquid is supplied to the entire surface of the substrate, the difficulty in supplying the previous alignment liquid is eliminated, and the positional adjustment between the counter substrate and the substrate can be appropriately and easily performed. Further, since the positional adjustment of the counter substrate and the substrate is appropriately performed as described above, the subsequent substrate processing can be appropriately performed.

亦可於上述對向基板,形成有於厚度方向貫通之液體逸出孔,於上述對向基板之上表面,設置有連通於上述液體逸出孔之液體逸出槽,於上述第5步驟中,利用毛細管現象將上述對準液或上述處理液自 上述半導體晶片上經由上述液體逸出孔而排出至上述液體逸出槽,從而維持上述對向基板相對於基板之配置。再者,亦可藉由此處所提及之液體逸出,於半導體晶片與對向基板之間產生對準液或處理液所產生之保持力,而使基板與對向基板吸附。 A liquid escape hole penetrating in the thickness direction may be formed on the opposite substrate, and a liquid escape groove communicating with the liquid escape hole may be provided on the upper surface of the opposite substrate, in the fifth step , using the capillary phenomenon to the above alignment liquid or the above treatment liquid The semiconductor wafer is discharged to the liquid escape groove through the liquid escape hole, thereby maintaining the arrangement of the opposite substrate with respect to the substrate. Furthermore, the substrate can be adsorbed to the counter substrate by the escaping force generated by the immersion liquid or the treatment liquid between the semiconductor wafer and the counter substrate by the liquid escaping mentioned herein.

另一觀點之本發明係一種基板處理治具,其係用以對形成有複數個半導體晶片之基板進行特定之處理者,且形成有於厚度方向貫通之對準液排出孔,於上述形成有複數個半導體晶片之基板之整個表面被供給對準液,進而基板處理治具隔著上述對準液而配置於基板上之狀態下,上述對準液排出孔係以如下方式形成:利用毛細管現象上述對準液自上述半導體晶片間之切割道經由上述對準液排出孔而向基板處理治具之上表面側被排出,並且於上述基板處理治具與基板之間形成於上述切割道上之空間被供給空氣,而於上述半導體晶片之周緣部與基板處理治具之間形成氣液界面。再者,本發明中之基板處理治具包含上述發明中之對向基板。 Another aspect of the present invention is a substrate processing jig for performing a specific processing on a substrate on which a plurality of semiconductor wafers are formed, and forming an alignment liquid discharge hole penetrating in a thickness direction. The aligning liquid is supplied to the entire surface of the substrate of the plurality of semiconductor wafers, and the substrate processing jig is placed on the substrate via the alignment liquid. The alignment liquid discharge holes are formed in the following manner: using capillary phenomenon The aligning liquid is discharged from the scribe line between the semiconductor wafers to the upper surface side of the substrate processing jig via the alignment liquid discharge hole, and a space formed on the dicing street between the substrate processing jig and the substrate Air is supplied to form a gas-liquid interface between the peripheral portion of the semiconductor wafer and the substrate processing jig. Furthermore, the substrate processing jig of the present invention comprises the opposite substrate of the above invention.

根據本發明,可適當且容易地進行基板處理治具與基板之位置調整,且適當地進行使用該基板處理治具之基板處理。 According to the present invention, the positional adjustment of the substrate processing jig and the substrate can be appropriately and easily performed, and the substrate processing using the substrate processing jig can be appropriately performed.

10‧‧‧晶圓 10‧‧‧ wafer

10a‧‧‧正面 10a‧‧‧ positive

10b‧‧‧背面 10b‧‧‧back

11‧‧‧晶片 11‧‧‧ wafer

12‧‧‧切割道 12‧‧‧ cutting road

12a‧‧‧晶圓側面開口部 12a‧‧‧ Wafer side opening

13‧‧‧貫通孔 13‧‧‧through holes

14‧‧‧晶圓側電極 14‧‧‧ Wafer-side electrode

20‧‧‧模板 20‧‧‧ template

20a‧‧‧正面 20a‧‧‧ positive

20b‧‧‧背面 20b‧‧‧back

21‧‧‧處理區域 21‧‧‧Processing area

22‧‧‧空氣供給溝 22‧‧‧Air supply ditch

22a‧‧‧模板側面開口部 22a‧‧‧Template side opening

23‧‧‧對準液排出孔 23‧‧‧ alignment liquid discharge hole

24‧‧‧對準液排出槽 24‧‧‧ alignment liquid discharge tank

24a‧‧‧細溝 24a‧‧‧ rill

25‧‧‧鍍敷液供給孔 25‧‧‧ plating solution supply hole

26‧‧‧鍍敷液排出孔 26‧‧‧ plating solution discharge hole

27‧‧‧鍍敷液供給槽 27‧‧‧ plating solution supply tank

27a‧‧‧細溝 27a‧‧‧ rill

28‧‧‧鍍敷液排出槽 28‧‧‧ plating solution draining tank

28a‧‧‧細溝 28a‧‧‧ rill

29‧‧‧模板側電極 29‧‧‧Template side electrode

30‧‧‧保持機構 30‧‧‧ Keeping institutions

40‧‧‧空間 40‧‧‧ space

50‧‧‧直流電源 50‧‧‧DC power supply

60‧‧‧貫通電極 60‧‧‧through electrodes

60a‧‧‧鍍銅 60a‧‧‧copper plating

70‧‧‧間接電極 70‧‧‧Indirect electrode

71‧‧‧電極 71‧‧‧Electrode

72‧‧‧絕緣體 72‧‧‧Insulator

73‧‧‧開關 73‧‧‧ switch

80‧‧‧對準液逸出孔 80‧‧‧ alignment liquid escape hole

81‧‧‧對準液逸出槽 81‧‧‧ alignment liquid escape slot

81a‧‧‧細溝 81a‧‧‧ rill

A‧‧‧空氣 A‧‧‧Air

F‧‧‧氣液界面 F‧‧‧ gas-liquid interface

M‧‧‧鍍敷液 M‧‧‧ plating solution

P‧‧‧對準液 P‧‧‧ alignment fluid

圖1係表示晶圓之構成之概略之俯視圖。 Fig. 1 is a plan view showing the outline of a structure of a wafer.

圖2係表示晶圓之構成之概略之縱剖視圖。 Fig. 2 is a schematic longitudinal cross-sectional view showing the structure of a wafer.

圖3係表示模板之構成之概略之俯視圖。 Fig. 3 is a plan view showing a schematic configuration of a template.

圖4係表示模板之構成之概略之縱剖視圖。 Fig. 4 is a schematic longitudinal cross-sectional view showing the configuration of a template.

圖5係表示對準液排出槽、鍍敷液供給槽及鍍敷液排出槽之構成之概略之俯視圖。 Fig. 5 is a plan view showing a schematic configuration of an alignment liquid discharge tank, a plating solution supply tank, and a plating liquid discharge tank.

圖6係表示對晶圓之整個表面供給對準液之情況之說明圖。 Fig. 6 is an explanatory view showing a state in which an alignment liquid is supplied to the entire surface of the wafer.

圖7係表示將模板與晶圓對向地配置之情況之說明圖。 Fig. 7 is an explanatory view showing a state in which a template is placed opposite to a wafer.

圖8係表示對準液通過空氣供給溝進入對準液排出孔之情況之說明圖。 Fig. 8 is an explanatory view showing a state in which the alignment liquid enters the alignment liquid discharge hole through the air supply groove.

圖9係表示對準液通過空氣供給溝進入對準液排出孔時之俯視下的模板之情況之說明圖。 Fig. 9 is an explanatory view showing a state in which the alignment liquid passes through the air supply groove into the alignment liquid discharge hole in a plan view.

圖10係表示於晶片與處理區域之間形成有氣液界面之情況之說明圖。 Fig. 10 is an explanatory view showing a state in which a gas-liquid interface is formed between a wafer and a processing region.

圖11係表示於晶片與處理區域之間形成有氣液界面時之俯視下的模板之情況之說明圖。 Fig. 11 is an explanatory view showing a state in which a template is viewed in a plan view when a gas-liquid interface is formed between a wafer and a processing region.

圖12係表示解除利用保持機構對模板之保持之情況之說明圖。 Fig. 12 is an explanatory view showing a state in which the holding of the template by the holding mechanism is released.

圖13係表示對晶圓與模板進行位置調整之情況之說明圖。 Fig. 13 is an explanatory view showing a state in which the wafer and the template are positionally adjusted.

圖14係表示於晶圓側電極與模板側電極連接有直流電源之情況之說明圖。 Fig. 14 is an explanatory view showing a state in which a DC power source is connected to a wafer side electrode and a template side electrode.

圖15係表示將晶片與處理區域之間之對準液替換為鍍敷液的情況之說明圖。 Fig. 15 is an explanatory view showing a state in which an alignment liquid between a wafer and a processing region is replaced with a plating solution.

圖16係表示已將晶片與處理區域之間之對準液替換為鍍敷液的情況之說明圖。 Fig. 16 is an explanatory view showing a state in which the alignment liquid between the wafer and the processing region has been replaced with a plating solution.

圖17係表示於貫通孔內析出鍍銅之情況之說明圖。 Fig. 17 is an explanatory view showing a state in which copper plating is deposited in the through hole.

圖18係表示於貫通孔內形成有貫通電極之情況之說明圖。 Fig. 18 is an explanatory view showing a state in which a through electrode is formed in a through hole.

圖19係表示其他實施形態中之模板之構成之概略之縱剖視圖。 Fig. 19 is a longitudinal cross-sectional view showing the outline of a configuration of a template in another embodiment.

圖20係表示其他實施形態中之模板側電極之配置之俯視圖。 Fig. 20 is a plan view showing the arrangement of the template side electrodes in the other embodiment.

圖21係表示其他實施形態中之模板之構成之概略之縱剖視圖。 Fig. 21 is a longitudinal sectional view showing the outline of a configuration of a template in another embodiment.

圖22係表示於其他實施形態中將間接電極與電源連接之情況之說明圖。 Fig. 22 is an explanatory view showing a state in which an indirect electrode is connected to a power source in another embodiment.

圖23係表示於其他實施形態中將間接電極與模板側電極連接之情況之說明圖。 Fig. 23 is an explanatory view showing a state in which an indirect electrode is connected to a template side electrode in another embodiment.

圖24係表示其他實施形態中之模板之構成之概略之俯視圖。 Fig. 24 is a plan view showing the outline of a configuration of a template in another embodiment.

圖25係表示其他實施形態中之模板之構成之概略之縱剖視圖。 Fig. 25 is a longitudinal sectional view showing the outline of a configuration of a template in another embodiment.

圖26係表示其他實施形態中之對準液逸出槽之構成之概略之俯視圖。 Fig. 26 is a plan view showing the outline of the configuration of the alignment liquid escape groove in the other embodiment.

圖27係表示於其他實施形態中模板吸附於晶圓之情況之說明圖。 Fig. 27 is an explanatory view showing a state in which a template is adsorbed to a wafer in another embodiment.

以下,對本發明之實施形態進行說明。於本實施形態中,作為對作為本發明之基板之晶圓所進行之處理,針對在形成於晶圓之貫通孔內形成貫通電極之鍍敷處理,與該鍍敷處理中所使用之晶圓及作為基板處理治具(對向基板)之模板之構成一併進行說明。再者,於以下之說明中使用之圖式中,由於以技術理解之容易度為優先,故而各構成要素之尺寸未必對應實際之尺寸。 Hereinafter, embodiments of the present invention will be described. In the present embodiment, as a process performed on a wafer as a substrate of the present invention, a plating process for forming a through electrode formed in a through hole formed in a wafer, and a wafer used in the plating process are used. The configuration of the template as the substrate processing jig (opposing substrate) will be described together. In addition, in the drawings used in the following description, since the ease of technical understanding is prioritized, the size of each component does not necessarily correspond to the actual size.

首先,對本實施形態之鍍敷處理中所使用之晶圓及模板之構成進行說明。如圖1及圖2所示,於晶圓10之正面10a,形成有半導體晶片11(以下,存在稱為「晶片11」之情況)與切割道12。晶片11於晶圓面內均勻地形成有複數個。切割道12於複數個晶片11、11間延伸,形成為格子狀。又,切割道12係較晶片11更低地形成。進而,切割道12於晶圓10之側面開口,形成有晶圓側面開口部12a。再者,所謂切割道係將晶圓切斷而分割成複數個半導體晶片時之線道。 First, the configuration of the wafer and the template used in the plating process of the present embodiment will be described. As shown in FIGS. 1 and 2, a semiconductor wafer 11 (hereinafter referred to as "wafer 11") and a dicing street 12 are formed on the front surface 10a of the wafer 10. The wafer 11 is uniformly formed in a plurality of planes in the wafer surface. The dicing street 12 extends between the plurality of wafers 11, 11 and is formed in a lattice shape. Further, the scribe line 12 is formed lower than the wafer 11. Further, the scribe line 12 is opened on the side surface of the wafer 10, and the wafer side opening portion 12a is formed. Further, the scribe line is a lane in which a wafer is cut and divided into a plurality of semiconductor wafers.

於各晶片11,形成有於厚度方向自晶圓10之正面10a延伸至背面10b側之貫通孔13。再者,於本實施形態中,貫通孔13並未貫通晶圓10,但由於在特定之處理後將晶圓10之背面10b薄化而貫通,故而為方便起見,稱為「貫通孔」。於貫通孔13之背面10b側,設置有與下述之模板20之模板側電極29相對應之晶圓側電極14。再者,於晶片11,除貫通孔13及晶圓側電極14以外,亦形成有電子電路或配線等。 Each of the wafers 11 is formed with a through hole 13 extending in the thickness direction from the front surface 10a of the wafer 10 to the side of the back surface 10b. Further, in the present embodiment, the through hole 13 does not penetrate the wafer 10. However, since the back surface 10b of the wafer 10 is thinned and penetrated after a specific process, it is referred to as a "through hole" for the sake of convenience. . A wafer side electrode 14 corresponding to the template side electrode 29 of the template 20 to be described later is provided on the back surface 10b side of the through hole 13. Further, in the wafer 11, an electronic circuit, a wiring, or the like is formed in addition to the through hole 13 and the wafer side electrode 14.

圖3及圖4所示之模板20例如具有大致圓盤形狀,且具有與晶圓10之俯視下之形狀相同之形狀。模板20係使用例如碳化矽(SiC)等。再 者,圖4中圖示出如下所述般與晶圓10對向配置之模板20之狀態,正面20a位於下側,背面20b位於上側。 The template 20 shown in FIGS. 3 and 4 has, for example, a substantially disk shape and has the same shape as that of the wafer 10 in plan view. The template 20 is made of, for example, tantalum carbide (SiC) or the like. again 4 shows a state in which the template 20 is disposed opposite to the wafer 10 as follows, the front surface 20a is located on the lower side, and the back surface 20b is located on the upper side.

於模板20之正面20a,形成有處理區域21,其用於使用作為處理液之鍍敷液對晶片11進行鍍敷處理。處理區域21於與晶圓10之複數個晶片11相對應之位置形成有複數個。再者,作為鍍敷液,例如使用將硫酸銅與硫酸溶解而得之混合液。 On the front surface 20a of the template 20, a processing region 21 for plating the wafer 11 using a plating solution as a processing liquid is formed. The processing region 21 is formed in plural at positions corresponding to the plurality of wafers 11 of the wafer 10. Further, as the plating solution, for example, a mixed solution obtained by dissolving copper sulfate and sulfuric acid is used.

又,於模板20之正面20a,形成有空氣供給溝22。空氣供給溝22於複數個處理區域21、21間延伸,呈格子狀地形成於與晶圓10之切割道12相對應之位置上。空氣供給溝22於模板20之側面開口,形成有模板側面開口部22a。而且,空氣供給溝22係於面方向貫通模板20而形成。又,空氣供給溝22具有較正面20a凹陷之溝形狀,且較處理區域21低地形成。而且,於將模板20與晶圓10對向地配置之狀態下,空氣供給溝22可向切割道12供給空氣。再者,空氣供給溝22之位置或形狀並不限定於本實施形態,只要可向切割道12供給空氣,便可任意地設計。 Further, an air supply groove 22 is formed on the front surface 20a of the template 20. The air supply groove 22 extends between the plurality of processing regions 21 and 21 and is formed in a lattice shape at a position corresponding to the dicing street 12 of the wafer 10. The air supply groove 22 is opened on the side surface of the template 20, and a template side opening portion 22a is formed. Further, the air supply groove 22 is formed to penetrate the template 20 in the surface direction. Further, the air supply groove 22 has a groove shape which is recessed from the front surface 20a and is formed lower than the treatment area 21. Further, in a state where the template 20 and the wafer 10 are opposed to each other, the air supply groove 22 can supply air to the dicing street 12. Further, the position or shape of the air supply groove 22 is not limited to this embodiment, and any air can be supplied to the cutting path 12, and can be arbitrarily designed.

於模板20,形成有複數個用以排出對準液之對準液排出孔23。對準液排出孔23係於厚度方向自正面10a貫通至背面10b之細管。又,對準液排出孔23連通於空氣供給溝22。即,對準液排出孔23形成為於將模板20與晶圓10對向地配置之狀態下,位於切割道12之正上方。再者,作為對準液,例如使用純水。 In the template 20, a plurality of alignment liquid discharge holes 23 for discharging the alignment liquid are formed. The alignment liquid discharge hole 23 is a thin tube that penetrates from the front surface 10a to the back surface 10b in the thickness direction. Further, the alignment liquid discharge hole 23 communicates with the air supply groove 22. That is, the alignment liquid discharge hole 23 is formed to be positioned directly above the dicing street 12 in a state in which the stencil 20 and the wafer 10 are opposed to each other. Further, as the alignment liquid, for example, pure water is used.

於各對準液排出孔23,與該對準液排出孔23連通地設置有對準液排出槽24。對準液排出槽24設置於模板20之背面20b。對準液排出槽24為可貯存之槽以排出對準液,且具有收容對準液之特定之容積。於本實施形態中,如圖5所示,對準液排出槽24具有自對準液排出孔23分支成複數個細溝24a之細溝構造。再者,對準液排出槽24之內部之構成並不限定於此,可任意地設計。例如亦可利用多孔質體構成對準液排出槽24。針對通過對準液排出孔23進入至多孔質體之對準液,毛細管現 象發揮作用。如海綿吸收水般多孔質體亦吸收對準液,故而發揮自對準液排出槽24汲取對準液之作用。 The alignment liquid discharge grooves 24 are provided in the alignment liquid discharge holes 23 in communication with the alignment liquid discharge holes 23. The alignment liquid discharge groove 24 is provided on the back surface 20b of the template 20. The alignment liquid discharge tank 24 is a storable tank for discharging the alignment liquid and has a specific volume for accommodating the alignment liquid. In the present embodiment, as shown in FIG. 5, the alignment liquid discharge groove 24 has a rill structure in which a plurality of narrow grooves 24a are branched from the alignment liquid discharge holes 23. Further, the configuration of the inside of the alignment liquid discharge groove 24 is not limited thereto, and can be arbitrarily designed. For example, the alignment liquid discharge groove 24 may be formed of a porous body. For the alignment liquid that enters the porous body through the alignment liquid discharge hole 23, the capillary is now Like to play a role. If the sponge absorbs water, the porous body also absorbs the alignment liquid, so that the self-aligning liquid discharge groove 24 functions as an alignment liquid.

對準液排出孔23與對準液排出槽24以如下方式設計:於將模板20與晶圓10對向地配置之狀態下,對準液利用毛細管現象自切割道12經由對準液排出孔23而流通至對準液排出槽24。例如若使切割道12之寬度、對準液排出孔23之直徑、對準液排出槽24之細溝24a之寬度依序逐步變小,則使對準液產生毛細管現象。因此,即便不使用泵等之外在的力,亦可排出對準液。 The alignment liquid discharge hole 23 and the alignment liquid discharge groove 24 are designed in such a manner that, in a state in which the template 20 and the wafer 10 are opposed to each other, the alignment liquid is ejected from the cutting path 12 through the alignment liquid discharge hole by capillary action. 23 flows to the alignment liquid discharge tank 24. For example, if the width of the scribe line 12, the diameter of the alignment liquid discharge hole 23, and the width of the narrow groove 24a of the alignment liquid discharge groove 24 are gradually reduced, the alignment liquid is caused to have a capillary phenomenon. Therefore, the alignment liquid can be discharged without using a force other than a pump or the like.

如圖3及圖4所示,於模板20,形成有供給鍍敷液之作為處理液供給孔之鍍敷液供給孔25、及排出鍍敷液之作為處理液排出孔之鍍敷液排出孔26。鍍敷液供給孔25與鍍敷液排出孔26分別為於厚度方向自正面20a貫通至背面20b之細管,且於正面20a開口。又,鍍敷液供給孔25與鍍敷液排出孔26分別於每一處理區域21各設置有一處。 As shown in FIG. 3 and FIG. 4, in the template 20, a plating liquid supply hole 25 as a processing liquid supply hole for supplying a plating liquid, and a plating liquid discharge hole as a processing liquid discharge hole for discharging a plating liquid are formed. 26. The plating solution supply hole 25 and the plating solution discharge hole 26 are thin tubes that penetrate from the front surface 20a to the back surface 20b in the thickness direction, and are opened to the front surface 20a. Further, a plating liquid supply hole 25 and a plating liquid discharge hole 26 are provided in each of the processing regions 21, respectively.

於各鍍敷液供給孔25,與該鍍敷液供給孔25連通地設置有作為處理液供給槽之鍍敷液供給槽27。又,於各鍍敷液排出孔26,亦與該鍍敷液排出孔26連通地設置有作為處理液排出槽之鍍敷液排出槽28。鍍敷液供給槽27與鍍敷液排出槽28分別設置於模板20之背面20b。 In each of the plating solution supply holes 25, a plating solution supply tank 27 as a processing liquid supply tank is provided in communication with the plating solution supply hole 25. Further, in each plating liquid discharge hole 26, a plating liquid discharge groove 28 as a processing liquid discharge tank is also provided in communication with the plating liquid discharge hole 26. The plating solution supply tank 27 and the plating solution discharge tank 28 are provided on the back surface 20b of the template 20, respectively.

鍍敷液供給槽27為可貯存之槽以供給鍍敷液。於本實施形態中,如圖5所示,鍍敷液供給槽27具有分支成複數個細溝27a之細溝構造。於此情形時,供給至細溝27a且於該細溝27a內前進之鍍敷液進入至鍍敷液供給孔25。如此,藉由利用細管或細溝構成自鍍敷液供給槽27至鍍敷液供給孔25,而使處於其內部之鍍敷液產生毛細管現象。因此,即便不使用泵等之外在的力,亦可供給鍍敷液。再者,鍍敷液供給槽27之內部之構成並不限定於此,可任意地設計。 The plating solution supply tank 27 is a storable tank for supplying a plating liquid. In the present embodiment, as shown in FIG. 5, the plating solution supply tank 27 has a rill structure which is branched into a plurality of narrow grooves 27a. In this case, the plating liquid supplied to the narrow groove 27a and advanced in the narrow groove 27a enters the plating liquid supply hole 25. In this manner, the plating solution supply hole 27 is formed by the thin tube or the narrow groove from the plating solution supply groove 27 to the plating solution supply hole 25. Therefore, the plating solution can be supplied without using a force other than a pump or the like. Further, the configuration of the inside of the plating solution supply tank 27 is not limited thereto, and can be arbitrarily designed.

鍍敷液排出槽28為可貯存之槽以排出鍍敷液,且具有收容鍍敷液之特定之容積。於本實施形態中,鍍敷液排出槽28具有自鍍敷液排出 孔26分支成複數個細溝28a之構成。如此,藉由利用細管或細溝構成自鍍敷液排出孔26至鍍敷液排出槽28,而使處於其內部之鍍敷液產生毛細管現象。因此,即便不使用泵等之外在的力,亦可排出鍍敷液。再者,鍍敷液排出槽28之內部之構成並不限定於此,可任意地設計。例如亦可利用多孔質體構成鍍敷液排出槽28。針對通過鍍敷液排出孔26進入至多孔質體之鍍敷液,毛細管現象發揮作用。如海綿吸收水般多孔質體亦吸收鍍敷液,故而發揮自鍍敷液排出槽28汲取鍍敷液之作用。 The plating solution discharge tank 28 is a storable tank for discharging the plating liquid and has a specific volume for accommodating the plating liquid. In the present embodiment, the plating solution discharge tank 28 is discharged from the plating solution. The hole 26 is branched into a plurality of fine grooves 28a. Thus, the plating liquid in the inside thereof is caused to have a capillary phenomenon by forming the plating liquid discharge hole 26 from the plating liquid discharge hole 26 by the thin tube or the fine groove. Therefore, the plating solution can be discharged without using a force other than a pump or the like. Further, the configuration of the inside of the plating solution discharge tank 28 is not limited thereto, and can be arbitrarily designed. For example, the plating solution discharge groove 28 may be formed of a porous body. The capillary phenomenon acts on the plating solution that has entered the porous body through the plating solution discharge hole 26. If the sponge absorbs water, the porous body also absorbs the plating solution, so that it acts as a plating solution from the plating solution discharge tank 28.

鍍敷液供給槽27、鍍敷液供給孔25、鍍敷液排出孔26、鍍敷液排出槽28以如下方式設計:於將模板20與晶圓10對向地配置之狀態下,鍍敷液利用毛細管現象自鍍敷液供給槽27而流通至鍍敷液排出槽28。例如若使鍍敷液供給槽27之細溝27a之寬度、鍍敷液供給孔25之直徑、鍍敷液排出孔26之直徑、鍍敷液排出槽28之細溝28a之寬度依序逐步變小,則使鍍敷液產生毛細管現象。關於具體之尺寸,可使用公知之拉普拉斯式等而算出,或者亦可進行模擬或實驗等而導出。於此情形時,自鍍敷液供給孔25對處理區域21供給新鍍敷液,進而自鍍敷液排出孔26排出處理後之鍍敷液。如此,處理區域21一直被供給新的鍍敷液,由於鍍敷液不滯留,故而可適當地進行該鍍敷處理。 The plating solution supply tank 27, the plating solution supply hole 25, the plating liquid discharge hole 26, and the plating liquid discharge groove 28 are designed to be plated in a state in which the template 20 and the wafer 10 are opposed to each other. The liquid flows from the plating solution supply tank 27 by capillary action to the plating solution discharge tank 28. For example, the width of the narrow groove 27a of the plating solution supply tank 27, the diameter of the plating solution supply hole 25, the diameter of the plating liquid discharge hole 26, and the width of the narrow groove 28a of the plating liquid discharge groove 28 are gradually changed. Small, the plating solution is capillary. The specific size can be calculated using a known Laplace type or the like, or can be derived by simulation, experiment, or the like. In this case, a new plating solution is supplied from the plating solution supply hole 25 to the processing region 21, and the treated plating solution is discharged from the plating solution discharge hole 26. In this way, the processing region 21 is always supplied with a new plating solution, and since the plating solution is not retained, the plating treatment can be appropriately performed.

再者,於本實施形態中,空氣供給溝22、對準液排出孔23、鍍敷液供給孔25、鍍敷液排出孔26可藉由例如光微影處理及蝕刻處理而同時形成。同樣地,對準液排出槽24、鍍敷液供給槽27、鍍敷液排出槽28亦可藉由例如光微影處理及蝕刻處理而同時形成。 Further, in the present embodiment, the air supply groove 22, the alignment liquid discharge hole 23, the plating liquid supply hole 25, and the plating liquid discharge hole 26 can be simultaneously formed by, for example, photolithography and etching. Similarly, the alignment liquid discharge tank 24, the plating liquid supply tank 27, and the plating liquid discharge tank 28 can be simultaneously formed by, for example, photolithography processing and etching treatment.

如圖4所示,於模板20之處理區域21,設置有用以對該處理區域21之鍍敷液施加電壓之模板側電極29。模板側電極29設置為於將模板20與晶圓10對向地配置之狀態下,位於貫通孔13之正上方。 As shown in FIG. 4, a template side electrode 29 for applying a voltage to the plating solution of the processing region 21 is provided in the processing region 21 of the template 20. The template side electrode 29 is disposed directly above the through hole 13 in a state in which the template 20 and the wafer 10 are opposed to each other.

其次,對使用如以上般構成之晶圓10及模板20之鍍敷處理進行說明。 Next, a plating process using the wafer 10 and the template 20 configured as described above will be described.

首先,如圖6所示,向晶圓10之正面10a整面供給對準液P。對準液P亦進入至切割道12與貫通孔13之內部。再者,於在上述鍍敷處理前之製程,例如蝕刻步驟之後,要將晶圓10之正面10a洗淨,而上述對準液P亦可使用該洗淨所使用之純水。即,無需利用另外之步驟進行洗淨後之乾燥、或對準液P之供給,晶圓10之洗淨兼作對準液P之供給。 First, as shown in FIG. 6, the alignment liquid P is supplied to the entire surface 10a of the wafer 10. The alignment liquid P also enters the inside of the dicing street 12 and the through hole 13. Further, after the plating process, for example, the etching step, the front surface 10a of the wafer 10 is washed, and the alignment liquid P may be pure water used for the cleaning. That is, it is not necessary to perform the cleaning after the cleaning by another step or the supply of the alignment liquid P, and the cleaning of the wafer 10 serves as the supply of the alignment liquid P.

繼而,如圖7所示,於晶圓10之正面10a側,隔著對準液P而配置模板20。模板20係以晶片11與處理區域21對向之方式而配置。再者,晶片11與處理區域21無需嚴密地對應。如圖7所示,即便於該等之位置稍微偏移之情形時,亦於下述之步驟中進行晶圓10與模板20之位置調整。 Then, as shown in FIG. 7, the template 20 is placed on the front surface 10a side of the wafer 10 with the alignment liquid P interposed therebetween. The template 20 is disposed such that the wafer 11 and the processing region 21 face each other. Furthermore, the wafer 11 does not need to be closely associated with the processing region 21. As shown in Fig. 7, even when the positions are slightly offset, the position adjustment of the wafer 10 and the template 20 is performed in the following steps.

模板20之配置係藉由保持機構30而進行。藉由該保持機構30,將模板20保持為特定之高度。再者,只要保持機構30為可保持模板20者,則其構成並無特別限定。 The configuration of the template 20 is performed by the holding mechanism 30. The template 20 is held at a specific height by the holding mechanism 30. In addition, the configuration of the holding mechanism 30 is not particularly limited as long as it can hold the template 20.

配置模板20後,如圖8及圖9所示,對準液P利用毛細管現象通過空氣供給溝22進入至對準液排出孔23。如圖10及圖11所示,該對準液P利用毛細管現象進而流通至對準液排出槽24而排出。此時,隨著對準液P之排出,空氣自模板側面開口部22a與晶圓側面開口部12a進入(圖11之箭頭),向於空氣供給溝22與切割道12之間形成之空間40供給空氣A。如此,於晶片11之周緣部與處理區域21之周緣部之間形成氣液界面F。 After the template 20 is placed, as shown in FIGS. 8 and 9, the alignment liquid P enters the alignment liquid discharge hole 23 through the air supply groove 22 by capillary action. As shown in FIGS. 10 and 11, the alignment liquid P is further discharged by the capillary phenomenon to the alignment liquid discharge groove 24. At this time, as the alignment liquid P is discharged, air enters from the template side opening portion 22a and the wafer side opening portion 12a (arrow of FIG. 11), and a space 40 is formed between the air supply groove 22 and the dicing street 12. Supply air A. In this manner, a gas-liquid interface F is formed between the peripheral portion of the wafer 11 and the peripheral portion of the processing region 21.

於如此般形成氣液界面F之期間,模板20藉由保持機構30而保持為特定之高度。換言之,模板20之高度不會隨著對準液P自切割道12排出至對準液排出槽24而下降。因此,可維持切割道12、對準液排出孔23、對準液排出槽24之關係,而可維持對準液P產生之毛細管現象。因此,可適當地形成氣液界面F。 During the formation of the gas-liquid interface F as such, the template 20 is maintained at a specific height by the holding mechanism 30. In other words, the height of the template 20 does not decrease as the alignment liquid P is discharged from the dicing street 12 to the alignment liquid discharge groove 24. Therefore, the relationship between the dicing street 12, the alignment liquid discharge hole 23, and the alignment liquid discharge groove 24 can be maintained, and the capillary phenomenon of the alignment liquid P can be maintained. Therefore, the gas-liquid interface F can be formed as appropriate.

再者,於形成氣液界面F之期間,晶片11與處理區域21間之對準 液P利用毛細管現象亦進入至鍍敷液供給孔25與鍍敷液排出孔26。 Furthermore, during the formation of the gas-liquid interface F, the alignment between the wafer 11 and the processing region 21 The liquid P also enters the plating solution supply hole 25 and the plating solution discharge hole 26 by capillary action.

於晶片11與處理區域21之間形成氣液界面F後,如圖12所示,解除利用保持機構30對模板20之保持。如此,如圖13所示,藉由氣液界面F中之對準液P之表面張力,使模板20移動之恢復力(圖13之箭頭)作用於模板20。如此,即便於晶片11之位置與處理區域21之位置偏移之情形時,模板20亦以使該等晶片11與處理區域21對向之方式移動,而高精度地進行晶圓10與模板20之位置調整。 After the gas-liquid interface F is formed between the wafer 11 and the processing region 21, as shown in FIG. 12, the holding of the template 20 by the holding mechanism 30 is released. Thus, as shown in FIG. 13, the restoring force (arrow of FIG. 13) for moving the template 20 is applied to the template 20 by the surface tension of the alignment liquid P in the gas-liquid interface F. Thus, even when the position of the wafer 11 is shifted from the position of the processing region 21, the template 20 is moved in such a manner that the wafers 11 and the processing region 21 face each other, and the wafer 10 and the template 20 are accurately performed. Position adjustment.

進行晶圓10與模板20之位置調整後,繼而進行鍍敷處理。於進行該鍍敷處理時,如圖14所示,於晶圓側電極14與模板側電極29,連接直流電源50。晶圓側電極14連接於直流電源50之負極側。模板側電極29連接於直流電源50之正極側。再者,直流電源50係作為對模板20之複數個晶圓側電極14與複數個模板側電極29共用之電源而使用。 After the position adjustment of the wafer 10 and the template 20 is performed, a plating process is performed. When this plating process is performed, as shown in FIG. 14, the DC power source 50 is connected to the wafer side electrode 14 and the template side electrode 29. The wafer side electrode 14 is connected to the negative electrode side of the DC power source 50. The template side electrode 29 is connected to the positive electrode side of the DC power source 50. Further, the DC power source 50 is used as a power source shared by a plurality of wafer side electrodes 14 of the template 20 and a plurality of template side electrodes 29.

其後,如圖15所示,向鍍敷液供給槽27供給鍍敷液M,該鍍敷液M如圖16所示般利用其毛細管現象自鍍敷液供給槽27流通至鍍敷液排出槽28。即,處於自鍍敷液供給槽27至鍍敷液排出槽28之對準液P被替換為鍍敷液M。而且,供給至晶片11上之鍍敷液M進入至貫通孔13,從而該貫通孔13內之對準液P亦被替換為鍍敷液M。 Then, as shown in FIG. 15, the plating liquid M is supplied to the plating solution supply tank 27, and the plating liquid M flows from the plating liquid supply tank 27 to the plating liquid discharge by the capillary phenomenon as shown in FIG. Slot 28. That is, the alignment liquid P in the self-plating solution supply tank 27 to the plating liquid discharge tank 28 is replaced with the plating liquid M. Further, the plating liquid M supplied onto the wafer 11 enters the through hole 13, and the alignment liquid P in the through hole 13 is also replaced with the plating liquid M.

其後,藉由直流電源50,以模板側電極29為陽極、以晶圓側電極14為陰極而對鍍敷液M施加電壓。如此,對貫通孔13內之鍍敷液M進行電解鍍敷,而如圖17所示,於貫通孔13內析出鍍銅60a。 Thereafter, a voltage is applied to the plating solution M by the DC power source 50 using the template side electrode 29 as an anode and the wafer side electrode 14 as a cathode. In this manner, the plating solution M in the through hole 13 is electrolytically plated, and as shown in FIG. 17, the copper plating 60a is deposited in the through hole 13.

其後,於貫通孔13內進行鍍敷處理後之鍍敷液M被排出至鍍敷液排出孔26。如此,晶片11上一直連續地被供給新的鍍敷液M,鍍敷液M不會滯留。因此,可於貫通孔13內均勻地析出鍍銅50。 Thereafter, the plating liquid M after the plating treatment in the through hole 13 is discharged to the plating liquid discharge hole 26. In this manner, a new plating solution M is continuously supplied to the wafer 11, and the plating solution M does not remain. Therefore, the copper plating 50 can be uniformly deposited in the through hole 13.

而且,藉由連續地進行該鍍敷處理,鍍銅60a成長,而如圖18所示,於貫通孔13內形成貫通電極60。 Further, by continuously performing the plating treatment, the copper plating 60a is grown, and as shown in FIG. 18, the through electrode 60 is formed in the through hole 13.

根據以上之實施形態,對晶圓10之正面10a整面供給對準液P之 後,僅存在於切割道12上之對準液P利用毛細管現象經由對準液排出孔23而排出至對準液排出槽24。同時,向空氣供給溝22與切割道12之間形成之空間40供給空氣A,藉此於晶片11之周緣部與處理區域21之周緣部之間形成氣液界面F。而且,藉由氣液界面F中之對準液P之表面張力,使模板20移動之恢復力發生作用,而高精度地進行模板20相對於晶圓10之位置調整。如此,於本實施形態中,由於對晶圓10之正面10a整面供給對準液P,故而消除先前之對準液供給之困難性,可適當且容易地進行晶圓10與模板20之位置調整。 According to the above embodiment, the alignment liquid P is supplied to the entire surface 10a of the wafer 10 Thereafter, only the alignment liquid P existing on the dicing street 12 is discharged to the alignment liquid discharge groove 24 through the alignment liquid discharge hole 23 by capillary action. At the same time, the air A is supplied to the space 40 formed between the air supply groove 22 and the dicing street 12, whereby the gas-liquid interface F is formed between the peripheral edge portion of the wafer 11 and the peripheral portion of the processing region 21. Further, by the surface tension of the alignment liquid P in the gas-liquid interface F, the restoring force of the movement of the template 20 acts, and the positional adjustment of the template 20 with respect to the wafer 10 is performed with high precision. As described above, in the present embodiment, since the alignment liquid P is supplied to the entire surface 10a of the wafer 10, the difficulty of supplying the previous alignment liquid is eliminated, and the position of the wafer 10 and the template 20 can be appropriately and easily performed. Adjustment.

又,於將模板20配置於晶圓10上之後至在晶片11與處理區域21之間形成氣液界面F為止之期間,藉由保持機構30保持模板20。因此,於對準液P自切割道12排出至對準液排出槽24之期間,亦可維持對準液P產生之毛細管現象,而可適當地形成氣液界面F。 Further, after the template 20 is placed on the wafer 10 until the gas-liquid interface F is formed between the wafer 11 and the processing region 21, the template 20 is held by the holding mechanism 30. Therefore, while the alignment liquid P is discharged from the dicing street 12 to the alignment liquid discharge groove 24, the capillary phenomenon generated by the alignment liquid P can be maintained, and the gas-liquid interface F can be appropriately formed.

又,用於對晶圓10與模板20進行位置調整之對準液P為純水。如本實施形態般於晶圓10形成貫通電極60時,事先要將晶圓10之正面10a洗淨。於正面10a之洗淨中,例如使用純水作為洗淨液,藉由利用該純水,而無需另外供給對準液。因此,可效率良好地進行晶圓10與模板20之位置調整。 Further, the alignment liquid P for adjusting the position of the wafer 10 and the template 20 is pure water. When the through electrode 60 is formed on the wafer 10 as in the present embodiment, the front surface 10a of the wafer 10 is washed in advance. In the washing of the front surface 10a, for example, pure water is used as the washing liquid, and by using the pure water, it is not necessary to supply the aligning liquid separately. Therefore, the position adjustment of the wafer 10 and the template 20 can be performed efficiently.

又,由於氣液界面F係利用切割道12(晶片11之周緣部)而形成,故而無需於晶圓10上在形成元件之區域另外形成溝。因此,可使晶圓10上之空間有用地活用,從而包含電子電路或配線等之半導體元件之設計之自由度提高。 Further, since the gas-liquid interface F is formed by the dicing street 12 (the peripheral portion of the wafer 11), it is not necessary to form a groove on the wafer 10 in the region where the element is formed. Therefore, the space on the wafer 10 can be effectively utilized, and the degree of freedom in designing a semiconductor element including an electronic circuit or wiring can be improved.

又,由於如此般適當地進行晶圓10與模板20之位置調整,故而其後可向晶片11上(貫通孔13內)適當地供給鍍敷液M。而且,可將貫通孔13內之對準液P替換為鍍敷液M,而適當地進行鍍敷處理。 Further, since the position adjustment of the wafer 10 and the template 20 is appropriately performed as described above, the plating liquid M can be appropriately supplied to the wafer 11 (in the through hole 13). Further, the alignment liquid P in the through hole 13 can be replaced with the plating liquid M, and the plating treatment can be appropriately performed.

此處,先前,於貫通孔內形成貫通電極時,貫通孔內部存在空氣,故而需要使該空氣溶解於鍍敷液。上述使空氣溶解於鍍敷液之步驟較 為困難且花費時間。相對於此,於本實施形態中,由於將對準液P替換為鍍敷液M,故而可省略先前之使空氣溶解之步驟,而可效率良好地進行鍍敷處理。 Here, when a through electrode is formed in the through hole, air is present inside the through hole, and therefore it is necessary to dissolve the air in the plating solution. The above steps of dissolving air in the plating solution It is difficult and time consuming. On the other hand, in the present embodiment, since the alignment liquid P is replaced with the plating liquid M, the previous step of dissolving the air can be omitted, and the plating treatment can be performed efficiently.

又,近年來,於半導體元件中,圖案之微細化、高縱橫化不斷發展,於對晶圓進行洗淨之步驟中,擔心有因洗淨液之表面張力而產生之所謂的圖案崩塌缺陷。於本實施形態中,藉由將純水之對準液P替換為鍍敷液M,而可一口氣連續地進行自晶圓10之洗淨至貫通電極60之形成。因此,可抑制如上所述之圖案崩塌。 Further, in recent years, in the semiconductor element, the pattern is refined and the height and cross direction are continuously developed, and in the step of cleaning the wafer, there is a fear of a so-called pattern collapse defect caused by the surface tension of the cleaning liquid. In the present embodiment, by replacing the alignment liquid P of pure water with the plating solution M, the cleaning from the wafer 10 to the formation of the through electrode 60 can be continuously performed in one go. Therefore, pattern collapse as described above can be suppressed.

於以上之實施形態中,將模板側電極29設置於模板20之與晶圓10對向之面,但模板側電極29之配置並不限於此。如圖19所示,亦可於鍍敷液供給槽27之細溝27a之底面,設置模板側電極29。即,配置於模板20之與晶圓10對向之面之相反側。如觀察圖20亦可知,鍍敷液供給槽27之細溝27a對於鍍敷液M具有較大之表面積。因此,配置於細溝27a之底面之模板側電極29可更高效率地進行與鍍敷液M之電荷交換(鍍敷處理)。 In the above embodiment, the template side electrode 29 is provided on the surface of the template 20 opposite to the wafer 10, but the arrangement of the template side electrode 29 is not limited thereto. As shown in FIG. 19, the template side electrode 29 may be provided on the bottom surface of the narrow groove 27a of the plating solution supply tank 27. That is, it is disposed on the opposite side of the surface of the template 20 opposite to the wafer 10. As can be seen from observation of Fig. 20, the narrow groove 27a of the plating solution supply tank 27 has a large surface area for the plating liquid M. Therefore, the template side electrode 29 disposed on the bottom surface of the narrow groove 27a can perform charge exchange (plating treatment) with the plating solution M more efficiently.

進而,如圖21所示,亦可於模板側電極29之下方,設置間接電極70。間接電極70係藉由利用絕緣體72覆蓋電極71而形成。間接電極70藉由開關73而於模板側電極29之連接與直流電源50之連接之間進行切換。於此情形時,首先,如圖22所示,使模板側電極29為電性浮動之狀態之後,將間接電極70連接於直流電源50之正極側。於間接電極70與晶圓側電極14之間施加電場,故而鍍敷液M中之正離子與負離子分別被牽引至晶圓側電極14與間接電極70。然而,由於間接電極70之電極71被絕緣體72覆蓋,故而被牽引之離子不進行電荷交換,而堆積於模板側電極29與晶圓側電極14之表面。其次,如圖23所示,藉由切換開關73,而使間接電極70與模板側電極29連接。於是,儲存於間接電極70之正電荷移動至模板側電極29,與堆積於模板側電極29之表面之 負離子進行電荷交換。於晶圓側電極14亦進行電荷交換,因此正離子被還原,而於晶圓側電極14之表面析出鍍銅60a。若如此般進行控制,則可將鍍敷液中之離子效率良好地搬送至晶圓側電極14,故而可使鍍敷處理加速。 Further, as shown in FIG. 21, the indirect electrode 70 may be provided below the template side electrode 29. The indirect electrode 70 is formed by covering the electrode 71 with an insulator 72. The indirect electrode 70 is switched between the connection of the template side electrode 29 and the connection of the DC power source 50 by the switch 73. In this case, first, as shown in FIG. 22, after the template side electrode 29 is electrically floating, the indirect electrode 70 is connected to the positive electrode side of the DC power source 50. Since an electric field is applied between the indirect electrode 70 and the wafer side electrode 14, positive ions and negative ions in the plating solution M are drawn to the wafer side electrode 14 and the indirect electrode 70, respectively. However, since the electrode 71 of the indirect electrode 70 is covered by the insulator 72, the pulled ions are deposited on the surfaces of the template side electrode 29 and the wafer side electrode 14 without charge exchange. Next, as shown in FIG. 23, the indirect electrode 70 is connected to the template side electrode 29 by switching the switch 73. Then, the positive charge stored in the indirect electrode 70 is moved to the template side electrode 29, and is deposited on the surface of the template side electrode 29. Negative ions carry out charge exchange. Since the wafer side electrode 14 also performs charge exchange, the positive ions are reduced, and copper plating 60a is deposited on the surface of the wafer side electrode 14. By controlling in this manner, the ions in the plating solution can be efficiently transferred to the wafer-side electrode 14, so that the plating treatment can be accelerated.

於以上之實施形態之模板20,如圖24及圖25所示,亦可設置對準液逸出孔80與對準液逸出槽81。對準液逸出孔80係於厚度方向自正面20a貫通至背面20b之細管,且於正面20a開口。又,對準液逸出孔80於每一處理區域21設置有一處。 In the template 20 of the above embodiment, as shown in FIGS. 24 and 25, the alignment liquid escape hole 80 and the alignment liquid escape groove 81 may be provided. The alignment liquid escape hole 80 is a thin tube that penetrates from the front surface 20a to the back surface 20b in the thickness direction, and is opened to the front surface 20a. Further, the alignment liquid escape hole 80 is provided at one portion of each of the processing regions 21.

對準液逸出槽81連通於對準液逸出孔80,設置於模板20之背面20b。對準液逸出槽81為可貯存之槽以排出對準液P。於本實施形態中,如圖26所示,對準液逸出槽81具有自對準液逸出孔80分支成複數個細溝81a之構成。如此,藉由利用細管或細溝構成自對準液逸出孔80至對準液逸出槽81,而使處於其內部之對準液P產生毛細管現象。再者,對準液逸出槽81之內部之構成並不限定於此,可任意地設計。例如亦可利用多孔質體構成對準液逸出槽81。 The alignment liquid escape groove 81 communicates with the alignment liquid escape hole 80 and is provided on the back surface 20b of the template 20. The alignment liquid escape groove 81 is a storable tank to discharge the alignment liquid P. In the present embodiment, as shown in Fig. 26, the alignment liquid escape groove 81 has a configuration in which a plurality of narrow grooves 81a are branched from the alignment liquid escape hole 80. Thus, by constituting the self-aligning liquid escape hole 80 to the alignment liquid escape groove 81 by the thin tube or the fine groove, the alignment liquid P inside thereof is caused to cause a capillary phenomenon. Further, the configuration of the inside of the liquid escaping groove 81 is not limited thereto, and can be arbitrarily designed. For example, the alignment liquid escape groove 81 may be formed of a porous body.

如上所述般於晶片11與處理區域21之間形成氣液界面F後,解除利用保持機構30對模板20之保持,進行晶圓10與模板20之位置調整。即,於後續進行之鍍敷處理中,模板20未被保持機構30保持,但於該鍍敷處理中亦需要維持模板20之位置。然而,若解除利用保持機構30對模板20之保持,則存在如下情況:因模板20之自重,而對晶片11與處理區域21之間之對準液P(鍍敷液M)作用壓力,從而氣液界面F成為正壓。於此情形時,無法維持模板20之位置。 After the gas-liquid interface F is formed between the wafer 11 and the processing region 21 as described above, the holding of the template 20 by the holding mechanism 30 is released, and the position of the wafer 10 and the template 20 is adjusted. That is, in the subsequent plating process, the template 20 is not held by the holding mechanism 30, but it is also necessary to maintain the position of the template 20 in the plating process. However, if the holding of the template 20 by the holding mechanism 30 is released, there is a case where the pressure of the alignment liquid P (plating liquid M) between the wafer 11 and the processing region 21 is applied due to the weight of the template 20, thereby The gas-liquid interface F becomes a positive pressure. In this case, the position of the template 20 cannot be maintained.

為避免上述情況,於本實施形態中,如圖27所示,利用毛細管現象使晶片11與處理區域21之間之對準液P(鍍敷液M)自對準液逸出孔80流通至對準液逸出槽81。如此,可抑制氣液界面F成為正壓之情況,使晶片11與處理區域21之間之對準液P(鍍敷液M)產生適當之保持力。藉 由該保持力,模板20吸附於晶圓10,而維持該模板20之位置。 In order to avoid the above, in the present embodiment, as shown in FIG. 27, the alignment liquid P (plating liquid M) between the wafer 11 and the processing region 21 is caused to flow from the alignment liquid escape hole 80 by capillary action. The alignment liquid escapes the groove 81. In this manner, it is possible to suppress the gas-liquid interface F from becoming a positive pressure, and to generate an appropriate holding force for the alignment liquid P (plating liquid M) between the wafer 11 and the processing region 21. borrow From this retention, the template 20 is adsorbed to the wafer 10 while maintaining the position of the template 20.

根據本實施形態,藉由於模板20設置對準液逸出孔80與對準液逸出槽81,而於進行鍍敷處理之期間,可適當地維持模板20之位置。因此,可適當地進行該鍍敷處理。 According to the present embodiment, since the alignment liquid escape hole 80 and the alignment liquid escape groove 81 are provided in the template 20, the position of the template 20 can be appropriately maintained during the plating process. Therefore, the plating treatment can be suitably performed.

於以上之實施形態中,使用純水作為對準液P,但亦可使用其他對準液,例如鍍敷液或蝕刻液等。 In the above embodiment, pure water is used as the alignment liquid P, but other alignment liquid such as a plating solution or an etching liquid may be used.

於以上之實施形態中,在每一晶片11設置有鍍敷液供給槽27、鍍敷液排出槽28、對準液逸出槽81,但亦可將該等設為對複數個晶片11共用之槽。 In the above embodiment, the plating solution supply groove 27, the plating solution discharge groove 28, and the alignment liquid escape groove 81 are provided for each of the wafers 11, but these may be used for sharing the plurality of wafers 11. Slot.

於以上之實施形態中,於模板20形成有空氣供給溝22,但亦可省略該空氣供給溝22。總之,只要於模板20與晶圓10之間形成向切割道12上供給空氣之空間即可,於此情形時,空氣進入至該空間,而於晶片11之周緣部與處理區域21之周緣部之間形成氣液界面F。 In the above embodiment, the air supply groove 22 is formed in the template 20, but the air supply groove 22 may be omitted. In short, as long as a space for supplying air to the dicing street 12 is formed between the stencil 20 and the wafer 10, in this case, air enters the space, and the peripheral portion of the wafer 11 and the peripheral portion of the processing region 21 are formed. A gas-liquid interface F is formed between them.

於以上之實施形態中,對作為晶圓10之特定之處理而進行鍍敷處理之情況進行了說明,但本發明可應用於各種液體處理。亦可將本發明應用於例如使用蝕刻液之蝕刻處理等其他電場處理,或者亦可將本發明應用於例如使用洗淨液之洗淨處理等除電解處理以外之液體處理。又,亦可將本發明應用於半導體元件之檢查,例如可使接觸液總括地接觸微細且複數個貫通電極,以晶圓為單位檢查該貫通電極。進而,亦可將本發明應用於例如將基板彼此接合時之基板之位置調整。於此情形時,作為基板處理治具之模板20作為要接合於晶圓10之對向基板而發揮功能。又,亦可於進行基板彼此之位置對準之後,藉由紅外線等之照射而使基板彼此要接觸之面活化。 In the above embodiment, the case where the plating treatment is performed as the specific processing of the wafer 10 has been described, but the present invention is applicable to various liquid treatments. The present invention can also be applied to other electric field treatment such as etching treatment using an etching liquid, or the present invention can also be applied to liquid processing other than electrolytic treatment such as washing treatment using a cleaning liquid. Further, the present invention can also be applied to the inspection of a semiconductor element. For example, the contact liquid can be collectively brought into contact with a fine and a plurality of through electrodes, and the through electrodes can be inspected in units of wafers. Further, the present invention can also be applied to, for example, positional adjustment of a substrate when substrates are joined to each other. In this case, the template 20 as the substrate processing jig functions as a counter substrate to be bonded to the wafer 10. Further, after the substrates are aligned with each other, the surfaces on which the substrates are to be in contact with each other may be activated by irradiation of infrared rays or the like.

以上,一面參照隨附圖式一面對本發明之較佳之實施形態進行了說明,但本發明並不限定於該例。顯然業者可於申請專利範圍所記載之思想之範疇內想到各種變更例或修正例,應明白該等當然亦屬於本 發明之技術範圍內。 Hereinabove, the preferred embodiments of the present invention have been described with reference to the accompanying drawings, but the invention is not limited thereto. It is obvious that the practitioners may think of various modifications or amendments within the scope of the ideas described in the scope of application for patents, and it should be understood that these are of course also Within the technical scope of the invention.

20‧‧‧模板 20‧‧‧ template

20a‧‧‧正面 20a‧‧‧ positive

21‧‧‧處理區域 21‧‧‧Processing area

22‧‧‧空氣供給溝 22‧‧‧Air supply ditch

22a‧‧‧模板側面開口部 22a‧‧‧Template side opening

23‧‧‧對準液排出孔 23‧‧‧ alignment liquid discharge hole

25‧‧‧鍍敷液供給孔 25‧‧‧ plating solution supply hole

26‧‧‧鍍敷液排出孔 26‧‧‧ plating solution discharge hole

Claims (12)

一種基板處理方法,其係對形成有複數個半導體晶片之基板進行特定之處理者,且包括:第1步驟,其係對上述形成有複數個半導體晶片之基板之整個表面供給對準液;第2步驟,其係將形成有於厚度方向貫通之對準液排出孔之對向基板隔著上述對準液而配置於基板上;第3步驟,其係利用毛細管現象將上述對準液自上述半導體晶片間之切割道經由上述對準液排出孔而朝上述對向基板之上表面側排出,並且於上述對向基板與基板之間形成於上述切割道上之空間供給空氣,而於上述半導體晶片之周緣部與上述對向基板之間形成氣液界面;及第4步驟,其係藉由上述氣液界面中之上述對準液之表面張力,進行上述對向基板相對於基板之位置調整。 A substrate processing method for treating a substrate on which a plurality of semiconductor wafers are formed, and comprising: a first step of supplying an alignment liquid to an entire surface of the substrate on which the plurality of semiconductor wafers are formed; In the second step, the opposite substrate on which the alignment liquid discharge hole penetrating in the thickness direction is formed is disposed on the substrate via the alignment liquid, and the third step is to use the capillary phenomenon to apply the alignment liquid from the above a scribe line between the semiconductor wafers is discharged toward the upper surface side of the opposite substrate via the alignment liquid discharge hole, and air is supplied to a space formed on the scribe line between the opposite substrate and the substrate, and the semiconductor wafer is The gas-liquid interface is formed between the peripheral portion and the opposite substrate; and the fourth step is to adjust the position of the counter substrate relative to the substrate by the surface tension of the alignment liquid in the gas-liquid interface. 如請求項1之基板處理方法,其中於上述對向基板,在與上述切割道相對應之位置形成有於面方向貫通之空氣供給溝,上述對準液排出孔係連通於上述空氣供給溝而形成。 The substrate processing method according to claim 1, wherein the opposite substrate is formed with an air supply groove penetrating in a surface direction at a position corresponding to the dicing street, and the alignment liquid discharge hole is connected to the air supply groove. form. 如請求項1之基板處理方法,其中於上述對向基板之上表面,設置有連通於上述對準液排出孔之對準液排出槽,於上述第3步驟中,利用毛細管現象將上述對準液自上述切割道經由上述對準液排出孔而排出至上述對準液排出槽。 The substrate processing method of claim 1, wherein an alignment liquid discharge groove communicating with the alignment liquid discharge hole is provided on an upper surface of the opposite substrate, and in the third step, the alignment is performed by capillary action The liquid is discharged from the scribe line through the alignment liquid discharge hole to the alignment liquid discharge tank. 如請求項1之基板處理方法,其中於上述第2步驟中,藉由保持機構將上述對向基板保持為特定之高度,而將該對向基板配置於基板上,於上述第3步驟中,繼續利用上述保持機構保持上述對向基板, 於上述第4步驟中,解除利用上述保持機構對上述對向基板之保持,進行上述對向基板相對於基板之位置調整。 The substrate processing method according to claim 1, wherein in the second step, the opposing substrate is placed on the substrate by the holding mechanism to maintain the opposite substrate at a specific height, and in the third step, Continue to use the above holding mechanism to maintain the opposite substrate, In the fourth step, the holding of the opposing substrate by the holding means is released, and the positional adjustment of the opposing substrate with respect to the substrate is performed. 如請求項1之基板處理方法,其中於上述對向基板,形成有於厚度方向貫通之處理液供給孔、及於厚度方向貫通之處理液排出孔,於上述對向基板之上表面,設置有連通於上述處理液供給孔之處理液供給槽、及連通於上述處理液排出孔之處理液排出槽,於上述第4步驟之後包括第5步驟,該第5步驟係利用毛細管現象使處理液自上述處理液供給槽經由上述處理液供給孔、上述半導體晶片上、上述處理液排出孔而流通至上述處理液排出槽,將上述半導體晶片與上述對向基板之間之上述對準液替換為上述處理液,藉由該處理液對上述半導體晶片進行特定之處理。 The substrate processing method according to claim 1, wherein the counter substrate has a processing liquid supply hole penetrating in a thickness direction and a processing liquid discharge hole penetrating in a thickness direction, and an upper surface of the counter substrate is provided on the counter substrate a processing liquid supply tank that communicates with the processing liquid supply hole and a processing liquid discharge tank that communicates with the processing liquid discharge hole, and after the fourth step, includes a fifth step of utilizing a capillary phenomenon to cause the treatment liquid to be self-contained The processing liquid supply tank flows into the processing liquid discharge tank through the processing liquid supply hole, the semiconductor wafer, and the processing liquid discharge hole, and replaces the alignment liquid between the semiconductor wafer and the counter substrate The treatment liquid is subjected to a specific treatment of the semiconductor wafer by the treatment liquid. 如請求項5之基板處理方法,其中於上述對向基板,形成有於厚度方向貫通之液體逸出孔,於上述對向基板之上表面,設置有連通於上述液體逸出孔之液體逸出槽,於上述第5步驟中,利用毛細管現象將上述對準液或上述處理液自上述半導體晶片上經由上述液體逸出孔而排出至上述液體逸出槽,從而維持上述對向基板相對於基板之配置。 The substrate processing method of claim 5, wherein the opposite substrate is formed with a liquid escape hole penetrating in a thickness direction, and the upper surface of the opposite substrate is provided with a liquid escape communicating with the liquid escape hole In the fifth step, the alignment liquid or the treatment liquid is discharged from the semiconductor wafer through the liquid escape hole to the liquid escape groove by capillary action, thereby maintaining the opposite substrate relative to the substrate Configuration. 如請求項1之基板處理方法,其中上述對準液為純水。 The substrate processing method of claim 1, wherein the alignment liquid is pure water. 一種基板處理治具,其係用於對形成有複數個半導體晶片之基板進行特定之處理者,且形成有於厚度方向貫通之對準液排出孔,於上述形成有複數個半導體晶片之基板之整個表面被供給對準液,進而基板處理治具隔著上述對準液而配置於基板上之狀態下,上述對準液排出孔係以如下方式形成:利用毛細管現象上述 對準液自上述半導體晶片間之切割道經由上述對準液排出孔而朝基板處理治具之上表面側被排出,並且於上述基板處理治具與基板之間形成於上述切割道上之空間被供給空氣,而於上述半導體晶片之周緣部與基板處理治具之間形成氣液界面。 A substrate processing jig for treating a substrate on which a plurality of semiconductor wafers are formed, and forming an alignment liquid discharge hole penetrating in a thickness direction, in the substrate on which the plurality of semiconductor wafers are formed The aligning liquid is supplied to the entire surface, and the substrate processing jig is placed on the substrate via the alignment liquid. The alignment liquid discharge hole is formed in the following manner: The aligning liquid is discharged from the dicing line between the semiconductor wafers to the upper surface side of the substrate processing jig via the alignment liquid discharge hole, and a space formed on the dicing street between the substrate processing jig and the substrate is Air is supplied to form a gas-liquid interface between the peripheral portion of the semiconductor wafer and the substrate processing jig. 如請求項8之基板處理治具,其中於與上述切割道相對應之位置形成有於面方向貫通之空氣供給溝,上述對準液排出孔係連通於上述空氣供給溝而形成。 The substrate processing jig according to claim 8, wherein an air supply groove penetrating in a surface direction is formed at a position corresponding to the dicing street, and the alignment liquid discharge hole is formed to communicate with the air supply groove. 如請求項8之基板處理治具,其進而包含對準液排出槽,該對準液排出槽設置於基板處理治具之上表面,且連通於上述對準液排出孔,上述對準液排出槽係以如下方式設置:利用毛細管現象將上述對準液自上述切割道經由上述對準液排出孔而排出至上述對準液排出槽。 The substrate processing jig of claim 8, further comprising an alignment liquid discharge groove disposed on an upper surface of the substrate processing jig and communicating with the alignment liquid discharge hole, wherein the alignment liquid is discharged The groove system is provided in such a manner that the alignment liquid is discharged from the scribe line through the alignment liquid discharge hole to the alignment liquid discharge groove by capillary action. 如請求項8之基板處理治具,其進而包含:於厚度方向貫通之處理液供給孔;於厚度方向貫通之處理液排出孔;處理液供給槽,其設置於基板處理治具之上表面,並連通於上述處理液供給孔;及處理液排出槽,其設置於基板處理治具之上表面,並連通於上述處理液排出孔;且上述處理液供給槽、上述處理液供給孔、上述處理液排出孔及上述處理液排出槽係以利用毛細管現象使對上述半導體晶片進行特定之處理之處理液流通之方式設置。 The substrate processing jig according to claim 8, further comprising: a processing liquid supply hole penetrating in a thickness direction; a processing liquid discharge hole penetrating in a thickness direction; and a processing liquid supply tank provided on an upper surface of the substrate processing jig; And the processing liquid supply hole; and the processing liquid discharge tank provided on the upper surface of the substrate processing jig and connected to the processing liquid discharge hole; and the processing liquid supply tank, the processing liquid supply hole, and the treatment The liquid discharge hole and the treatment liquid discharge tank are provided such that the treatment liquid for performing the specific treatment on the semiconductor wafer is circulated by capillary action. 如請求項11之基板處理治具,其進而包含:於厚度方向貫通之液體逸出孔;及液體逸出槽,其設置於基板處理治具之上表面,並連通於上述 液體逸出孔;且上述液體逸出孔及上述液體逸出槽分別以如下方式設置:利用毛細管現象將上述對準液或上述處理液自上述半導體晶片上經由上述液體逸出孔而排出至上述液體逸出槽,從而維持基板處理治具相對於基板之配置。 The substrate processing jig of claim 11, further comprising: a liquid escape hole penetrating in a thickness direction; and a liquid escape groove disposed on the upper surface of the substrate processing jig and communicating with the above a liquid escape hole; and the liquid escape hole and the liquid escape groove are respectively disposed in such a manner that the alignment liquid or the treatment liquid is discharged from the semiconductor wafer through the liquid escape hole to the above by a capillary phenomenon The liquid escapes the trough to maintain the configuration of the substrate processing fixture relative to the substrate.
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