TW201539957A - Buck converting controller - Google Patents

Abstract

A buck converting controller, adapted to control a DC-DC buck converting circuit to convert an input voltage into an output voltage, is disclosed. The buck converting controller comprises a feedback control circuit, an off-time determination circuit and a load control circuit. The feedback control circuit turns on and off a high-side transistor and a low-side transistor of the DC-DC buck converting circuit in response to a feedback signal indicative of the output voltage. The off-time determination circuit determines a preset off-time period according to the input voltage and the output voltage and generates an off notice signal. The load control circuit is coupled to the DC-DC buck converting circuit and determines whether to release an electronic energy stored in the DC-DC buck converting circuit according to the off notice signal.

Description

Buck converter controller

The present invention relates to a buck switching controller, and more particularly to a buck switching controller for preventing overshoot.

Compared to the fixed frequency control architecture, the constant on-time (COT) control architecture of the DC-to-DC buck conversion circuit is greatly improved in the undershoot of the output voltage. However, there is no significant improvement in the overshoot of the output voltage.

Please refer to the first figure, which is a circuit diagram of a DC-to-DC buck conversion circuit with an overshoot suppression circuit disclosed in U.S. Patent No. 7,274,177. The driving circuits 208 and 210 of the buck pulse width regulating stage respectively output an upper arm control signal UG and a lower arm control signal LG to respectively control a pair of power switches SW1 and SW2. The power switches SW1 and SW2 are coupled to an input voltage Vin and ground to generate an inductor current IL flowing through an inductor L. A capacitor Co is charged by the inductor current IL to generate an output voltage Vout to supply a load 212. An overshoot suppression circuit 400 includes an inductor 412 and a transistor 414 coupled to the output voltage Vout and ground. An operational amplifier 416 acts as a voltage detector to detect the output The voltage Vout compares the output voltage Vout with a reference voltage Vref to generate a signal P1 to switch the transistor 414. The transistor 414 is generally turned off, and when the output voltage Vout is higher than the reference voltage Vref, the signal P1 conducts the transistor 414. A diode D is coupled between the inductor 412 and a battery 418. When the load 212 is changed from heavy load to light load, if the capacitance Co is insufficient to absorb the energy released by the inductor L, the output voltage Vout will exceed the reference voltage Vref. This causes the operational amplifier 416 to output a signal P1 to conduct the crystal 414. After the transistor 414 is turned on, the energy released by the inductor L charges the inductor 412, thereby pulling down the output voltage Vout. Until the output voltage Vout drops to the reference voltage Vref or lower, the operational amplifier 416 turns off the transistor 414, and most of the additional energy released by the load 212 is passed from the inductor 412 through the diode D to the battery 418. Battery 418 can supply power to other components whereby the system has no additional energy consumption.

Please refer to the second figure, which is a circuit diagram of a voltage-mode DC-to-DC buck conversion circuit disclosed in U.S. Patent No. 8,330,442. The DC-to-DC buck conversion circuit includes a control circuit 610, a gate drive circuit 620, and a power stage circuit 630. Control circuit 610 includes an error amplifier 612, a modulator 614, a signal generator 616, and a comparator 618. The error amplifier 612 receives an output voltage Vout and a reference voltage Vref, and compares the output voltage Vout with the reference voltage Vref to generate a compensation signal Sc to the modulator 614. In addition, the signal generator 616 can selectively output a ramp signal Sr to the modulator 614 at a first frequency F1 or a second frequency F2, so that the modulator 614 generates a pulse width modulation according to the compensation signal Sc and the ramp signal Sr. Signal Sp. Gate drive circuit The 620 receives the pulse width modulation signal Sp to generate a first driving signal S1d and a second driving signal S2d to the power stage circuit 630, so that the power stage circuit 630 provides an output current Iout and an output voltage Vout.

The signal generator 616 can output not only the ramp signal Sr but also the first frequency F1 and the second frequency F2, and can output other waveform signals, such as a triangular wave, at the first frequency F1 and the second frequency F2. The first frequency F1 is lower than the second frequency F2. In addition, the comparator 618 receives a threshold voltage Vth and an output voltage Vout. When the output voltage Vout is lower than the threshold voltage Vth, the comparator 618 outputs a first level signal to the signal generator 616, so that the signal generator 616 outputs the ramp signal Sr of the first frequency F1 to the modulator 614. In contrast, when the output voltage Vout is higher than the threshold voltage Vth, the comparator 618 outputs a second level signal to the signal generator 616, so that the signal generator 616 outputs the ramp signal Sr of the second frequency F2 to the modulator 614.

When the compensation signal Sc is higher than the ramp signal Sr, the pulse width modulation signal Sp is at a high level. In contrast, when the compensation signal Sc is lower than the ramp signal Sr, the pulse width modulation signal Sp is a low level. Obviously, when the ramp signal Sr changes, the pulse width modulation signal Sp changes, and when the ramp signal Sr is the first frequency F1, the pulse width modulation signal Sp operates at the first frequency F1; when the ramp signal When Sr is the second frequency F2, the pulse width modulation signal Sp operates at the second frequency F2. Thereby, when the output voltage Vout is higher than the threshold voltage Vth, that is, when an overshoot occurs, the operating frequency is increased to increase the switching speed of the power stage circuit 630, thereby suppressing the overshoot phenomenon.

The above conventional technique for suppressing overshoot is to perform a method of suppressing overshoot when it is judged that an overshoot occurs by comparing the output voltage with the reference voltage. Please refer to the third figure, which is a waveform diagram of a conventional technique for comparing the output voltage with a reference voltage to suppress overshoot. The output voltage Vout is detected to be higher than the threshold voltage Vth at a time point t0. However, because of the circuit delay, the suppression of overshoot is performed until time t1. Therefore, circuit delay can impair the suppression of overshoot. Furthermore, if the setting of the reference voltage is too low, the feedback control will be affected, and the feedback control of the system is unstable. If it is too high, the effect of suppressing the overshoot is poor.

In view of the defects of the conventional overshoot suppression technique, the present invention proposes to estimate the occurrence of an overshoot phenomenon by detecting the on-time of the lower arm transistor, and suppressing the overshoot when the overshoot is estimated, thereby achieving better suppression. The effect of the punching is also avoided by setting the reference voltage of the overshoot determination too high or too low.

To achieve the above object, the present invention provides a buck switching controller for controlling a DC-DC converter circuit to convert an input voltage into an output voltage. The buck conversion controller includes a feedback control circuit, a cutoff time circuit, and a load control circuit. The feedback control circuit controls the upper arm transistor and the lower arm transistor to be turned on and off according to one of the representative output voltage feedback signals. The cutoff time circuit calculates a predetermined cutoff time length based on the input voltage and the output voltage and generates a cutoff notification signal. The load control circuit generates an overshoot prevention signal according to the cutoff notification signal. Wherein, when the feedback control circuit receives the overshoot prevention signal, Control the lower arm transistor to be off.

The present invention also provides a buck conversion controller for controlling a DC to DC buck conversion circuit to convert an input voltage into an output voltage. The buck conversion controller includes a feedback control circuit, a cutoff time circuit, and a load control circuit. The feedback control circuit controls the upper arm transistor and the lower arm transistor to be turned on and off according to one of the representative output voltage feedback signals. The cutoff time circuit calculates a predetermined cutoff time length based on the input voltage and the output voltage and generates a cutoff notification signal. The load control circuit is coupled to the DC-to-DC buck conversion circuit, and determines whether to release one of the energy stored in the DC-to-DC buck conversion circuit according to the cutoff notification signal.

The present invention also provides a buck conversion controller for controlling a DC-DC converter circuit to convert an input voltage into an output voltage. The buck conversion controller includes a feedback control circuit, a cut-off circuit, and a load. Control circuit. The feedback control circuit controls the ON-DC transistor and the lower arm transistor to turn on and off according to one of the representative output voltage feedback signals, wherein the upper arm transistor has a fixed on-time at each cycle. value. The cutoff time circuit calculates a predetermined cutoff time length based on the input voltage and the output voltage and generates a cutoff notification signal. The load control circuit generates an overshoot prevention signal based on the cutoff notification signal. The feedback control circuit shortens the on-time of the upper arm transistor or stops the upper arm transistor conduction after receiving the overshoot prevention signal for a predetermined number of cycles.

The above summary and the following detailed description are exemplary in order to further illustrate the scope of the claims. Other objects and advantages of the present invention will be described in the following description and drawings.

Prior art:

208, 210‧‧‧ drive circuit

212‧‧‧load

400‧‧‧Overshoot suppression circuit

412, L‧‧‧Inductance

414‧‧‧Optoelectronics

416‧‧‧Operational Amplifier

418‧‧‧Battery

610‧‧‧Control circuit

612‧‧‧Error amplifier

614‧‧‧Modulator

616‧‧‧Signal Generator

618‧‧‧ comparator

620‧‧‧ gate drive circuit

630‧‧‧Power level circuit

Co‧‧‧ capacitor

D‧‧‧ diode

F1‧‧‧ first frequency

F2‧‧‧second frequency

IL‧‧‧Inductor Current

Iout‧‧‧Output current

LG‧‧‧ Lower arm control signal

P1‧‧‧ signal

S1d‧‧‧first drive signal

S2d‧‧‧second drive signal

Sc‧‧‧compensation signal

Sp‧‧‧ pulse width modulation signal

Sr‧‧‧ ramp signal

SW1, SW2‧‧‧ power switch

T0, t1‧‧‧ time point

UG‧‧‧Upper arm control signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vref‧‧‧reference voltage

Vth‧‧‧ threshold voltage

this invention:

100‧‧‧Buck converter controller

102‧‧‧ deadline circuit

104‧‧‧Load control circuit

105‧‧‧Feedback control circuit

106‧‧‧ comparator

108‧‧‧ On-time circuit

110‧‧‧Logic Control Circuit

304‧‧‧Mirror circuit

306‧‧‧ Comparator

308‧‧‧ and gate

402‧‧‧ and gate

404‧‧‧current source

406‧‧‧Optoelectronics

407‧‧‧Operational Amplifier

408‧‧‧Timer

422‧‧‧Optoelectronics

424‧‧‧current source

426‧‧‧ Capacitance

428‧‧‧ and gate

BJT1‧‧‧ first double carrier transistor

BJT2‧‧‧Second double carrier transistor

BJT3‧‧‧ third double carrier transistor

C1‧‧‧ capacitor

CLG‧‧‧ deadline signal

COUT‧‧‧ output capacitor

FB‧‧‧ feedback signal

I1‧‧‧discharge current source

Iin‧‧‧ Current

Imir‧‧‧Mirror current

Iosp‧‧‧Load current

L‧‧‧Inductance

LG‧‧‧ Lower arm control signal

M1‧‧‧Upper arm transistor

M2‧‧‧ lower arm transistor

M3‧‧‧O crystal

R1‧‧‧first resistance

R2‧‧‧second resistance

R3‧‧‧ third resistor

Sosp‧‧‧Overshoot prevention signal

Toff‧‧End notice signal

UG‧‧‧Upper arm control signal

V1, v2‧‧‧ potential

Vbe‧‧‧ cutoff reference voltage

VDD‧‧‧ drive voltage

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vramp‧‧‧ ramp voltage

Vref‧‧‧reference voltage

Td‧‧‧ scheduled delay time

The first figure is a circuit diagram of a DC-to-DC buck conversion circuit with an overshoot suppression circuit disclosed in U.S. Patent No. 7,274,177.

The second figure is a circuit diagram of a voltage-mode DC-to-DC buck conversion circuit disclosed in U.S. Patent No. 8,330,442.

The third figure is a waveform diagram of a conventional technique of comparing an output voltage with a reference voltage to suppress overshoot.

The fourth figure is a circuit diagram of a buck switching controller in accordance with a first preferred embodiment of the present invention.

The fifth picture shows the signal waveform of the buck conversion controller and the traditional buck converter controller in the fourth figure when an overshoot occurs.

Figure 6 is a circuit diagram of a cut-off time circuit in accordance with a first preferred embodiment of the present invention.

Figure 7 is a circuit diagram of a load control circuit in accordance with a first preferred embodiment of the present invention.

Figure 8 is a circuit diagram of a cut-off time circuit in accordance with a second preferred embodiment of the present invention.

Figure 9 is a diagram of load control power according to a second preferred embodiment of the present invention. Circuit diagram of the road.

Figure 11 is a circuit diagram of a load control circuit in accordance with a third preferred embodiment of the present invention.

Figure 11 is a signal waveform diagram of the load control circuit shown in the tenth figure.

4 is a circuit diagram of a buck switching controller according to a first preferred embodiment of the present invention for controlling a DC-DC converter circuit to convert an input voltage Vin into an output voltage Vout. The DC-to-DC buck conversion circuit includes an upper arm transistor M1, a lower arm transistor M2, an inductor L, and an output capacitor COUT. One end of the upper arm transistor M1 and one end of the lower arm transistor M2 are connected in series via a connection point, the other end of the upper arm transistor M1 is coupled to the input voltage Vin, and the other end of the lower arm transistor M2 is grounded. One end of the inductor L is coupled to the connection point of the upper arm transistor M1 and the lower arm transistor M2 and the other end is coupled to the output capacitor COUT to provide an output voltage Vout.

The buck converter controller 100 includes a feedback control circuit 105, a cutoff time circuit 102, and a load control circuit 104. The feedback control circuit 105 generates an upper arm control signal UG and a lower arm control signal LG according to one of the representative output voltages Vout to control the upper arm TFT M1 and the lower arm transistor M2, respectively. Turn-on and cut-off. The feedback control circuit 105 includes a comparator 106, an on-time circuit 108, and a logic control circuit 110. A non-inverting terminal of the comparator 106 receives a reference voltage Vref, An inverting terminal receives the feedback signal FB, and generates a high level signal at an output when the feedback signal FB is lower than the reference voltage Vref. The on-time circuit 108 is coupled to the comparator 106. When the comparator 106 receives the high-level signal, it generates a pulse signal having a fixed pulse width. The logic control circuit 110 generates an upper arm control signal UG and a lower arm control signal LG according to the pulse signal generated by the on-time circuit 108. The pulse width of the pulse signal generated by the on-time circuit 108 determines the pulse width of the upper arm control signal UG, that is, the on-time of the upper arm transistor M1. In order to avoid the occurrence of the backflow phenomenon, the logic control circuit 110 can further determine whether a reverse current occurs according to the current of the inductor L, and cut off the lower arm transistor M2 in advance to avoid the occurrence of backflow. The cutoff time circuit 102 calculates a predetermined cutoff time length based on the input voltage Vin and the output voltage Vout. In the steady state, the ratio of the length of the on period of the on period to the off period during the off period is On: Off = Vout: (Vin - Vout). Therefore, the predetermined cutoff time length calculated by the cutoff time circuit 102 based on the input voltage Vin and the output voltage Vout is the length of time during the steady state off period period Off. The logic control circuit 110 generates a cutoff period signal CLG to the off time circuit 102 representing the off period. The cutoff time circuit 102 starts counting when receiving the cutoff period signal CLG, generates a cutoff notification signal Toff, and stops generating the cutoff notification signal Toff when a predetermined cutoff time length elapses. The load control circuit 104 is coupled to the cutoff time circuit 102 to generate an overshoot prevention signal Sosp according to the cutoff notification signal Toff. The feedback control circuit 105 is coupled to the load control circuit 104 to control the lower arm transistor M2 to be turned off when receiving the overshoot prevention signal Sosp.

In addition, the on-time circuit 108 reduces the number of generated pulse signals by a predetermined number of cycles after the feedback control circuit 105 receives the overshoot prevention signal Sosp, for example, the first cycle or the first two cycles thereafter. width. In general, the effect of shortening the pulse width of the pulse signal can be achieved by reducing a turn-on reference voltage in the on-time circuit 108 or increasing the magnitude of a charging current for charging a conductive capacitor. Alternatively, the generation of the pulse signal may be stopped after a predetermined number of cycles after receiving the overshoot prevention signal Sosp. Therefore, the present invention can shorten the on-time of the upper arm transistor or stop the conduction of the upper arm transistor within a predetermined number of cycles thereafter. Thereby, the energy transmitted from the buck converter circuit to the output capacitor COUT during these cycles can be reduced, thereby achieving better suppression of overshoot.

Of course, the technical means for suppressing overshoot in this embodiment can be adopted separately or in combination depending on the actual circuit design.

Please refer to the fifth figure for the signal waveform of the buck conversion controller and the traditional buck converter controller shown in Figure 4. Before the dotted line in the fifth figure, the system operates at a steady state, and the lower arm control signal LG coincides with the cutoff notification signal Toff. When the length of the period during the actual off period exceeds the predetermined off time length, it represents that the load is decreased and the period of the off period of the current period becomes long. The lower arm control signal LG of the conventional buck converter controller is still at a high level, and continuously turns on the lower arm transistor M2. However, the cut-off time circuit 102 of the present invention stops generating the cut-off notification signal Toff when the predetermined cut-off time length elapses. At this time, the lower arm transistor M2 is turned off, so that the freewheeling current of the inductor L is electrically connected to the lower arm that was originally turned on. The crystal M2 is redirected through the body diode of the lower arm transistor M2, which increases the loss of the inductor current, thereby achieving the effect of suppressing overshoot. In addition, the load control circuit 104 of the present invention can also be coupled to a DC-to-DC buck conversion circuit, such as an output terminal, a connection point between the upper arm transistor and the lower arm transistor, and the DC-DC voltage is released according to the cutoff notification signal Toff. The energy stored in the energy storage component such as the inductance L of the conversion circuit and the output capacitor COUT is used to achieve a more rapid suppression of overshoot. As shown in the fourth embodiment, the load control circuit 104 is coupled to the output voltage Vout, and when the cutoff notification signal Toff generates a falling edge but does not enter the next cycle, the output voltage Vout is pulled to generate a load current. Iosp. Furthermore, in the subsequent predetermined number of cycles, the upper arm control signal UG can also shorten the pulse width or stop generating, which is indicated by a broken line.

The above two techniques for suppressing overshoot of the present invention can be selected individually or simultaneously depending on the actual situation. The load control circuit 104 can be used as a stop point of the load current Iosp for a fixed period of time or to detect the level of the output voltage Vout.

Please refer to a sixth diagram, which is a circuit diagram of a cut-off time circuit according to a first preferred embodiment of the present invention. A first dual carrier transistor BJT1 has a first collector, a first base and a first emitter. The first collector is coupled to a driving voltage VDD, the first base is coupled to an output voltage Vout, and the first emitter is coupled to a ground potential through a first resistor R1. Therefore, a potential v1=Vout-Vbe1 of a connection point between the first emitter of the first bipolar transistor BJT1 and the first resistor R1, wherein Vbe1 is a forward bias of the first bipolar transistor BJT1 . a second bipolar transistor BJT2 has a second collector and a second base And a second emitter. The second emitter is coupled to an input voltage Vin through a second resistor R2, and the second base is coupled to a junction of the first emitter of the first bipolar transistor BJT1 and the first resistor R1. A potential v2=v1+Vbe2=Vout-Vbe1+Vbe2 of a connection point between the second emitter of the second bipolar transistor BJT2 and the second resistor R2. When Vbe1=Vbe2, v2=Vout. Where Vbe2 is a forward bias of the second bipolar transistor BJT2. Therefore, the current flowing through the second bipolar transistor BJT2 at the second collector output is substantially the same as the current flowing through the second resistor R2, which is (Vin-Vout)/R2, that is, proportional to the input voltage Vin minus the output. The magnitude of the current of one of the voltages Vout.

A mirror circuit 304 mirrors the current Iin outputted by the second bipolar transistor BJT2 at the second collector, so that a mirror current Imir proportional to the voltage difference of the input voltage Vin minus the output voltage Vout flows through an electric Crystal M3. The transistor M3 is controlled by an upper arm control signal UG. During the on period of the upper arm control signal UG being a high level, the transistor M3 is turned on. A third resistor R3 is connected in parallel with a capacitor C1. During the on period, the mirror current Imir charges the capacitor C1 until the junction point potential of the third resistor R3 and the capacitor C1, that is, the ramp voltage Vramp=R3*Imir. A discharge current source I1 is simultaneously coupled to the capacitor C1 for discharging the capacitor C1. Since the mirror current Imir is much larger than the current of the discharge current source I1, the influence of the discharge current source I1 on the ramp voltage Vramp can be ignored during the on period. Since the mirror current Imir is proportional to the voltage difference between the input voltage Vin and the output voltage Vout, the magnitude of the change (the amplitude) of the capacitor C1 is also proportional to the voltage difference between the input voltage Vin minus the output voltage Vout. When the on period is over, the transistor M3 is turned off. The discharge current source I1 starts to discharge the capacitor C1, and the ramp voltage Vramp starts to drop. A predetermined off time Toff_c required for the ramp voltage Vramp to fall to zero is: Toff_c = (R3 * Imir) / I1 = (R3 * K * Iin) / I1 = R3 * K * (Vin - Vout) / (R2 * I1), where K is a constant.

Therefore, when I1=(R3*K*Vout)/(R2*Ton), Toff_c=Ton*(Vin-Vout)/Vout, where Ton is the length of time during the on period, that is, when the conversion circuit operates The on-time of the transistor M1 at a steady state.

A non-inverting terminal of a comparator 306 receives the ramp voltage Vramp, an inverting terminal is coupled to ground (or a positive potential slightly higher than the ground potential), and the output terminal is coupled to a gate 308. The gate 308 generates a turn-off notification signal Toff according to an output signal of the comparator 306 and a cut-off period signal CLG. When the off period signal CLG is at a high level and the ramp voltage Vramp is greater than zero, that is, a predetermined off time during the off period is performed, and the gate 308 generates the off notification signal Toff.

Referring to the seventh figure, there is shown a circuit diagram of a load control circuit according to a first preferred embodiment of the present invention. The load control circuit is coupled to an output voltage Vout, including a sum gate 402 and a current source 404. The gate 402 receives a reverse one of the cutoff notification signal Toff and a cutoff period signal CLG. Therefore, when entering the off period (the off period signal CLG is a high level) and a predetermined off time (the off notification signal Toff is turned to a low level), the gate 402 outputs a high level signal to enable the current source. 404. At this point, current source 404 begins to The output voltage Vout is released, and the output voltage Vout is turned on by a release current to output a pull-down output voltage Vout. Current source 404 can be a current source or a current source that becomes larger with time. Therefore, the load control circuit starts to release the energy stored in the DC-DC buck conversion circuit after the upper arm transistor M1 is turned from on to off for a predetermined period of time. Please also refer to the fourth figure. When the feedback signal FB is lower than the reference voltage Vref, that is, when the output voltage Vout returns to a predetermined output voltage, it enters the on period of the next cycle. At this time, the off period signal CLG is turned to a low level, and the gate 402 outputs a low level signal to stop the current source 404 from discharging the output voltage Vout.

Of course, the load control circuit may additionally add a comparator for determining whether the output voltage Vout returns to a pull-stop voltage as a judgment of stopping the current source 404, wherein the pull-stop voltage is slightly higher than the predetermined output voltage.

Please refer to the eighth figure, which is a circuit diagram of a cut-off time circuit according to a second preferred embodiment of the present invention. Compared to the embodiment shown in the sixth figure, the cut-off time circuit of the eighth figure adds a third bipolar transistor BJT3. The third bipolar transistor BJT3 is connected in series with the third resistor R3 in parallel with the capacitor C1. A third base of the third bipolar transistor BJT3 is coupled to a third collector. The non-inverting terminal of the comparator 306 receives the ramp voltage Vramp, the inverting terminal is coupled to an off-reference voltage Vbe, and the output terminal is coupled to the gate 308. During the on period, the mirror current Imir charges the capacitor C1 until a potential of the junction of the third resistor R3 and the capacitor C1, that is, the ramp voltage Vramp=R3*Imir+Vbe3, wherein Vbe3 is the third double carrier. A forward bias of the crystal BJT3, in this implementation For example, the forward bias voltage Vbe3 is equal to the cutoff reference voltage Vbe. When the on-period period ends, the transistor M3 is turned off so that the discharge current source I1 starts to discharge the capacitor C1, and the ramp-wave voltage Vramp starts to fall. A predetermined off time Toff_c required for the ramp voltage Vramp to fall to the cutoff reference voltage Vbe is: Toff_c=(R3*Imir+Vbe3-Vbe)/I1=(R3*K*Iin-out)/I1=R3*K* (VIN-VOUT)/(R2*I1), where K is a constant.

Therefore, the predetermined cutoff time Toff_c of the eighth embodiment is the same as that of the embodiment shown in the sixth figure.

Referring to FIG. 9 , which is a circuit diagram of a load control circuit according to a second preferred embodiment of the present invention, the overshoot can be suppressed by the off-time circuit shown in FIG. 8 . The load control circuit includes a transistor 406, an operational amplifier 407, and a timer 408. The timer 408 receives the cutoff notification signal Toff and enables the amplifier 407 to operate for a predetermined time after detecting the falling edge of the cutoff notification signal Toff. The operational amplifier 407 receives the cutoff reference voltage Vbe and the ramp voltage Vramp, and amplifies the voltages of the cutoff reference voltage Vbe and the ramp voltage Vramp to control the equivalent on-resistance value of the transistor 406. Please also refer to the eighth figure. If the conversion circuit operates in an unsteady state, the predetermined deadline is passed, but the upper arm control signal UG is still at the low level. At this time, the discharge current source I1 continues to discharge the capacitor C1 to lower the ramp voltage Vramp to 0V. The time required for the ramp voltage Vramp to fall to 0 V by the cutoff reference voltage Vbe is a predetermined extra length of time. Therefore, during the predetermined additional length of time, as the ramp voltage Vramp decreases, the voltage of one of the output signals of the operational amplifier 407 continues to rise, making the electricity The pull-up capability of the crystal 406 rises, that is, a release current that is turned on by the output voltage Vout and becomes larger as time passes. After a predetermined extra length of time has elapsed, the load carrying capacity of the transistor 406 is maintained constant, so that the discharge current is maintained at a fixed value to avoid the undershoot of the output voltage Vout caused by the excessive load carrying capacity.

Referring to the tenth figure, there is shown a circuit diagram of a load control circuit according to a third preferred embodiment of the present invention. The load control circuit generates an overshoot prevention signal Sosp after the cutoff notification signal Toff continues to generate a predetermined delay time to avoid possible malfunction of the circuit. A transistor 422 receives the turn-off notification signal Toff, and is turned on when the turn-off notification signal Toff is at a high level, so that a voltage of a capacitor 426 is maintained at 0V, and is turned off when the turn-off notification signal Toff is at a low level. A current source 424 is coupled in series with capacitor 426 to begin charging capacitor 426 when transistor 422 is turned off. The input terminal of one of the gates 428 is coupled to the capacitor 426 and the off-cycle signal CLG, and the overshoot prevention signal Sosp is output when the voltage of the capacitor 426 rises to a logic level and the off-cycle signal CLG is also at a high level. Please also refer to the eleventh figure, which is the signal waveform diagram of the load control circuit shown in the tenth figure. When the cutoff notification signal Toff turns to the low level and after a predetermined delay time Td and the off period signal CLG is still at the high level, the load control circuit generates the overshoot prevention signal Sosp until the off period signal CLG turns to the low level. . Please also refer to the fourth figure. When the logic control circuit 110 receives the overshoot prevention signal Sosp, the lower arm control signal LG immediately turns to the low level to cut off the lower arm transistor M2. In this way, in addition to the excess energy that can be dissipated through the body diode of the lower arm transistor M2 to suppress overshoot In addition, it is also possible to avoid damage to the system components when the lower arm transistor M2 is continuously turned on to cause backflow and reverse flow, for example, the upper arm transistor M1.

In addition, the load control circuit shown in the seventh and ninth diagrams is determined by the cut-off notification signal Toff as the start-up suppression overshoot, or may be changed by appropriate circuit adjustment as in the embodiment shown in FIG. The rush prevention signal Sosp is used as a judgment to suppress the overshoot, so as to avoid suppressing the overshoot.

As described above, the load control circuit can cut off the lower arm transistor M2 or/and release the energy storage of the DC-to-DC buck conversion circuit to achieve the effect of suppressing overshoot. Therefore, the load control circuit of the present invention can have the above two suppression overshoot effects in addition to the circuit as in the foregoing embodiment, in order to provide more overshoot suppression capability.

As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. The present invention has been disclosed in the foregoing, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the present invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

100‧‧‧Buck converter controller

102‧‧‧ deadline circuit

104‧‧‧Load control circuit

105‧‧‧Feedback control circuit

106‧‧‧ comparator

108‧‧‧ On-time circuit

110‧‧‧Logic Control Circuit

COUT‧‧‧ output capacitor

FB‧‧‧ feedback signal

L‧‧‧Inductance

LG‧‧‧ Lower arm control signal

M1‧‧‧Upper arm transistor

M2‧‧‧ lower arm transistor

Sosp‧‧‧Overshoot prevention signal

Toff‧‧End notice signal

UG‧‧‧Upper arm control signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vref‧‧‧reference voltage

Claims (16)

A buck conversion controller for controlling a DC-DC converter circuit to convert an input voltage into an output voltage, the buck conversion controller comprising: a feedback control circuit, which is fed back according to one of the output voltages a signal, which controls one of the upper arm transistor and the lower arm transistor to be turned on and off; a cutoff time circuit calculates a predetermined cutoff time length based on the input voltage and the output voltage and generates a cutoff notification signal And a load control circuit for generating an overshoot prevention signal according to the cutoff notification signal; wherein the feedback control circuit controls the lower arm transistor to be turned off when receiving the overshoot prevention signal. The buck switching controller of claim 1, wherein the off-time circuit comprises: a first bipolar transistor having a first collector, a first base, and a first emitter The first collector is coupled to a driving voltage, the first base is coupled to the output voltage, and the first emitter is coupled to a common potential through a first resistor; and a second dual carrier transistor Having a second collector, a second base, and a second emitter, the second emitter is coupled to the input voltage through a second resistor, and the second base is coupled to the first emitter One of the first resistors is connected to the point, and a current of the second collector output is proportional to the input voltage minus the output power One of the voltage differences. The buck switching controller of claim 1, wherein the load control circuit includes a release circuit coupled to the DC-to-DC buck conversion circuit to receive the overshoot prevention signal or The cut-off notification signal releases one of the energy stored in the DC-to-DC buck conversion circuit. The step-down conversion controller of claim 3, wherein the release circuit includes a transistor coupled to the output voltage, and when the release circuit receives the overshoot prevention signal or the cutoff notification signal, The transistor is turned on by the output voltage and discharged to a discharge current, and the discharge current becomes larger with time. The buck switching controller of claim 4, wherein the release current continues to increase for a predetermined period of time and is maintained at a fixed value. The buck switching controller of claim 4, wherein the load control circuit comprises a delay circuit for generating the overshoot prevention signal according to the cutoff notification signal and a predetermined delay time. A buck switching controller for controlling a DC-DC buck conversion circuit to convert an input voltage into an output voltage, the buck conversion controller comprising: a feedback control circuit for controlling an on-arm transistor and a lower arm transistor to be turned on and off according to a feedback signal representing one of the output voltages; a cut-off time circuit according to the input voltage and The output voltage is calculated for a predetermined cutoff time length and generates a cutoff notification signal; and a load control circuit is coupled to the DC to DC buck conversion circuit, and determines whether to release the DC to DC buck conversion circuit according to the cutoff notification signal One of the energy stored. The buck switching controller of claim 7, wherein the load control circuit releases the DC-DC buck conversion circuit after the upper arm transistor is turned from off to off for a predetermined length of time. This energy. The buck switching controller of claim 8, wherein the load control circuit comprises a delay circuit for generating the overshoot prevention signal according to the cutoff notification signal and a predetermined delay time. The buck switching controller of claim 7, wherein the load control circuit includes a transistor coupled to the output voltage, and determining, according to the cutoff notification signal, whether the output voltage is turned on by a discharge current. Where the release current increases with time. The buck switching controller of claim 10, wherein the release current continues to increase for a predetermined period of time and is maintained at a fixed value. A buck conversion controller for controlling a DC-DC converter circuit to convert an input voltage into an output voltage, the buck conversion controller comprising: a feedback control circuit, which is fed back according to one of the output voltages a signal, which controls an upper arm transistor and a lower arm transistor to be turned on and off, wherein an on-time of the upper arm transistor is fixed at a fixed value; a cut-off time circuit according to the input The voltage and the output voltage are calculated for a predetermined cutoff time length and generate a cutoff notification signal; and a load control circuit is configured to generate an overshoot prevention signal according to the cutoff notification signal; wherein the feedback control circuit receives the overshoot prevention After a predetermined number of cycles, the on-time of the upper arm transistor is shortened or the upper arm transistor is turned off. The buck switching controller of claim 12, wherein the off-time circuit comprises: a first bipolar transistor having a first collector and a first base And a first emitter, the first collector is coupled to a driving voltage, the first base is coupled to the output voltage, and the first emitter is coupled to a common potential through a first resistor; The second dual-carrier transistor has a second collector, a second base, and a second emitter. The second emitter is coupled to the input voltage through a second resistor, and the second base is coupled The first emitter is coupled to one of the first resistors, and a current of the second collector output is proportional to the input voltage minus a voltage difference of the output voltage. The buck switching controller of claim 12, wherein the load control circuit comprises a delay circuit for generating the overshoot prevention signal according to the cutoff notification signal and a predetermined delay time. The buck switching controller of claim 12, wherein the feedback control circuit controls the lower arm transistor to be turned off when receiving the overshoot prevention signal. The step-down conversion controller of claim 12, wherein the load control circuit is coupled to the DC-to-DC buck conversion circuit, and determines whether to release the DC-to-DC buck conversion circuit according to the cutoff notification signal. Store one of the energy.