JP5974733B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply device that can prevent an overshoot of an output voltage when power is turned on.

  A general switching power supply device includes an error amplifier that amplifies an error voltage between a feedback voltage that varies according to an output voltage and a reference voltage and outputs an error voltage signal. A PWM signal having a duty corresponding to the comparison result between the error voltage signal and the ramp wave is generated, and switching control is performed using the PWM signal. Such a switching power supply apparatus includes a soft start circuit as means for preventing an inrush current flowing in the switching power supply circuit when the power is turned on (see, for example, Patent Document 1).

  The soft start circuit described in Patent Document 1 instructs the lamp oscillator to reduce the slope of the voltage waveform as the feedback voltage increases after the power is turned on. As a result, the PWM comparator that generates the PWM signal generates a PWM signal with a small pulse width after the power is turned on, and generates a PWM signal with a large pulse width when the steady voltage is reached, thereby reducing the inrush current to the switching power supply circuit. It is preventing.

JP 2010-220330 A

  In Patent Document 1, the ramp oscillator is configured to output a ramp wave signal in response to a command from the soft start circuit. However, when a module incorporating the oscillator is designed, the ramp wave signal cannot be controlled. In this case, the switching power supply circuit described in Patent Document 1 cannot always stably prevent overshoot when the power is turned on.

  On the other hand, if the soft start period is set longer than necessary in order to sufficiently suppress the inrush current when the power is turned on, the rise of the output voltage to the load is delayed. Further, if the soft start period is too short or if the soft start function is not provided, the rise of the output voltage to the load becomes steep and there is a possibility that the output voltage overshoots.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a switching power supply apparatus that can stably prevent the occurrence of output voltage overshoot.

  A switching power supply according to the present invention compares an error amplifier that amplifies a difference between a feedback voltage corresponding to an output voltage and a reference voltage and outputs an error amplified signal, the error amplified signal and the soft start voltage, A buffer circuit that outputs a smaller voltage, a comparator that compares the output of the buffer circuit with a triangular wave signal and outputs a pulse width modulation signal, and a switch element that is controlled by the pulse width modulation signal. The switching power supply device further includes a capacitor and a rectifier connected in series between an inverting input of the error amplifier to which the feedback voltage is input and an output of the buffer circuit, and the rectifier includes A charging circuit connected so that the charging direction of the capacitor is a forward direction, and discharging for discharging a voltage charged in the capacitor Characterized in that it comprises a road, a.

  In this configuration, the output of the buffer circuit is input (negative feedback) to the inverting input portion of the error amplifier via the capacitor and the rectifying element. Since the output voltage is low when the switching power supply is turned on, the feedback voltage corresponding to the output voltage is also low, and an error amplification signal corresponding to the difference between the feedback voltage and the reference voltage is output. Since the output of the error amplifier is negatively fed back to the inverting input portion of the error amplifier to which the feedback voltage is input, the voltage at the inverting input portion of the error amplifier becomes larger than that without the capacitor and the rectifying element. By correcting the voltage at the inverting input of the error amplifier in this way, the voltage at the inverting input of the error amplifier apparently reaches the reference voltage before the output voltage reaches the set value. The error amplification signal to be output does not saturate to the maximum output voltage as in the case where there is no capacitor and rectifier, and is held at a level close to the steady state value.

  After the power is turned on, the output voltage rises by gradually increasing the on-duty ratio of the pulse width modulation signal until the output voltage reaches the set value, but when the output voltage reaches the set value, that is, feedback When the voltage reaches the reference voltage, the output of the error amplifier decreases to a steady state, and the on-duty ratio is controlled to be constant. Without the capacitor and the rectifying element, there is a response delay until the output of the error amplifier reaches the steady state from the saturation voltage, and during that time, the on-duty ratio becomes unnecessarily large and an overshoot of the output voltage occurs. When there is a rectifying element, the output of the error amplifier does not saturate after the power is turned on and is maintained at a level close to a steady state, so there is no response delay and overshoot can be prevented.

  The discharge circuit may include a diode that allows a discharge current to flow between the output unit of the buffer circuit and the ground.

  In this configuration, the charging circuit can be reset by discharging the capacitor. For this reason, it is possible to prevent overshoot even when the operation of the switching power supply device is once stopped and then restarted in a short time. Further, since the discharge is performed by the diode, a discharge control circuit is not required.

  The discharge circuit may include a discharge switch element connected to both ends of the capacitor.

  In this configuration, since a closed circuit including a capacitor is formed, discharge can be instantaneously performed as compared with a case where discharge is performed by a diode, and thus a large-capacity capacitor can be employed.

  The switching power supply device may include a constant voltage element that is connected between the output unit of the buffer circuit and the capacitor and generates an offset voltage.

  In this configuration, by inserting the constant voltage element in series with the capacitor, the output of the buffer circuit can be increased by the constant voltage of the constant voltage element. Thereby, overshoot can be suppressed even when the potential difference between the output of the buffer circuit and the inverting input portion of the error amplifier is small, for example, even when it is smaller than the forward voltage of the rectifying element.

  According to the present invention, the output of the buffer circuit is input (negative feedback) to the inverting input portion of the error amplifier via the capacitor and the rectifying element. For this reason, it is possible to prevent overshoot at the rise of the output voltage to the load.

1 is a circuit diagram of a switching power supply device according to Embodiment 1. FIG. It is a figure which shows each voltage waveform with and without an overshoot prevention circuit, (A) is each waveform of output voltage Vo, COMP terminal voltage Vcomp, and feedback voltage Vfb, (B) is a soft start voltage. Waveforms of Vss and error voltage Verr. FIG. 4 is a circuit diagram of a switching power supply device according to a second embodiment. FIG. 5 is a circuit diagram of a switching power supply device according to a third embodiment.

<Embodiment 1>
FIG. 1 is a circuit diagram of a switching power supply device according to the first embodiment. The switching power supply apparatus 101 includes a switching control signal generation circuit (hereinafter referred to as a signal generation circuit) 1, an overshoot prevention circuit 2, and a switching circuit 3. The switching circuit 3 includes a switching element that is PWM-controlled by a PWM signal (a pulse width modulation signal of the present invention) generated by a signal generation circuit 1 described later. The switching circuit 3 converts the DC voltage input from the input terminal Pi and outputs the DC voltage Vo from the output terminal Po by PWM control of the switch element.

  The switch element included in the switching circuit 3 is, for example, a transistor. A base signal is applied to the base of the transistor from a drive circuit (not shown), and the transistor is turned on and off. In the present embodiment, the drive circuit is configured to turn on the switch element when the PWM signal input from the signal generation circuit 1 is at a high level, and to turn off the switch element when the PWM signal is at a low level.

  The signal generation circuit 1 includes an error amplifier 11, a reference voltage source 12, a comparator 13, a ramp wave oscillator 14, an error amplifier 15, and an FET 16.

  A reference voltage source 12 is connected to the non-inverting input terminal (+) of the error amplifier 11, and an FB (feedback) terminal is connected to the inverting input terminal (−). The GND terminal is connected to the ground. The FB terminal is connected to a voltage dividing output point of the resistors R2 and R3 connected to the output terminal Po. A feedback voltage Vfb obtained by dividing the output voltage Vo output from the output terminal Po is input to the FB terminal. The error amplifier 15, the FET 16 and the constant voltage source VCC constitute a buffer circuit 4. The output of the error amplifier 11 is connected to the COMP terminal via the buffer circuit 4.

  More specifically, regarding the buffer circuit 4, the SS terminal is connected to the non-inverting input terminal (+) of the error amplifier 15, and the output of the error amplifier 11 is connected to the inverting input terminal (-). The output of the error amplifier 15 is connected to the gate of the FET 16. The drain of the FET 16 is connected to the output of the error amplifier 11, and the source is connected to the GND terminal. The constant voltage source VCC is connected to the output of the error amplifier 11.

  A phase compensation circuit including a capacitor C1 and a resistor R1 connected in series is connected to a feedback line from the COMP terminal to the FB terminal of the signal generation circuit 1.

  An overshoot prevention circuit 2 is connected to the COMP terminal of the signal generation circuit 1. The overshoot prevention circuit 2 includes a capacitor C2, a diode (rectifier element of the present invention) D1, and a diode D2. One end of the capacitor C2 is connected to the COMP terminal, and the other end is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the FB terminal. The diode D2 has a cathode connected to a connection point between the capacitor C2 and the diode D1, and an anode connected to the GND terminal. The capacitor C2 and the diode D1 constitute a charging circuit of the present invention. The diode D2 constitutes the discharge circuit of the present invention.

  The error amplifier 11 outputs an error voltage (error amplified signal of the present invention) Verr obtained by amplifying the difference between the feedback voltage Vfb input from the FB terminal and the reference voltage Vref of the reference voltage source 12. The error voltage Verr becomes a high level when the reference voltage Vref is higher than the feedback voltage Vfb. Since the output voltage Vo is low when the switching power supply 101 is turned on, the feedback voltage Vfb is also low. For this reason, the error voltage Verr output from the error amplifier 11 is saturated to the maximum output voltage of the error amplifier 11 when the overshoot prevention circuit 2 is not provided. However, since the present invention includes the overshoot prevention circuit 2, it does not saturate to the maximum output voltage as will be described later. When the output voltage reaches a set value as time elapses, the error voltage Verr output from the error amplifier 11 decreases to a steady state voltage.

  The SS terminal is connected to a soft start circuit including a constant current source 5 built in the signal generation circuit 1 and a capacitor C3 provided outside the signal generation circuit 1. The soft start circuit is configured to generate the soft start voltage Vss by charging the capacitor C3 with a constant current by the constant current source 5. The soft start voltage Vss increases with time.

  The buffer circuit 4 compares the error voltage Verr and the soft start voltage Vss, and outputs the smaller one of the voltages. The soft start voltage Vss increases with time. When the soft start voltage Vss is smaller than the error voltage Verr, the error amplifier 15 acts to equalize the non-inverting input terminal (+) and the inverting input terminal (−). By outputting a signal and controlling the conduction of the FET 16, the error voltage Verr is set to the same voltage as the soft start voltage Vss. As a result, the buffer circuit 4 outputs the soft start voltage Vss.

  When the error voltage Verr becomes smaller than the soft start voltage Vss, the output of the error amplifier 15 becomes low and the FET 16 becomes non-conductive. Therefore, the error voltage Verr is output from the buffer circuit 4.

  The output of the buffer circuit 4 becomes the COMP terminal voltage, and charges the capacitor C2 of the overshoot prevention circuit 2. When the switching power supply 101 is turned on, the capacitor C2 is uncharged, and as the soft start voltage Vss, which is the output of the buffer circuit 4, increases, the charging current of the capacitor C2 passes through the diode D1 and the resistor R3. It flows to GND. Therefore, a voltage generated in the resistor R3 due to the charging current of the capacitor C2 is superimposed on the feedback voltage Vfb which is the FB terminal voltage.

  Since the charging current flows through the capacitor C2 until the output voltage Vo reaches the set voltage after the soft start is started, the voltage generated in the resistor R3 due to the charging current of the capacitor C2 is included in the feedback voltage Vfb which is the FB terminal voltage. Superimposed. Therefore, unlike the case where the overshoot prevention circuit 2 is not provided, the feedback voltage Vfb apparently approaches the reference voltage Vref before the output voltage Vo reaches the set value. Therefore, the error voltage Verr output from the error amplifier 11 does not saturate to the maximum output voltage as in the case where the overshoot prevention circuit 2 is not provided, and the occurrence of overshoot due to the response delay of the error amplifier can be prevented.

  When the power supply of the switching power supply device 101 is turned off, the voltage charged in the capacitor C2 is discharged through the diode D2 connected to the ground. As a result, even when the switching power supply device 101 returns after an instantaneous power failure, the operation of the switching power supply device 101 can be started with the capacitor C2 being reset.

  A ramp wave oscillator 14 is connected to the non-inverting input terminal (+) of the comparator 13. The ramp wave oscillator 14 outputs a reference triangular wave voltage (ramp wave voltage). Further, the buffer circuit 4 is connected to the inverting input terminal (−) of the comparator 13, and the output of the buffer circuit 4 is inputted.

  The comparator 13 compares the output of the buffer circuit 4 with the ramp wave voltage from the ramp wave oscillator 14 and generates a PWM signal with a duty corresponding to the comparison result. The output of the comparator 13 is connected to the OUT terminal, and the PWM signal generated by the comparator 13 is output from the OUT terminal to the switching circuit 3.

  As described above, the error voltage Verr takes a value higher than the steady state until the output voltage Vo reaches the set value, and decreases to the steady state when the output voltage Vo reaches the set value. In addition, the soft start voltage Vss increases with time. That is, when the switching power supply device 101 is turned on, the soft start voltage Vss is lower than the error voltage Verr, and thereafter, after a certain timing (hereinafter referred to as the crossing timing), the error voltage Verr becomes lower than the soft start voltage Vss. The buffer circuit 4 outputs the smaller one of the error voltage Verr and the soft start voltage Vss.

  Therefore, the comparator 13 compares the soft start voltage Vss with the ramp wave voltage for a certain period from when the power is turned on, and generates a PWM signal having a duty according to the comparison result. Then, after the crossing timing, the comparator 13 compares the error voltage Verr and the ramp wave voltage, and generates a PWM signal having a duty according to the comparison result. Thus, after the error voltage Verr and the soft start voltage Vss intersect, the pulse width of the PWM signal is controlled by the feedback voltage Vfb.

  Without the overshoot prevention circuit 2, as the soft start voltage Vss increases, the output voltage Vo reaches the set value and then the crossing timing is delayed due to the response delay of the error amplifier 11. It becomes too large and overshoot occurs.

  However, in this embodiment, the overshoot prevention circuit 2 is provided, and the output of the buffer circuit 4 is negatively fed back to the FB terminal via the capacitor C2, thereby preventing the output of the error amplifier 11 from being saturated, and crossing timing. Can be expedited. For this reason, the comparator 13 can generate a PWM signal from the corrected error voltage Verr and the ramp wave voltage until the output voltage Vo becomes the set voltage. Occurrence can be prevented.

  The negative feedback amount of the output of the buffer circuit 4 is adjusted by the capacitance of the capacitor C2. In this case, a negative feedback amount may be adjusted by connecting a resistor to the capacitor C2. In addition, the gradient of increasing the soft start voltage Vss is adjusted by the capacitance of the capacitor C3.

  2A and 2B are diagrams illustrating voltage waveforms with and without the overshoot prevention circuit 2, and FIG. 2A illustrates the output voltage Vo and the COMP terminal voltage Vcomp. The waveforms of the feedback voltage Vfb are shown. FIG. 2B shows waveforms of the soft start voltage Vss and the error voltage Verr. 2A and 2B, time is plotted on the horizontal axis and voltage value is plotted on the vertical axis. The broken lines in FIGS. 2A and 2B are voltage waveforms when the overshoot prevention circuit 2 is not provided, and the solid lines are voltage waveforms when the overshoot prevention circuit 2 is provided.

  As shown in FIG. 2 (A), the PWM signal is generated based on the soft start voltage Vss for a certain period of time after the power is turned on, regardless of the presence or absence of the overshoot prevention circuit 2, so that the slope of the output voltage Vo is the same. It becomes. On the other hand, since the COMP terminal voltage Vcomp is negatively fed back via the capacitor C2 of the overshoot prevention circuit 2, the feedback voltage Vfb is different from the case where there is no overshoot prevention circuit 2 (broken line) and the output voltage Vo is set. The reference voltage Vref is reached before the voltage is reached. Further, as shown in FIG. 2B, the error voltage Verr output from the error amplifier 11 is saturated to the maximum voltage that can be output when there is no overshoot prevention circuit 2 (broken line). When there is the overshoot prevention circuit 2, it is held at a level close to the steady-state voltage. As a result, the crossing timing is advanced, and as a result, overshoot of the output voltage is prevented as shown in FIG.

<Embodiment 2>
FIG. 3 is a circuit diagram of the switching power supply device according to the second embodiment. The switching power supply 102 according to the second embodiment is different from the first embodiment in the discharge circuit that discharges the charging voltage of the capacitor of the charging circuit.

  In this embodiment, the overshoot prevention circuit 2A includes a capacitor C2, a diode D1, and a pnp transistor (discharge switch element of the present invention) 21. The pnp transistor 21 has an emitter and a collector connected to both ends of the capacitor C2. The pnp transistor 21 is turned on / off when a reset signal Vreset according to the on / off of the power supply of the switching power supply 102 is input to the base. Specifically, the pnp transistor 21 is turned off when the switching power supply 102 is in an on state, and the pnp transistor 21 is turned on when the switching power supply 102 is in an off state. When the pnp transistor 21 is turned on, a closed circuit including the capacitor C2 is formed, and the voltage charged in the capacitor C2 is instantaneously discharged. Since the voltage can be discharged instantaneously, even if the capacitor C2 has a large capacity, the charge of the capacitor C2 can be reset when the input voltage of the switching power supply 102 is momentarily interrupted or instantaneous power failure.

<Embodiment 3>
FIG. 4 is a circuit diagram of the switching power supply device according to the third embodiment. The switching power supply device 103 according to the third embodiment is different from the soft start circuit according to the first and second embodiments in an overshoot prevention circuit 2B. The overshoot prevention circuit 2B according to this embodiment includes a capacitor C2, diodes D1 and D3, a transistor 21, a Zener diode (constant voltage element of the present invention) 22, and a resistor R4.

  The anode of the diode D 3 is connected to the COMP terminal of the signal generation circuit 1, and the cathode is connected to the anode of the Zener diode 22. The cathode of the Zener diode 22 is connected to the anode of the diode D1 through the capacitor C2. A connection point between the Zener diode 22 and the diode D3 is connected to the ground via a resistor R4. Further, a power source is connected to a connection point between the Zener diode 22 and the capacitor C2 via a current limiting resistor R30, and a voltage Vext is applied. The transistor 21 has an emitter and a collector connected to both ends of the capacitor C2. The transistor 21 is a discharge circuit of the capacitor C2, and is the same as the transistor 21 according to the second embodiment.

  If the error voltage Verr output from the COMP terminal is not sufficiently higher than the feedback voltage Vfb immediately after the power is turned on, for example, smaller than the forward voltage of the diode D2, the negative feedback to the feedback voltage input unit is sufficiently It doesn't take. The third embodiment corresponds to that case.

  As shown in FIG. 4, the error voltage Verr is raised by the Zener voltage (the offset voltage of the present invention) of the Zener diode 22 by inserting a constant voltage generating circuit using the Zener diode 22 in series with the capacitor C2. With this configuration, the effect of suppressing overshoot can be enhanced.

  A diode may be connected between the Zener diode 22 and the resistor R30. For example, the voltage Vext applied to the overshoot prevention circuit 2B may be lower than the error voltage Verr. In that case, by inserting a diode, it is possible to prevent a current from flowing from the Zener diode 22 toward the resistor R30. .

  The specific configuration and the like of the switching power supply apparatus described above can be changed in design as appropriate, and the actions and effects described in the above-described embodiments are merely a list of the most preferable actions and effects resulting from the present invention. The operations and effects of the present invention are not limited to those described in the above embodiment.

1-signal generation circuit 2, 2A, 2B-overshoot prevention circuit 3-switching circuit 4-buffer circuit 5-constant current source 11, 15-error amplifier 12-reference voltage source 13-comparator 14-ramp wave oscillator 16-FET
21-transistor (discharging switch element)
22-Zener diode (constant voltage element)
101-Switching power supply device D1-diode (rectifier element)
D2-Diode D3-Diodes C1, C2, C3-Capacitors R1, R2, R3, R4, R30-Resistor FB-FB terminal SS-SS terminal COMP-COMP terminal Verr-Error voltage Vfb-Feedback voltage Vss-Soft start voltage Vref -Reference voltage Vo-Output voltage Vreset-Reset signal

Claims (4)

An error amplifier that amplifies the difference between the feedback voltage according to the output voltage and the reference voltage and outputs an error amplified signal;
A buffer circuit that compares the error amplification signal and the soft start voltage and outputs the smaller one of the voltages;
A comparator that compares the output of the buffer circuit with a triangular wave signal and outputs a pulse width modulation signal; and a switch element that is switching-controlled by the pulse width modulation signal;
In a switching power supply device comprising:
A capacitor and a rectifier connected in series between an inverting input of the error amplifier to which the feedback voltage is input and an output of the buffer circuit; the rectifier in order of charge direction of the capacitor A charging circuit connected in a direction,
A discharge circuit for discharging the voltage charged in the capacitor;
A switching power supply device comprising: The discharge circuit includes a diode that allows a discharge current to flow between the output unit of the buffer circuit and the ground.
The switching power supply device according to claim 1. The discharge circuit has a discharge switch element connected to both ends of the capacitor,
The switching power supply device according to claim 1. A constant voltage element connected between the output of the buffer circuit and the capacitor and generating an offset voltage;
A switching power supply device according to any one of claims 1 to 3.

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