TW201014135A - Adaptive power supply and related circuitry - Google Patents

Abstract

A power supply configuration includes a monitor circuit to monitor an output voltage and output current of a power supply. The output voltage can be used to supply power to a dynamic load. The power supply varies a rate of changing an adaptive output voltage reference value that tracks the output voltage. Based on a comparison of the output voltage with respect to the adaptive output voltage reference voltage value, a controller associated with the power supply controls switching operation of the power supply to maintain the output voltage within a voltage range. For example, modifying the rate of changing the adaptive output voltage reference value over time depending on current operating conditions of the power supply changes a responsiveness and ability of the power supply to provide current to the dynamic load.

Description

201014135 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to adaptive power supply and related circuits. [Prior Art] A conventional voltage regulator module (VRM) can be used to adjust the DC voltage supplied to a load such as a microprocessor. The VRM may include a power converter, such as a DC-DC converter, and may include other components, such as a controller for controlling the operation of the power converter. An example of a DC-DC converter is a synchronous buck converter, which has very small components and is therefore widely used in VRM applications. In an example application, the input voltage of the buck converter is typically 12 VDC. The output voltage produced by the VRM may be 5.0 VDC, 3.3 VDC, or even lower. A conventional multi-phase interleaved VRM power supply topology can include two or more power converter phases operating in parallel with each other to convert power and supply Φ power to a corresponding load. The implementation of a multiphase voltage converter topology (compared to a single voltage converter phase topology) can thus enhance the output current capacity of the power supply system. A typical configuration of a VRM such as a so-called synchronous buck converter includes an inductor, a high side switch, and a low side switch. A controller associated with the buck converter repeatedly pulses the high side switch to turn on to deliver power from the power source to the dynamic load via the inductor. In order to maintain the output voltage at a relatively constant 値, the controller repeatedly pulsates between the high-side switch and the low-side switch to effectively alternate between the node connection -5 - 201014135 of the inductor and the voltage source and ground. Control the output of the buck converter. The energy stored in the inductor increases during the period when the high side switch is open and decreases during the period when the low side switch is open. During the switching operation, the inductor transfers energy from the input of the converter to the output ' to maintain the output voltage relatively fixed. Today's microprocessors and high-performance ASIC chips can operate at low voltages and require a wide range of currents, such as from less than 1 amp to more than 100 amps. The load can operate for long or short periods of time at these extreme currents. 0 SUMMARY OF THE INVENTION A conventional voltage converter circuit as discussed above can tolerate some disadvantages. For example, to meet transient demands, conventional voltage regulator circuits sometimes must use a number of capacitors to temporarily store the energy that will be supplied to the dynamic load when needed. The use of many large capacitors in individual power supply circuits increases both their size and associated cost. In addition, power supply circuits with a large number of so-called large capacitors may be more susceptible to failure because the parts @ themselves will fail and the capacitors must be connected to the board. The connection to the board will malfunction. Therefore, it is generally undesirable to use an excessive number of large/filter capacitors. The notion of adaptive voltage positioning (also known as AVP) has been widely used in more recent known voltage regulator designs. The adaptive voltage positioning requires control of the power supply output voltage Vo' relative to the fixed reference voltage Vref such that the individual power supply circuits have corresponding fixed output impedances. For example, one conventional AVP method involves the use of a fixed reference voltage in an individual conventional power supply -6 - 201014135 supply circuit. The controller associated with the power supply controls the power supply output voltage based on the Vref-IoRESR instead of the output voltage that drives the power supply relative to Vref. In this case, the power converter circuit behaves as if it had a voltage source that is Vref and is always a real impedance and equal to the output impedance of Res. Through voltage mode control, it is sometimes impossible to achieve a substantially fixed power supply output impedance. In so-called current mode control applications, the AVP φ design depends on the accuracy of the DC (direct current) gain. A technique called Active Down Control can be used to solve these problems by using an infinite DC gain design. However, the time constant of the output filter capacitor can have a significant impact on the feedback loop design and the performance of the converter. Therefore, it is often difficult to accurately maintain the desired output impedance by conventional methods. Furthermore, when the power supply is supplied online, it is not easy to modify the output impedance (e.g., actively maintain the output voltage and drive the load). The techniques discussed herein are separate from the prior art. For example, a particular embodiment herein relates to the ability of an enhanced power supply circuit to supply a high instantaneous current to a dynamic load in which no substantial "ringing" is required or generated at the power supply output voltage. More specifically, the example power supply can include a monitor circuit to monitor an output voltage of a power supply. This output voltage is used to supply power to a dynamic load. This power supply change changes the rate at which one of the adaptive output voltages is referenced. Based on the comparison of the output voltage to the adaptive output voltage reference voltage ,, a controller associated with the power supply controls the switching operation of the power supply to maintain the output voltage within a voltage range -7-201014135. Depending on the current operating state of the power supply, the rate at which the adaptive output voltage reference 改 is changed over time by modification changes the reactivity and capability of the power supply to provide current to the dynamic load. The power supply according to embodiments herein may also include an adaptive output current reference 値 that is adjusted (relatively with, etc.) to the adaptive output voltage reference 値. Thus, the adaptive output voltage reference 値 and the adaptive output current reference 可 can be time varying signals. In one embodiment, the time varying adaptive output voltage reference _ can follow (or be proportional to) the power supply output voltage. It should be noted that the adaptive output voltage reference 可以 can be changed in a continuous manner rather than in a stepwise manner. Comparing the output voltage with the time change or the adaptive output voltage reference 及 and/or comparing the output current to the corresponding time varying output current reference ,, the controller circuit associated with the power supply controlling the power supply A switching operation is supplied to adjust the power supply output voltage. In other embodiments, the corresponding reference voltage generator generates the time varying output reference voltage (eg, as the name suggests, the adjustable reference voltage ❹ changes over time) to depend on the output voltage relative to the adaptability The output voltage refers to the proximity, crossover, etc. of the 値, and is thixotropic between different step voltages, such as high and low step voltages. In one embodiment, the reference voltage generator periodically or occasionally adjusts the time varying output reference voltage by a step amount such that the time varying output voltage reference 値 follows the power supply output voltage. In an exemplary embodiment, during operation, the reference voltage generator sets the time-varying output voltage reference 値 and the corresponding time-varying output -8-201014135 output current reference 随着 to a step voltage 不同 of different amplitudes over time. This power supply has a substantially fixed output impedance 値. According to other embodiments, the reference voltages may be stepped up and down with different magnitudes of voltage over time depending on the current operating conditions of the power supply. When more current is required to supply power to the load, the voltage step adjustments relative to the reference voltages can be relatively large to increase the reactivity and/or capability of the power supply to drive the dynamic load. φ is the substantially fixed output impedance of the power supply. When the time-varying output reference voltage increases, the corresponding time-varying output reference current decreases, and vice versa. This illustrates an example of how the adaptive output voltage reference 値 and the adaptive output current reference 値 can be blended in relation to each other. The adaptive output voltage reference 値 divided by the adaptive output current reference 値 can represent the output impedance of the power supply. Varying the two can set the output impedance of the power supply to a relatively fixed or controlled output impedance for different loads. Φ As discussed above, the controller can be configured to compare the output of the power supply. Voltage and the adaptive output voltage reference 値. Adjust the adaptive output voltage reference 为 to follow the output voltage. The corresponding adaptive output current reference 调整 is adjusted relative to the adaptive output voltage reference 値. At the beginning of an individual switching cycle, the controller initiates the activation of the high side regulator switch of the power supply to transfer power from the source or sources to the dynamic load via a storage device such as an inductor. The activation of the high side switch increases the amount of output current associated with the power supply output voltage such that the output voltage maintains the output voltage within a range even if the dynamic load consumption demand -9-201014135 changes. The controller can also monitor the amount of current supplied to the dynamic load. The controller initiates switching of the high side switch to the off state when the amount of current supplied to the dynamic load equals or exceeds the threshold set by the adaptive output current reference 。. Thus, a power supply in accordance with embodiments herein may include a spike current mode controller. Thus, in accordance with embodiments herein, the power supply can include a voltage control loop and a current control loop. Recall that the controller as described herein can be configured to vary the rate of the adaptive output voltage reference 随着 over time, depending on the operating conditions of the power supply. As mentioned, the adaptation output voltage reference 値 and the modification of the adaptive output current reference 改变 change the reactivity of the power supply. For example, depending on the particular mode of operation, the power supply circuit controls the output current associated with the output voltage such that the output current is limited by the peak current reference 値〇 that is varied depending on the adaptive output voltage reference 値〇 In the first linear control mode of the output current, the reference voltage generator adjusts the peak current reference 以 in a first step amount in each of the plurality of adjustment periods. In the second linear control mode that controls the output current, the reference voltage generator adjusts the peak current reference 以 in a second step amount in each of the plurality of adjustment periods. Accordingly, embodiments herein include changing the adaptive output voltage reference 値 or the adaptive output current reference 以 at a first step amount during a first mode of operation such that the adaptive output voltage reference 値 follows the output -10- 201014135 Voltage; and during the second mode of operation, the rate at which the adaptive output current or the adaptive output current reference 値 is changed is increased by the second step adaptive output voltage reference 値. As will be discussed later in this specification, the addition of the reference voltages in steps can be performed in a plurality of subsequent cycles or samples. Responding to the detection of the output voltage being greater than the output voltage reference 在一 in a duration or condition, such as the adaptive output voltage reference φ. The adaptive output voltage reference 値 is compared with the output voltage for a plurality of times each of which is greater than the output voltage The ginseng according to embodiments herein may increase the instantaneous state of the rate at which the adaptive output voltage reference 改变 is changed. As described elsewhere herein, other methods can be used to detect transient conditions when the dynamic load requires more flow. For example, the circuit can be configured to monitor the rate of change or level of the output voltage to a state. Ο the magnitude of the second step amount is greater than the larger step voltage 该 of the first step amount, compared to a response for adjusting the output current with the first control mode, the second Linear control is used to adjust a faster response of one of the amplitudes of the output current to maintain the voltage in the range. Therefore, the power supply can be in a start-up mode, or a more reactive mode in which the power supply can supply more power loads when needed. The instantaneous state cannot be satisfied by the first or second linear control mode that his linear control mode is satisfied. In response to the change in the dynamics, the voltage reference is reduced or increased over the adaptive input. The subsequent sampling tests the voltage to resolve or less the power to identify the instantaneousity of the monitor. Because the mode associated with the mode provides the output of the second line to the dynamic or any of its load consumption -11 - 201014135 is greater than the current available in the first linear control mode or the second linear control mode a detection of a transient state (such as within a predetermined amount of time), the power supply being configurable to perform a non-linearity of synchronous activation of at least one of the high side switches included in each of the plurality of power converter phases of the power supply Control Mode 'This non-linear control mode supplies power to the dynamic load to prevent the output voltage from falling outside of this range. The synchronous start of the multi-high side switch enables the power supply to quickly generate a large amount of current to meet the consumption requirements of the dynamic load. Eventually, the operational condition may warrant that the power supply is switched back to one of the linear modes for adjusting the output voltage and output current associated with the power supply. The transient can include switching from the non-linear control mode to the second linear control mode, and thereafter, to the first linear control mode. The second linear control mode can be a connected mode to smooth the transfer of the power supply from the non-linear control mode back to the linear mode. Thus, embodiments herein may include switching the power supply job from a linear mode to a non-linear mode, and vice versa, such as switching from a linear mode to a non-linear mode, depending on one or more different power supply parameters. The output voltage, such as the rate of change associated with the output voltage, the proximity of the output voltage to the target 、, the ability of the particular 'mode to provide an appropriate output current consumed by the dynamic load, and the like. Thus, the clue to switch from one mode to the other can be based on any number of different suitable trigger events. In other words, the power supply can be configured to output current according to different conversion rates depending on the current operation of the power supply and/or load. For example, if the output voltage of the power supply is close to the target, the power supply can operate in a mode with a relatively low current output slew rate. Conversely, if the output voltage of the power supply is away from the target or the target operation, the power supply can operate in an individual mode with a relatively high current output slew rate. In one embodiment, the power supply can be switched directly from the first linear control mode to a non-linear control mode of the high side switch that synchronously activates the multi-power converter phase to supply power to the dynamic load. Therefore, examples of implementations herein may include detecting transient conditions. In response to the detection of the transient state, one or more of the high side switches of each of the plurality of power converter phases of the power supply are initiated to initiate simultaneous supply of additional power to the dynamic load during the transient state. Conversely, it must be noted that the transient state can include a sudden decrease in current consumption. In such an example, the power supply can initiate simultaneous activation of one or more of the low side switches of each of the multiple power converter phases to rapidly reduce the amount of current supplied to the load. • As discussed above, and as discussed below, the techniques herein are well suited for use in switched power supply circuits to enhance the power supply circuit to provide more/less current during transient conditions, and during transient current conditions. Provides the ability to stabilize the output voltage. However, it should be noted that the embodiments herein are not limited to use in such applications, and that the techniques discussed herein are also well suited for other applications. It is also noted that the various features, techniques, configurations, etc. discussed herein can be performed independently or in combination with any or all of the other features described herein. Thus, the present invention can be embedded, viewed, or applied in many different ways. This short description is not intended to identify each embodiment of the present invention or the invention, or the novel embodiments. Instead, this short description merely provides a preliminary discussion of the different embodiments and novelty corresponding points beyond the prior art. For additional details and/or possible observations or variations of the present invention, the reader is directed to the embodiments and the corresponding figures of the present disclosure as discussed below. ❹ [Embodiment] The concept of adaptive voltage positioning (AVP) has been widely used in the design of voltage regulators (VRs) for computer microprocessors. In AVP control, the regulator's output voltage (F.) decreases as the output current (8) increases, and vice versa. The use of adaptive voltage positioning reduces the number of output capacitors required in a voltage regulator, which saves cost and board area. The basic commemoration of the AVP is to achieve the fixed output impedance of the regulator (Λ. ❹ ). In the AVP, the output voltage of the regulator is given as follows: V〇=Vomax-I0-R0 (Equation 1) The difference equation (1), the output impedance of the regulator is given as follows: R〇= (Equation 2) - 14- 201014135 The digitization equation (2), the digital expression of the output impedance is given as follows: Based on equation (3) above, a new digital controller circuit is proposed to achieve the desired AVP control. The commemoration is adjusted by time to φ the reference voltage and the reference current / 〃 /. When the reference current is increased, the reference voltage Fre/ is reduced, i.e., by implementing one or more closed control loops, the output voltage of the power supply, such as the buck converter, can be adjusted in a relationship, where Λ. The desired output impedance of the regulator. FIG. 1 is a diagram showing an example of a digital controller circuit 100 in accordance with an embodiment herein. Receiver 100 includes a control function /(7) in module 140 that defines a relational function between L, / and /~/, which is represented as follows: AIre/=f(z)-AVref (Equation 4) The AVP is related to the steady-state operation of the regulator. If the following equation is implemented, the AVP control f(z~>l) will be achieved: -\IR〇 (Equation 5) The simple control function is -15- 201014135 f(z ) = -\/R〇 (Equation 6) The AVP control discussed in this paper is for steady-state operation. The controller 100 can switch between different operating modes as will be discussed later in this specification. 2 is a diagram depicting an example of a control circuit 200 in accordance with an embodiment herein. Control circuit 200 includes digital controller circuit 100 and power converter phase 2 1 0. In one embodiment, the digital controller circuit 100 includes a digital control algorithm 22 5 , a digital pulse width modulation circuit 23 0 , and a reference voltage generator 235-1, such as a current reference voltage (Z^C/m/). And a reference voltage generator 23 5 -2 such as an output reference voltage (IMCFre/). The digital controller circuit 100 also includes two comparators, a comparator 240-1 (comparator I) and a comparator 240-2 (comparator V). A digital control algorithm 225 can be implemented to obtain the desired reference current data and the desired reference voltage data. For example, reference voltage generator 23 5-1 (IMCJre/) receives reference current voltage set point data from digital control algorithm 225 and produces the peak current voltage reference 値Iref. The reference voltage generator 23 5-2 receives the reference voltage data from the digital control algorithm 225 and generates a reference voltage Fre/. During operation, comparator 240-1 compares the generated spike reference current /re/ with inductor current iL, which is sensed by current monitor 245. Based on the comparison of the current produced by the power converter phase 210 with the reference voltage generated by the reference voltage generator 201014135 23 5- 1, the comparator 240-1 produces an output C/ that is transmitted to the digital control algorithm 225 and the digital pulse. Width modulation circuit 230. The digital pulse width modulation circuit 230 generates a gate drive signal to control switching devices such as MOSFETs (M1 and M2) in the power converter phase 210. The comparator 240-2 compares the φ generated reference voltage generated by the reference voltage generator 235-2 with the output voltage of the power converter phase 210 (output voltage 180). Monitor circuit 246 monitors output voltage 180 for driving a dynamic load labeled Rload. Comparator 240-2 produces a comparison result CF that is sent to digital control algorithm 225. The digital control algorithm 225 sequentially adjusts the reference current data and the reference voltage data according to the control rules. In one embodiment, the digital controller circuit 1 operates in a fixed frequency spike current mode (PCM) operation. The high side switch Μ 1 is turned on and the low side is synchronized. 9 The switch M2 is turned off by the timing information generated by the digital pulse width modulation circuit 230. The digital pulse width modulation circuit 230 starts the closing of the high side switch M1 and the subsequent turning of the low side synchronous switch M2 based on the comparison result C/ of the comparator 240-1. For example, if the inductor current through the inductor Lf increases to the peak reference current (C/r e/) set by the reference voltage generator 235-1, the high side switch Μ 1 will be turned off and the low side synchronous switch M2 will be turned on. In one embodiment, to implement an adaptive voltage positioning (A VP ) technique, the digital controller circuit 1 reduces the reference voltage -17-201014135 voltage & e/ when the reference current increases, and vice versa. The two reference voltages are controllably controlled such that the output impedance of the power converter phase 210 is substantially fixed. The change in the reference current can be closely followed by a change in the reference voltage. However, the change in the reference current is driven by the change in the reference voltage. According to an embodiment, the control rules implemented by the digital controller circuit 1 include generating a reference voltage Vref from the reference voltage generator 235-2 to follow the output voltage 180. If the required load current suddenly increases, the output voltage 180 will drop. In such an example, the digital control algorithm 225 will reduce the reference voltage Vref such that it follows the output voltage 180. The digital controller circuit 100 will increase Iref accordingly until a new steady state is established. If the required load current is reduced, the output voltage will rise. In such an example, the digital control algorithm 22 5 will increase the reference voltage such that it follows the output voltage 180. This reference current will be reduced by the digital controller circuit 100 until a new steady state is established. Thus, the example control to implement AVP in accordance with embodiments herein is summarized as follows: a. If the logic signal CV generated by comparator 240-2 is at a high level (CV = 1), it indicates that output voltage 180 exceeds reference voltage generator 23 The reference voltage Vref set by 5-2, the digital control algorithm 225 increases the reference voltage Vref by the amount AVref, and decreases the peak reference voltage Iref by the amount Alref. If Vref reaches or exceeds its maximum allowable 値, no changes will be made to Vref. b. If the logic signal CV generated by the comparator 240-2 is low (201014135 CV = 0), which indicates that the output voltage 180 is less than the reference voltage Vref, the digital control algorithm 225 reduces the reference voltage Vref by the amount AVref, and Alref increases the spike reference voltage Iref. If Vref reaches or exceeds its minimum allowable 値, no changes will be made to Vref. 3 is an example timing diagram in accordance with an embodiment herein. In general, the timing diagram of Figure 3 shows the steady state operational waveform of an example buck converter with digital controller circuit 100. Φ As described above, in one embodiment, the buck converter controls operation in a fixed switching frequency spike current mode. The turning on of the high side switch Μ 1 and the turning off of the low side switch M2 are scheduled by the system clock (labeled as a clock) by the individual gate signals generated by the digital pulse width modulation circuit 230. Adjust the adaptive output voltage reference 为 to follow the output voltage. The corresponding adaptive output current reference 调整 is adjusted relative to the adaptive output voltage reference 维持 to maintain the controlled output impedance for the power supply. At the beginning of an individual switching cycle, such as time to, the controller initiates activation of the high side regulator switch of the Φ power supply to transfer power from one or more sources to the dynamic load via a storage device such as an inductor. . Typically, for a given switching period, such as between times t0 and t4, as shown, the digital pulse width modulation circuit 230 initiates the activation of the high side switch M1 at the beginning of the switching period. The activation of the switch causes energy to be delivered to the inductor, which in turn provides power to the dynamic load. The inductor current ΰ (such as the individual current supplied by the power converter phase) is sensed by the monitor circuit 245 (gain Λ,) and compared to the reference current generated by the reference voltage generator 23 5-1. When the inductor -19-201014135 current reaches the set spike current specified by reference VIII, the digital controller circuit 100 initiates the closing of the high-side switch Μ 1 via the digital pulse width modulation circuit 23 0 and the individual switch driver. And the low side opens p M2. In one embodiment, the following assumptions are made to simplify the analysis of the steady state: 1) The clock functions as the operating clock for both the target FPGA and the reference voltage generator 23 5 (eg, two DACs): 2) There may be four clock cycles in a power supply switching cycle; 3) the output voltage chopping of the output voltage 180 can be ignored to simplify the analysis; 4) The circuit delay is assumed to be zero. The steady state operation of this power supply can be explained as follows: Before the to, the power supply operates in steady state. The time to represents the rising edge of the first clock in a switching cycle. At this time, the digital controller circuit 1 turns on the switch M1 via the signal generated by the digital pulse width modulation circuit 230 and the individual driver and turns off the switch M2. When the high side switch M1 is on, the inductor current ΰ increases linearly. At time t1, the sense inductor current ΰ reaches the peak reference current /re/, and the logic comparison result C/ generated by the comparator 240-1 shown in FIG. 2 is set to a high level, and the logic "1" is based on this. In this case, the switch M1 is turned off and the switch M2 is turned on. Since the high side-off relationship is in the off state, the inductor current ΰ linearly decreases. The reference voltage is greater than the output voltage V during the first clock cycle between times t1 and t2. And set the logical comparison result CV to a low level, logically "〇". As a result, at time t2, such as the rising edge of the second clock in the first switching week 201014135, the peak reference current '" is increased by a small amount of A/re/ with a small amount of AFre/reduced reference voltage. During the second clock period 'such as the period after time t3, the reference voltage Fre / is smaller than the output voltage V. Therefore, the logical comparison result cr becomes a high level, and the logic is "1". As a result, at time t3, the rising edge of the third clock of the first switching period increases the reference voltage Fre/ by a small amount A and decreases the peak reference current /re/ by a small amount A/re/. The reference voltage be/ and the reference current /, e/ are varied in steps (Δ P%e/ and A/re/) depending on the logical comparison result or the like in the previous clock cycle. Time t4 indicates the beginning of a new (or second) switching cycle. The timing diagram of Figure 3 depicts the reference voltage and the reference current as a function of time. For example, in the steady state mode, when the error between the average output voltage 匕 and the average reference voltage <be/> is within AFre/, the average output voltage 匕β follows the average reference voltage <he/> . If AF, e/ is less than voltage chopping, the reference voltage will also reflect the shape of the voltage chopping. In other words, the reference voltage generator 235-2 modifies the reference voltage Vref by a step amount every clock cycle so that it follows the output voltage 180. On the other hand, the digital controller circuit 1 控制 based on the spike reference current /re/ controls the peak inductor current 八*. For this buck converter in continuous current mode (CCM), the average inductor current can be estimated as: τ / Γ Δ Δ / J Fo (1 - Ζ)) * Tsw Ιο = (< II >= Ιρκ ~— = Ιρκ---- C Equation 6) 2 2Lf 201014135 where β is the duty cycle ratio, the system switching period, and Δ/ is the current-wave amplitude. For a given design, assume that it has a fixed input voltage and the output voltage 'this duty cycle Ζ) is constant, so it will have: (Equation 7) (Equation 8) (Equation 9) (Equation 1 0)

AI〇= (A<lL>) = Mpk = (A<Ire/>) = AIref AV0 = (A<V0>) = (A<Vre/>) = AVre/ 2m AT/ χτ ~Vtol AVref = N- where 'A/re/ is the predetermined adjustment step of the peak reference current /rg/, which is the lowest current DA C (m bits, Z) JC/re/) in the reference voltage generator 235-1 Μ times the effective bit (LSB), and Δ Fre/ is used for the predetermined adjustment step 参考 of the reference voltage Fre/, which is the voltage DAC (n bit, DJCFre/) in the reference voltage generator 23 5 -2 The least significant bit © (LSB) is N times 'and AF,. , is the maximum allowable voltage tolerance. As previously discussed, the digital controller circuit 1 〇〇 controls the reference voltage generated by the reference voltage generator 235 such that the power supply circuit has a controlled output impedance. 4 is a diagram depicting a sample of a power supply system 4A in accordance with an embodiment herein. According to the control rules described above, when the current J is input. Increase Δ/. At time, the output voltage h decreases by ΔΓ. ,vice versa. During no load (/.), -22- 201014135 output voltage will have its maximum 値 (assuming this is )). Therefore, the buck converter with the proposed digital controller circuit can be modeled as an equivalent resistor. The ideal voltage source for series connection. As shown in Figure 4, Λ. Can be approximated as: R〇 =

^ AVref SIref

AVt〇i N_ Iref max M (Equation 11) • As discussed above, the substantially fixed output impedance Λ. This can be achieved using the proposed digital controller circuit 100, independent of the equivalent series resistance of the output capacitor C/. From this equivalent circuit, it can be inferred that: y 〇 = vomax - i0, ji0 (Equation 12) Therefore, an adaptive voltage positioning (AVP) control system can be realized. Changing the ratio JV/Μ will adjust the output impedance L. Usually, to simplify the design, # will be equal to M ( ). 3. Instantaneous Load Operation If a large load transient current occurs and occurs on the output voltage 180, the reference voltage and the reference current can be changed fast enough to establish a new balance so that the output voltage does not drop or overshoot. Depending on the application requirements, different control modes can be applied during transient loads. For example, three control modes can be used, which are summarized as follows: 1) as if operating in steady state (control mode I); -23- 201014135 2) fast seek mode (control mode π); 3) instantaneous mode (control mode III) 4) Dual voltage loop control (Control Mode IV) Control Mode I is used as the basis for other control modes. In control mode I there is no difference between transient and steady state. For example, when a transient rising load occurs (such as a load increase for more current demand), the reference voltage will decrease and the reference current will increase until a new steady state is established. When a momentary falling load occurs (such as a current that requires less load), the reference voltage will increase and the reference current will decrease until a new steady state is established. In this control mode, it is not necessary to determine if it is in the transient. A high operating clock frequency can be used to achieve a fast instantaneous response speed so that even small changes in the current consumed by the load can be provided before the output voltage falls outside of the operating range. Control Mode II supports fast search and faster power supply response. For example, a control rule can be implemented to determine if the dynamic load is experiencing transients. In an embodiment, a counter TU (discussed below in Figure 7) may be used when counting or attempting to overuse the output voltage 180 to count the number of reductions of the reference voltage produced by the reference voltage generator 23 5-2. The other counter (counter TD) keeps track of the number of increments of the reference voltage generated by the reference voltage generator 23 5-2. If the counter TU reaches a certain number (predefined in the program) ' when the load requires more current, this indicates the instantaneous state of the load transient rise. If the counter TD arrives at a specific number (predefined in the program), it will be judged to have a transient descent load. -24- 201014135 During the transient state, the amplitude of the adjustment step for this reference voltage/current can be increased in amplitude over the magnitude of the step used in steady state. When a larger step size is implemented, the reference voltage and the reference current will reach the new balance faster than when the step size is smaller. This larger step is implemented to adjust the reference voltage produced by the reference voltage generator 23 5 to increase the reactivity of the power supply and its ability to supply an appropriate amount of current to the load. • Control Mode I and the following are the methods discussed above. However, the control mode II implements a relatively large step voltage adjustment for the reference voltage generated by the reference voltage generator 235. In control mode III (such as instantaneous mode), when a relatively large instantaneous state occurs, the control unit determines that it cannot be processed by control modes I and II. When in this transient mode, the non-linear control can be implemented by the digital controller circuit. In the steady state or low transient of modes I and II, the spike current mode control (linear control) as discussed above is applied. However, in this transient mode, the spike current mode control can be disabled and the reference voltage/current adjustment step will increase to a larger (predefined) amount than normal operation. Control Mode III provides a very fast instantaneous load speed to manage the transient state, particularly in the multi-phase VRM, where individual high side switches in the multi-power converter phase can be synchronized to resolve the transient state. More specifically, in the multi-phase VRM, all high side switches can be turned off and all low side switches can be turned on during the load transient rise state. During the load transient state, all high side switches can be turned on and -25- 201014135 can be turned off or all low side switches turned on. Therefore, the control mode Π has a faster instantaneous load speed than the control mode Ϊ J or control mode I. In control mode IV, a two voltage loop can be used to smooth the load transient transfer. One is a slow voltage loop and the other is a fast voltage loop. A dedicated transient detection circuit is added to detect transients when powering the dynamic load. As will be discussed later in this specification, control mode IV includes two modes: normal operation mode, instantaneous mode, and connection mode. For example, in one embodiment, spike current mode control is used in the normal mode of operation and the connected mode. The low speed voltage loop is turned off in the normal mode of operation 'but the fast voltage loop is turned off in the connected mode. The nonlinear control system is used in this transient mode to disable the spike current mode control. This connection mode enables the power supply to produce instantaneous smoothing from one mode to another. 5 is an example timing diagram depicting transient state and power supply control detection in accordance with embodiments herein. At time t5, a so-called load transient rise occurs, where the dynamic load consumes more current or power. The output voltage V is output because the state of the load has been increased. begin descending. The digital controller circuit can operate in either Control Mode I or Control Mode II to resolve the transient state 输出 Output voltage V due to the additional current required by the dynamic load. Small; ^ reference voltage he/. Based on the applied control rules, the reference voltage Fre/ is gradually decreased by a small amount of Δ Fre/, and the peak reference current is gradually increased by a small corresponding amount. Because the output voltage is lower than Vref at many rising edges 201014135 of the clock, the digital controller circuit 100 begins to reduce the adaptive output reference voltage 値Vref at a plurality of subsequent sampling times in which the reference voltage Vref compares the output voltage 180. . However, it is assumed that the current of the inductor continues to drop even after the reference voltage is adjusted for a plurality of cycles. At time t6, the digital controller circuit 100 initiates the opening of the switch Μ 1 scheduled by the digital pulse width modulation circuit 230 and the closing of the switch M2. The inductor current then begins to increase. At time t7 φ, the inductor current reaches the current consumption of the dynamic load. At time t8, switch M1 is turned off and switch M2 is turned on by comparing logic C/. Thereafter, the digital controller circuit establishes a new steady state. Figure 6 is a diagram showing an example of a sampling waveform of an instantaneous descent state in accordance with an embodiment herein. At time t9, a load transient drop occurs and the output voltage v. Therefore, it starts to rise because the load consumes less power, current, and the like. The output voltage νβ ('that is, the output voltage 180) is greater than the reference voltage Fre/. Based on the implementation of the ❹ control rule, the digital controller circuit 100 increases the reference voltage by a small step amount Δ Le/ on a step-by-step basis. As shown, the digital controller circuit 100 reduces the peak reference current by eight e/ on a step-by-step basis. The inductor current ζ·£ continues to decrease. At time t10', if the inductor current q is less than the peak reference voltage ", as scheduled by the pulse width modulation circuit 230, the switch M1 is turned on and the switch M2 is turned off. In this state, the inductor current begins to increase. At time 11 1 ', switch Μ1 is turned off and switch M2 is turned on by comparison logic c/. And the inductor current begins to decrease. At time t12, the inductor -27-201014135 current reaches its new load current, which becomes the steady state. If the target FPGA and D/A converter's operating clock / η * is high enough, a very fast instantaneous load speed can be achieved. If the operating clock Λα meets the following conditions, only the inductance (〇) will affect the instantaneous current of the inductor current. The load will rise instantaneously. · fclk . hdref > — one t (Equation 1 3 )

Lf load transient drop: fdk.MrefA (Equation 14)

Lf where A/re/ is defined in equation (9). In this control mode 豪|, normally, Μ is set to 1 to utilize the current-based digits in the reference voltage generator 23 5-1 to the full range of the analog converter.

Control Mode II In this control mode, the control unit is used to determine the operating status of the voltage regulator module. These typical operating waveforms are similar to the waveforms discussed above in relation to control mode I. However, the reference adjustment step amount (AFu/ and A/re/) in the transient stage can be set to a step amount larger than the step size of the actual operation in the control mode I. It is possible to select a relatively low frequency for this job clock pin. The counter TU can be used to count the number of step reductions associated with the reference voltage. Another counter TD can be used to count the number of step increases associated with the reference voltage. If the counter TU reaches a critical threshold or limit 値 (LMT_TU, pre-defined in the program), the digital controller circuit 1 detects that the dynamic load consumption is more current than the power supply can supply immediately in the control mode I. The load of the current rises instantaneously. If the counter TD reaches the limit (-28-201014135 LMT_TD, pre-defined in the program), it will judge that there is a load transient drop. These thresholds can be determined as follows: LMT TU > mini int , int AVo, r - 1 _2A_ ^AVref ^ LMT TD > mini int fdk , int 'byo,r -1 2>_ _AVKf\ ί + 1 + 1 (Equation 15) (Equation 16) where D is the duty cycle, /〃 switching frequency, the operating clock of the target FPGA and DAC, AFa, r-system spike-to-spike output chopping voltage, which is greater than X The function of the smallest integer, and the lesser 7 is the function of taking the smaller one from X and less. In equation (9) of the steady state level, assume. The M for this transient stage can be selected to achieve the following good dynamic performance:

Instantaneous load rise: Instantaneous load drop: M >int M > 'mt

Vin — Vo Alref · Lf * fclk V〇AIrrf · Lf · fclk (Equation 17) (Equation 18) where A/re/ is the function of the adjustment of the reference current in the steady state and takes a function smaller than the smallest integer of X . If the Λ/system in equation (9) is selected by equations (17) and (18) for the transient stage, during the transient load stage, equations (13) and (14) will always be satisfied. Specify these states. FIG. 7 depicts a diagram of an example process associated with digital controller circuit 100 in accordance with an embodiment herein. -29- 201014135 As shown and as discussed above, the digital controller circuit 100 can include a pair of counters, in other words, a counter TD and a counter TU. For each clock cycle, the digital controller circuit 1 checks whether the output voltage 180 is greater than the current value of the reference voltage Vref. If true, the digital controller circuit increments the TD counter and resets the TU counter to zero. In addition, the digital controller circuit 1 increases the reference voltage by a suitable step amount so that the reference voltage follows the output voltage. Conversely, if the output voltage 180 is not greater than the reference voltage during the sampling period, the digital controller circuit 100 increments the 计数器 counter TU by one and resets the counter TD to zero. In addition, the digital controller circuit 1 reduces the reference voltage by a suitable amount of step so that the reference voltage follows the output voltage. During the sampling period, if the digital controller circuit 1 detects that the counter TU or the counter TD is less than the individual threshold 値, the digital controller circuit 100 continues to operate in the steady state control mode (ie, control mode I or Control mode II). If the output voltage 180 is greater than the Q reference voltage Vref in a continuous period of more than the critical threshold, the digital controller circuit 100 detects that the dynamic load immediately requires an instantaneous drop in current less than the current supplied by the power supply. status. Conversely, for a given sampling period, if the output voltage 180 is less than the reference voltage Vref in a continuous period of more than the critical threshold, the digital controller circuit 1 detects the dynamic load and immediately requests the power supply. The instantaneous current rise of the current supplied by the current. The digital controller circuit 1 can recognize the transient state by, for example, monitoring the output current or the change of the output voltage with time, monitoring the level of the output voltage, and the like. -30- 201014135

Control Mode III The control function used to determine the presence or absence of a transient can also be implemented in Control Mode . The processing of the mode control function in this mode is the same as the processing in control mode I or π' as previously discussed in relation to Figure 7. In the embodiment, when in control mode III, the digital controller circuit 100 operates in a non-linear mode. Figure 8 is a diagram depicting an example of different control modes in accordance with embodiments herein. As shown, based on the decision logic in mode control unit 810, digital controller circuit 100 can be in a linear mode (eg, a spike current control mode such as control mode I or control mode II) or in a non-linear mode (eg, Work in non-spike control mode). As previously discussed, the digital controller circuit 1 performs peak current mode control (linear control) when in this steady state. When this transient state is relatively minimal, Figure 8 shows this as the normal mode of operation. • When in the transient mode, such as when the dynamic load experiences an instantaneous state, the digital controller circuit 100 de-energizes the spike current mode and adjusts the adjustment of the reference voltage/current to a more normal operating period The step size achieved by the step is larger (predefined). More specifically, during the load transient rise state, when the dynamic load requires additional power, all of the high side switches can be turned "on" by the digital controller circuit 100 to resolve the transient condition. The contour switch is turned on almost immediately to resolve a sudden change in load, after which the power supply can again operate in steady state mode or linear control mode. -31 - 201014135 All high side switches can be turned off during a load transient drop state, such as when the dynamic load consumes less power on the fly. After the transient state, the digital controller mode can be re-executed during the steady state state when the power consumption does not change slightly with time. According to an embodiment, this transient mode provides faster transient load response speeds than control modes I and 11. However, 'different from control modes I and II' this transient mode does not control the operation based on the spike current mode. 0

Control Mode IV FIG. 9 is a diagram depicting an example of a dual voltage loop control mode, such as control mode IV, in accordance with an embodiment herein. In such an embodiment the circuit operates at different speeds: one voltage loop is a low speed loop and the other - the voltage loop is a fast loop. One purpose of the two voltage loops is to smooth the transition between the instantaneous control mode and the non-instantaneous control mode. A dedicated transient load detection circuit 900 can be implemented to detect the transient and non-transient and when to switch between them. FIG. 10 is a diagram showing an example of voltage gap limitations for a transient load detection circuit 900 in accordance with an embodiment herein. This voltage gap follows the reference voltage 匕". In steady state, the reference voltage follows the output voltage V〇, which is fed back by the slow voltage loop. If the instantaneous rising load occurs, the output voltage Vq which is the feedback of the fast voltage loop will fall toward the leading output voltage Vo and the reference voltage Vref. When the output voltage Vq arrives and becomes less than the lower limit hz) of the voltage limiting gap, the transient detecting circuit will issue a signal indicating the instantaneous rising load state -32-201014135. In such an example, the digital controller circuit 100 will enter the instantaneous (rising) mode. When in the instantaneous rise mode, the spike current mode control is applied and nonlinear control is applied so that the transient can be quickly satisfied. For example, the digital controller circuit 100 simultaneously turns on a plurality of high side switches to achieve a high inductor current slew rate. A relatively large reference current/voltage step can be used to follow this new balance point. • When the output voltage V q returns to this voltage gap limit, the digital controller circuit 1〇〇 will enter the connected mode. In an embodiment, the connected mode portion provides a smooth transition from the transient mode back to the normal mode. However, when transitioning from the normal mode to the transient mode, care must be taken to skip the connection mode and implement a transition between the normal mode and the transient mode because the transient mode can bring current faster when needed. Provided to the dynamic load. When in the connected mode, the fast voltage loop is closed and the slow voltage loop is open. The reference voltage Vref follows the output voltage Vq. This new balance point can be followed by a medium amplitude reference current/voltage step. Peak current mode control is available. When the reference voltage again crosses the output voltage Vo, after a number of cycles following the output voltage, the digital controller circuit 100 will enter the normal mode of operation from the connection mode. In this mode, the slow voltage loop is closed and the fast voltage loop is open. As previously discussed, the digital controller circuit 100 can implement a relatively small magnitude of reference current/voltage step to vary the reference voltages. A spike current mode is also applied. -33- 201014135 Similarly, if the instantaneous descent load occurs (such as the dynamic load suddenly requires less current), the output voltage Vq that is the feedback of the fast voltage loop will increase at the leading output voltage Vo and the reference voltage Vref. When the output voltage Vq arrives and becomes greater than the upper limit Fit of the voltage limiting gap, the transient detecting circuit 900 will issue a signal indicating the instantaneous falling state of the load. In such an example, the digital controller circuit 1 will enter the instantaneous drop mode. In the instantaneous descent mode, the digital current mode control is disabled by the digital controller circuit 100 and a non-linear control is applied to control the individual high and low side switches. For example, to accommodate the transient descent state, the digital controller circuit 100 can simultaneously activate a plurality of individual low side switches of the power supply's multiple power converter phases and stop the individual high side switches to achieve high inductor current switching. rate.

When in the instantaneous descent mode, the new balance point can be followed using a relatively large reference current/voltage step. When the turn-off voltage Vq eventually returns to the voltage gap limit, the controller will enter the connected mode. D In this connection mode, the fast voltage loop is closed and the slow voltage loop is open. The reference voltage Vref follows the output voltage Vq. A medium amplitude reference current/voltage step can be used by the digital controller circuit 100 to follow this new balance point. Peak current mode control can be applied. When the reference voltage crosses the output voltage Vo again, the digital controller circuit 1 can be configured to enter the normal operating mode. In this normal mode, the slow voltage loop is closed and the fast voltage loop is open. Small reference current/voltage steps can be used. Also apply -34- 201014135 with spike current mode. Figure 11 is a diagram showing an example of multiple modes and mode shifts in accordance with embodiments herein. As previously discussed, the digital controller circuit 100 transitions between the initial modes of the dual voltage control loop (such as the normal, transient mode, and connected mode) as previously described in relation to Figure ί. It should be noted that depending on the detection of a higher instantaneous load current state, the φ bit controller circuit 100 will enter the transient mode earlier and provide the desired high load current slew rate. As previously discussed, if the load current is relatively low or the required load current conversion rate is low, the digital controller 1 may not enter the transient mode because the normal operating mode (embedded fast seek mode) can handle this Instantaneous load. Figure 12 is a diagram depicting an example of a power supply including multiple power conversion bits in accordance with an embodiment herein. In this example configuration, the power supply includes multiple power converter phases controlled by digital controller circuit 100. During normal mode, digital controller circuit 100 operates the converter phases out of phase. During the transient state, the digital controller circuit 100 can be activated simultaneously with multiple high side switches or multiple low side switches to account for transient transient conditions. The interleaving of multiple power converter phases not only reduces the ripple in the total output ® stream, but also increases the total output current frequency. The frequency of the total inductor current is twice the frequency of each channel (i.e., the phase of the power converter). The use of multiple power converter phases significantly reduces the need for output filter capacitors that are coupled to the power supply. Similarly, the multi-power converter inter-transfer can be discussed in the base mode, and the number is compared to the flow-step circuit input stage 1200. The source is converted to the original radio frequency. Interleaving in phase-35-201014135 can also significantly reduce the need for input filter capacitors. However, the interleaving of multiple power converter phases may include not only the need for more control signals, but also the timing of the control signals. match. According to an embodiment, the way 100 implements a current between different channels (e.g., phase) to balance the multi-power converter phase or channel drive to the load as shown, and Figure 12 shows the phase with the suggested digit 100. The circuit configuration of the buck converter, where the #+ / ) comparator. A comparator is used to compare the phase of the respective power converters with the corresponding reference current voltage 値. The output reference voltage 値Vref is compared using another comparator in the voltage loop. The inductor currents of each phase are sensed and compared with the peak reference current generated by the parameter 23 5 _1 . The current is set to the phase peak reference current. Each phase logic signal is used to turn off the low side switches owned by the individual high side switches it owns. The turn-on signal and the low-close signal of the high side switch are generated by the pulse width modulation circuit 230. In a pulse width modulation circuit 23 0 is a counter-comparator method phase buck converter, the counter bit "given as follows 〇 more complex control of the different channels of the bit controller power sharing control, access. The controller circuit is used in total (in conjunction with the current voltage 180 to generate the test voltage. In the embodiment where the peak is turned off and the side switch is turned on, the implementation is performed. For n = int[log2iV] (Equation 19) 201014135 where function r; uses the result of the high rounding of integers. Figure 13 is a diagram depicting an example architecture for executing instructions, methods, techniques, etc., associated with control application 140-1 in accordance with embodiments herein. The controller circuit 100 may be configured to include a processor such as a DSP (digital signal processor), an FPGA (field effect programmable gate array), a microcontroller, other related circuits as described herein, to implement The techniques discussed above and below. (In such an embodiment, control circuitry 140 may include an interconnect 1311 of coupled memory system 1312, processor 1313, input/output interface 1314, and communication interface 1317. The memory system can be encoded by the control application 140-1, which enables the processor to support the generation of appropriate data, control, and communication signals for phase adjustment via one or more voltage converters. The overall output voltage is 180. Accordingly, the corresponding control application 140-1 can be embedded as a software code that supports processing functionality in accordance with various embodiments described herein, such as data and/or φ logic instructions (eg, stored in the memory) Or a code in another computer readable medium, such as a hard disk. During a job in accordance with an embodiment, the processor 1313 accesses the memory system 1312 via the use of the interconnect 1311 to launch, run, execute, and resolve. The logic instructions of the control application 14 0-1 are translated or otherwise implemented. The execution of the control application generates processing functionality in the control program 140-2. In other words, the control program 140-2 represents the processor 13. One or more portions of control application 140_1 executed within or on 13. It should be noted that other embodiments of the present application include the control application in addition to the control program such as -37-201014135 that implements the example method operations as discussed herein. Program 140-1 itself, such as logic instructions and/or data for generating control signals that are not executed or implemented, to control one of the power supply systems A plurality of voltage converter phases, a reference voltage generator, etc. The control application 1 40-1 may be stored in a computer readable medium (eg, a repository) such as a floppy disk, a hard disk, or an optical medium. According to other embodiments, the control application 140-1 may also be stored in a memory type system, such as in firmware, read only memory (ROM), or as in this example, as in the memory system (eg, Executable code, etc. in random access memory or RAM. It should be noted that in other exemplary embodiments, any part of the digital controller circuit 100 can be configured as a hardware, such as combinatorial logic, digital circuit The functionality supported by the equal-digit digital controller circuit 1 and associated circuitry will now be discussed via the flowcharts in Figures 14 through 17 respectively. It should be noted that it will partially overlap with the concepts discussed above. Furthermore, it should be noted that the steps in the following flow diagrams are not always required to be performed in the order shown. More specifically, Figure 14 depicts a flow diagram 1400 of techniques for improving power supply efficiency in accordance with embodiments herein. In step 1410, digital controller circuit 100 monitors the output voltage 180 of the power supply. As previously discussed, the output voltage 180 is used to supply power to a dynamic load, such as Rload. In step 1 420, the digital controller circuit 100 changes the rate at which an adaptive output voltage reference 値 (201014135 such as Vref) generated by the reference voltage generator 235-2 is changed. In step 143, the digital controller circuit 100 compares the output voltage 180 with the adaptive output voltage reference 値. Based on the comparison, the digital controller circuit 1 controls the switching operation of the power supply to maintain the output voltage 180 within the voltage range. 15 and 16 are combined to form a flowchart 1500 (e.g., flowchart 1 500-1 and flowchart 1 500-2) depicting that at least φ according to embodiments herein is improved based in part on switching between different modes of operation Power supply reactive technology. In step 15 10, digital controller circuit 100 monitors the output voltage 180 of the individual power supplies. As previously discussed, the output voltage 180 can be used to supply power to a dynamic load (Rload), such as processor devices, or other circuits that consume different amounts of power over time. In step 1515, the digital controller circuit 100 monitors the output voltage 180 and detects a rate of change associated with the output voltage 180, such as a plurality of subsequent sampling times by comparing the output voltage 180 at the parametric adaptive output voltage reference 値. The detection adaptive output voltage reference 値Vref is greater than the output voltage 1 80 in each. In step 1 520, the digital controller circuit 100 changes the rate at which the adaptive output voltage reference 値 (i.e., Vref) is changed based, at least in part, on the rate of change associated with the output voltage 180. In other words, if the output voltage 180 changes rapidly such that a small step change in the adaptive output voltage reference 不能 cannot catch up with the output voltage 180, the digital controller circuit 100 implements a larger step size, thereby increasing the power supply. The reactivity is supplied to the -39-201014135 power supply to the dynamic load. Therefore, the mode setting of the power supply reflects what is currently required to supply the appropriate amount of current to the load. In a sub-step 1 52 5 , in response to the detection that the output voltage 1 80 is greater than the adaptive output voltage reference 在一 for a duration, the digital controller circuit 1 〇〇 increases the rate at which the adaptive output voltage reference 改变 is changed, Make Vref change faster with time. In a second step 1 5 3 0, during the first mode of operation, the digital controller circuit 100 changes the adaptive output voltage reference 値Vref by a first step amount such that the adaptive output voltage reference 値 follows the output voltage 180. In step 1 5 3 5, during the second mode of operation, the digital controller circuit 100 changes the adaptive output voltage reference 値Vref by a second step amount, increasing the rate at which the adaptive output voltage reference 改变 is changed. The second step is greater than the first step. The second linear control mode provides a faster response for adjusting the amplitude of the output current to maintain the output voltage in the range compared to the response associated with the first control mode for adjusting the output current . Therefore, the second mode is more responsive to supply power to the dynamic load. In step 1540, the digital controller circuit 100 adjusts the output current reference 依据 (generated by the reference voltage generator 23 5- 1 according to the adaptive output voltage reference 値 (Vref signal from the reference voltage generator 235-2). Iref signal) to control the output impedance of the power supply. In step 1545, a comparison of the adaptive output voltage reference 经由 via output voltage 180 and a comparison of the supply current to the adaptive output current reference ,, as used previously discussed using voltage and current control loops, -40- 201014135 The digital controller circuit 100 controls the switching operation of the power supply to maintain the output voltage 180 within the voltage range. In step 1550, the digital controller circuit 1 0 0 is in response to detecting that the dynamic load consumes an instantaneous state of the additional current that can be supplied by the first linear control mode and the second linear control mode for a predetermined amount of time. Job in nonlinear control mode. When in the non-linear control mode, the digital controller circuit 100 initiates simultaneous activation of one or more high side switches of the plurality of power converter phase φ of the power supply to provide power to the dynamic load, To prevent the output voltage 1800 from falling outside the range. In step 1555, depending on the rate of change associated with the output voltage 180 or the dynamic load promptly requires more or less detection of the instantaneous state of the current, the digital controller circuit 1 is in the power supply in linear mode and Non-linear mode switching between jobs to produce an output voltage of 180. In one embodiment, as previously discussed, the digital controller circuit 100 can monitor the output voltage 180 to detect transient conditions. The response requires more • the detection of the instantaneous state of the current, the digital controller circuit 100 starts the simultaneous start of the high side switch in the multi-supply converter phase to supply additional power to the dynamic load during this transient state. 17 is a flow diagram 1700 depicting techniques for improving power supply efficiency and reactivity based on switching between different modes of operation in accordance with embodiments herein. In step 1710, digital controller circuit 100 controls the output current associated with output voltage 180. To limit the peak current reference 値(lref), the peak current reference 依 varies proportionally to the adaptive output voltage reference 値(Vref) -41 - 201014135. As described herein, the spike current reference 値 is used in conjunction with the adaptive output current reference 値 to maintain the power supply within a substantially constant output impedance range. If necessary, it should be noted that the digital controller circuit 100 can also be configured to control the output impedance of an unfixed 値 (eg, varying 値). In step 1715, when in the first linear control mode that controls the output current, the digital controller circuit 100 adjusts the peak current reference 値Iref by a first step amount in each of the plurality of adjustment periods. In step 1702, when in the second linear control mode controlling the output current, the digital controller circuit 1 adjusts the peak current reference 値Iref by a second step amount in each of the plurality of adjustment periods, The second step amount is greater than the first step amount such that the power supply is more reactive to output additional current to the dynamic load when needed. In step 1 725, when in the linear control mode, responding to the dynamic load consuming more than a current that is sufficiently supplied by the first linear control mode and the second linear control mode for a predetermined amount of time The detection of the instantaneous state of the current, the digital controller circuit 100 performs a non-linear control mode including at least one of the high side switches of the plurality of power converter phases that synchronously activate the power supply to supply power to the dynamic load to prevent The output voltage falls outside of the desired voltage range 180. In step 1 730, after the switching operation according to the nonlinear control mode satisfies the transient state, the digital controller circuit 100 shifts back to the first line by first executing the second linear mode (eg, the connected mode). The control mode controls the output voltage to control the output voltage 180. -42- 201014135 It should be noted that the techniques in this document are suitable for use in power supply applications. However, it should be noted that the embodiments herein are not limited to use in such applications, and that the techniques discussed herein are also suitable for other applications. Having clearly described and described the invention with reference to the preferred embodiments, it will be understood by those skilled in the <RTIgt; The spirit and scope of the case. Such variations are intended to be encompassed by the scope of this application. In this regard, the foregoing description of the embodiments of the present application is not intended to be a limitation. Rather, any limitations of the invention are presented in the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become apparent from the In the drawings, similar reference characters are referenced to the same part at each Φ of the different figures. The figures are not necessarily to scale, the emphasis is placed on the description of the embodiments, principles, and concepts. 1 is an illustration of a power supply system including a current control loop and a voltage control loop in accordance with an embodiment herein. 2 is an exemplary diagram of a power supply in accordance with an embodiment herein. 3 is an example timing diagram in accordance with an embodiment herein. 4 is a diagram depicting a pattern of power supply model modes in accordance with embodiments herein. 5 and 6 are example timing diagrams in accordance with embodiments herein. -43- 201014135 Figure 7 is a diagram depicting an example of a method for detecting transient conditions in accordance with embodiments herein. FIG. 8 is a diagram showing an example of mode transitions in accordance with embodiments herein. 9 is a diagram depicting an example of a power supply configuration in accordance with an embodiment herein. FIG. 1 is an exemplary timing diagram in accordance with the present application. 11 is a diagram of an example depicting mode transitions in accordance with embodiments herein. Figure 12 is an illustration of a power supply system including multiple power converter phases in accordance with an embodiment herein. Figure 13 is a diagram depicting an example of circuitry for performing a job in accordance with an embodiment herein. 14 through 17 are diagrams showing an example flow diagram of an example method in accordance with embodiments herein. [Main component symbol description] 1〇〇: Digital controller circuit 140: Control function 140-1: Control application 140-2: Control program 180: Output voltage 200: Control circuit 210: Power converter phase 225: Digital control calculation Method 230: Digital Pulse Width Modulation Circuit 201014135 235-1, 235-2: Reference Voltage Generator 240-1, 240-2: Comparator 245: Current Monitor 246: Monitor Circuit 400: Power Supply System 8 1 0: mode control unit 900: temporary load detection circuit 1 2 0 0 . power supply 1 3 1 1 : interconnection 1 3 1 2 : memory system 1313 : processor 1314 : input / output interface 1 3 1 7 : communication Interface Cf: Output Capacitor: Output • CV: Logic Signal ESR: Equivalent Series Resistance /. ·' Output current iL: Inductor current Iref: Reference current Lf: Inductor LMT_TD, LMT_TU : P艮

Ml, M2: Switching device *·.

Ri _·gain -45- 201014135

Rload: Dynamic load A. : Output impedance TD, TU: Counter V L D : Lower limit VLU : Upper limit L, V. , Vq : output voltage : reference voltage △ I : current chopping amplitude Alref, ΔVref : quantity

-46 -

Claims (1)

201014135 VII. Patent Application Range: 1. A method comprising: monitoring an output voltage of a power supply for supplying power to a dynamic load; changing a rate of an adaptive output voltage reference ;; The switching of the power supply is controlled via the comparison of the output voltage to the adaptive output voltage reference voltage , to maintain the output voltage within the g-voltage range. 2. The method of claim 1, further comprising: detecting a rate of change associated with the output voltage; and changing the change in the adaptive output voltage reference 根据 based on the rate of change associated with the output voltage rate. 3. The method of claim 1, further comprising: changing the adaptive output voltage reference 以 by a first step amount during a first mode of operation such that the adaptive output voltage reference 値 follows the φ Outputting a voltage; and during a second mode of operation, increasing a rate at which the adaptive output voltage reference 改变 is changed by changing the adaptive output voltage reference 以 by a second step amount, the second step amount being greater than the The first step amount. 4- The method of claim 1, further comprising: responsive to detecting that the output voltage is greater than the adaptive output voltage reference 在一 for a duration, increasing a rate at which the adaptive output voltage reference 改变 is changed. 5. The method of claim 1, wherein the step of controlling the switching operation of the power supply - 47 - 201014135 to maintain the power supply output voltage within a voltage range comprises: depending on the output voltage associated with the output voltage The rate of change is switched from a linear mode to a non-linear mode to produce the output voltage. 6. The method of claim 5, further comprising: based on comparing the adaptive output voltage reference 値 with a plurality of subsequent sampling times of the output voltage, wherein the adaptive output voltage reference 値 is greater than the output voltage Detecting, detecting the rate of change associated with the output voltage. 7. The method of claim 6, wherein the method further comprises: reducing the adaptive output voltage reference 针对 for each of the plurality of subsequent sampling times. &lt; 8. The method of claim 1, wherein the step of monitoring the output voltage of the power supply comprises detecting a transient state, the method further comprising: detecting the instantaneous state, starting the power supply The high side switches of the plurality of power converter phases are synchronously activated to supply additional power to the dynamic load during the transient state. 9. The method of claim 1, further comprising: controlling an output current associated with the output voltage to limit a peak current reference 値, the peak current reference 値 relative to the adaptive output voltage reference ratio Ground change, the spike current reference 値 is used in conjunction with the adaptive output current reference 用于 to maintain the power supply having an output impedance that is substantially constant; and -48-201014135 is controlling a first linearity of the output current In the control mode, the peak current reference 调整 is adjusted by a first step amount in each of the plurality of adjustment periods; and in a second linear control mode that controls the output current, in each of the plurality of adjustment periods A second step amount adjusts the peak current reference 値, the second step amount is greater than the first step amount. The method of claim 9, wherein the second linear control mode provides for adjusting the output current as compared to the response for adjusting the output current associated with the φ first linear control mode. A faster response of a magnitude to maintain the output voltage in the range. 11. The method of claim 9, further comprising: responding to the dynamic load consuming a greater amount of current than the first linear control mode or the second linear control mode for a predetermined amount of time Detecting one of the instantaneous states of the current, performing a non-linear control mode including simultaneous activation of at least one of the plurality of power converter phases of the power supply to supply power to the dynamic load to prevent the The output voltage falls outside of this range. 12. A system comprising: a processor; a memory unit storing instructions associated with an application executed by the processor; and an interconnect coupling the processor and the memory unit to enable The processor executes the instructions and performs the following operations: monitoring an output voltage of a power supply for supplying a power of -49-201014135 to a dynamic load; changing the change to an adaptive output voltage reference a rate; and a comparison of the adaptive output voltage reference voltage 经由 via the output voltage, controlling a switching operation of the power supply to maintain the output voltage within a voltage range. 1 3 - The system of claim 12, wherein the execution of the instructions further supports the following operations: detecting a rate of change associated with the output voltage; and changing according to the rate of change associated with the output voltage The rate of the adaptive output voltage reference 値 is changed. 14. The system of claim 12, wherein the instructions further support the following operations by execution of the processor: when in a first mode of operation, changing the adaptive output by a first step amount The voltage reference 値 is such that the adaptive output voltage reference 値 follows the output voltage; and when in a second mode of operation, the adaptation is increased by changing the adaptive output voltage reference 以 by a second step amount The rate of the output voltage reference 値 is greater than the first step amount. 15. The system of claim 12, wherein the instructions further support the following operations by execution of the processor: responding to the detection of the output voltage being greater than the adaptive output voltage reference for a duration, increasing A rate at which the adaptive output voltage reference 値 is changed. 16. The system of claim 12, wherein the step of controlling the switching operation of the source--50-201014135 source supply to maintain the power supply output voltage reference 値 within a voltage range comprises: depending on the output voltage The rate of change associated with the power supply is switched from a linear mode to a non-linear mode to produce the output voltage. 17. The system of claim 16, wherein the instructions further support the following operations by execution of the processor: 0 based on the adaptive output voltage reference 値 greater than the output voltage in each of a plurality of subsequent sampling times The detecting detects a rate of change associated with the output voltage, the adaptive output voltage reference 比较 being compared to the output voltage during the sampling times. 18. The system of claim 17, wherein the instructions further support the operation by the execution of the processor: reducing the adaptive output voltage reference for each of the plurality of subsequent sampling times. Φ 19 as in the system of claim 12, wherein the instructions support the following operations by the execution of the processor: detecting a transient state; and detecting the transient state, starting the power supply The high side switches in the phase of the power converter are synchronously activated to supply additional power to the dynamic load during the transient state. 2. A system as claimed in claim 12, wherein the instructions further support the following operations by execution of the processor: controlling one of the output currents associated with the output voltage to limit the current at a spike -51 - 201014135 The peak current reference 改变 is proportionally changed with respect to the adaptive output voltage reference ,, and the peak current reference 値 is used in conjunction with the adaptive output current reference 用于 to maintain the power supply having an output impedance that is substantially constant. Supplying; and in a first linear control mode controlling the output current, adjusting the peak current reference 以 in a first step amount in each of the plurality of adjustment periods; and controlling a second of the output current In the linear control mode, the peak current reference 调整 is adjusted by a second step amount in each of the plurality of adjustment periods, and the second step amount is greater than the first step amount. 21. The system of claim 20, wherein the second linear control mode provides for adjusting the output current as compared to a response associated with the first linear control mode for adjusting the output current. A faster response of a magnitude to maintain the output voltage in the range. 22. The system of claim 20, wherein the instructions further support the operation by execution of the processor: responding to the dynamic load being consumed for a predetermined amount of time compared to the first linear control mode and The second linear control mode is capable of supplying a current with one of a plurality of additional currents, and detecting a transient state of at least one high side switch included in each of the plurality of power converter phases of the power supply The mode is controlled to supply power to the dynamic load to prevent the output voltage from falling outside of the range. 23. A tangible computer readable medium having instructions stored therein that, when executed by a processing device, enable the processing device to: - monitor an output of a power supply a voltage, the output voltage is used to supply power to a dynamic load; adjusting an adaptive output voltage reference 値; and controlling the switching of the power supply via the comparison of the output voltage reference voltage 値The output voltage is maintained within a voltage range. 2. A tangible computer readable medium as claimed in claim 2, wherein the instructions, when executed by a processing device, enable the processing device to perform the following operations: monitoring an output current of a power supply, The output current is used to supply power to a dynamic load; setting a rate of changing an adaptive output current reference ;; and controlling the switching of the power supply via the comparison of the output current reference 値The output voltage is maintained within a voltage range. The tangible computer readable medium of claim 24, wherein the instructions, when executed by a processing device, enable the processing device to perform the following operations: detecting a transient state; and responding to a transient state Detecting, synchronizing the start of the high side switch in the multi-supply converter phase of the power supply to supply additional power to the dynamic load during the transient state. -53-