TWI409609B - Driving circuit and control for non-linear load - Google Patents

Abstract

A controller adapted to control a transforming circuit to drive a non-linear load is disclosed. The controller comprises a feedback unit, a pulse width modulated unit and an overshoot damping unit. The feedback unit generates a feedback signal according to a current feedback signal indicative of a load current flowing through the non-linear load. The pulse width modulated unit generates a control signal to control an electric power output of the transforming unit. The overshoot damping unit generates an overshoot damping signal when the load current upwardly cross through a predetermined value. Wherein, the pulse width modulated unit receives the overshoot damping signal and accordingly reduces the duty cycle of the control signal.

Description

Nonlinear load drive circuit and controller

The present invention relates to a non-linear load driving circuit and controller, and more particularly to a non-linear load driving circuit and controller capable of reducing overshoot.

Please refer to the first figure, which is a circuit diagram of a conventional LED driving circuit. The LED driving circuit comprises a controller 10, a conversion circuit 50 and a light emitting diode module 60. The conversion circuit 50 is coupled to an input voltage source Vin, and the controller 10 generates a control signal Sc to control the conversion circuit 50 to transfer the amount of power from the input voltage source Vin to an output. The output end of the conversion circuit 50 is coupled to the LED module 60 to apply an output voltage Vout to the LED module 60, so that the LED module 60 emits light through an output current Iout. The output current Iout flows through a current detecting resistor 65 to generate a current feedback signal IFB.

The controller 10 includes an error amplifier 12, a triangular wave generator 14, a pulse width modulation comparator 16, and a drive circuit 18. The error amplifier 12 receives the current feedback signal IFB and a reference voltage Vr, and generates an error amplification signal Vea accordingly. The triangular wave generator 14 generates a triangular wave signal to the pulse width modulation comparator 16. The pulse width modulation comparator 16 simultaneously receives the error amplification signal Vea to generate a pulse width modulation signal to the driving circuit 18, and the driving circuit 18 generates the control signal according to the pulse width modulation signal of the pulse width modulation comparator 16. Sc.

In general, the controller 10 stabilizes the output current Iout to a predetermined output current Io, at which time the output voltage Vout is also stabilized at a predetermined output voltage Vo. However, the error amplifier 12 compares the current feedback signal IFB and the reference voltage Vr, and integrates the errors of the two signals to adjust the level of the error amplification signal Vea. Such a feedback control process causes the output current Iout and the output voltage Vout to oscillate above and below the predetermined output current Io and the predetermined output voltage Vo (i.e., the amplitude becomes smaller).

Please refer to the second figure, which is the signal waveform diagram of the LED driving circuit shown in the first figure during the startup process. When the controller 10 has not been started, the output voltage Vout, the output current Iout, the error amplification signal Vea, and the control signal Sc are all at a low level. When the controller 10 is activated at the time point T0, since the output current Iout is much lower than the predetermined output current Io, the error amplification signal Vea rises rapidly, so that the duty cycle of the control signal Sc is also rapidly increased. At this time, the output voltage Vout also starts to rise. Since the output voltage Vout reaches the threshold voltage Vf of the LED module 60, that is, before the time point T1, the output current Iout flowing through the LED module 60 remains at the zero level. Since the output current Iout continues to be much lower than the predetermined output current Io during the time T0-T1, the error amplification signal Vea rises to the highest level. At the time point T1, the output current Iout starts to rise, and reaches the predetermined output current Io at the time point T2.

After the time point T2, the output current Iout is higher than the predetermined output current Io, so that the error amplifier 12 starts to pull down the level of the error amplification signal Vea. However, due to the integral relationship, the error amplification signal Vea cannot be directly lowered to an error stable value Veao (this value is the level of the corresponding error amplification signal Vea when the output current Iout stabilizes the predetermined output current Io). This causes the duty cycle of the control signal Sc at this time to be too large, so that the output current Iout continues to rise until the error amplification signal Vea is lower than the error stable value Veao, so that the duty cycle of the control signal Sc is too low. At the time point T3, the output current Iout is again lower than the predetermined output current Io, so that the error amplification signal Vea rises again and exceeds the error stable value Veao. The above process will continue until the time point T4, and the output current Iout, the output voltage Vout, and the error amplification signal Vea respectively converge to the corresponding predetermined output current Io, the predetermined output voltage Vo, and the error stable value Veao.

In addition to the overshoot phenomenon of the output current caused by the startup process of the controller 10, the same overshoot phenomenon is also caused when performing the Burst Dimming of the LED module. Moreover, when the output current Io reaches the predetermined output current Io for the first time, the error amplification signal Vea is maintained at the highest level, causing the overshoot amplitude of the output current Iout and the output voltage Vout to be relatively large. Excessive current and voltage overshoot not only reduces the stability of the circuit, but also increases the possibility of circuit damage.

In view of the severe overshoot phenomenon in the prior art, the stability of the feedback control is reduced and the risk of circuit damage is increased. The present invention provides overshoot control to reduce the output current for feedback control of nonlinear loads such as light-emitting diodes. The overshoot amplitude of the output voltage achieves the advantages of avoiding the above prior art problems.

To achieve the above object, the present invention provides a controller for controlling a conversion circuit to drive a non-linear load. The controller includes a feedback unit, a pulse width control unit and an overshoot mitigation unit. The feedback unit generates a feedback signal based on a current feedback signal representing one of the load currents flowing through the non-linear load. The pulse width control unit generates a control signal according to the feedback signal to control the power output of the conversion circuit. The overshoot mitigation unit generates an overshoot mitigation signal when the load current is judged to be greater than a predetermined value from less than a predetermined value according to the current feedback signal. The pulse width control unit receives the overshoot mitigation signal to reduce the duty cycle of the control signal according to the overshoot mitigation signal.

The present invention also provides a controller for controlling a conversion circuit to drive a non-linear load. The controller includes a feedback unit, a pulse width control unit and an overshoot mitigation unit. The feedback unit generates a feedback signal based on a current feedback signal representing one of the load currents flowing through the non-linear load. The pulse width control unit generates a control signal according to the feedback signal to control the power output of the conversion circuit. The overshoot mitigation unit generates an overshoot mitigation signal based on a voltage feedback signal representative of one of the load voltages applied to the non-linear load. The pulse width control unit receives the overshoot mitigation signal to reduce the duty cycle of the control signal according to the overshoot mitigation signal.

The invention further provides a non-linear load driving circuit for driving a non-linear load. The nonlinear load driving circuit includes a conversion circuit and a controller. The conversion circuit is configured to couple an input voltage source and a non-linear load to receive power from the input voltage source and convert the driven nonlinear load. The controller generates at least one control signal to control the conversion circuit for power conversion according to a current feedback signal representing one of the load currents flowing through the non-linear load. Wherein, the controller reduces at least one control signal when the load current flowing through the non-linear load is changed from less than a predetermined current value or a load voltage applied to the non-linear load from less than a predetermined voltage value Working period.

The above summary and the following detailed description are exemplary in order to further illustrate the scope of the claims. Other objects and advantages of the present invention will be described in the following description and drawings.

Referring to the third figure, there is shown a circuit diagram of a non-linear load driving circuit according to a first preferred embodiment of the present invention. The non-linear load driving circuit includes a controller 100 and a conversion circuit 150 for driving a non-linear load 160. In this embodiment, the non-linear load 160 is exemplified by a light-emitting diode module. The conversion circuit 150 is a switching conversion circuit including at least one switch (not shown) and coupled to an input voltage source Vin. The switch is controlled by the control signal Sc generated by the controller 100 to control the magnitude of the power transmitted from the input voltage source Vin to the conversion circuit 150. The conversion circuit 150 converts the power to provide a load current Iout and a load voltage Vout to drive the nonlinearity. Load 160.

The controller 100 includes a feedback unit 112, a pulse width control unit 110, and an overshoot mitigation unit 120. The feedback unit 112 can be an error amplifier or a feedback circuit with integral action, according to a current feedback signal IFB (generated by the current detection circuit 165) and a reference voltage flowing through one of the load currents Iout of the non-linear load 160. Vr generates a feedback signal Vcomp. The overshoot mitigation unit 120 includes an OR gate 122, a first comparator 124, and a second comparator 126. The first comparator 124 receives the current feedback signal IFB and a first reference signal Vr1, and generates a high level signal when the current feedback signal IFB is higher than the first reference signal Vr1. The second comparator 126 receives a voltage feedback signal VFB (generated by the voltage detecting circuit 155) and a second reference signal Vr2 representing the output voltage Vout, and generates a voltage feedback signal VFB higher than the second reference signal Vr2. High level signal. The OR gate 122 is coupled to the first comparator 124 and the second comparator 126 to output an overshoot mitigation signal Sa accordingly. The pulse width control unit 110 includes an oscillator 114, a pulse width modulation comparator 116, a pulse width limiter 116a, and a driving circuit 118. The oscillator 114 generates a triangular wave signal to the inverting input of the pulse width modulation comparator 116, and the non-inverting input of the pulse width modulation comparator 116 receives the feedback signal Vcomp to generate a pulse width modulation accordingly. Signal to drive circuit 118. The pulse width limiter 116a is coupled to the overshoot mitigation unit 120 to receive the overshoot mitigation signal Sa generated by the overshoot mitigation unit 120. When the pulse width limiter 116a receives the overshoot mitigation signal Sa, a limit control signal having a predetermined duty cycle (i.e., a fixed pulse width) is generated to the drive circuit 118. The driving circuit 118 is coupled to the pulse width modulation comparator 116, the pulse width limiter 116a, and the overshoot mitigation unit 120. When the overshoot mitigation signal Sa is not generated, the control signal is output according to the pulse width modulation signal, and the overshoot mitigation signal is outputted. After Sa is generated, the control signal is output according to the pulse width modulation signal and the lower duty cycle of the control signal.

Next, please refer to the fourth figure, which is the signal waveform diagram of the nonlinear load driving circuit shown in the third figure. When the controller 100 has not been started, the output voltage Vout, the output current Iout, the feedback signal Vcomp, and the control signal Sc are all at a low level. When the controller 100 is started at the time point t0, at this time, since the output current Iout is much lower than the predetermined output current Io, the feedback signal Vcomp rises rapidly, so that the duty cycle of the control signal Sc also increases rapidly at the same time. At time t1, the voltage feedback signal VFB is converted from the second reference signal Vr2 to be greater than the second reference signal Vr2. At this time, the output voltage Vout reaches a predetermined voltage VR2, and the second comparator 126 outputs a high level signal to enable or The gate output overshoots the mitigation signal Sa. The pulse width limiter 116a receives the overshoot mitigation signal Sa and outputs a limit control signal of a fixed pulse width. At this time, since the feedback signal Vcomp is still at the highest level, the duty cycle of the pulse width modulation signal output by the pulse width modulation comparator 116 is greater than the duty cycle of the limit control signal, and the driving circuit 118 controls the output according to the limit control signal. Signal Sc. Therefore, the duty cycle of the control signal Sc decreases after the time point t1. Next, at time t2, the output voltage Vout rises to the threshold voltage Vf of the non-linear load 160, and the non-linear load 160 starts to flow through the current, causing the output current Iout to start to rise. At time t3, the current feedback signal IFB is equal to the first reference signal Vr1. At this time, the output current Iout reaches a predetermined current VR1, and the first comparator 124 outputs a high level signal, wherein the predetermined current VR1 is smaller than the predetermined output current Io. At the time point t4, the output current Iout rises to the predetermined output current Io, and the feedback signal Vcomp starts to decrease. At time t5, the feedback signal Vcomp will be returned to the feedback stable value Vcompo.

Between the time points t4-t5, as the feedback signal Vcomp decreases, the duty cycle of the pulse width modulation signal outputted by the pulse width modulation comparator 116 gradually decreases and is less than the duty cycle of the control signal, the driving circuit 118 is turned to output the control signal Sc according to the pulse width modulation signal. Compared with the prior art, the duty cycle of the control signal Sc is small from the time point t4 until the duty cycle of the pulse width modulation signal is less than the duty cycle of the limit control signal, so that the output current Iout and the rising slope of the output voltage Vout They are all small, thus reducing the magnitude of the overshoot. The setting of the first reference signal Vr1 (corresponding to the predetermined current VR1) and the second reference signal Vr2 (corresponding to the predetermined voltage VR2) may be adjusted or omitted according to actual circuit conditions. For example, the first comparator 124 or the second comparator 126 may be omitted, so that the controller 100 determines whether to reduce the duty cycle of the control signal based on whether the output voltage Vout or the output current Iout reaches a predetermined value. In addition, when the first comparator 124 and the second comparator 126 are simultaneously provided, the time point at which the output voltage Vout reaches the predetermined voltage VR2 does not necessarily need to be earlier than the time point at which the output voltage Vout reaches the predetermined current VR1, and the predetermined voltage VR2 may also be based on The practical application is higher or lower than the threshold voltage Vf. The advantage of providing the first comparator and the second comparator at the same time is that the problem that the reaction time may be insufficient when a single judgment point is avoided can be avoided. For example, when the load is a light-emitting diode, when only the first comparator 124 is set, the time during which the output current Iout rises from the predetermined current VR1 to the predetermined output current Io may be relatively short, and the controller 100 may not have time to reduce the duty cycle of the control signal Sc. . Therefore, the second comparator 126 is added, and the output voltage Vout can be used to assist the determination. When any of the determination conditions is reached, the duty cycle of the control signal Sc is reduced to reduce the possibility that the controller 100 cannot react immediately.

Referring to the fifth figure, there is shown a circuit diagram of a non-linear load driving circuit according to a second preferred embodiment of the present invention. Compared with the embodiment of the third figure, a third comparator 128 and a pulse width limiter 116b are additionally added in this embodiment. The third comparator 128 receives the voltage feedback signal VFB and a third reference signal Vr3, and generates a high level signal to the driving circuit 118 and the pulse width limiter 116b when the voltage feedback signal VFB is higher than the third reference signal Vr3. . The voltage value of the output voltage Vout corresponding to the third reference signal Vr3 is smaller than the predetermined voltage VR2 and the threshold voltage Vf corresponding to the second reference signal Vr2, so that the time point of generating the overshoot mitigation signal Sb is earlier than the time point at which the overshoot mitigation signal Sa is generated. . The pulse width limiter 116b receives the overshoot mitigation signal Sb to generate a limit control signal having a predetermined duty cycle (ie, a fixed pulse width) to the driving circuit 118, wherein the duty cycle of the limit control signal generated by the pulse width limiter 116b is greater than The duty cycle of the control signal generated by the pulse width limiter 116a is limited. The driving circuit 118 outputs the control signal according to the pulse width modulation signal when the overshoot mitigation signal Sb is not generated, and the limit control signal generated by the pulse width modulation signal and the pulse width limiter 116b after the overshoot mitigation signal Sb is generated. The lower duty cycle outputs the control signal.

In this way, the controller can phase down the duty cycle of the control signal Sc, and further avoid the possibility that the controller fails to reduce the duty cycle in time.

In addition, the controller may add a delay unit 130. The delay unit 130 generates a delayed stop signal td to the driving circuit 118 after receiving the overshoot mitigation signal Sa for a predetermined length of time. After receiving the delayed stop signal td, the driving circuit 118 stops the duty cycle of the control signal Sc according to the limit control signal generated by the pulse width limiters 116a, 116b. In this manner, the driving circuit 118 returns to the duty cycle of the pulse width modulation signal adjustment control signal Sc according to the pulse width modulation comparator 116 to avoid continuously limiting the duty cycle of the control signal Sc to affect the transient response capability.

6 is a circuit diagram of a non-linear load driving circuit according to a third preferred embodiment of the present invention. In contrast to the embodiment of the third figure, a delay unit 230 is additionally added in this embodiment. The delay unit 230 receives the current feedback signal IFB, a current upper limit reference signal VrH, and a current lower limit reference signal VrL, wherein the current upper limit reference signal VrH is higher than the reference voltage Vr, and the current lower limit reference signal VrL is lower than the reference voltage VrL. Reference voltage Vr. After receiving the overshoot mitigation signal Sa, the delay unit 230 starts comparing the current feedback signal IFB, the current upper limit reference signal VrH, and the current lower limit reference signal VrL. When the current feedback signal IFB continues for a predetermined length of time, the current upper limit reference signal VrH And in the interval of the current lower limit reference signal VrL, a delay stop signal td is generated to the driving circuit 118 to stop reducing the duty cycle of the control signal Sc according to the overshoot mitigation signal Sa. Through the delay unit 230, it can be confirmed that the output current Iout reduces the duty cycle of the control signal Sc when the amplitude is too large, that is, when the overshoot amplitude is too large, and stops the operation of limiting the control signal Sc when the overshoot amplitude is reduced to an acceptable range. A better transient response capability is obtained by cycle.

The above embodiment illustrates the current change slope greater than the voltage change slope when operating with the non-linear load 160. If the actual non-linear load 160 is in operation, the voltage change slope is greater than the current change slope, the delay unit 230 of the embodiment may instead replace the voltage feedback signal VFB according to the current feedback signal IFB to determine the slowdown overshoot amplitude. The length of time.

7 is a circuit diagram of a non-linear load driving circuit according to a fourth preferred embodiment of the present invention. Compared with the embodiment of the sixth embodiment, the delay unit 330 in this embodiment detects the feedback signal Vcomp to determine the time point at which the duty cycle of the control signal Sc is stopped. The delay unit 230 starts comparing the feedback signal Vcomp and a reference signal Vc after receiving the overshoot mitigation signal Sa, and generates a delayed stop signal td to the driving circuit 118 when the feedback signal Vcomp falls below the reference signal Vc. This achieves the same effect of slowing the overshoot. Alternatively, the delay unit 330 may also output the delayed stop signal td after determining that the feedback signal Vcomp continues to be lower than the reference signal Vc for a predetermined length of time. In this way, in addition to the effect of slowing the overshoot amplitude, when the non-linear load 160 is short-circuited or other problems cause an overload phenomenon, and the feedback signal Vcomp continues to be too high, the output power of the conversion circuit 150 is limited.

Referring to FIG. 8, a circuit diagram of a non-linear load driving circuit according to a fifth preferred embodiment of the present invention. Compared with the embodiment of the third figure, in the embodiment, the delay unit 130 is additionally added to limit the period length of the duty cycle process of the control signal Sc to obtain a better transient response capability, and the pulse width limiter 116c outputs The duty cycle of the limit control signal is generated in a gradually decreasing manner, which is different from the limit output of the pulse width limiter 116a, and the control signal is a fixed duty cycle.

Next, please refer to the ninth figure, which is a sixth preferred embodiment according to the present invention. A schematic diagram of a circuit of a non-linear load drive circuit. In this embodiment, the non-linear load driving circuit includes a controller 200 and a conversion circuit 250 for driving a non-linear load, wherein the controller 200 is a current mode control (Current-Mode Control), and the above embodiment The voltage mode control (Voltage-Mode Control) controller is different.

The controller 200 includes a feedback unit 212, a pulse width control unit 210, an overshoot mitigation unit 220, and a delay unit 430. The feedback unit 212 can be an error amplifier or a feedback circuit having an integral action, and the feedback signal Vcomp is generated according to the current feedback signal IFB and the reference voltage Vr representing the load current Iout flowing through the non-linear load. The overshoot mitigation unit 220 includes an OR gate 222, a first comparator 224, and a second comparator 226. The first comparator 224 receives the current feedback signal IFB and the first reference signal Vr1, and generates a high level signal when the current feedback signal IFB is higher than the first reference signal Vr1. The second comparator 226 receives the voltage feedback signal VFB and the second reference signal Vr2 representing the output voltage Vout, and generates a high level signal when the voltage feedback signal VFB is higher than the second reference signal Vr2. The OR gate 222 is coupled to the first comparator 224 and the second comparator 226 to output an overshoot mitigation signal Sa accordingly.

The pulse width control unit 210 includes a slope compensator 214, a pulse generator 215, a pulse width modulation comparator 216, a pulse width limiter 217, an OR gate 218, and an SR type latch 219. The slope compensator 214 generates a slope compensation signal to the inverting input of the pulse width modulation comparator 216 according to a current sensing signal Cs representing the current IL flowing through a switching switch SW of the conversion circuit 250, and the pulse width modulation The non-inverting input of comparator 216 receives feedback signal Vcomp to thereby generate a pulse width modulated signal to OR gate 218. The pulse generator 215 generates a pulse signal to the set terminal S of the SR type latch 219 at a fixed frequency, and turns the control signal Sc outputted by the SR type latch 219 at the output terminal Q to a high level to turn on the switch SW of the conversion circuit 250. The power of the input voltage source Vin is transmitted. Or the gate 218 outputs a signal to the SR-type latch 219 at the reset terminal R, so that the control signal Sc outputted by the SR-type latch 219 at the output terminal Q is turned to a low level to turn off the switch SW of the conversion circuit 250 to stop transmitting the input voltage source. Vin's electricity.

When the current feedback signal IFB is changed from less than the first reference signal Vr1, the first comparator 224 generates a high level signal, or when the voltage feedback signal VFB is changed from less than the second reference signal Vr2, the second comparison The 226 generates a high level signal, or the gate 222 generates an overshoot mitigation signal Sa. When the pulse width limiter 217 receives the overshoot mitigation signal Sa, the phase shift (Phase Shift) is performed according to the pulse signal of the pulse generator 215, so that the pulse signal generated by the pulse width limiter 217 and the pulse signal of the pulse generator 215 are maintained one. The phase difference is fixed and output through the OR gate 218 operation to reduce/limit the duty cycle of the control signal Sc. The delay unit 430 counts after receiving the overshoot mitigation signal Sa, and generates a delay stop signal td to the pulse width limiter 217 after a predetermined length of time to stop reducing the duty cycle of the control signal Sc according to the overshoot mitigation signal Sa.

Longitudinally, when there is a big difference between the initial state of the voltage or current of the non-linear load and the predetermined stable value, it is easy to cause a large overshoot phenomenon of the voltage or current of the feedback control process, for example, the controller. Just started or dimming control. The invention utilizes a voltage or current that detects a non-linear load to reduce the control signal of the controller before the voltage or current begins to reach a predetermined stable value, so as to reduce the speed of the power transmitted by the input voltage source to slow down the overshoot.

As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

Prior art:

10. . . Controller

12. . . Error amplifier

14. . . Triangle wave generator

16. . . Pulse width modulation comparator

18. . . Drive circuit

50. . . Conversion circuit

60. . . Light-emitting diode module

Vin. . . Input voltage source

Sc. . . Control signal

Vout. . . The output voltage

Iout. . . Output current

65. . . Current detecting resistor

IFB. . . Current feedback signal

Vr. . . Reference voltage

Vea. . . Error amplification signal

Io. . . Predetermined output current

Vo. . . Predetermined output voltage

Vf. . . Threshold voltage

T0, T1, T2, T3, T4. . . Time point

this invention:

100, 200. . . Controller

110, 210. . . Pulse width control unit

112, 212. . . Feedback unit

114. . . Oscillator

116. . . Pulse width modulation comparator

116a, 116b, 116c. . . Pulse width limiter

118. . . Drive circuit

120, 220. . . Overshoot mitigation unit

122, 222. . . Gate

124, 224. . . First comparator

126, 226. . . Second comparator

128. . . Third comparator

130, 230, 330, 430. . . Delay unit

150, 250. . . Conversion circuit

155. . . Voltage detection circuit

160. . . Nonlinear load

165. . . Current detection circuit

214. . . Slope compensator

215. . . Pulse generator

216. . . Pulse width modulation comparator

217. . . Pulse width limiter

218. . . Gate

219. . . SR type latch

Vin. . . Input voltage source

Sc. . . Control signal

Vin. . . Input voltage source

Iout. . . Load current

Vou. . . Load voltage

IFB. . . Current feedback signal

Vr. . . Reference voltage

Vcomp. . . Feedback signal

Vr1. . . First reference signal

Vr2. . . Second reference signal

Vr3. . . Third reference signal

VFB. . . Voltage feedback signal

Sa, Sb. . . Overshoot mitigation signal

T0, t1, t2, t3, t4, t5. . . Time point

Io. . . Predetermined output current

VR2. . . Predetermined voltage

Vf. . . Threshold voltage

VR1. . . Predetermined current

Vcompo. . . Feedback stable value

Td. . . Delay stop signal

VrH. . . Current limit reference signal

VrL. . . Current lower limit reference signal

Vc. . . Reference signal

SW. . . Toggle switch

IL. . . Current

Cs. . . Current sensing signal

Q. . . Output

R. . . Reset end

S. . . Setting end

The first figure is a schematic circuit diagram of a conventional LED driving circuit.

The second figure is a signal waveform diagram of the LED driving circuit shown in the first figure during the startup process.

The third figure is a circuit diagram of a non-linear load driving circuit in accordance with a first preferred embodiment of the present invention.

The fourth figure is the signal waveform diagram of the nonlinear load driving circuit shown in the third figure.

Figure 5 is a circuit diagram of a non-linear load driving circuit in accordance with a second preferred embodiment of the present invention.

Figure 6 is a circuit diagram of a non-linear load driving circuit in accordance with a third preferred embodiment of the present invention.

Figure 7 is a circuit diagram of a non-linear load driving circuit in accordance with a fourth preferred embodiment of the present invention.

Figure 8 is a circuit diagram of a non-linear load driving circuit in accordance with a fifth preferred embodiment of the present invention.

Figure 9 is a circuit diagram of a non-linear load driving circuit in accordance with a sixth preferred embodiment of the present invention.

100. . . Controller

110. . . Pulse width control unit

112. . . Feedback unit

114. . . Oscillator

116. . . Pulse width modulation comparator

116a. . . Pulse width limiter

118. . . Drive circuit

120. . . Overshoot mitigation unit

122. . . Gate

124. . . First comparator

126. . . Second comparator

150. . . Conversion circuit

155. . . Voltage detection circuit

160. . . Nonlinear load

165. . . Current detection circuit

Vin. . . Input voltage source

Sc. . . Control signal

Vin. . . Input voltage source

Iout. . . Load current

Vou. . . Load voltage

IFB. . . Current feedback signal

Vr. . . Reference voltage

Vcomp. . . Feedback signal

Vr1. . . First reference signal

VFB. . . Voltage feedback signal

Vr2. . . Second reference signal

Sa. . . Overshoot mitigation signal

Claims (12)

A controller for controlling a conversion circuit for driving a non-linear load, the controller comprising: a feedback unit, the reference signal representing one of the predetermined output currents and one of the load currents flowing through the non-linear load The current feedback signal generates a feedback signal; a pulse width control unit generates a control signal according to the feedback signal to control the power output of the conversion circuit; and an overshoot mitigation unit determines the load according to the current feedback signal When the current is changed from less than a predetermined value, an overshoot mitigation signal is generated; wherein the predetermined output current is greater than the predetermined value, and the pulse width control unit receives the overshoot mitigation signal to reduce the overshoot mitigation signal according to the overshoot mitigation signal Control the working cycle of the signal. The controller of claim 1, further comprising a delay unit coupled to the overshoot mitigation unit, wherein the delay unit generates a delay stop signal after receiving the overshoot mitigation signal for a length of time to make the pulse width The control unit stops reducing the duty cycle of the control signal according to the overshoot mitigation signal. The controller of claim 2, wherein the delay unit determines whether to generate the delayed stop signal according to a predetermined length of time, the load current or the feedback signal. The controller of claim 1, wherein the overshoot mitigation unit generates a limit signal when the load voltage applied to the non-linear load changes from less than a predetermined voltage value, so that the pulse width control is performed. The unit fixes the duty cycle of the control signal to a predetermined duty cycle. A controller for controlling a conversion circuit to drive a non-linear load, the controller comprising: a feedback unit generating a feedback signal according to a reference signal representing a predetermined output current and a current feedback signal representing a load current flowing through one of the non-linear loads; a pulse width control unit generating the signal according to the feedback signal a control signal for controlling the power output of the conversion circuit; and an overshoot mitigation unit for generating an overshoot mitigation signal according to a voltage feedback signal representative of a load voltage applied to the non-linear load; wherein the pulse width control unit Receiving the overshoot mitigation signal to reduce the duty cycle of the control signal according to the overshoot mitigation signal. The controller of claim 5, further comprising a delay unit coupled to the overshoot mitigation unit, wherein the delay unit generates a delay stop signal after receiving the overshoot mitigation signal for a length of time to make the pulse width The control unit stops reducing the duty cycle of the control signal according to the overshoot mitigation signal. The controller of claim 6, wherein the delay unit determines whether to generate the delayed stop signal according to a predetermined length of time, the load current or the feedback signal. The controller of claim 5, wherein the overshoot mitigation unit generates a limit signal when the load voltage applied to the non-linear load changes from less than a first predetermined voltage value to the pulse The wide control unit fixes the duty cycle of the control signal to a predetermined duty cycle. The controller of claim 5, wherein the overshoot mitigation unit simultaneously determines whether the overshoot mitigation signal is generated according to the current feedback signal, and determines that the load current is changed from less than a predetermined current value or The overshoot mitigation signal is generated when the load voltage is changed from less than a second predetermined voltage value. A non-linear load driving circuit for driving a non-linear load, the non-linear load driving circuit comprising: a conversion circuit for coupling an input voltage source and the non-linear load to receive power from the input voltage source and converting Stabilizing at a predetermined output current to drive the non-linear load; and a controller generating at least one control signal to control the conversion circuit for power conversion according to a current feedback signal representing one of the load currents flowing through the non-linear load; wherein The controller reduces the at least one control signal when a load current flowing through the non-linear load changes from less than a predetermined current value or a load voltage applied to the non-linear load changes from less than a predetermined voltage value a duty cycle, wherein the predetermined voltage value is less than the predetermined output current. The non-linear load driving circuit of claim 10, wherein the non-linear load is a light emitting diode module. The non-linear load driving circuit of claim 10, wherein the controller determines whether to stop reducing the duty cycle of the at least one control signal according to a predetermined length of time or the load current.