CN112383220B - Control circuit and switching converter using same - Google Patents
Control circuit and switching converter using same Download PDFInfo
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- CN112383220B CN112383220B CN202011207783.2A CN202011207783A CN112383220B CN 112383220 B CN112383220 B CN 112383220B CN 202011207783 A CN202011207783 A CN 202011207783A CN 112383220 B CN112383220 B CN 112383220B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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Abstract
The application discloses a control circuit and a switching converter applying the same. The technical scheme of the embodiment of the invention can dynamically adjust the cut-off time of the switching period in response to the change of the output power so as to change the length of the switching period, thereby automatically reducing the working frequency of the switch when the conversion ratio is large or small, so as to widen the range of the conversion ratio and enable the switching converter to realize the self-adaptive application of wide input voltage and wide output voltage.
Description
Technical Field
The invention relates to the power electronic technology, in particular to a switching converter and a control circuit thereof.
Background
A switching converter is a power conversion circuit capable of converting an input voltage into another fixed output signal or an adjustable output signal through different forms of architectures, and thus is widely used in electronic products such as mobile devices. Constant off time (CFT) control is a Pulse Frequency Modulation (PFM) control technique that regulates the output voltage by controlling the power transistors of the switching converter to turn off for a fixed time in each switching cycle.
In the prior art, an IR LED driver for security monitoring generally has a wide input voltage range and a wide output voltage range, so an adaptive control scheme with a wide conversion ratio of a switching converter has very strong application requirements. The common technical scheme is that a setting signal is given by a fixed frequency clock signal according to a fixed frequency to control the conduction time of a power transistor, and a reset signal is given by the maximum conduction time tON_MAXAnd a current comparison signal generated according to the inductor current sampling signal and the current reference value. The minimum pulse width of the set signal is also controlled by the minimum on-time tON_MINLimitation, so that for a constant frequency controlled driver, the minimum and maximum switching ratio is determined by the minimum on-time tON_MINAnd maximum on-time tON_MAXAnd (4) limiting. The conversion ratio calculation formula of a BUCK converter is as follows
Usually minimum on-time tON_MAXLess than the period Ts of the fixed frequency, so that the prior art solutionsMinimum and maximum conversion ratio with fixed fSIs limited by the higher the voltage.
Disclosure of Invention
Embodiments of the present invention provide a switching converter and a control circuit thereof, so that the switching converter can achieve adaptive application of wide input voltage and wide output voltage.
According to a first aspect of the embodiments of the present invention, there is provided a control circuit for a switching converter, the control circuit is configured to adjust a switching control signal according to a compensation signal indicative of output power of the switching converter, so as to control a switching state of a power transistor of the switching converter to meet a circuit conversion ratio requirement, wherein a length of a switching period of the power transistor is in a piecewise linear relationship with the compensation signal.
Preferably, when the power transistor operates in the minimum on-time, the length of the switching period of the power transistor is adjusted according to the compensation signal so as to expand the range of the minimum conversion ratio.
Preferably, when the power transistor operates at the maximum on-time, the length of the switching period of the power transistor is adjusted according to the minimum off-time to expand the range of the maximum conversion ratio.
Preferably, the control circuit adjusts the length of the switching period when switching from one range interval to another range interval in response to the compensation signal.
Preferably, the control circuit is configured to adjust the off-time of the power transistor to adjust the length of its switching period.
Preferably, the control circuit is configured to maintain a length of a switching period of the power transistor constant when the compensation signal is in a first range interval.
Preferably, the control circuit is configured to, when the compensation signal is in a second range interval, the length of the switching period of the power transistor is opposite to the variation trend of the compensation signal.
Preferably, the control circuit is configured to generate a timing signal from the compensation signal and to adjust the off-time of the power transistor by comparing the timing signal with a timing reference signal.
Preferably, the control circuit adjusts the conduction time of the power transistor according to a current comparison signal of an inductive current of the switching converter and a current reference value, a minimum conduction time control signal and a maximum conduction time control signal.
Preferably, the control circuit includes:
the first control circuit is configured to generate a first control signal according to the compensation signal and the duty ratio of the switching converter to adjust the length of the switching period, so that the switching state of a power transistor of the switching converter is controlled to meet the requirement of a circuit conversion ratio when the output power of the switching converter is changed.
Preferably, the first control circuit includes:
the timing circuit generates a timing current according to the compensation signal, the timing current charges a timing capacitor to generate a timing signal, and the magnitude of the timing current and the compensation signal are in a piecewise linear relation;
and when the compensation signal is in a first range interval, the magnitude of the timing current is kept unchanged, and when the compensation signal is in a second range interval, the magnitude of the timing current is in a direct proportion relation with the compensation signal.
Preferably, the timing current when the compensation signal is in the first range interval is larger than the timing current when the compensation signal is in the second range interval.
Preferably, the first control circuit includes:
and the timing reference signal generating circuit is used for receiving the switching control signal to generate a timing reference signal opposite to the duty ratio variation trend of the switching converter.
Preferably, the timing reference signal generation circuit further includes:
and the clamping circuit is connected to the output end of the timing reference signal generation circuit and is used for clamping the timing reference signal at the clamping voltage to increase the length of the switching period when the timing reference signal is smaller than the clamping voltage.
Preferably, the first control circuit further comprises:
and a first comparator, wherein a first input end of the first comparator receives the timing signal, a second input end of the first comparator receives the timing reference signal, and when the timing signal reaches the timing reference signal, the first comparator generates the first control signal.
Preferably, the control circuit further comprises a second control circuit comprising:
a logic circuit, configured to generate an effective second control signal when the maximum on-time control signal is in an effective state, or the minimum on-time control signal and the current comparison signal are both in an effective state; and generating the switch control signal according to the first control signal and the second control signal.
According to a second aspect of embodiments of the present invention, there is provided a switching converter comprising;
a power stage circuit comprising a power transistor coupled to an inductor element, wherein the inductor element couples an input; and the number of the first and second groups,
the control circuit is used for controlling the power transistor to generate an output signal at an output end to drive a load.
The switching converter of the embodiment of the invention can respond to the change of the output power and dynamically adjust the cut-off time of the switching period so as to change the length of the switching period, thereby automatically reducing the working frequency of the switch when the conversion ratio is larger or smaller, so as to widen the range of the conversion ratio and enable the switching converter to realize the self-adaptive application of wide input voltage and wide output voltage.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram of a switching converter according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a second control circuit of an embodiment of the present invention;
FIG. 3 is a circuit diagram of a first control circuit of an embodiment of the present invention;
FIG. 4 is a graph of the timing current versus the compensation signal of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
Fig. 1 is a circuit diagram of a switching converter according to an embodiment of the present invention. As shown in fig. 1, a switching converter 1 of an embodiment of the present invention includes a power stage circuit. The power stage circuit is a BUCK topology and specifically comprises a power transistor Q1, wherein a first end of the power transistor Q1 receives an input voltage Vin; an inductor L having a first terminal connected to the second terminal of the power transistor Q1 and a second terminal connected to the output terminal of the switching converter; a diode D1 having a cathode connected to the second terminal of the power transistor Q1 and an anode coupled to the ground reference of the switching converter. An output capacitor Cout is connected in parallel with the output of the power converter to generate an output voltage Vout across it, and is connected in parallel with a load to provide energy storage. In this embodiment the load is a plurality of Light Emitting Diodes (LEDs) connected in series. In dimming applications, the brightness can be changed by changing the magnitude of the current Iout flowing through the light emitting diode, so that the output power of the switching converter in practical applications changes along with the change of the current Iout. The control circuit 10 adjusts the switching control signal PWM in a closed-loop control mode in accordance with a compensation signal Vcomp indicative of the output power Pout of the switching converter 1 to control the switching state of said power transistor Q1 and to adjust the output current Iout of the switching converter to supply energy to said load. In the present embodiment, the length of the switching period of the power transistor Q1 is in a piecewise linear relationship with the compensation signal Vcomp, and the control circuit 10 can dynamically adjust the length of the switching period in response to the variation of the output power Pout, so as to maintain the output current Iout to meet the driving requirement of the load by controlling the switching state of the power transistor Q1 of the switching converter 1 to meet the requirement of the circuit conversion ratio.
Further, the control circuit 10 adjusts the length of the switching period in response to the input compensation signal Vcomp being switched from one range section to another range section. Specifically, when the compensation signal Vcomp is in the first range section, the length of the switching period of the power transistor Q1 remains unchanged; when the compensation signal Vcomp is in the second range section, the length of the switching period of the power transistor Q1 is opposite to the variation trend of the compensation signal Vcomp. And the control circuit 10 also adjusts the length of the switching period in response to the switching converter 1 entering the minimum off-time control. Preferably, the control circuit 10 is configured to adjust the off-time of the power transistor Q1 to adjust the length of its switching period. Referring to fig. 1, in one embodiment, the control circuit 10 includes a first control circuit 101. The first control circuit 101 adjusts the switching period of the switching converter according to the compensation signal Vcomp representing the output power Pout of the switching converter 1 and the duty ratio of the switching converter to dynamically adjust the length of the switching period when the output power Pout of the switching converter changes, so as to meet the requirement of the circuit conversion ratio by controlling the switching state of the power transistor Q1 of the switching converter 1 to maintain the output current Iout to meet the driving requirement of the load. In the present embodiment, the first control circuit 101 receives the switching control signal PWM to obtain the duty ratio of the switching converter. In one implementation, the switching period includes an on-time and an off-time. The first control circuit 101 generates a timing signal according to the compensation signal Vcomp, and adjusts the length of the off-time of the power transistor Q1 to change the length of the switching period by comparing the timing signal with a timing reference signal, wherein the timing reference signal is related to the duty ratio of the switching converter, and the timing signal is a ramp signal whose rising slope is in a piecewise linear relationship with the compensation signal Vcomp. When the timing signal reaches the timing reference signal, the first control circuit 101 generates a first control signal Vset to control the power transistor Q1 to be turned on, and the switching converter supplies energy to the load through the input voltage Vin. For example, when the output power Pout changes so that the compensation signal Vcomp changes, the rising speed of the timing signal changes, and the time during which the timing signal can rise to the timing reference signal also changes, so that the length of the off-time of the power transistor Q1 is shortened or lengthened, and the length of the entire switching period is also shortened or lengthened.
In the present invention, a feedback circuit 100 is further provided for generating a compensation signal Vcomp representing the output power Pout of the switching converter. Preferably, the feedback circuit 100 generates the compensation signal Vcomp by obtaining an error amplification signal between a feedback signal Vfb representing the output current Iout and a reference value Vref representing the output current Iout, and takes the compensation signal Vcomp as a current reference value. The control circuit 10 further comprises a second control circuit 102. The second control circuit 102 adjusts the on-time of the power transistor Q1 according to the inductor current sampling signal Vsen of the switching converter and the current reference value.
As shown in fig. 2, which is a circuit diagram of a second control circuit according to an embodiment of the present invention, the second control circuit 102 adjusts the on-time of the power transistor Q1 according to a current comparison signal VCMP generated by an inductor current sampling signal Vsen of the switching converter and a current reference value, i.e., a compensation signal Vcomp, a minimum on-time control signal MIN _ TON and a maximum on-time control signal MAX _ TON. The second control circuit 102 includes a comparator CMP and a logic circuit constituted by an and gate 201 and an or gate 202. Specifically, the non-inverting input terminal of the comparator CMP receives the inductor current sampling signal Vsen, the inverting input terminal receives the compensation signal Vcomp, and the output terminal thereof outputs the current comparison signal VCMP to control the on-time of the power transistor Q1. The logic circuit is configured to generate an active second control signal Vres to adjust the on-time of the power transistor Q1 when the maximum on-time control signal MAX _ TON is in an active state, or the minimum on-time control signal MIN _ TON and the current comparison signal VCMP are in active states. And generates a switching control signal PWM based on the first control signal Vset and the second control signal Vres. Based on this, the and gate 201 in the setting logic circuit receives the minimum on-time control signal MIN _ TON and the current comparison signal VCMP and outputs an intermediate signal Vand, and the or gate 202 receives the intermediate signal Vand and the maximum on-time control signal MAX _ TON and outputs the second control signal Vres. In the embodiment shown in fig. 2, the second control circuit 102 may control the on-time of the power transistor Q1 using different control modes to adjust the length of the on-time of the power transistor Q1. For example, a peak current control mode, a constant on-time control mode, or the like is employed.
With continued reference to fig. 1, in an embodiment of the present invention, the control circuit 10 further includes a driving circuit 103. The driving circuit 103 generates a switching control signal PWM to control the power transistor Q1 to be turned on and off according to the first control signal Vset and the second control signal Vres. In one implementation, the driving circuit 103 includes an RS flip-flop. The RS flip-flop receives a first control signal Vset at a set terminal and a second control signal Vres at a reset terminal to generate a switching control signal PWM at an output terminal. It will be appreciated that to enhance the drive capability, a driver or other form of circuitry is added between the output of the RS flip-flop and the control terminal of the power transistor Q1 to better control the power stage circuitry.
In another embodiment, the first control circuit 101 may include a timing circuit and a timing reference signal generation circuit. The timing circuit generates a timing current according to the compensation signal Vcomp, and the timing current generates a timing signal by charging a timing capacitor. Wherein the timing current is piecewise linear with a compensation signal Vcomp. The timing reference signal generating circuit generates a timing reference signal according to the switching control signal PWM. When the output power Pout changes, the timing reference signal changes slowly, and the cut-off of the switching period is dynamically adjusted in response to the output power change, so that the switching state of the power transistor Q1 of the control switching converter 1 can be ensured to meet the requirement of the circuit conversion ratio to maintain the output current Iout to meet the driving requirement of the load.
Fig. 3 is a circuit diagram of a first control circuit of an embodiment of the present invention. The first control circuit 101 includes a timing circuit 30 and a timing reference signal generation circuit 31. Timing circuit 30 includes a controlled current source S1 and a timing capacitor C1 connected in parallel. The first control terminal of the controlled current source S1 receives the compensation signal Vcomp, and the second control terminal is connected to the reference ground of the switching converter, and is controlled by the compensation signal Vcomp to generate the timing current I1. Timing current I1 generates timing signal VB by charging timing capacitor C1. The timing circuit further includes a timing switch K1, the timing switch K1 is connected in parallel across the controlled current source S1 and the timing capacitor C1 to control the timing current I1 to start charging the timing capacitor C1 during the off period of the power transistor Q1 and to reset the timing signal VB to zero when the power transistor Q1 is turned on.
FIG. 4 is a graph of the timing current versus the compensation signal of the present invention. Specifically, when the compensation signal Vcomp is in the first range interval, that is, the compensation signal Vcomp is greater than V2 and less than Vmax, the timing circuit 30 keeps the magnitude of the timing current I1 unchanged, and the length of the switching period of the power transistor Q1 in this stage keeps unchanged; when the compensation signal Vcomp is in the second range section, i.e. the compensation signal Vcomp is greater than V1 and less than V2, the magnitude of the timing current I1 is in direct proportion to the compensation signal Vcomp, and the length of the switching period of the power transistor Q1 in this stage is opposite to the variation trend of the compensation signal Vcomp. And the timing current I1 when the compensation signal Vcomp is in the first range section is larger than the timing current I1 when the compensation signal Vcomp is in the second range section.
With continued reference to fig. 3, the timing reference signal generation circuit 31 includes a current source S2, a switch K2, and a resistor R1. The current source S2 and the switch K2 are connected in parallel, and the resistor R1 is connected in parallel with the current source S2 and the switch K2. The switch K2 is controlled by a switch control signal PWM. During the on-time of the power transistor Q1, the switch K2 is turned on, the voltage across the resistor R1 is zero, and during the off-time of the power transistor Q1, the current source S2 generates the current I2 to charge the resistor R1, and the voltage across the resistor R1 is generated, so that the voltage across the resistor R1 is approximately a square wave. The timing reference signal generation circuit further includes a filtering circuit for filtering the voltage across resistor R1 to generate timing reference signal VA, such that timing reference signal VA is proportional to the duty cycle of the switching converter. In the present embodiment, the filter circuit includes a resistor R2 and a capacitor C2 connected in series, and the timing reference signal VA is generated at the common terminal of the resistor R2 and the capacitor C2.
In addition, the timing reference signal generation circuit 31 further includes a clamp circuit connected to an output terminal of the timing reference signal generation circuit 31 for clamping the timing reference signal VA to be lower than the clamp voltage VOFF_MINWhile the timing reference signal VA is clamped at the clamping voltage VOFF_MINTo increase the length of the switching period. The first control circuit 101 further comprises a comparison circuit CMP1, a first input terminal (e.g. an inverting input terminal) of the comparison circuit CMP1 receiving the timing reference signal VA, a second input terminal (e.g. a non-inverting input terminal) receiving the timing signal VB, and generating the first control signal Vset by comparing the timing reference signal VA and the timing signal VB. In the bookIn an embodiment, the timing reference signal VA can be expressed as follows:
VA＝I2×R1×(1-D)
where D is the duty cycle of the switching converter.
The timing signal VB can be expressed as follows:
where Ts is the switching period of the switching converter. When the timing signal VB reaches the timing reference signal VA, the first control circuit 101 generates the active first control signal Vset, and the power transistor Q1 is turned on again. The switching period of a switching converter can therefore be expressed as follows:
therefore, when the timing current I1 outputted by the current source S1 is a constant value, the switching period Ts of the switching converter is a constant value, so that the system operates in the quasi-constant frequency mode. Under the normal conversion ratio, when the compensation signal Vcomp is in the first range, i.e. the compensation signal Vcomp is greater than V2 and less than Vmax, the magnitude of the timing current I1 remains unchanged, and the length of the switching period of the power transistor Q1 remains unchanged during this stage.
When the conversion is small, that is, the duty ratio is small, the existing scheme will be due to the preset minimum on-time tON_MINThe energy is still too large and the on-time ton is too large resulting in too high an output current Iout. The loop will now have its inductor current reduced, but due to the minimum on-time tON_MINThe limitation of (2) has not fallen; in the embodiment of the present invention, the compensation signal Vcomp is always decreased due to the too high output current Iout, which causes the timing current I1 output by the current source S1 to decrease, the off-time of the switching period to increase, and the frequency of the switching period to decrease by increasing the length of the switching period. In this phase, I1 is k × Vcomp, k is smaller than 1, and the controlled current source S1 is controlled by the compensation voltage Vcomp. At this timeEntering a down-conversion mode of operation, the minimum conversion ratio is calculated as follows:
the minimum conversion ratio at this time is only limited by the minimum on-time tON_MINAnd the coefficient k, so that smaller conversion ratio occasions can be accommodated.
When the conversion ratio is large, the timing reference signal VA is too small, and the value of the timing reference signal VA is clamped by the clamping voltage VOFF_MINClamping, in which case the switching period of the switching converter
The formula will not hold. The set signal output from the first control circuit 101 is based on the clamp voltage VOFF_MINMinimum off-time t of controlOFF_MINAnd (4) generating. At this time the timing current I1 is a constant value,
at this time, the down-conversion mode is entered, and the maximum conversion ratio is calculated as follows:
the maximum conversion ratio at this time is not limited by the fixed frequency fSLimited by only the maximum on-time tON_MAXAnd minimum on-time tOFF_MINCan exceed the original switching period Ts.
Thereby being capable of adapting to larger conversion ratio occasions.
In summary, in the embodiment of the invention, when the power transistor operates in the minimum on-time, the switching converter adjusts the length of the switching period of the power transistor according to the compensation signal to expand the range of the minimum conversion ratio, and when the power transistor operates in the maximum on-time, the switching converter adjusts the length of the switching period of the power transistor according to the minimum off-time to expand the range of the maximum conversion ratio. The length of the switching period is changed by dynamically adjusting the cut-off time of the switching period in response to the change of the output power, so that the working frequency of the switch is automatically reduced when the conversion ratio is large or small, the range of the conversion ratio is widened, and the switch converter can realize the wide-input-voltage and wide-output-voltage self-adaptive application.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (15)
1. A control circuit for a switching converter, the control circuit being configured to adjust a switching control signal based on a compensation signal indicative of an output power of the switching converter, to control the switching state of the power transistors of the switching converter to meet the circuit switching ratio requirements, wherein the length of the switching period of the power transistor is piecewise linear with the compensation signal, the length of the switching period of the power transistor is kept unchanged when the compensation signal is in a first range interval, when the compensation signal is in a second range interval, the length of the switching period of the power transistor is opposite to the variation trend of the compensation signal, the lowest value of the first range is not less than the highest value of the second range, and the compensation signal is generated according to an error amplification signal between a feedback signal representing the output current and a reference value representing the output current.
2. The control circuit of claim 1, wherein the length of the switching period of the power transistor is adjusted according to the compensation signal when the power transistor operates at the minimum on-time to expand the range of minimum conversion ratio.
3. The control circuit of claim 1, wherein the length of the switching period of the power transistor is adjusted according to the minimum off-time to extend the range of the maximum slew rate when the power transistor is operated at the maximum on-time.
4. The control circuit of claim 1, wherein the control circuit adjusts the length of the switching period in response to the compensation signal switching from one range interval to another.
5. The control circuit of claim 1, wherein the control circuit is configured to adjust an off-time of the power transistor to adjust a length of a switching period thereof.
6. The control circuit of claim 5, wherein the control circuit is configured to generate a timing signal based on the compensation signal and to adjust the off-time of the power transistor by comparing the timing signal to a timing reference signal.
7. The control circuit of claim 1, wherein the control circuit generates a sampling signal based on an inductor current of the switching converter, generates a current comparison signal by comparing the sampling signal to a current reference, and adjusts the on-time of the power transistor based on the current comparison signal, a minimum on-time control signal, and a maximum on-time control signal.
8. The control circuit of claim 1, wherein the control circuit comprises:
the first control circuit is configured to generate a first control signal according to the compensation signal and the duty ratio of the switching converter to adjust the length of the switching period, so that the switching state of a power transistor of the switching converter is controlled to meet the requirement of a circuit conversion ratio when the output power of the switching converter is changed.
9. The control circuit of claim 8, wherein the first control circuit comprises:
the timing circuit generates a timing current according to the compensation signal, the timing current charges a timing capacitor to generate a timing signal, and the magnitude of the timing current and the compensation signal are in a piecewise linear relation;
and when the compensation signal is in a first range interval, the magnitude of the timing current is kept unchanged, and when the compensation signal is in a second range interval, the magnitude of the timing current is in a direct proportion relation with the compensation signal.
10. The control circuit of claim 9, wherein the timing current when the compensation signal is in a first range interval is greater than the timing current when the compensation signal is in a second range interval.
11. The control circuit of claim 9, wherein the first control circuit comprises:
and the timing reference signal generating circuit is used for receiving the switching control signal to generate a timing reference signal opposite to the duty ratio variation trend of the switching converter.
12. The control circuit of claim 11, wherein the timing reference signal generation circuit further comprises:
and the clamping circuit is connected to the output end of the timing reference signal generation circuit and is used for clamping the timing reference signal at the clamping voltage to increase the length of the switching period when the timing reference signal is smaller than the clamping voltage.
13. The control circuit of claim 12, wherein the first control circuit further comprises:
and a first comparator, wherein a first input end of the first comparator receives the timing signal, a second input end of the first comparator receives the timing reference signal, and when the timing signal reaches the timing reference signal, the first comparator generates the first control signal.
14. The control circuit of claim 8, further comprising a second control circuit comprising:
the logic circuit is used for generating an effective second control signal when the maximum on-time control signal is in an effective state, or the minimum on-time control signal and the current comparison signal are in effective states; and generating the switch control signal according to the first control signal and the second control signal.
15. A switching converter, comprising;
a power stage circuit comprising a power transistor coupled to an inductor element, wherein the inductor element couples an input; and the number of the first and second groups,
a control circuit according to any of claims 1 to 14 for controlling the power transistor to produce an output signal at an output terminal to drive a load.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101795068A (en) * | 2009-05-26 | 2010-08-04 | 杭州矽力杰半导体技术有限公司 | Switch type regulator and control method thereof |
| CN102013807A (en) * | 2005-07-08 | 2011-04-13 | 电力集成公司 | Method and apparatus for increasing the power capability of a power supply |
| CN104779799A (en) * | 2015-04-28 | 2015-07-15 | 矽力杰半导体技术(杭州)有限公司 | Control circuit, control method and flyback converter using same |
| CN106100352A (en) * | 2016-08-05 | 2016-11-09 | 广州金升阳科技有限公司 | Flyback control circuit and control method |
| CN107834875A (en) * | 2017-11-14 | 2018-03-23 | 西安矽力杰半导体技术有限公司 | A kind of frequency control circuit and its control method and switched mode converter |
| CN108075634A (en) * | 2016-11-17 | 2018-05-25 | 台达电子电源(东莞)有限公司 | For the control device and control method of power factor correcting converter |
| CN109936294A (en) * | 2019-04-01 | 2019-06-25 | 矽力杰半导体技术(杭州)有限公司 | Control circuit and the inverse excitation type converter for applying it |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108667291B (en) * | 2018-03-29 | 2020-03-06 | 矽力杰半导体技术(杭州)有限公司 | Switch type converter and control circuit thereof |
-
2020
- 2020-11-03 CN CN202011207783.2A patent/CN112383220B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102013807A (en) * | 2005-07-08 | 2011-04-13 | 电力集成公司 | Method and apparatus for increasing the power capability of a power supply |
| CN101795068A (en) * | 2009-05-26 | 2010-08-04 | 杭州矽力杰半导体技术有限公司 | Switch type regulator and control method thereof |
| CN104779799A (en) * | 2015-04-28 | 2015-07-15 | 矽力杰半导体技术(杭州)有限公司 | Control circuit, control method and flyback converter using same |
| US10951120B2 (en) * | 2015-04-28 | 2021-03-16 | Silergy Semiconductor Technology (Hangzhou) Ltd | Flyback converter, control circuit and control method therefor |
| CN106100352A (en) * | 2016-08-05 | 2016-11-09 | 广州金升阳科技有限公司 | Flyback control circuit and control method |
| CN108075634A (en) * | 2016-11-17 | 2018-05-25 | 台达电子电源(东莞)有限公司 | For the control device and control method of power factor correcting converter |
| CN107834875A (en) * | 2017-11-14 | 2018-03-23 | 西安矽力杰半导体技术有限公司 | A kind of frequency control circuit and its control method and switched mode converter |
| CN109936294A (en) * | 2019-04-01 | 2019-06-25 | 矽力杰半导体技术(杭州)有限公司 | Control circuit and the inverse excitation type converter for applying it |
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| CN112383220A (en) | 2021-02-19 |
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