CN108667291B - Switch type converter and control circuit thereof - Google Patents

Switch type converter and control circuit thereof Download PDF

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CN108667291B
CN108667291B CN201810273992.3A CN201810273992A CN108667291B CN 108667291 B CN108667291 B CN 108667291B CN 201810273992 A CN201810273992 A CN 201810273992A CN 108667291 B CN108667291 B CN 108667291B
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switch
circuit
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control circuit
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CN108667291A (en
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邱建平
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Hangzhou Silergy Semiconductor Technology Ltd
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Hangzhou Silergy Semiconductor Technology Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a switch-type converter and a control circuit thereof, wherein the switch-type converter comprises a super-audio control circuit, a compensation signal is changed in a smaller range by controlling the first conduction time of a rectifier switch of the switch-type converter to be continuously adjustable along with a duty ratio and a switching frequency in a light load or no-load mode, and a feedback signal is introduced to adjust the first conduction time of the rectifier switch, so that the adjustment speed of an output signal is accelerated, and the accuracy and the stability of the output signal are ensured while audio noise is avoided in the light load or no-load mode of the switch-type converter, thereby being suitable for application occasions with wide input and wide output and adjustable switching frequency.

Description

Switch type converter and control circuit thereof
Technical Field
The present invention relates to power electronics, and more particularly, to a switching converter and a control circuit thereof.
Background
The portable equipment has high requirements on efficiency in a light load mode, and the switching type converter of the BUCK topology (BUCK) can turn off the power switch when the inductive current crosses zero, so that the switching frequency of the power switch is reduced, the switching loss of the power switch is reduced, and the efficiency of the whole circuit system is improved. There is a problem in that if the switching frequency is lower than 20kHz in the light or no-load mode, audio noise is generated, which is unacceptable for the portable device. In order to avoid audio noise while improving light load efficiency, a super-audio mode is usually designed to be between the conventional light load efficient mode and the forced continuous mode. The super audio mode is an operation mode for controlling the switching frequency of the power switch and the rectifier switch to be always above 20kHz when the switch type converter runs in light load or no load, so that the audio noise can be prevented.
However, how to ensure the accuracy and stability of the output voltage in the super-audio mode is an urgent problem to be solved.
Disclosure of Invention
In view of this, the present invention provides a switch-type converter and a control circuit thereof, so as to avoid audio noise in a light load or no-load mode and ensure accuracy and stability of an output signal, thereby being suitable for wide input and wide output and application occasions with adjustable switching frequency.
In a first aspect, a switch-mode converter is provided, comprising a power stage circuit and a super-audio control circuit, wherein the power stage circuit comprises a rectifier switch configured to have a first on-time to regulate an output signal of the switch-mode converter;
the super-audio control circuit is configured to adjust the first on-time according to the duty ratio and the switching frequency of the switch-type converter in a super-audio mode so as to maintain the output signal not to be detuned in the whole duty ratio range.
Further, the superaudio control circuit adjusts the first conduction time according to the duty ratio and the switching frequency, so that a compensation signal changes in a preset range, wherein the compensation signal represents a difference value between a feedback signal and a reference signal;
the feedback signal is used for representing an output signal of the switch type converter, and the reference signal is used for representing a desired value of the output signal of the switch type converter.
Further, the super-audio control circuit is further configured to adjust the first on-time according to a feedback signal to improve response speed.
Further, the superaudio control circuit is configured to control the switch-mode converter in a light load or no load mode.
Further, the power stage circuit further comprises a power switch, and the super-audio control circuit is configured to control the power switch to be conducted for a third conducting time after the first conducting time is over.
Further, the ultrasonic control circuit controls the third on-time to be a predetermined value.
Further, the ultrasonic control circuit is configured to control the rectifier switch to conduct for a second conduction time after the third conduction time to freewheel the inductor current.
Further, the superaudio control circuit is configured to control the power switch and the rectifier switch to remain off for a predetermined standby time after the inductor current freewheels to a predetermined value.
Further, the super-audio control circuit comprises:
a delay circuit configured to generate a first set signal;
a regulating circuit configured to generate a second set signal and a rectified switch indication signal to control the first on-time according to the first set signal, a duty cycle of the switching type converter, a switching frequency, and a compensation signal, the compensation signal characterizing a difference of the feedback signal and a reference signal; and
a logic circuit configured to generate control signals of the rectifier switch and the power switch according to the rectifier switch indication signal, the second set signal and a zero-crossing signal to control the on and off of the rectifier switch and the power switch;
wherein the reference signal is indicative of an expected value of an output signal of the switched mode converter.
Further, the logic circuit is further configured to generate a standby state signal according to control signals of the rectifier switch and the power switch.
Further, the delay circuit starts timing when receiving an effective standby state signal, and generates the first set signal after a predetermined standby time.
Further, the adjusting circuit includes:
the feedback adjusting signal generating circuit is controlled by the rectifying switch indicating signal and generates a feedback adjusting signal according to the duty ratio, the switching frequency and a first reference threshold value;
a reference adjustment signal generation circuit configured to generate a reference adjustment signal according to the compensation signal and a second reference threshold;
a comparator configured to compare the feedback adjustment signal and the reference adjustment signal to generate the second set signal.
Further, the first reference threshold and the second reference threshold are equal bias voltage signals;
alternatively, the first reference threshold value characterizes the feedback signal and the second reference threshold value characterizes the reference signal.
Further, the adjusting circuit further includes:
and the set end of the first RS trigger inputs the first set signal, the reset end of the first RS trigger inputs the second set signal, and the rectifier switch indicating signal is output.
Further, the feedback adjustment signal generation circuit includes:
a first switch connected between a first terminal and a first input terminal of the comparator;
a second switch;
the first controlled current source is controlled by the duty ratio and the switching frequency, and the second switch is connected between the first input end of the comparator and the ground end in series;
the first capacitor is connected between the first input end of the comparator and a grounding end; and
a first transistor connected between the first terminal and a ground terminal;
the first switch and the second switch are controlled by the rectifier switch indication signal to be switched on or switched off;
the reference adjustment signal generation circuit includes:
a second transistor connected between the second terminal and a ground terminal;
the second controlled current source is controlled by the compensation signal and is connected between the second input end of the comparator and the grounding end; and
a resistor connected between the second input terminal of the comparator and the second terminal.
Further, the logic circuit includes:
a timing circuit configured to receive a control signal of the power switch to control the power switch to be turned on for a third on-time, and output a reset signal;
the second RS trigger has a setting end for inputting the second setting signal, a resetting end for inputting the resetting signal and an output end for outputting a control signal of the power switch;
a NOR logic circuit configured to generate a control signal of the rectifier switch according to the power switch indication signal, the zero-crossing signal, and a negation of a control signal of the power switch;
the nor logic circuit is further configured to generate a standby state signal according to control signals of the power switch and the rectifier switch.
In a second aspect, a control circuit for a switching converter is provided, comprising:
a control loop configured to output a third set signal for driving switching of a power switch and a rectifier switch of a switching type converter according to a feedback signal of a power stage circuit of the switching type converter; and
and the superaudio control circuit is configured to adjust the first conduction time of the rectifier switch according to the duty ratio and the switching frequency of the switch type converter in a superaudio mode so as to maintain the output signal of the switch type converter not to be detuned in the whole duty ratio range.
Further, the super-audio control circuit is further configured to adjust the first on-time according to the feedback signal to improve response speed.
Further, the superaudio control circuit is configured to control the switch-mode converter in a light load or no load mode.
Further, the superaudio control circuit is further configured to control the power switch to conduct for a third conduction time after the first conduction time ends.
Further, the ultrasonic control circuit is configured to control the rectifier switch to conduct for a second conduction time after the third conduction time to freewheel the inductor current.
Further, the superaudio control circuit is configured to control the power switch and the rectifier switch to remain off for a predetermined standby time after the inductor current freewheels to a predetermined value.
The compensation signal is changed in a small range by controlling the first conduction time of the rectifier switch of the switch type converter to be continuously adjustable along with the duty ratio and the switching frequency in a light load or no-load mode, so that the accuracy and the stability of an output signal are ensured while audio noise is avoided in the light load or no-load mode of the switch type converter, and the switch type converter is suitable for wide-input wide-output and switching frequency adjustable application occasions.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a circuit schematic of a switch mode converter according to an embodiment of the present invention;
FIG. 2 is a circuit schematic of a control circuit of an embodiment of the present invention;
FIG. 3 is a waveform diagram illustrating the operation of a switch-mode converter according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a delay circuit of an embodiment of the present invention;
FIG. 5 is a circuit diagram of a regulating circuit of a comparative example;
FIG. 6 is a circuit diagram of a conditioning circuit of an embodiment of the present invention;
FIG. 7 is a detailed circuit diagram of the conditioning circuit of an embodiment of the present invention;
FIG. 8 is a graph of compensation signal versus duty cycle for an embodiment of the present invention;
FIG. 9 is a graph of gain versus duty cycle of a compensation signal according to an embodiment of the present invention;
FIG. 10 is a waveform diagram illustrating operation of a conditioning circuit according to an embodiment of the present invention;
fig. 11 is a circuit diagram of a logic circuit of an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
Fig. 1 is a circuit schematic diagram of a switching type converter according to an embodiment of the present invention. As shown in fig. 1, a switching type converter includes a power stage circuit 1 and a control circuit 2 employing a buck type topology. The power stage circuit comprises a power switch S1, a rectifier switch S2, an inductor L, a load RL and an output capacitor CL. The power switch S1 is connected between the input Vi and the intermediate terminal M, and the rectifier switch S2 is connected between the intermediate terminal M and the ground terminal. The inductance L is connected between the intermediate terminal M and the output terminal O of the power stage circuit 1. The load RL and the output capacitor CL are connected in parallel between the output terminal O of the power stage circuit 1 and the ground terminal.
The control circuit 2 is configured to adjust the time length of the first on-time Toff1 of the rectifier switch S2 according to the duty cycle D and the switching frequency Fsw of the switch-type converter in the super-audio mode, so as to maintain the output signal of the switch-type converter not to be detuned during the whole period (i.e. within the duty cycle). It should be understood that the switching frequency Fsw is a frequency at which the rectifier switch and the power switch are alternately turned on when the switching type converter operates in the inductor current continuous mode. In the super-audio mode, the operating frequency of the switch-mode converter is controlled above 20kHz to prevent the occurrence of audio noise. Preferably, the control circuit 2 is further configured to adjust the first on-time Toff1 of the rectifier switch S2 according to the feedback signal FB of the switch-type converter output signal to improve the response speed of the circuitry.
Preferably, the control circuit 2 adjusts the first on-time Toff1 of the rectifier switch S2 according to the duty ratio D and the switching frequency Fsw of the switch-type converter to make the error signal vary within a predetermined range, so that the switch-type converter of the present embodiment is suitable for wide-input wide-output and adjustable-switching-frequency applications. The compensation signal represents a difference between a feedback signal representing an output signal of the switching type converter and a reference signal representing a desired value of the output signal of the switching type converter.
The control circuit 2 controls the switch type converter to work in a superaudio mode when the switch type converter is in a light load or no-load mode; and controlling the switching converter to exit the ultrasonic frequency and controlling the stability of the output voltage when the switching converter is in the heavy-load mode.
The control circuit 2 is used for generating control signals TOP _ ON and BOT _ ON of the power switch S1 and the rectifier switch S2 to control the ON and off of the power switch S1 and the rectifier switch S2.
The control circuit 2 controls the rectifier switch S2 to be turned ON for the first ON-time Toff1 by the control signal BOT _ ON to maintain the output signal of the switch-type converter stable. After the rectifier switch S2 is turned ON for the first ON time Toff1, the control circuit 2 controls the power switch S1 to be turned ON for the third ON time Ton by the control signal TOP _ ON. After the power switch S1 is turned ON for the third ON-time Ton, the control circuit 2 controls the rectifier switch S2 to be turned ON for the second ON-time Toff2 by the control signal BOT _ ON to freewheel the current ON the inductor L. After the rectifier switch S2 is turned ON for the third ON-time, the control circuit 2 controls the power switch S1 and the rectifier switch S2 to remain off for a predetermined standby time Tstandby by the control signals BOT _ ON and TOP _ ON.
In summary, each cycle time of the switching converter in the super audio mode is:
T＝Toff1+Ton+Toff2+Tstandby＝Tsw+Tstandby＝1/Fsw+Tstandby
therefore, according to the setting range of the switching frequency Fsw of the switch-type converter, a reasonable standby time Tstandby is set, so that the working frequency of the switch-type converter in the light load or no-load mode is always larger than 20 kHz.
It is easy to understand that the power stage circuit is not limited to the BUCK-type topology, and a BOOST-type topology (BOOST), a BUCK-BOOST-type topology (BUCK-BOOST), an isolation-type topology, or the like can be adopted.
In summary, in the embodiment, the first on-time of the rectifier switch of the switch-type converter is controlled to be continuously adjustable along with the duty ratio and the switching frequency of the switch-type converter in the light-load or no-load mode, so that the compensation signal is changed in a small range, and the accuracy and the stability of the output signal of the switch-type converter are ensured while audio noise is avoided in the light-load or no-load mode, so that the switch-type converter is suitable for wide-input wide-output and application occasions with adjustable switching frequency.
Fig. 2 is a circuit diagram of a control circuit according to an embodiment of the present invention. As shown in fig. 2, the control circuit 2 includes a super audio control circuit 21 and a control loop 22. The control loop 22 includes a differential amplifier EA and a set signal generation circuit 221. The differential amplifier EA is used to generate a compensation signal VC based on the feedback signal FB and a reference signal REF that is representative of a desired value of the output voltage. The compensation signal VC is used to characterize the degree to which the output voltage deviates from a desired value. It is to be understood that the circuit configuration for generating the compensation signal VC is not limited to the differential amplifier, and may be replaced with a circuit configuration in which a combination of a comparator and an amplifier or the like can achieve the above-described effects.
The set signal generating circuit 221 is configured to generate a third set signal err to participate in generating the control signals for the power switch S1 and the rectifier switch S2. In one embodiment, the set signal generating circuit 221 may include a comparator and an adder. The adder is used for adding the compensation signal VC and the reference signal REF and outputting a added signal REF + VC. The comparator is configured to compare the feedback signal FB (or the slope-compensated feedback signal FB1) with the superimposed signal REF + VC to output a third set signal err. It is to be understood that the set signal generating circuit 221 is not limited to the above-described circuit configuration, and a circuit configuration capable of achieving the above-described operation may be used instead of the above-described circuit configuration.
The super audio control circuit 21 includes a delay circuit 211, a regulator circuit 212, and a logic circuit 213. Wherein the delay circuit 211 is configured to start timing when receiving the active Standby state signal Standby and output the first Set signal Set1 after timing the predetermined Standby time Tstandby.
The adjusting circuit 212 is configured to generate a second Set signal Set2 and a rectified switch indication signal BOT _ ON1 to control the first ON-time Toff1 according to the first Set signal Set1, the duty ratio D of the switching type converter, the switching frequency Fsw, and the compensation signal VC.
The logic circuit 213 is configured to generate the control signals TOP _ ON and BOT _ ON of the power switch S1 and the rectifier switch S2 to control the power switch S1 and the rectifier switch S2 to be turned ON and off according to the rectifier switch indication signal BOT _ ON1, the second Set signal Set2, the third Set signal err, and the zero-crossing signal Ineg, so as to adjust the time lengths of the first ON-time Toff1, the second ON-time Toff2, and the third ON-time Ton.
Fig. 3 is a waveform diagram illustrating the operation of a switching converter according to an embodiment of the present invention. As shown in fig. 3, the start of the cycle is the start of the standby state. At time t0, the rectifier switch S2 and the power switch S1 are both turned off, the Standby state signal Standby is equal to 1, the delay circuit 211 is controlled to start operating, and the first Set signal Set1 is output when the predetermined Standby time Tstandby is delayed. The time is t1, i.e. the predetermined standby time Tstandby is the time period from t0 to t 1.
At time t1, the first Set signal Set1 is equal to 1, and the regulating circuit 212 is controlled to output the commutating switch indication signal BOT _ ON1 is equal to 1. At this time, the zero-cross signal Ineg is pulled down to 0, the control logic circuit 213 outputs the control signal BOT _ ON of the rectifier switch S2 to 1, the rectifier switch S2 starts to be turned ON, and the inductor current starts to decrease from the predetermined current value.
At time t1, the adjusting circuit 212 is controlled to operate for a period of time (i.e., the first ON-time Toff1 of the rectifier switch S2) and then outputs the second Set signal Set2 equal to 1, so that the rectifier switch S2 indicates that the signal BOT _ ON1 is equal to 0, which is time t 2.
At time t2, the logic circuit 213 outputs the control signals TOP _ ON and BOT _ ON of the power switch S1 and the rectifier switch S2 under the control of the second Set signal Set2, where the power switch S1 is turned ON and the rectifier switch S2 is turned off. The first on-time Toff1 of the rectifier switch S2 is from t1 to t 2.
At time t2, the logic circuit 213 starts timing, and after timing the predetermined third ON-time Ton, the control signal TOP _ ON of the power switch S1 is controlled to be 0, and the power switch S1 is turned off, at this time t3, that is, the predetermined third ON-time of the power switch S1 is from time t2 to time t 3.
At time t3, the logic circuit 213 controls the control signal BOT _ ON of the rectifier switch S2 to 1 according to the zero-crossing signal Ineg, and the rectifier switch S2 is turned ON to freewheel the inductor current. When the inductor current is freewheeling to a predetermined current value, the zero-crossing signal Ineg is equal to 1, the logic circuit 213 controls the control signal BOT _ ON of the rectifier switch S2 to be equal to 0, and the rectifier switch S2 is turned off at time t4, that is, the second ON-time of the rectifier switch S2 is from time t3 to time t 4.
At time t4, the control signals TOP _ ON and BOT _ ON for the power switch S1 and the rectifier switch S2 are both 0, so the Standby state signal Standby is equal to 1 and a new cycle begins.
When the switch-type converter operates in idle load, the average current in the time points t1-t4 is zero, and the decreasing change rate of the inductor current is equal, so Toff1 is equal to Toff 2. As the load current increases, Toff1 decreases, Toff2 increases, and finally Toff1 decreases to 0, the system exits the super-audio mode and operates in the inductor current discontinuous mode or inductor current continuous mode, and the operating frequency must exceed the set value of the super-audio frequency (20kHz), so that the switching type converter operates in a full-load range without noise.
In summary, in the embodiment, the first on-time of the rectifier switch of the switch-type converter is controlled to be continuously adjustable along with the duty ratio and the switching frequency of the switch-type converter in the light-load or no-load mode, so that the compensation signal changes in a smaller range, the feedback signal is introduced to adjust the first on-time of the rectifier switch, the adjustment speed of the output signal is increased, the switch-type converter avoids audio noise in the light-load or no-load mode, and meanwhile, the accuracy and the stability of the output signal are ensured, so that the switch-type converter is suitable for wide-input wide-output and switching frequency adjustable application occasions.
Fig. 4 is a circuit diagram of a delay circuit according to an embodiment of the present invention. The delay circuit 211 is configured to generate the first Set signal Set 1. As shown in fig. 4, the delay circuit 211 includes an inverter 41 and a timing circuit 42. The timing circuit 42 includes a switch transistor N1, a capacitor C1, a current source IB1, and a comparator Cmp 1. The input end of the inverter 41 inputs the Standby state signal Standby, and the output end thereof is connected to the control end of the switching tube N1. The current source IB1 is connected between the power supply terminal and the intermediate terminal N, and outputs a predetermined current IB 1. The capacitor C1 and the switch tube N1 are connected in parallel between the middle end N and the grounding end. One input terminal of the comparator Cmp1 is connected to the intermediate terminal N, and receives the voltage VCAP1, and the other input terminal receives the predetermined voltage VREF 1.
When the Standby state signal Standby is 1 (i.e., when both the control signals TOP _ ON and BOT _ ON of the power switch S1 and the rectifier switch S2 are 0), the signal after passing through the inverter 41 is 0, the switching tube N1 is turned off, and the voltage of the capacitor C1 rises, i.e., the input voltage VCAP1 of the comparator Cmp1 starts rising. After the input voltage VCAP1 rises to be greater than the predetermined voltage VREF1, the delay circuit 21 outputs a first Set signal Set 1.
The preset voltage VREF1 is set according to the setting range of the switching frequency Fsw of the switch-type converter, and the length of the standby time Tstandby is set according to the sizes of the switch tube N1, the capacitor C1 and the current source IB1, so that the working frequency of the switch-type converter in a light load or no-load mode is always larger than 20 kHz.
In summary, the Standby time Tstandby (i.e. the time period t0-t1 in fig. 3) of the switching converter is the time period from the time when the Standby state signal Standby is set to 1 to the time when the comparator Cmp1 flips. That is, the time when the input voltage VCAP1 at one end of the comparator rises from 0 to the predetermined voltage VREF 1.
VCAP1 ═ VREF1, i.e.
Figure BDA0001613228030000101
The standby time Tstandby is:
Figure BDA0001613228030000102
it is easy to understand that the switch tube N1 in fig. 4 is an N-type tube, and in another embodiment, the inverter is eliminated and the switch tube is a P-type tube to achieve the above function. Meanwhile, it is easy to understand that other circuit configurations capable of achieving the above-described functions may be adopted instead of the delay circuit 21.
Fig. 5 is a circuit diagram of a regulating circuit of a comparative example. The regulating circuit is used for regulating the first conduction time of a rectifying switch in the power stage circuit and outputting a second Set signal Set 2. As shown in fig. 5, the adjusting circuit of the comparative example includes an RS flip-flop 51, an inverter 52, and a timing circuit 53. The timing circuit 53 includes a switch transistor N2, a capacitor C2, a controlled current source IB2_ t, and a comparator Cmp 2. The RS flip-flop 51 has a Set terminal to which the first Set signal Set1 is input, a reset terminal to which the second Set signal Set2 is input, and an output terminal to which the rectifier switch indication signal BOT _ ON1 is output. The input end of the inverter 52 inputs the rectified switch indication signal BOT _ ON1, and the output end thereof is connected to the control end of the switch tube N2. The current source IB2_ t is connected between the power supply terminal and the intermediate terminal a, and outputs currents IB2_ t, IB2_ t being gm VC _ t controlled by the compensation signal. The capacitor C2 and the switch tube N2 are connected in parallel between the intermediate terminal a and the ground terminal. One input terminal of the comparator Cmp2 is connected to the intermediate terminal a, and receives the voltage VCAP2, and the other input terminal receives the predetermined voltage VREF2, and outputs the second Set signal Set2 when the comparator Cmp2 is inverted.
When the first Set signal Set1 is at a high level (i.e., at the end of the standby time), the RS flip-flop 51 outputs a high-level rectifier switch indication signal BOT _ ON1, at which time the control signal BOT _ ON of the rectifier switch is 1, and the rectifier switch is turned ON. The second Set signal Set2 output by the regulating circuit controls the rectifier switch to be turned off through the control logic circuit, and the power switch is turned on. Therefore, the regulating circuit of the comparative example can regulate the first conduction time of the rectifier switch by compensating the change of the signal VC _ t, so that the output voltage of the switch-type converter is more stable.
In summary, the first on time Toff1_ t of the rectifier switch of the comparative example is the period from the setting of the first Set signal Set1 to the flipping of the comparator Cmp 2. That is, the time when the input voltage VCAP2 at one end of the comparator rises from 0 to the predetermined voltage VREF 2.
VCAP2 ═ VREF2, i.e.
Figure BDA0001613228030000111
The first on-time Toff1_ t of the rectifier switch is:
Figure BDA0001613228030000112
since the switch-type converter has a change amount of 0 in one period when no load occurs, and the slope of the inductor current drop is kept constant when no load occurs. Therefore, the first conduction time and the second conduction time of the rectifier switch are equal.
If the duty ratio of the switch-type converter is D, the switching frequency is Fsw. And the alternate on-off time of the rectifier switch and the power switch of the switching converter meets the following conditions:
Figure BDA0001613228030000113
since Toff1 is Toff2 when the switching converter is in no-load, the first on-time Toff1 of the rectifier switch is:
Figure BDA0001613228030000121
the first on-time Toff1 — t of the rectifier switch of the switching converter of the comparative example is:
Figure BDA0001613228030000122
the compensation signal VC _ t of the switching converter of the comparative example is:
Figure BDA0001613228030000123
wherein,
Figure BDA0001613228030000124
vi, Vo are the input voltage and the output voltage of the switching converter, respectively.
As can be seen from the above formula, the control method compensation signal VC _ t of the switching converter in the comparative example is inversely proportional to (1-D) and directly proportional to the switching frequency, and therefore, in the control method of the comparative example, when the input voltage and the output voltage (i.e., the duty ratio D changes) or the switching frequency changes, the compensation signal VC _ t changes greatly, which results in slow system response speed and unstable output voltage of the switching converter, and thus it is difficult to satisfy the application of the switching converter with adjustable switching frequency and wide input and output.
Fig. 6 is a circuit diagram of a regulating circuit of an embodiment of the present invention. As shown in fig. 6, the adjusting circuit 212 of the present embodiment includes a first RS flip-flop 61, a feedback adjustment signal generating circuit 62, a reference adjustment signal generating circuit 63, and a comparator Cmp 3. The Set end of the first RS flip-flop 61 inputs the first Set signal Set1, the reset end thereof inputs the second Set signal Set2, and the output end thereof outputs the rectifying switch indication signal BOT _ ON 1. The feedback adjustment signal generation circuit 62 includes a ramp signal generation circuit 621 and an adder 622. The ramp signal generating circuit 621 is configured to generate a ramp signal Vr related to the duty ratio D and the switching frequency Fsw when receiving the valid rectifying switch indication signal BOT _ ON1, and the adder 622 is configured to subtract the first reference threshold FB' and the ramp signal Vr to output the feedback adjustment signal FB _ adj. The reference adjustment signal generation circuit 63 includes an adder 631. The adder 631 is configured to subtract the compensation signal VC from the second reference threshold REF' and output a reference adjustment signal REF _ adj. The comparator Cmp3 has one input terminal receiving the feedback adjustment signal FB _ adj and the other input terminal receiving the reference adjustment signal REF _ adj, and outputs a second Set signal Set2 when the comparator Cmp3 flips.
Preferably, the first reference threshold FB 'and the second reference threshold REF' are equal bias voltage signals.
Preferably, the first reference threshold FB 'characterizes the feedback signal FB and the second reference threshold REF' characterizes the reference signal REF.
Fig. 7 is a specific circuit diagram of a regulating circuit of the embodiment of the present invention. In the embodiment shown in fig. 7, the first reference threshold FB 'and the second reference threshold REF' are the feedback signal FB and the reference signal REF, respectively. It should be understood that the first reference threshold FB 'and the second reference threshold REF' may be replaced by other bias voltage signals that turn on the transistors. As shown in fig. 7, the feedback adjustment signal generating circuit 62 includes a first current source Ib0, a first switch N3, a second switch P1, a capacitor C3, a first transistor M1, and a first controlled current source Ib 1. Wherein the first current source Ib0 is connected between the supply terminal and the first terminal E. The first transistor M1 is connected between the first terminal E and the ground terminal, and is controlled to be terminated with the feedback signal FB. The capacitor C3 is connected between the first input terminal of the comparator Cmp3 and ground. The first switch N3 is connected between the first terminal E and a first input terminal of the comparator Cmp3 and is controlled by the rectified switch indication signal BOT _ ON 1. The second switch P1 and the first controlled current source Ib1 are connected in series between the first input terminal of the comparator Cmp3 and the ground terminal, the second switch P1 is controlled by the rectified switch indication signal BOT _ ON1, and the first controlled current source Ib1 is controlled by the duty ratio D and the switching frequency Fsw.
The reference adjustment signal generation circuit 63 includes a second current source Ib3, a resistor R1, a second transistor M2, and a second controlled current source Ib 2. Wherein the second current source Ib3 is connected between the supply terminal and the second terminal F. The resistor R1 is connected between the second terminal F and the second input terminal of the comparator Cmp 3. The second transistor M2 is connected between the second terminal F and the ground terminal and controlled by the reference signal REF. The second controlled current source is connected between the second input terminal of the comparator Cmp3 and the ground terminal, and is controlled by the compensation signal VC.
Preferably, the adjusting circuit 2 adjusts the first on-time Toff1 of the rectifier switch S2 according to the duty ratio D and the switching frequency Fsw of the switch-type converter to make the error signal Vc vary within a predetermined range, so that the switch-type converter of the present embodiment is suitable for wide-input wide-output and adjustable-switching-frequency applications.
As shown in fig. 7, when the rectified switch indication signal BOT _ ON1 is equal to 0, the first switch N3 is turned ON, the second switch P1 is turned off, and the voltage across the capacitor C3 (i.e., the feedback adjustment signal) is:
FB_adj＝FB+Vsg1
here, Vsg1 is a gate-source voltage of the first transistor M1.
When the rectified switch indication signal BOT _ ON1 is equal to 1, the first switch N3 is turned off, the second switch P1 is turned ON, and the capacitor C3 discharges with the fixed current Ib1, where the feedback regulation signal FB _ adj is:
Figure BDA0001613228030000141
the feedback regulation signal FB _ adj decreases with the slope of Ib1/C3 until the comparator Cmp3 flips, the second Set signal Set2 is output, and the first on-time of the rectifier switch ends. That is, when the comparator Cmp3 flips, the feedback regulation signal FB _ adj is:
Figure BDA0001613228030000142
the first controlled current source Ib1 is controlled by the duty cycle D and the switching frequency Fsw of the switching type converter, Ib1 ═ K × Fsw × D. And the duty ratio D is Vo/Vi. Fsw is the switching frequency of the set switch-type converter in the inductor current continuous mode. Ib1 represents the product of two currents, K being a constant representing the conversion factor, proportional to the switching frequency Fsw and the duty cycle D, respectively, Vi, Vo being the input voltage and the output voltage of the switch-mode converter, respectively.
The reference adjustment signal REF _ adj is derived by circuitry of the reference adjustment signal generation circuit 63 as:
REF_adj＝REF+Vsg2-Ib2*R1
the second controlled current source Ib2 is controlled by the compensation signal VC, Ib2 ═ I0-gm*VC，I0For fixed bias, Vsg2 is the gate-source voltage of the second transistor M2.
When the comparator Cmp3 flips, the feedback regulation signal FB _ adj is equal to the reference regulation signal REF _ adj, i.e., the feedback regulation signal FB _ adj is equal to the reference regulation signal REF _ adj
Figure BDA0001613228030000143
Figure BDA0001613228030000144
Preferably, the first transistor M1 is the same size as the second transistor M2, then:
Figure BDA0001613228030000151
it can be seen from the above formula that the feedback signal FB can directly influence the first on-time Toff1 of the rectifier switch, effectively improving the transient response speed.
When the switching converter is in a steady state, that is, FB is equal to REF, the first on-time Toff1 of the rectifier switch is:
Figure BDA0001613228030000152
wherein,
Figure BDA0001613228030000153
and because the change quantity of the inductive current in one period is 0 when the circuit is in idle load, and the descending slope of the inductive current is kept unchanged. Therefore, the first on-time Toff1 of the rectifier switch is equal to the second on-time Toff 2.
Figure BDA0001613228030000154
The compensation signal VC of the embodiment of the present invention can be calculated from equations (1) and (2) as:
Figure BDA0001613228030000155
in the embodiment of the invention, the compensation signal VC is independent of the switching frequency Fsw and is in direct proportion to D (1-D), and when the switching frequency Fsw changes, the compensation signal VC changes within a preset range and the change range is small. Therefore, the switch-type converter of the present embodiment can be applied to an application where the switching frequency is adjustable.
The change curves of the compensation signal VC of the switching type converters of the comparative example and the embodiment of the present invention when the value D of the duty ratio D is changed from 5% to 95% at a constant switching frequency Fsw are shown in fig. 8. As can be seen from fig. 8, D (1-D) is introduced in the calculation of the first on-time Toff1 of the rectifier switch, so that the influence of the input voltage and the output voltage variation (i.e., the variation of the duty ratio D) on the compensation signal VC is compensated, the variation range of the compensation signal VC is reduced, and the accuracy and stability of the output voltage are ensured, thereby being applicable to wide-input and wide-output application occasions.
FIG. 9 is a graph of gain versus duty cycle of a compensation signal according to an embodiment of the present invention. In the embodiment of the present application, as can be obtained from equation (1), the Gain _ Toff1 from the compensation signal VC to the first on-time Toff1 of the rectifier switch is:
Figure BDA0001613228030000161
in the comparative example, the following examples were used,
Figure BDA0001613228030000162
wherein,
Figure BDA0001613228030000163
as can be seen from the above equation, in the control mode of the comparative example, the Gain _ Toff1_ t is in direct proportion to the square of (1-D) and in inverse proportion to the square of the switching frequency, and the Gain _ Toff1_ t has a wide variation range when the duty ratio is large or the switching frequency is small, i.e. when the switching frequency is changed or the input is wide, the first conduction time Toff1_ t is large, the variation range of the error signal VC _ t is required to be large, the loop response speed of the switching type converter is seriously influenced, and the output signal of the switching type converter is disordered. The embodiment of the invention effectively reduces the change rate of the Gain _ toff1, and when the input and output are wide or the switching frequency is changed, the error signal VC is changed in a smaller preset range, thereby improving the stability and the output precision of the system. As shown in fig. 9, when the switching frequency Fsw is constant and the duty ratio D is varied in the range of 5% to 95%, the gain variation of the present embodiment is much smaller than that of the comparative example.
In summary, in the switch-type converter of this embodiment, when the switching frequency is fixed, the compensation signal VC is within the range of 5% to 95% of the duty ratio, and the stable modulation of the output voltage can be realized only by changing the range with a small change.
Fig. 10 is a waveform diagram of the operation of the regulating circuit of the embodiment of the present invention. As shown in fig. 10, when FB > REF, the feedback adjustment signal FB _ adj will increase along with FB, and the compensation signal VC decreases, the current Ib2 of the second controlled current source increases, and the reference adjustment signal REF _ adj decreases, so that the first on-time of the rectifier switch is increased, and the output of the switching converter is rapidly adjusted back. If FB < REF, the feedback regulation signal FB _ adj will decrease with FB, while the compensation signal VC increases, the current Ib2 of the second controlled current source decreases, and the reference regulation signal REF _ adj increases, so that the first on-time of the rectifier switch is shortened, and the output of the switching converter rapidly increases. Therefore, the accuracy and stability of the output voltage are ensured.
Fig. 11 is a circuit diagram of a logic circuit of an embodiment of the present invention. As shown in fig. 11, the logic circuit 213 includes a timing circuit 111, a second RS flip-flop 112, and an or-not logic circuit 113. The nor logic circuit 113 includes a nor gate c, a nor gate d, and a nor gate e. The input signals of the nor gate c are the output signal TON _ ON' (i.e., the negation of the signal TON _ ON) of the second RS flip-flop 112 and the rectification switch indication signal BOT _ ON1, respectively. The input signals of the nor gate d are the output signal of the nor gate c and the zero-crossing signal Ineg respectively, and the output signal is the control signal BOT _ ON of the rectifier switch. The input signals of the nor gate e are the output signal of the nor gate d and the output signal TON _ ON of the second RS flip-flop 112, respectively, and the output signal is the Standby state signal Standby. The control method of the logic circuit of the present embodiment is described below with reference to fig. 3.
At time t1, the standby time of the switching converter ends, and the delay circuit 211 outputs the first Set signal Set. The first RS flip-flop in the regulating circuit 212 is controlled to generate the rectified switch indication signal BOT _ ON1 (i.e. BOT _ ON1 ═ 1), so the output signal of the nor gate c is 0. At this time, the zero-crossing signal Ineg is 0, and the output signal of the nor gate c is 0, so that the output signal of the nor gate d is BOT _ ON is 1, and the rectifier switch starts to be turned ON. The output signal of the nor gate e is the Standby state signal Standby 0.
At time t2, the comparator Cmp3 in the regulator circuit 212 is inverted, and the regulator circuit 212 outputs the second Set signal Set 2. The Q terminal of the second RS flip-flop is controlled to output the control signal TOP _ ON of the power switch to 1, and the power switch is turned ON. At this time, the first RS flip-flop in the regulating circuit 212 is controlled to be reset, the output rectifying switch indication signal BOT _ ON1 is equal to 0, and since the output signal TOP _ ON 'of the Q' end of the second RS flip-flop is equal to 0 and the output signal of the nor gate c is 1, the output signal BOT _ ON of the nor gate d is equal to 0 and the rectifying switch is turned off, so that the first ON time of the rectifying switch is the time period t1-t 2.
At time t2, the timing circuit 111 starts timing under the control of the control signal TOP _ ON of the power switch being 1, outputs the reset signal r after a predetermined third ON-time (i.e., outputs the reset signal r at time t 3), controls the output TOP _ ON of the second RS flip-flop Q terminal to be 0, and turns off the power switch, so that the third ON-time of the power switch is the time period t2-t 3.
At time t3, the output signal TOP _ ON 'of the second RS flip-flop Q' is 1, the output of the nor gate c is 0, and since the inductor current of the power stage circuit does not have a zero crossing and the zero crossing signal Ineg is 0, the output signal of the nor gate d is BOT _ ON1, and the rectifier switch starts to conduct. When detecting that the inductor current of the power stage circuit passes through zero (i.e., at time t 4), the zero-crossing signal Ineg is 1, the output signal of the nor gate d is BOT _ ON is 0, and at this time, the rectifier switch is turned off, and the second ON time (i.e., the time period t3-t 4) of the rectifier switch is ended. At this time, the output signal Standby of the nor gate e becomes 1, and the delay circuit 211 is controlled to operate, and a new cycle starts.
It should be understood that the logic circuit is not limited to the above-described circuit configuration, and other logic circuits capable of realizing the above-described control method can be substituted for the logic circuit 213.
In summary, in the embodiment, the first on-time of the rectifier switch of the switch-type converter is controlled to be continuously adjustable along with the duty ratio and the switching frequency of the switch-type converter in the light-load or no-load mode, so that the compensation signal changes in a smaller range, the feedback signal is introduced to adjust the first on-time of the rectifier switch, the adjustment speed of the output signal is increased, the switch-type converter avoids audio noise in the light-load or no-load mode, and meanwhile, the accuracy and the stability of the output signal are ensured, so that the switch-type converter is suitable for wide-input wide-output and switching frequency adjustable application occasions.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (20)

1. A switched mode converter comprising a power stage circuit and a super-audio control circuit, wherein the power stage circuit comprises a rectifier switch configured to have a first on-time to regulate an output signal of the switched mode converter;
the super-audio control circuit is configured to adjust the first conduction time according to the duty ratio and the switching frequency of the switch-type converter in a super-audio mode so as to maintain the output signal not to be detuned in the whole duty ratio range;
wherein the superaudio control circuit is configured to control the switch-mode converter in a light load or no load mode.
2. The switched mode converter of claim 1, wherein the superaudio control circuit adjusts the first on time in accordance with the duty cycle and the switching frequency such that a compensation signal varies within a predetermined range, wherein the compensation signal is indicative of a difference between a feedback signal and a reference signal;
the feedback signal is used for representing an output signal of the switch type converter, and the reference signal is used for representing a desired value of the output signal of the switch type converter.
3. The switch-mode converter of claim 1, wherein the super-audio control circuit is further configured to adjust the first on-time in accordance with a feedback signal to increase response speed.
4. The switched mode converter of claim 1, wherein the power stage circuit further comprises a power switch, and wherein the super-audio control circuit is configured to control the power switch to conduct for a third conduction time after the first conduction time ends.
5. The switch-mode converter according to claim 4, wherein the super-audio control circuit controls the third on-time to a predetermined value.
6. The switched mode converter of claim 4, wherein the megasonic control circuit is configured to control the rectifier switch to conduct for a second conduction time to freewheel inductor current after the third conduction time ends.
7. The switched mode converter of claim 6, wherein the super-audio control circuit is configured to control the power switch and the rectifier switch to remain off for a predetermined standby time after the inductor current freewheels to a predetermined value.
8. The switch-mode converter of claim 1, wherein the super-audio control circuit comprises:
a delay circuit configured to generate a first set signal;
a regulating circuit configured to generate a second set signal and a rectified switch indication signal to control the first on-time according to the first set signal, a duty cycle of the switching type converter, a switching frequency, and a compensation signal, the compensation signal characterizing a difference of a feedback signal and a reference signal; and
a logic circuit configured to generate control signals of the rectifier switch and the power switch according to the rectifier switch indication signal, the second set signal and a zero-crossing signal to control the on and off of the rectifier switch and the power switch;
wherein the feedback signal is used to characterize an output signal of the switch-type converter, and the reference signal is used to characterize a desired value of the output signal of the switch-type converter.
9. The switched mode converter of claim 8, wherein the logic circuit is further configured to generate a standby state signal based on control signals of the rectifier switch and the power switch.
10. The switch-mode converter of claim 9, wherein the delay circuit begins timing when a valid standby state signal is received, and the first set signal is generated after a predetermined standby time.
11. The switched mode converter according to claim 8, wherein said regulation circuit comprises:
the feedback adjusting signal generating circuit is controlled by the rectifying switch indicating signal and generates a feedback adjusting signal according to the duty ratio, the switching frequency and a first reference threshold value;
a reference adjustment signal generation circuit configured to generate a reference adjustment signal according to the compensation signal and a second reference threshold;
a comparator configured to compare the feedback adjustment signal and the reference adjustment signal to generate the second set signal.
12. The switched mode converter of claim 11, wherein the first reference threshold and the second reference threshold are equal bias voltage signals;
alternatively, the first reference threshold value characterizes the feedback signal and the second reference threshold value characterizes the reference signal.
13. The switched mode converter of claim 8, wherein the regulation circuit further comprises:
and the set end of the first RS trigger inputs the first set signal, the reset end of the first RS trigger inputs the second set signal, and the rectifier switch indicating signal is output.
14. The switched mode converter of claim 11, wherein the feedback regulation signal generation circuit comprises:
a first switch connected between a first terminal and a first input terminal of the comparator;
a second switch;
the first controlled current source is controlled by the duty ratio and the switching frequency, and the second switch is connected between the first input end of the comparator and the ground end in series;
the first capacitor is connected between the first input end of the comparator and a grounding end; and
a first transistor connected between the first terminal and a ground terminal;
the first switch and the second switch are controlled by the rectifier switch indication signal to be switched on or switched off;
the reference adjustment signal generation circuit includes:
a second transistor connected between the second terminal and a ground terminal;
the second controlled current source is controlled by the compensation signal and is connected between the second input end of the comparator and the grounding end; and
a resistor connected between the second input terminal of the comparator and the second terminal.
15. The switched mode converter of claim 8, wherein the logic circuit comprises:
a timing circuit configured to receive a control signal of the power switch to control the power switch to be turned on for a third on-time, and output a reset signal;
the second RS trigger has a setting end for inputting the second setting signal, a resetting end for inputting the resetting signal and an output end for outputting a control signal of the power switch;
a NOR logic circuit configured to generate a control signal of the rectifier switch according to the power switch indication signal, the zero-crossing signal, and a negation of a control signal of the power switch;
the nor logic circuit is further configured to generate a standby state signal according to control signals of the power switch and the rectifier switch.
16. A control circuit for a switching converter, comprising:
a control loop configured to output a third set signal for driving switching of a power switch and a rectifier switch of a switching type converter according to a feedback signal of a power stage circuit of the switching type converter; and
a super-audio frequency control circuit configured to adjust a first conduction time of the rectifier switch according to a duty ratio and a switching frequency of the switch type converter in a super-audio frequency mode so as to maintain an output signal of the switch type converter not to be detuned in an entire duty ratio range;
wherein the superaudio control circuit is configured to control the switch-mode converter in a light load or no load mode.
17. The control circuit of claim 16, wherein the super-audio control circuit is further configured to adjust the first on-time in accordance with the feedback signal to increase response speed.
18. The control circuit of claim 16, wherein the super-audio control circuit is further configured to control the power switch to conduct for a third conduction time after the first conduction time ends.
19. The control circuit of claim 18, wherein the ultrasonic frequency control circuit is configured to control the rectifier switch to conduct for a second conduction time to freewheel inductor current after the third conduction time ends.
20. The control circuit of claim 19, wherein the super-audio control circuit is configured to control the power switch and the rectifier switch to remain off for a predetermined standby time after the inductor current freewheels to a predetermined value.
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