TW201539744A - 一種在基底上製造半導體裝置之鰭結構的方法 - Google Patents

一種在基底上製造半導體裝置之鰭結構的方法 Download PDF

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TW201539744A
TW201539744A TW104105777A TW104105777A TW201539744A TW 201539744 A TW201539744 A TW 201539744A TW 104105777 A TW104105777 A TW 104105777A TW 104105777 A TW104105777 A TW 104105777A TW 201539744 A TW201539744 A TW 201539744A
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layer
hard mask
fin
patterned
fin region
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TWI676292B (zh
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Boon Teik Chan
Safak Sayan
Min-Soo Kim
Doni Parnell
Roel Gronheid
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Imec Vzw
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Abstract

本發明揭示一種在一半導體基底之一區域中使用定向自組裝(DSA)微影圖案化來製造鰭結構之方法，其包括：提供一半導體基底，該半導體基底之一側上覆蓋有一淺溝渠隔離(STI)層堆疊；在該基底之該側上界定一鰭區域，其中將藉由執行不包括DSA之一微影圖案化步驟來製造該等鰭結構；及其後，根據一預定鰭圖案，使用DSA微影圖案化來製造該半導體基底上之該鰭區域內之該等鰭結構；且製造相關聯之半導體結構。

Description

一種在基底上製造半導體裝置之鰭結構的方法
本發明係關於半導體處理之領域。更具體言之，本發明係關於一種在一基底上製造一半導體裝置之鰭結構的方法。
在先前技術中，不同技術係用於界定半導體裝置(例如，鰭式場效電晶體類型之半導體裝置)之鰭結構。
鰭式場效電晶體裝置之鰭結構(亦稱作通道)之尺寸及間距及間距之尺寸遵循ITRS藍圖且變得愈來愈小。現今，可藉由先進半導體處理技術來達成10奈米之一鰭間距(技術節點10)。
此等技術之一者係稱為自對準雙重圖案化(SADP)技術。此技術包括形成虛設核心結構，該等虛設核心結構之側壁由一間隔結構預見，藉此導致窄間隔結構包圍該等虛設核心結構。接著，移除該等虛設核心結構且接著藉由移除該間隔結構之端部分來使該等間隔結構斷開且經由一微影步驟(一所謂的「CUT微影步驟」)來圖案化該等間隔結構。接著，使用剩餘極細圖案化間隔結構作為用於蝕刻一下伏基底之一遮罩以藉此在一鰭式場效電晶體裝置之基底中界定由窄溝渠分離之鰭結構。
熟習技術者應瞭解，對於與小於10奈米(例如7奈米(技術節點7，N7))之鰭間距相關聯之仍然較細間距，EUV微影不用於界定鰭結構， 則SADP技術似乎已達到極限。
EUV微影技術已被視為一可行解決方案，但歸因於源功率及EUV遮罩基礎结构限制，其用於大量生產之插入時序現仍不確定。因此，將SADP用於小於N10之技術節點係不利的。
替代地，一種所謂的定向自組裝(DSA)新技術可用於形成小於可藉由習知微影技術來達成之鰭結構的鰭結構。
DSA係指示為用於超過10奈米節點之CMOS積體電路圖案化之一可能方法。熟習技術者應瞭解，將此技術應用於CMOS中仍存在各種缺點，下文將描述該等缺點之部分。
因此，需要替代技術來製造半導體裝置(尤其是具有小於10奈米(技術節點10，N10)之鰭間距之裝置)之鰭結構。
本發明之一目的係提供一種在一半導體基底之一區域中使用DSA微影圖案化來製造鰭結構之方法，其解決存在於當前最先進技術中之問題。
一進一步目的係提供與上述方法相關聯之半導體結構。
根據展示獨立技術方案之技術特性之本發明之半導體結構及方法來達成此目的。
在本發明之一第一態樣中，揭示一種在一半導體基底之一區域中使用DSA微影圖案化來製造鰭結構之方法，該方法包括：- 提供一半導體基底，該半導體基底之一側上覆蓋有一淺溝渠隔離層堆疊；- 在該基底之該側上界定一鰭區域，其中將藉由執行不包括DSA之一微影圖案化步驟來製造該等鰭結構；及- 其後，根據一預定鰭圖案，使用DSA微影圖案化來製造該半導體基底上之該鰭區域內之該等鰭結構。
該半導體基底可為(例如)一矽基底、SOI及III/V族及任何IV族基底(例如一鍺基底)。
定向自組裝微影圖案化係一種最先進微影技術，其中經由一定向自組裝程序來製造一遮罩層。可藉由使用一DSA層堆疊來實施DSA微影圖案化。一DSA層堆疊包括以下各者或由以下各者組成：一預遮罩圖案(例如交聯聚苯乙烯(X-PS)圖案，例如條帶結構)、一平坦化中性刷塗層(NUL)及一自組織嵌段共聚物(BCP)層(例如PS-b-PMMA之一雙嵌段共聚物)。將預遮罩層(例如x-PS層)沈積於表面上且藉由使用一光阻劑及一相關聯之微影步驟來圖案化該預遮罩層。據此，圖案化光阻層。接著，修整經圖案化之光阻層之結構。接著，使用經修整之光阻結構來圖案化預遮罩層以導致預遮罩圖案。中性層之旋塗填充預遮罩圖案之間之空間以導致一平坦化層，接著進行一烘乾及沖洗步驟。接著，根據預遮罩圖案來對BCP層進行旋塗及退火以導致聚合物成分之自組織，藉此(例如)BCP之PS組分與x-PS預遮罩圖案對準。在藉由選擇性蝕刻來移除聚合物成分之一者(例如PMMA組分)之後，準備將圖案轉印至(若干)下伏層中。
熟習技術者已知一淺溝渠隔離層堆疊。其可(例如)包括氮化矽及襯墊氧化物SiO2。
不同於DSA之一微影圖案化步驟可(例如)包括193奈米或193奈米浸漬、EUV單圖案化、SADP(自對準三重圖案化)、SAQP(自對準四重圖案化)、SATP(自對準三重圖案化)等等。
應瞭解，可直接或間接界定一鰭區域。直接界定對應於一第一類型之實施例，且包含在實際蝕刻鰭結構之前之一階段蝕刻半導體基底。由一第二類型之實施例體現之該鰭區域之一間接界定包含在覆於半導體基底上之一硬遮罩層中界定該鰭區域。
根據該第一類型之實施例，界定一鰭區域包括： - 在該淺溝渠隔離層堆疊上提供一圖案化光阻層；- 電漿蝕刻該STI層堆疊及該基底以藉此由自該半導體基底突出之橫向側壁實體地界定該半導體基底上之該鰭區域，該鰭區域定位於該圖案化光阻層下方。
根據較佳實施例，提供一圖案化光阻層包括：- 在該淺溝渠隔離層堆疊上提供一光阻層；- 圖案化該光阻層。
根據較佳實施例，該方法包括：- 自該STI層堆疊選擇性地移除該圖案化光阻層；- 提供至少嵌入該等橫向側壁之一填充層；- 對該填充層執行一表面平整步驟以移除該填充層之過量材料，藉此曝露該STI層堆疊且達成一平整表面；- 在該平整表面上提供一硬遮罩層；- 在該硬遮罩層上提供一DSA層堆疊；- 將該DSA層堆疊圖案化成一條帶圖案；- 蝕刻該條帶圖案之條帶之間之該硬遮罩層、該STI層堆疊及該基底，藉此界定該等鰭結構，該等鰭結構係由溝渠分離；- 用一第二填充層填充該等溝渠；- 對該第二填充層執行一表面平整步驟以移除該第二填充層之過量材料，藉此曝露該STI層堆疊且達成一平整表面。
根據較佳實施例，圖案化該光阻層進一步包括圖案化對應於一對準特徵之該光阻層，且其中電漿蝕刻該基底包括在該基底上製造對準特徵。
根據一第二類型之較佳實施例，該方法包括：- 在該平坦化填充層上提供一DSA層堆疊，且將其圖案化成一條帶圖案； - 使用DSA微影圖案化來將該平坦化填充層及該硬遮罩層圖案化成一條帶圖案；- 蝕刻該圖案化硬遮罩層之該條帶圖案之條帶之間之該STI層堆疊及該基底，藉此界定該等鰭結構，該等鰭結構係由溝渠分離；- 用一第二填充層填充該等溝渠；- 對該第二填充層執行一表面平整步驟以移除該第二填充層之過量材料，藉此曝露該STI層堆疊且達成一平整表面。
根據較佳實施例，提供該圖案化硬遮罩層進一步包括：根據對應於一對準特徵之一圖案來圖案化該硬遮罩層。
根據較佳實施例，該硬遮罩層包括不同子層，且圖案化該等子層包括：僅移除一或多個子層，且不移除該等子層之最下層。
根據較佳實施例，該硬遮罩層自上而下包括一SiOC子層、一高級圖案化膜(APF)子層、氮化矽(例如Si3N4)子層及一SiO2子層之一層堆疊，且圖案化該硬遮罩層包括：僅移除該鰭區域中之該SiOC子層及該APF子層，同時亦移除該鰭區域外之該氮化矽層。接著，該氮化矽子層及該SiO2子層保留於該鰭區域中。接著，僅該SiO2子層保留於該鰭區域外。
根據較佳實施例，該硬遮罩層自上而下包括一SiOC子層、一APF子層、氮化矽子層及一SiO2子層之一層堆疊，且圖案化該硬遮罩層包括：- 移除該鰭區域外之該SiOC子層及該APF子層；其後- 移除該鰭區域中之該SiOC子層，且移除該鰭區域外之該氮化矽子層；其後- 移除該鰭區域中之該APF子層。
根據該第一類型及該第二類型之實施例之方法經較佳地執行/可經執行以製造具有小於10奈米之一間距之一組鰭結構。
在本發明之一第二態樣中，揭示一種半導體結構，其包括：- 一半導體基底，其包括在其一側上之一淺溝渠隔離層堆疊；- 一鰭區域，其位於該半導體基底上，該鰭區域自該半導體基底突出，包括該淺溝渠隔離層堆疊之一部分，且包括橫向側壁；- 一填充層，其至少嵌入該鰭區域之該等橫向側壁，該填充區域及該鰭區域鄰接一共同平坦表面，例如一前表面；- 一圖案化硬遮罩層，其位於該共同平坦表面之頂部上，至少在該鰭區域中延伸，且包括一條帶圖案。
根據較佳實施例，該半導體結構進一步包括該鰭區域中之溝渠，藉此界定該半導體基底上之鰭結構，該等溝渠對應於該條帶圖案。
在本發明之一第三態樣中，揭示一種半導體結構，其包括：- 一半導體基底，其包括在其一側上之一淺溝渠隔離層堆疊；- 一圖案化硬遮罩層，其位於該淺溝渠隔離層堆疊上且自該淺溝渠隔離層堆疊突出，該圖案化硬遮罩層對應於一鰭區域；- 一填充層，其鄰接一平坦前表面且嵌入該圖案化遮罩層，根據該鰭區域中之一條帶圖案來進一步圖案化該填充層。
根據較佳實施例，圖案化硬遮罩層在該鰭區域中自上而下包括氮化矽子層及一SiO2子層之一層堆疊，且在該鰭區域外僅包括一SiO2子層。
熟習技術者將認知，本發明之上述態樣之一者所揭示之特徵及優點據此亦隱含地揭示經適當修改之其他態樣。
1‧‧‧圖案化光阻層
2‧‧‧淺溝渠隔離(STI)層堆疊
3‧‧‧填充層
4‧‧‧定向自組裝(DSA)層堆疊
5‧‧‧硬遮罩層
6‧‧‧第二填充層
7‧‧‧半導體基底
41‧‧‧交聯聚苯乙烯(x-PS)層
41'‧‧‧交聯聚苯乙烯(x-PS)引導條帶/交聯聚苯乙烯(x-PS)引導結構/引導條帶圖案
42‧‧‧中性層(NUL)
42'‧‧‧中性層(NUL)結構
43‧‧‧聚苯乙烯(PS)圖案/聚苯乙烯(PS)組分/第一組分
44‧‧‧聚甲基丙烯酸甲酯(PMMA)組分/第二組分
51‧‧‧SiOC子層/上層
51'‧‧‧SiOC層
52‧‧‧高級圖案化膜(APF)子層/高級圖案化膜(APF)層
52'‧‧‧高級圖案化膜(APF)層/高級圖案化膜(APF)膜
53‧‧‧氮化矽子層/氮化矽層
53'‧‧‧氮化矽台面結構/氮化矽層/氮化矽圖案
54‧‧‧SiO2子層/SiO2層
54'‧‧‧SiO2圖案/下硬遮罩層
61‧‧‧旋塗玻璃(SoG)層
61'‧‧‧圖案化旋塗玻璃(SoG)層/旋塗玻璃(SoG)圖案
62‧‧‧旋塗碳(SoC)層
62'‧‧‧旋塗碳(SoC)圖案
f1‧‧‧鰭結構
f2‧‧‧鰭結構
f3‧‧‧鰭結構
f4‧‧‧鰭結構
t1‧‧‧溝渠
t2‧‧‧溝渠
t3‧‧‧溝渠
t4‧‧‧溝渠
t5‧‧‧溝渠
將經由以下描述及附圖來進一步闡述本發明。
圖1(a)至圖1(j)繪示根據第一類型之本發明之第一態樣之一方法之一程序流程。
圖2(a)至圖2(m)繪示根據第二類型之本發明之第一態樣之一方法之一程序流程。
圖3(a)至圖3(s)繪示根據第二類型之本發明之第一態樣之一方法之一替代程序流程。
類似特徵由類似參考元件符號指示。根據所繪示之程序流程期間之層N之不同狀態，用於層N之參考數字N可指示為「N」、「N'」及「N"」等等。例如，經圖案化之一層N可由「N'」指示；經圖案化之一層「N'」可由「N"」指示；等等。
對於小於10奈米之鰭間距(其中DSA可用於形成鰭結構)，切割微影提出不同挑戰。由於難以在DSA形成之後對準零標記，所以在一DSA圖案化步驟之後執行切割微影步驟會成問題。對準對小於N10之技術節點而言尤其關鍵。此外，DSA之後之一切割微影可導致圖案化鰭之線邊緣粗糙度(LER)/線寬粗糙度(LWR)增大，此危害具有由DSA技術提供之低LWR/LER值之優點。
根據圖1(a)及圖1(b)中所繪示之一第一類型之較佳實施例，界定一鰭區域包括：- 在淺溝渠隔離層堆疊(2)上提供一圖案化光阻層(1)；- 電漿蝕刻STI層堆疊(2)及基底(7)以藉此由自半導體基底突出之橫向側壁實體地界定半導體基底上之鰭區域，該鰭區域定位於圖案化光阻層(1)下方。
光阻層(1)可為(例如)用於X-PS引導條帶圖案化之NTD(負性顯影)光阻劑(M19)，且可(例如)由PTD(正性顯影)光阻劑(5484)及85奈米BARC(底部抗反射塗層)提供以保持切割結構。
根據較佳實施例，提供一圖案化光阻層包括：- 在淺溝渠隔離層堆疊上提供一光阻層； - 圖案化該光阻層。
根據較佳實施例，方法進一步包括：- 自STI層堆疊(2)選擇性地移除圖案化光阻層(1)(圖1(c))；- 提供至少嵌入橫向側壁之一填充層(圖1(c))；- 對該填充層執行一表面平整步驟(例如一CMP(化學機械拋光)步驟)以移除該填充層之過量材料，藉此曝露STI層堆疊(2)且達成一平整表面(圖1(d))。
例如，方法可進一步包括：- 在該平整表面上提供一硬遮罩層(5)(圖1(e))；- 在該硬遮罩層上提供一DSA層堆疊(4)(圖1(e))；- 將該DSA層堆疊圖案化成一條帶圖案(例如將相對於圖3(f)至圖3(j)來更詳細地解釋)；- 在一或多個蝕刻步驟中，(例如)各基於不同蝕刻化學反應來蝕刻該條帶圖案之條帶之間之硬遮罩層(5)(圖1(g))、STI層堆疊(2)及基底(7)，藉此界定鰭結構(f1、f2、f3、f4)，該等鰭結構係由溝渠(t1、t2、t3、t4、t5)分離(圖1(h))；- 較佳地，在已移除該硬遮罩之剩餘部分(例如該硬遮罩之剩餘條帶圖案)之後，用一第二填充層(6)填充該等溝渠(圖1(i))；- (例如)經由CMP來對第二填充層(6)執行一表面平整步驟以移除該第二填充層之過量材料，藉此曝露該STI層堆疊且達成一平整表面(圖1(j))。
較佳地，在平整表面上提供一硬遮罩層包括：提供一硬遮罩層堆疊。因此，該硬遮罩層可包括子層。較佳地，該硬遮罩層堆疊可為包括氮化矽/a-Si/SiOC/APF之一分層結構之一堆疊。替代地，該堆疊可為如SoC/SoG或AlN/SiON或SiON/APF或SiO2/APF或SiOC/APF之一分層結構。
蝕刻硬遮罩層可本身包括(例如)基於不同蝕刻化學反應之一或多個蝕刻步驟。
就一化學磊晶DSA程序而言，一DSA層堆疊可包括(例如)嵌段共聚物(例如PS-b-PMMA)材料及中性刷塗層(例如末端為羥基之聚(苯乙烯-隨機-甲基丙烯酸甲酯)(P(S-r-MMA)-OH))及使用X-PS(交聯聚苯乙烯)之引導條帶。
一條帶圖案係包括複數個條帶(例如3個、4個、5個或6個條帶)之一圖案。BCP自組裝倍增可用於產生該條帶圖案。較佳地，BCP(聚苯乙烯)組分形成具有尺寸且具有一間距之條帶，該間距對應於預定鰭尺寸。較佳地，該等條帶實質上平行或平行。較佳地，BCP自組裝片層較佳地用於線性/空間應用。
填充層及第二填充層兩者或各者可包括一介電材料或由一介電材料組成。較佳地，該介電材料包括SiO2，例如，熱氧化物或CVD或PECVD氧化物、低溫氧化物或旋塗玻璃。
根據較佳實施例，圖案化光阻層進一步包括圖案化對應於一對準特徵之光阻層，且其中電漿蝕刻基底包括在基底上製造對準特徵。
熟習技術者已知一對準特徵。用於不同微影步驟之圖案應彼此對準。通常，對準特徵包含於被轉印至基底之第一圖案中。此等對準特徵係用作為參考以有助於將隨後圖案定位至第一圖案。一對準特徵之形狀可包括(例如)一交叉形特徵(當自上方觀看時)，且用於使隨後半導體處理步驟彼此對準。
例如，經由圖2(a)至圖2(m)及圖3(a)至圖3(s)來繪示一第二類型之較佳實施例。
根據一第二類型之一較佳實施例，例如圖2(a)中所繪示，界定鰭區域包括：- 在淺溝渠隔離層堆疊上提供一圖案化硬遮罩層(5)，該圖案化 硬遮罩層之一圖案對應於該鰭區域；- 將該硬遮罩層嵌入於一平坦化填充層(6)中(圖2(b))。
硬遮罩層(5)可(例如)包括SiO2/APF(高級圖案化膜，例如一非晶碳層)、SiOC/APF、SiON(CVD)/APF、SiON(PVD)/AlN、SoG/SoC等等(例如呈一分層結構之形式)。較佳地，硬遮罩層(5)包括氮化矽/a-Si/APF，較佳地呈一分層結構。
圖案化硬遮罩層可包括使用一光阻劑/BARC(1)。
根據本發明之較佳實施例，圖案化硬遮罩層可包括完全或部分地移除硬遮罩。例如，可在硬遮罩之一第一區域中將硬遮罩層之厚度減小至零，使得下伏STI堆疊變成曝露於該區域中。亦可僅在硬遮罩之一(可能額外)區域中減小硬遮罩之厚度，使得硬遮罩層中之垂直側壁界定鰭區域。若硬遮罩包括不同子層，則可藉由僅移除一或多個子層且不移除該等子層之最下層來達成該等子層。
平坦化填充層(6)可為(例如)SoG及/或SoC(旋塗玻璃及/或旋塗碳)或光阻劑/BARC(底部抗反射塗層)。
較佳地，嵌入圖案化硬遮罩層之步驟包括：由平坦化填充層完全覆蓋硬遮罩層。
根據較佳實施例，方法進一步包括：- 在平坦化填充層上提供一DSA層堆疊(4)，且將其圖案化成一條帶圖案(圖2(f)；例如將相對於圖3(f)至圖3(j)來更詳細地解釋)；- 使用DSA微影圖案化來將平坦化填充層(6)(圖2(g))及硬遮罩層(5)(圖2(h))圖案化成一條帶圖案(例如，選擇性地蝕刻穿過平坦化填充層且停止於硬遮罩上，接著選擇性地蝕刻穿過硬遮罩(圖2(i))且停止於STI層堆疊(2)上；據此，蝕刻穿過硬遮罩之步驟可包括適合於各自子層之不同隨後選擇性蝕刻步驟)；- 蝕刻圖案化硬遮罩層(5)之條帶圖案之條帶之間之STI層堆疊 (2)(圖2(j))及基底(7)(圖2(k))，藉此界定鰭結構，該等鰭結構係由溝渠分離；- 較佳地，在已移除硬遮罩之剩餘部分(例如硬遮罩之剩餘條帶圖案)之後，用一第二填充層(3)填充該等溝渠(圖2(l))；- 對該第二填充層執行一表面平整步驟(例如一CMP步驟)以移除該第二填充層之過量材料，藉此曝露該STI層堆疊且達成一平整表面(圖2(m))。
提供一DSA層堆疊且圖案化該DSA層堆疊之步驟類似於針對第一類型之實施例所描述之步驟。
第二填充層可為(例如)SiO2。
根據較佳實施例，提供圖案化硬遮罩層進一步包括：根據對應於一對準特徵之一圖案來圖案化硬遮罩層。
根據一第二類型之另一較佳實施例，例如圖3(a)中所繪示，界定鰭區域包括在淺溝渠隔離層堆疊上提供一圖案化硬遮罩層(5)，該圖案化硬遮罩層之一圖案對應於該鰭區域；其中該硬遮罩包括不同子層。
硬遮罩層5包括一層堆疊，其係一SiOC子層51(15奈米)、一APF子層52(50奈米)、氮化矽(Si3N4)子層53(15奈米)及一SiO2子層54(15奈米)之一自上而下層堆疊。
在不同步驟中圖案化硬遮罩層。首先，例如，在硬遮罩5之上層51之頂部上提供一組合BARC及光阻層1。圖案化該光阻層以界定對應於鰭區域之一區域(圖3(a))。選擇性地移除該鰭區域外之區域中之BARC層。接著，選擇性地移除該鰭區域外之區域中之SiOC層(圖3(b))。接著，選擇性地移除該鰭區域外之區域中之APF層52。移除該鰭區域中之組合光阻層及BARC 1(圖3(b))。接著，移除該鰭區域中之SiOC層51'，且移除該鰭區域外之氮化矽層53(圖3(c))。
接著，選擇性地移除鰭區域外之區域中之氮化矽層。接著，選擇性地移除鰭區域中之APF層52'。結果係SiO2子層54之頂部上之氮化矽台面結構53'以形成圖案化硬遮罩層5(圖3(d))。
表1中提供可(例如)用於上述程序步驟之蝕刻程序參數(壓力、電漿功率、偏壓電壓、夾盤溫度、氣流速率、蝕刻時間)。
SiOC蝕刻係基於一基於規則CF4之程序。
APF蝕刻步驟係一基於HBr/O2/N2之程序以最佳化筆直APF輪廓，且N2用於改良蝕刻期間之側壁鈍化。
第一氮化矽蝕刻ME1係基於C4F8以比APF膜52'下方之氮化矽還快地蝕刻APF層52'之頂部上之剩餘SiOC層51'。因此，移除SiOC層51'，同時僅使一小凹槽進入氮化矽53。
第二氮化矽蝕刻ME2係基於蝕刻剩餘氮化矽之CF4，但對氮化矽下方之SiO2不具有一良好選擇性。
因此，執行一第三氮化矽蝕刻步驟(氮化矽OE)，其係基於 CH3F/O2且對SiO2具有一高選擇性，且將確保蝕刻整個氮化矽層。
現在氮化矽層53及SiO2層54上施加一平坦化填充層6，平坦化填充層6包括完全覆蓋硬遮罩層之一旋塗碳(SoC)層62(40奈米厚)及一旋塗玻璃(SoG)層61(15奈米厚)(圖3(e))。在平坦化填充層6上提供一交聯聚苯乙烯(x-PS)層41(x-PS厚度約為7奈米)。隨後，將交聯聚苯乙烯層41圖案化成引導條帶圖案41'。因此，一組合光阻層/BARC(底部抗反射塗層)1施加於x-PS層41上且經圖案化以形成一光阻層/BARC結構1(圖3(f))。修整光阻層/BARC結構1(大小減小)且將其轉印至x-PS層41中(圖3(g))。後一程序可發生於一單個步驟中，且可應用於兩個獨立步驟中。圖中已展示：執行兩個獨立步驟係有利的，此係因為(例如)其容許製造具有最小英尺長度(footage)之接近垂直輪廓，對x-PS無損害，可易於剝離PR，使用一易處置之氣體，且達成較小x-PS臨界尺寸(CD)。例如，可使用表2中所繪示之參數來執行兩個蝕刻步驟。
第一蝕刻係用於修整PR，此可使用一各向同性蝕刻來完成。此執行於高壓及O2/N2之高流量處。
第二蝕刻係依低壓及低氣體流速蝕刻X-PS層。在圖案化x-PS層41之後，執行一各向異性蝕刻以切割可存在於x-PS結構41'之底部處之X-PS底腳。
現施加嵌入x-PS引導條帶41'之一中性層(NUL)42。例如，可施加嵌入引導條帶41'之一刷塗層。該刷塗層之下部分經接枝且(例如)藉由沖洗來移除非接枝部分(其係過量的)。NUL層42及接枝程序可經預定使得接枝部分之高度實質上等於引導結構41'之高度(圖3(h))。
在X-PS 41'/NUL層(引導層)42上提供一BCP(嵌段共聚物；PS-PMMA：聚苯乙烯-聚甲基丙烯酸甲酯)層。施加一適合退火步驟以容許基於定向自組裝(DSA)藉由使一第一組分43及一第二組分44之線結構交替來形成之一週期性線圖案中之BCP層之相分離。此導致PMMA 44及PS 43之一交替條帶圖案(圖3(i))。相對於PS組分43來選擇性地移除PMMA組分44(圖3(j))。
現將PS圖案43轉印至下伏NUL層42中(與X-PS引導結構41'一起形成引導層)以形成NUL層結構42'。據此，亦可蝕刻/移除x-PS結構41'之可能底腳。
將PS圖案43轉印至SoG層61中(圖3(k))以導致一圖案化SoG層61'。
移除剩餘PS圖案43以及x-PS層41'/NUL 42'。接著，將剩餘SoG圖案61'轉印至SoC層62中以停止於鰭區域內之氮化矽層53'及鰭區域外之SiO2層54處(圖3(l))。
表3中提供可用於上述蝕刻程序步驟之程序參數之一概述。
PMMA蝕刻係基於O2，其中相對於PS來選擇性地蝕刻PMMA。通常，達成7之一選擇率。
NUL蝕刻係用於在BCP組裝之前蝕刻中性層及在XPS圖案化期間產生之一些XPS底腳。
氮化矽蝕刻係基於CF4/CHF3之對PS具選擇性之一蝕刻化學反應。
SoG蝕刻係基於CF4/CHF3。
SoC蝕刻係基於H2/H3。
選擇性地移除SoG圖案61'。接著，亦將SoC圖案62'轉印至氮化矽層53中(圖3(m))，且接著選擇性地移除SoC圖案62'(圖3(n))。現產生僅存在於鰭區域中之氮化矽圖案53'。
接著，將氮化矽圖案53'轉印至SiO2層54中(圖3(o))。隨後，選擇性地移除氮化矽層53'以留下一SiO2圖案54'，接著，將SiO2圖案54'轉印至STI層堆疊2中(例如一30奈米氮化矽/3奈米襯墊SiO2)(圖3(p))。選擇性地移除下硬遮罩層54'、SiO2層。接著，將圖案化STI層堆疊2'進一步轉印至下伏矽基底7中(圖3(q))。形成由基底中之溝渠t1、t2、t3分離之鰭結構f1、f2、f3、f4。
用一第二填充層3填充溝渠。對第二填充層3(例如SiO2)執行一表面平整步驟(例如一CMP步驟)以移除第二填充層之過量材料，藉此曝露STI層堆疊且達成一平整表面(圖3(s))。
相對於圖3(a)至圖3(s)所繪示之程序之一優點在於：硬遮罩蝕刻 輪廓SiOC/APF可經較佳地控制使得可達成(例如)一較小錐度圖案。
應瞭解，執行根據本發明之實施例之用於製造具有小於10奈米之一間距之一組鰭結構之一方法遠比執行最先進技術方法有利。
2‧‧‧淺溝渠隔離(STI)層堆疊
5‧‧‧硬遮罩層
6‧‧‧第二填充層
7‧‧‧半導體基底
53'‧‧‧氮化矽台面結構/氮化矽層/氮化矽圖案
54‧‧‧SiO2子層/SiO2層
61'‧‧‧圖案化旋塗玻璃(SoG)層/旋塗玻璃(SoG)圖案
62'‧‧‧旋塗碳(SoC)圖案

Claims (16)

  1. 一種用於在一半導體基底之一區域中使用定向自組裝(DSA)微影圖案化來製造鰭結構之方法，其包括：提供一半導體基底(7)，該半導體基底(7)之一側上覆蓋有一淺溝渠隔離(STI)層堆疊(2)；在該基底之該側上界定一鰭區域，其中將藉由執行不包括DSA之一微影圖案化步驟來製造該等鰭結構(f1，f2，f3，f4)；及其後，根據一預定鰭圖案，使用DSA微影圖案化來製造該半導體基底(7)上之該鰭區域內之該等鰭結構(f1，f2，f3，f4)。
  2. 如請求項1之方法，其中界定該鰭區域包括：在該淺溝渠隔離層堆疊(2)上提供一圖案化硬遮罩層(5)，該圖案化硬遮罩層(5)之一圖案對應於該鰭區域；將該硬遮罩層(5)嵌入於一平坦化填充層(6)中。
  3. 如請求項2之方法，其進一步包括：在該平坦化填充層(6)上提供一DSA層堆疊(4)，且將其圖案化成一條帶圖案；使用DSA微影圖案化來將該平坦化填充層(6)及該硬遮罩層(5)圖案化成一條帶圖案；蝕刻該圖案化硬遮罩層(5)之該條帶圖案之該等條帶之間之該STI層堆疊(2)及該基底(7)，藉此界定該等鰭結構(f1，f2，f3，f4)，該等鰭結構係由溝渠(t1、t2、t3)分離；用一第二填充層(3)填充該等溝渠；對該第二填充層(3)執行一表面平整步驟以移除該第二填充層(3)之過量材料，藉此曝露該STI層堆疊(2)且達成一平整表面。
  4. 如請求項2或3之方法，其中提供該圖案化硬遮罩層(5)進一步包 括：根據對應於一對準特徵之一圖案來圖案化該硬遮罩層(5)。
  5. 如請求項2或3中任一項之方法，其中該硬遮罩層包括不同子層，且其中圖案化該等子層包括：僅移除一或多個子層，且不移除該等子層之最下層。
  6. 如請求項5之方法，其中該硬遮罩層自上而下包括一SiOC子層(51)、一高級圖案化膜(APF)子層(52)、氮化矽子層(53)及一SiO2子層(54)之一層堆疊，且其中圖案化該硬遮罩層包括：僅移除該鰭區域中之該SiOC子層(51)及該APF子層(52)，同時移除該鰭區域外之該SiOC子層(51)、該APF子層(52)及該氮化矽層(53)。
  7. 如請求項5之方法，其中該硬遮罩層自上而下包括一SiOC子層(51)、一APF子層(52)、氮化矽子層(53)及一SiO2子層(54)之一層堆疊，且其中圖案化該硬遮罩層(5)包括：移除該鰭區域外之該SiOC子層(51)及該APF子層(52)；且其後移除該鰭區域中之該SiOC子層(51)，且移除該鰭區域外之該氮化矽子層(53)；且其後移除該鰭區域中之該APF子層(52)。
  8. 如請求項1之方法，其中界定一鰭區域包括：在該淺溝渠隔離層堆疊上提供一圖案化光阻層(1)；電漿蝕刻該STI層堆疊(2)及該基底(7)以藉此由自該半導體基底(7)突出之橫向側壁實體地界定該半導體基底(7)上之該鰭區域，該鰭區域定位於該圖案化光阻層(1)下方。
  9. 如請求項8之方法，其中提供一圖案化光阻層(1)包括：在該淺溝渠隔離層堆疊(2)上提供一光阻層(1)；圖案化該光阻層(1)。
  10. 如請求項8或9之方法，其進一步包括：自該STI層堆疊選擇性地移除該圖案化光阻層(1)； 提供至少嵌入該等橫向側壁之一填充層(3)；對該填充層(3)執行一表面平整步驟以移除該填充層(3)之過量材料，藉此曝露該STI層堆疊(2)且達成一平整表面；在該平整表面上提供一硬遮罩層(5)；在該硬遮罩層(5)上提供一DSA層堆疊(4)；將該DSA層堆疊(4)圖案化成一條帶圖案；蝕刻該條帶圖案之該等條帶之間之該硬遮罩層(5)、該STI層堆疊(2)及該基底(7)，藉此界定該等鰭結構，該等鰭結構係由溝渠(t1、t2、t3、t4、t5)分離；用一第二填充層(6)填充該等溝渠(t1、t2、t3、t4、t5)；對該第二填充層(6)執行一表面平整步驟以移除該第二填充層(6)之過量材料，藉此曝露該STI層堆疊(2)且達成一平整表面。
  11. 如請求項9之方法，其中圖案化該光阻層(1)進一步包括圖案化對應於一對準特徵之該光阻層(1)，且其中電漿蝕刻該基底(7)包括在該基底(7)上製造對準特徵。
  12. 如請求項1至3中任一項之方法，其經執行以製造具有小於10奈米之一間距之一組鰭結構。
  13. 一種半導體結構，其包括：一半導體基底(7)，其包括在其一側上之一淺溝渠隔離(STI)層堆疊(2)；一鰭區域，其位於該半導體基底(7)上，該鰭區域自該半導體基底(7)突出，包括該淺溝渠隔離(STI)層堆疊(2)之一部分，且包括橫向側壁；一填充層(3)，其至少嵌入該鰭區域之該等橫向側壁，該填充區域及該鰭區域鄰接一共同平坦表面(一前表面)；一圖案化硬遮罩層(5)，其位於該共同平坦表面之頂部上，至 少在該鰭區域中延伸，且包括一條帶圖案。
  14. 如請求項13之半導體結構，其進一步包括該鰭區域中之溝渠，藉此界定該半導體基底上之鰭結構，該等溝渠對應於該條帶圖案。
  15. 一種半導體結構，其包括：一半導體基底(7)，其包括在其一側上之一淺溝渠隔離(STI)層堆疊(2)；一圖案化硬遮罩層(5)，其位於該淺溝渠隔離(STI)層堆疊(2)上且自該淺溝渠隔離(STI)層堆疊(2)突出，該圖案化硬遮罩層(5)對應於一鰭區域；一填充層(6)，其鄰接一平坦前表面且嵌入該圖案化遮罩層，根據該鰭區域中之一條帶圖案來進一步圖案化該填充層。
  16. 如請求項15之半導體結構，其中該圖案化硬遮罩層在該鰭區域中自上而下包括氮化矽子層及一SiO2子層之一層堆疊，且在該鰭區域外僅包括一SiO2子層。
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