TW201537645A - Package on package structure and manufacturing method thereof - Google Patents

Package on package structure and manufacturing method thereof Download PDF

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Publication number
TW201537645A
TW201537645A TW103109871A TW103109871A TW201537645A TW 201537645 A TW201537645 A TW 201537645A TW 103109871 A TW103109871 A TW 103109871A TW 103109871 A TW103109871 A TW 103109871A TW 201537645 A TW201537645 A TW 201537645A
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Taiwan
Prior art keywords
package
stack structure
package substrate
electronic device
electrical contact
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TW103109871A
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Chinese (zh)
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TWI556332B (en
Inventor
黃淑惠
江政嘉
王隆源
施嘉凱
廖俊明
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矽品精密工業股份有限公司
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Priority to TW103109871A priority Critical patent/TWI556332B/en
Priority to CN201410110895.4A priority patent/CN104934379B/en
Publication of TW201537645A publication Critical patent/TW201537645A/en
Application granted granted Critical
Publication of TWI556332B publication Critical patent/TWI556332B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

This invention provides a package on package structure, comprising: a package substrate having a plurality of first electrical contact pads and is provided with a semiconductor element, and an electronic component having a plurality of second electrical contact pads, the second electrical contact pads are provided with conductive elements, the conductive element is constituted by an insulating block and a conductive material that covers the insulating block, and the conductive elements correspondingly combine the first electrical contact pads, to make the electronic component stack on the package substrate, so as to be conducive to the stack operation by the design of the insulating block. This invention further provides a manufacturing method of the package on package structure.

Description

封裝堆疊結構及其製法 Package stack structure and its preparation method

本發明係有關一種封裝結構,尤指一種封裝堆疊結構及其製法。 The invention relates to a package structure, in particular to a package stack structure and a preparation method thereof.

隨著近年來可攜式電子產品的蓬勃發展,各類相關產品逐漸朝向高密度、高性能以及輕、薄、短、小之趨勢而走,各式樣封裝層疊(package on package,PoP)也因而配合推陳出新,以期能符合輕薄短小與高密度的要求。 With the rapid development of portable electronic products in recent years, various related products are gradually moving towards high density, high performance, light, thin, short, and small, and various package on package (PoP) Cooperate with innovation, in order to meet the requirements of light, short and high density.

如第1圖所示,係為習知封裝堆疊裝置1的剖視示意圖。如第1圖所示,該封裝堆疊裝置1包括兩相疊之封裝結構1a與另一封裝結構1b。 As shown in FIG. 1, it is a schematic cross-sectional view of a conventional package stacking device 1. As shown in FIG. 1, the package stacking device 1 includes two stacked package structures 1a and another package structure 1b.

封裝結構1a係包含具有相對之第一及第二表面11a,11b之第一基板11、覆晶結合該第一基板11之第一電子元件10、設於該第一表面11a上之電性接觸墊111、形成於該第一基板11上以包覆該第一電子元件10之第一封裝膠體13、形成於該第一封裝膠體13之開孔130中之電性接觸墊111上之銲錫材114、以及設於該第二表面11b上用於結合銲球14之植球墊112。 The package structure 1a includes a first substrate 11 having opposite first and second surfaces 11a, 11b, a first electronic component 10 overlying the first substrate 11, and an electrical contact disposed on the first surface 11a. a pad 111, a solder material formed on the first substrate 11 to cover the first encapsulant 13 of the first electronic component 10, and an electrical contact pad 111 formed in the opening 130 of the first encapsulant 13 114, and a ball pad 112 disposed on the second surface 11b for bonding the solder balls 14.

另一封裝結構1b係包含第二基板12、以打線方式結合於該第二基板12上之第二電子元件15a,15b、及形成於該第二基板12上以包覆該第二電子元件15a,15b之第二封裝膠體16,令該第二基板12藉由銲錫材114疊設且電性連接於該第一基板11之電性接觸墊111上。 The other package structure 1b includes a second substrate 12, second electronic components 15a, 15b bonded to the second substrate 12 in a wire bonding manner, and formed on the second substrate 12 to cover the second electronic component 15a. The second encapsulant 16 of the 15b is stacked on the second substrate 12 by the solder material 114 and electrically connected to the electrical contact pad 111 of the first substrate 11.

惟,習知封裝堆疊裝置1中,由於該第一與第二基板11,12間係以銲錫材114作為支撐與電性連接之元件,而隨著電子產品的接點(即I/O)數量愈來愈多,在封裝件的尺寸大小不變的情況下,各該銲錫材114間的間距需縮小,致使容易發生橋接(bridge)的現象,因而造成產品良率過低及可靠度不佳等問題,致使無法用於更精密之細間距產品。 However, in the conventional package stacking device 1, since the first and second substrates 11 and 12 are supported by the solder material 114 as electrical components, the contacts (ie, I/O) of the electronic product are used. As the number of packages is constant, the spacing between the solder materials 114 needs to be reduced, resulting in a bridge phenomenon, resulting in low product yield and reliability. Problems such as good results make it impossible to use finer pitch products.

再者,因該銲錫材114於回銲後之體積及高度之公差大,即尺寸變異不易控制,致使不僅接點容易產生缺陷(例如,於回銲時,該銲錫材114會先變成軟塌狀態,同時於承受上方第二基板12的重量後,該銲錫材114容易塌扁變形,繼而與鄰近該銲錫材114橋接),導致電性連接品質不良,且該銲錫材114所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良,導致接點應力(stress)不平衡而容易造成該兩封裝結構之間呈傾斜接置,甚至產生接點偏移之問題。 Moreover, since the tolerance of the volume and height of the solder material 114 after reflowing is large, that is, the dimensional variation is difficult to control, not only the contact is prone to defects (for example, in the case of reflow, the solder material 114 first becomes soft collapsed). In the state, while the weight of the second substrate 12 is received, the solder material 114 is easily collapsed and then bridged adjacent to the solder material 114, resulting in poor electrical connection quality, and the solder material 114 is arranged in a grid. A grid array is prone to poor coplanarity, resulting in an unbalanced bond stress, which tends to cause tilting between the two package structures and even a problem of contact offset.

又,該兩封裝結構之間僅藉由該銲錫材114作支撐,將因該兩封裝結構之間的空隙d過多,導致該第一與第二基板11,12容易發生翹曲(warpage)。 Moreover, the two package structures are supported by the solder material 114 only, and the first and second substrates 11, 12 are likely to warp due to the excessive gap d between the two package structures.

另外,該銲錫材114構成之金屬導電球因吸震能力較弱,故當該銲錫材114受到震動時,其容易產生偏移而發生短路(short)問題。 Further, since the metal conductive ball formed of the solder material 114 is weak in shock absorbing ability, when the solder material 114 is subjected to vibration, it is liable to be displaced and a short circuit problem occurs.

因此,如何克服習知技術中之種種問題,實已成目前亟欲解決的課題。 Therefore, how to overcome various problems in the prior art has become a problem that is currently being solved.

鑑於上述習知技術之種種缺失,本發明係提供一種封裝堆疊結構,係包括:封裝基板,係具有複數第一電性接觸墊;至少一半導體元件,係設於該封裝基板上;以及電子裝置,係具有複數第二電性接觸墊,且各該第二電性接觸墊上設有導電元件,該些導電元件並係對應結合至該些第一電性接觸墊,使該電子裝置堆疊於該封裝基板上,其中,該導電元件係由絕緣塊與包覆該絕緣塊之導電材所構成。 The present invention provides a package stack structure, comprising: a package substrate having a plurality of first electrical contact pads; at least one semiconductor component disposed on the package substrate; and an electronic device And having a plurality of second electrical contact pads, and each of the second electrical contact pads is provided with a conductive element, and the conductive elements are correspondingly coupled to the first electrical contact pads, so that the electronic device is stacked on the On the package substrate, the conductive element is composed of an insulating block and a conductive material covering the insulating block.

本發明復提供一種封裝堆疊結構之製法,係包括:提供一具有複數第一電性接觸墊之封裝基板與一具有複數第二電性接觸墊之電子裝置,並設置至少一半導體元件與該封裝基板上,其中,該第二電性接觸墊上設有導電元件,且該導電元件係由絕緣塊與包覆該絕緣塊之導電材所構成;以及對應結合該些導電元件至該些第一電性接觸墊,使該電子裝置堆疊於該封裝基板上。 The invention provides a method for fabricating a package stack structure, comprising: providing a package substrate having a plurality of first electrical contact pads and an electronic device having a plurality of second electrical contact pads, and disposing at least one semiconductor component and the package On the substrate, wherein the second electrical contact pad is provided with a conductive element, and the conductive element is composed of an insulating block and a conductive material covering the insulating block; and correspondingly combining the conductive elements to the first electric The contact pads are stacked on the package substrate.

前述之封裝堆疊結構及其製法中,該電子裝置藉由該些導電元件電性連接該封裝基板。 In the foregoing package stack structure and the manufacturing method thereof, the electronic device is electrically connected to the package substrate by the conductive elements.

前述之封裝堆疊結構及其製法中,該絕緣塊係為塑料 球,且該導電材係為銲錫材。 In the foregoing package stack structure and method of manufacturing the same, the insulating block is plastic The ball and the conductive material is a solder material.

前述之封裝堆疊結構及其製法中,該電子裝置係為另一封裝基板或半導體元件。 In the foregoing package stack structure and method of manufacturing the same, the electronic device is another package substrate or a semiconductor element.

前述之封裝堆疊結構及其製法中,該半導體元件位於該電子裝置與該封裝基板之間。又包括形成底膠於該封裝基板與該半導體元件之間。 In the foregoing package stack structure and method of fabricating the same, the semiconductor component is located between the electronic device and the package substrate. The method further includes forming a primer between the package substrate and the semiconductor element.

另外,前述之封裝堆疊結構及其製法中,復包括於對應結合該些導電元件與該些第一電性接觸墊之後,形成封裝材於該電子裝置與該封裝基板之間,以包覆該些導電元件。 In addition, in the foregoing package stack structure and the manufacturing method thereof, after the corresponding conductive elements and the first electrical contact pads are combined, a package material is formed between the electronic device and the package substrate to cover the package Some conductive elements.

由上可知,本發明之封裝堆疊結構及其製法,係藉由該絕緣塊之設計,以利於堆疊作業,且因該導電元件之尺寸變異容易控制,使其可克服堆疊結構間傾斜接置及接點偏移之問題。 It can be seen from the above that the package stack structure of the present invention and the manufacturing method thereof are designed by the insulating block to facilitate the stacking operation, and the size variation of the conductive element is easy to control, so that the tilting connection between the stacked structures can be overcome and Contact offset problem.

再者,該電子裝置與該封裝基板之間不僅藉由該導電元件作支撐,且藉由該封裝膠體填滿該電子裝置與該封裝基板之間的空隙,故可避免該電子裝置與該封裝基板發生翹曲。 Furthermore, the electronic device and the package substrate are not only supported by the conductive component, but also the gap between the electronic device and the package substrate is filled by the package adhesive, so that the electronic device and the package can be avoided. The substrate is warped.

又,該絕緣塊之吸震能力佳,故相較於習知金屬導電球,當該導電元件受到震動時,其不會產生偏移,進而能避免發生短路(short)問題。 Moreover, the insulating block has a good shock absorbing capability, so that when the conductive member is subjected to vibration, it does not shift, and the short circuit problem can be avoided as compared with the conventional metal conductive ball.

1‧‧‧封裝堆疊裝置 1‧‧‧Package stacking device

1a,1b‧‧‧封裝結構 1a, 1b‧‧‧ package structure

10‧‧‧第一電子元件 10‧‧‧First electronic components

11‧‧‧第一基板 11‧‧‧First substrate

11a,21a‧‧‧第一表面 11a, 21a‧‧‧ first surface

11b,21b‧‧‧第二表面 11b, 21b‧‧‧ second surface

111‧‧‧電性接觸墊 111‧‧‧Electrical contact pads

112,212‧‧‧植球墊 112,212‧‧‧Ball mat

114‧‧‧銲錫材 114‧‧‧ Solder

12‧‧‧第二基板 12‧‧‧second substrate

13‧‧‧第一封裝膠體 13‧‧‧First encapsulant

130,213a,223a‧‧‧開孔 130,213a, 223a‧‧‧ openings

14,24‧‧‧銲球 14,24‧‧‧ solder balls

15a,15b‧‧‧第二電子元件 15a, 15b‧‧‧Second electronic components

16‧‧‧第二封裝膠體 16‧‧‧Second encapsulant

2,2’,2”‧‧‧封裝堆疊結構 2,2’,2”‧‧‧Package stack structure

20‧‧‧半導體元件 20‧‧‧Semiconductor components

200‧‧‧電極墊 200‧‧‧electrode pads

200a‧‧‧銲錫凸塊 200a‧‧‧ solder bumps

21‧‧‧封裝基板 21‧‧‧Package substrate

211a,221a‧‧‧銲墊 211a, 221a‧‧ ‧ pads

211b‧‧‧第一電性接觸墊 211b‧‧‧First electrical contact pad

213,223‧‧‧絕緣保護層 213,223‧‧‧Insulating protective layer

22,32‧‧‧電子裝置 22,32‧‧‧Electronic devices

22a‧‧‧第三表面 22a‧‧‧ third surface

22b‧‧‧第四表面 22b‧‧‧Fourth surface

22c‧‧‧基材 22c‧‧‧Substrate

221b,321‧‧‧第二電性接觸墊 221b, 321‧‧‧Second electrical contact pads

23‧‧‧導電元件 23‧‧‧Conductive components

230‧‧‧絕緣塊 230‧‧‧Insulation block

231‧‧‧導電材 231‧‧‧Electrical materials

25‧‧‧封裝材 25‧‧‧Package

26‧‧‧底膠 26‧‧‧Bottom glue

32a‧‧‧作用面 32a‧‧‧Action surface

32b‧‧‧非作用面 32b‧‧‧Non-active surface

d‧‧‧空隙 D‧‧‧ gap

第1圖係為習知封裝堆疊裝置之製法的剖視示意圖;以及 第2A至2D圖係為係為本發明之封裝堆疊結構之製法之剖視示意圖;其中,第2C’圖係為第2C圖之另一態樣,第2D’及2D”圖係分別為第2D圖之不同態樣。 1 is a schematic cross-sectional view showing a method of manufacturing a conventional package stacking device; 2A to 2D are schematic cross-sectional views showing the manufacturing method of the package stack structure of the present invention; wherein the 2C' picture is another aspect of the 2Cth picture, and the 2D' and 2D" pictures are respectively Different aspects of the 2D map.

以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“下”、“第一”、“第二”、“第三”、“第四”、及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. At the same time, the terms "upper", "lower", "first", "second", "third", "fourth", and "one" as used in this specification are also for convenience only. It is to be understood that the scope of the invention is not limited by the scope of the invention.

第2A至2D圖係為本發明之封裝堆疊結構2之製法之剖視示意圖。 2A to 2D are schematic cross-sectional views showing the manufacturing method of the package stack structure 2 of the present invention.

如第2A圖所示,提供一封裝基板21與一設有複數導電元件23之電子裝置22。 As shown in FIG. 2A, a package substrate 21 and an electronic device 22 provided with a plurality of conductive elements 23 are provided.

於本實施例中,該封裝基板21具有相對之第一表面21a及第二表面21b,該第一表面21a上具有複數銲墊211a 與複數第一電性接觸墊211b,且該第二表面21b上具有複數植球墊212,並於該封裝基板21之第一及第二表面21a,21b上具有例如防銲層之絕緣保護層213,該絕緣保護層213形成有複數開孔213a,以藉由該些開孔213a外露該些銲墊211a、第一電性接觸墊211b及植球墊212。 In this embodiment, the package substrate 21 has a first surface 21a and a second surface 21b opposite thereto, and the first surface 21a has a plurality of pads 211a thereon. And a plurality of first electrical contact pads 211b, wherein the second surface 21b has a plurality of ball pads 212, and has an insulating protective layer such as a solder resist layer on the first and second surfaces 21a, 21b of the package substrate 21. 213. The insulating protection layer 213 is formed with a plurality of openings 213a for exposing the pads 211a, the first electrical contact pads 211b, and the ball pad 212 by the openings 213a.

再者,於該銲墊211a之外露表面上藉由銲錫凸塊200a設置一半導體元件20,即該半導體元件20之電極墊200以覆晶方式電性連接該封裝基板21。其中,該半導體元件20係為主動元件或被動元件,並可使用複數個半導體元件20,且可選自主動元件、被動元件或其組合,該主動元件係例如:晶片,而該被動元件係例如:電阻、電容及電感。 Further, a semiconductor device 20 is disposed on the exposed surface of the pad 211a by solder bumps 200a, that is, the electrode pads 200 of the semiconductor device 20 are electrically connected to the package substrate 21 in a flip chip manner. Wherein, the semiconductor component 20 is an active component or a passive component, and a plurality of semiconductor components 20 may be used, and may be selected from an active component, a passive component or a combination thereof, such as a wafer, and the passive component is, for example, : Resistance, capacitance and inductance.

又,該電子裝置22係為封裝基板構形。具體地,提供一具有相對之第三表面22a及第四表面22b之基材22c,該第三表面22a上具有複數銲墊221a,且該第四表面22b上具有複數第二電性接觸墊221b,又該基材22c之第三及第四表面22a,22b上具有例如防銲層之絕緣保護層223,且該絕緣保護層223形成有複數開孔223a,以藉該些開孔223a外露該些銲墊221a及第二電性接觸墊221b。 Moreover, the electronic device 22 is a package substrate configuration. Specifically, a substrate 22c having an opposite third surface 22a and a fourth surface 22b is provided. The third surface 22a has a plurality of pads 221a thereon, and the fourth surface 22b has a plurality of second electrical contact pads 221b thereon. Further, the third and fourth surfaces 22a, 22b of the substrate 22c have an insulating protective layer 223 such as a solder resist layer, and the insulating protective layer 223 is formed with a plurality of openings 223a for exposing the openings 223a. The pads 221a and the second electrical contact pads 221b.

另外,該導電元件23係形成於該基材22c之第二電性接觸墊221b之外露表面上,且該導電元件23具有絕緣塊230與包覆該絕緣塊230之導電材231,該絕緣塊230係為塑料球,且該導電材231係為銲錫材,如鎳錫、錫鉛或錫銀,但不限於此。 In addition, the conductive member 23 is formed on the exposed surface of the second electrical contact pad 221b of the substrate 22c, and the conductive member 23 has an insulating block 230 and a conductive material 231 covering the insulating block 230. 230 is a plastic ball, and the conductive material 231 is a solder material such as nickel tin, tin lead or tin silver, but is not limited thereto.

如第2B圖所示,對應結合該些導電元件23與該些第 一電性接觸墊211b,並回銲該導電材231,使該電子裝置22堆疊於該封裝基板21上,且該半導體元件20位於該電子裝置22與該封裝基板21之間。 As shown in FIG. 2B, the conductive elements 23 are combined with the first An electrical contact pad 211b, and the conductive material 231 is reflowed, the electronic device 22 is stacked on the package substrate 21, and the semiconductor component 20 is located between the electronic device 22 and the package substrate 21.

於本實施例中,該電子裝置22藉由該些導電元件23電性連接該封裝基板21。 In this embodiment, the electronic device 22 is electrically connected to the package substrate 21 by the conductive elements 23 .

如第2C圖所示,於該封裝基板21之第一表面21a(即其上之絕緣保護層213)與該電子裝置22之第四表面22b(即其上之絕緣保護層223)之間形成封裝材25,並包覆該些導電元件23與該半導體元件20。 As shown in FIG. 2C, a first surface 21a of the package substrate 21 (ie, the insulating protective layer 213 thereon) is formed between the first surface 21a of the package substrate 21 and the fourth surface 22b of the electronic device 22 (ie, the insulating protective layer 223 thereon). The package material 25 covers the conductive elements 23 and the semiconductor element 20.

於另一實施例中,如第2C’圖所示,亦可先形成底膠26於該封裝基板21與該半導體元件20之間,再形成該封裝材25。 In another embodiment, as shown in FIG. 2C', a primer 26 may be formed between the package substrate 21 and the semiconductor element 20 to form the package 25.

如第2D圖所示,於該封裝基板21之植球墊212之外露表面上結合銲球24。 As shown in FIG. 2D, the solder balls 24 are bonded to the exposed surface of the ball pad 212 of the package substrate 21.

於另一實施例中,如第2D’圖所示,該電子裝置32亦可為半導體元件,例如晶片之主動元件、或者例如電阻、電容及電感等之被動元件,故該電子裝置32具有相對之作用面32a與非作用面32b,於該作用面32a上具有複數第二電性接觸墊321,使該些導電元件23係對應形成於該第二電性接觸墊321上。 In another embodiment, as shown in FIG. 2D', the electronic device 32 can also be a semiconductor component, such as an active component of a chip, or a passive component such as a resistor, a capacitor, or an inductor, so that the electronic device 32 has a relative The active surface 32a and the non-active surface 32b have a plurality of second electrical contact pads 321 on the active surface 32a, and the conductive elements 23 are formed on the second electrical contact pads 321 correspondingly.

再者,於其它實施例中,如第2D”圖所示,亦可不設置該半導體元件20於該封裝基板21上。 Furthermore, in other embodiments, as shown in FIG. 2D, the semiconductor device 20 may not be disposed on the package substrate 21.

本發明之製法中,藉由該絕緣塊230之設計,以減少銲錫材之使用量,故於回銲時能減少融接處,以避免發生 橋接現象,俾提升產品之良率,且能滿足細間距(fine pitch)之需求。 In the manufacturing method of the present invention, the design of the insulating block 230 is used to reduce the amount of solder material used, so that the fusion joint can be reduced during reflow to avoid occurrence. The bridging phenomenon improves the yield of the product and meets the requirements of fine pitch.

再者,因該絕緣塊230於回銲時之體積及高度之公差小(幾乎不變),即該導電元件23之尺寸變異容易控制,使接點不易產生缺陷,而有效提升電性連接品質,且該導電元件23所排列成之柵狀陣列(grid array)之共面性(coplanarity)良好,以易於控制產品高度,且該封裝基板21與該電子裝置22,32之間不會呈傾斜接置。 Moreover, since the tolerance of the volume and height of the insulating block 230 during reflow is small (almost constant), that is, the dimensional variation of the conductive member 23 is easily controlled, the contact is less likely to cause defects, and the electrical connection quality is effectively improved. And the coplanarity of the grid array in which the conductive elements 23 are arranged is good to easily control the height of the product, and the package substrate 21 and the electronic devices 22, 32 are not inclined. Pick up.

又,該封裝基板21與該電子裝置22,32之間不僅藉由該導電元件23作支撐,且藉由例如封模方式(molding)使該封裝材25填滿該封裝基板21與該電子裝置22之間的空隙,故可避免該封裝基板21與該電子裝置22發生翹曲(warpage)。 Moreover, the package substrate 21 and the electronic device 22, 32 are not only supported by the conductive member 23, but the package 25 is filled with the package substrate 21 and the electronic device by, for example, molding. The gap between the 22, so that the package substrate 21 and the electronic device 22 can be prevented from warping.

另外,該絕緣塊230之吸震能力佳,故當該導電元件23受到震動時,其不會產生偏移,進而能避免發生短路(short)問題。 In addition, the insulating block 230 has a good shock absorbing capability, so that when the conductive member 23 is subjected to vibration, it does not shift, and the short circuit problem can be avoided.

本發明復提供一種封裝堆疊結構2,2’,2”,係包括:相堆疊之一封裝基板21、至少一半導體元件20以及一電子裝置22,32。 The present invention further provides a package stack structure 2, 2', 2" comprising: a phase stack of a package substrate 21, at least one semiconductor component 20, and an electronic device 22,32.

所述之封裝基板21係具有複數第一電性接觸墊211b。 The package substrate 21 has a plurality of first electrical contact pads 211b.

所述之半導體元件20係設於該封裝基板21上。 The semiconductor device 20 is disposed on the package substrate 21.

所述之電子裝置22,32係為另一封裝基板或半導體元件,其具有複數第二電性接觸墊221b,321,該第二電性接觸墊221b,321上設有導電元件23,該導電元件23係具有 絕緣塊230與包覆該絕緣塊230之導電材231,且該些導電元件23對應結合該些第一電性接觸墊211b,使該電子裝置22,32堆疊於該封裝基板21上,並藉由該些導電元件23電性連接該封裝基板21與該電子裝置22,32。 The electronic device 22, 32 is another package substrate or semiconductor component having a plurality of second electrical contact pads 221b, 321 , and the second electrical contact pads 221b, 321 are provided with a conductive element 23, the conductive Element 23 has The insulating block 230 and the conductive material 231 covering the insulating block 230, and the conductive elements 23 are coupled to the first electrical contact pads 211b, so that the electronic devices 22, 32 are stacked on the package substrate 21, and The package substrate 21 and the electronic devices 22, 32 are electrically connected by the conductive elements 23.

於一實施例中,該絕緣塊230係為塑料球,且該導電材231係為銲錫材。 In one embodiment, the insulating block 230 is a plastic ball, and the conductive material 231 is a solder material.

於一實施例中,該半導體元件20係位於該電子裝置22,32與該封裝基板21之間。又包括形成於該封裝基板21與該半導體元件20之間的底膠26。 In one embodiment, the semiconductor component 20 is located between the electronic device 22, 32 and the package substrate 21. Further, a primer 26 formed between the package substrate 21 and the semiconductor element 20 is included.

於一實施例中,所述之封裝堆疊結構2,2’,2”復包括形成於該電子裝置22,32與該封裝基板21之間的封裝材25,其包覆該些導電元件23。 In one embodiment, the package stack structure 2, 2', 2" includes a package 25 formed between the electronic device 22, 32 and the package substrate 21, which encapsulates the conductive elements 23.

綜上所述,本發明之封裝堆疊結構及其製法,主要係藉由絕緣塊之設計,以利於堆疊作業,且因該導電元件之尺寸變異容易控制,故該電子裝置與該封裝基板之間容易呈垂直接置,並有利於固定該導電元件之接觸點,而不會產生橋接現象,俾提升產品之良率。 In summary, the package stack structure of the present invention and the manufacturing method thereof are mainly designed by the insulating block to facilitate the stacking operation, and the size variation of the conductive component is easy to control, so the electronic device and the package substrate are It is easy to be vertically connected, and it is advantageous to fix the contact points of the conductive element without bridging and improving the yield of the product.

再者,該絕緣塊之吸震能力佳,故當該導電元件受到震動時,其不會產生偏移,亦能提升產品之良率。 Moreover, the insulating block has a good shock absorbing capability, so that when the conductive member is subjected to vibration, it does not shift, and the yield of the product can be improved.

上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧封裝堆疊結構 2‧‧‧Package stack structure

20‧‧‧半導體元件 20‧‧‧Semiconductor components

21‧‧‧封裝基板 21‧‧‧Package substrate

211b‧‧‧第一電性接觸墊 211b‧‧‧First electrical contact pad

212‧‧‧植球墊 212‧‧‧Ball mat

22‧‧‧電子裝置 22‧‧‧Electronic devices

221b‧‧‧第二電性接觸墊 221b‧‧‧Second electrical contact pads

23‧‧‧導電元件 23‧‧‧Conductive components

230‧‧‧絕緣塊 230‧‧‧Insulation block

231‧‧‧導電材 231‧‧‧Electrical materials

24‧‧‧銲球 24‧‧‧ solder balls

25‧‧‧封裝材 25‧‧‧Package

Claims (16)

一種封裝堆疊結構,係包括:封裝基板,係具有複數第一電性接觸墊;至少一半導體元件,係設於該封裝基板上;以及電子裝置,係具有複數第二電性接觸墊,且各該第二電性接觸墊上設有導電元件,該些導電元件並係對應結合至該些第一電性接觸墊,使該電子裝置堆疊於該封裝基板上,其中,該導電元件係由絕緣塊與包覆該絕緣塊之導電材所構成。 A package stack structure includes: a package substrate having a plurality of first electrical contact pads; at least one semiconductor component disposed on the package substrate; and an electronic device having a plurality of second electrical contact pads, and each The second electrical contact pad is provided with a conductive component, and the conductive component is correspondingly coupled to the first electrical contact pads, so that the electronic device is stacked on the package substrate, wherein the conductive component is insulated by the insulating block. It is composed of a conductive material covering the insulating block. 如申請專利範圍第1項所述之封裝堆疊結構,其中,該電子裝置藉由該些導電元件電性連接該封裝基板。 The package stack structure of claim 1, wherein the electronic device is electrically connected to the package substrate by the conductive elements. 如申請專利範圍第1項所述之封裝堆疊結構,其中,該絕緣塊係為塑料球。 The package stack structure of claim 1, wherein the insulating block is a plastic ball. 如申請專利範圍第1項所述之封裝堆疊結構,其中,該導電材係為銲錫材。 The package stack structure of claim 1, wherein the conductive material is a solder material. 如申請專利範圍第1項所述之封裝堆疊結構,其中,該電子裝置係為另一封裝基板或半導體元件。 The package stack structure of claim 1, wherein the electronic device is another package substrate or a semiconductor element. 如申請專利範圍第1項所述之封裝堆疊結構,其中,該半導體元件位於該電子裝置與該封裝基板之間。 The package stack structure of claim 1, wherein the semiconductor component is located between the electronic device and the package substrate. 如申請專利範圍第1項所述之封裝堆疊結構,復包括形成於該封裝基板與該半導體元件之間的底膠。 The package stack structure according to claim 1, further comprising a primer formed between the package substrate and the semiconductor element. 如申請專利範圍第1項所述之封裝堆疊結構,復包括形成於該電子裝置與該封裝基板之間的封裝材,用以包覆該些導電元件。 The package stack structure according to claim 1, further comprising a package formed between the electronic device and the package substrate for covering the conductive elements. 一種封裝堆疊結構之製法,係包括:提供一具有複數第一電性接觸墊之封裝基板與一具有複數第二電性接觸墊之電子裝置,並設置至少一半導體元件與該封裝基板上,其中,該第二電性接觸墊上設有導電元件,且該導電元件係由絕緣塊與包覆該絕緣塊之導電材所構成;以及對應結合該些導電元件至該些第一電性接觸墊,使該電子裝置堆疊於該封裝基板上。 A method for manufacturing a package stack structure includes: providing a package substrate having a plurality of first electrical contact pads and an electronic device having a plurality of second electrical contact pads, and disposing at least one semiconductor component on the package substrate, wherein The second electrical contact pad is provided with a conductive element, and the conductive element is composed of an insulating block and a conductive material covering the insulating block; and correspondingly connecting the conductive elements to the first electrical contact pads, The electronic device is stacked on the package substrate. 如申請專利範圍第9項所述之封裝堆疊結構之製法,其中,該電子裝置藉由該些導電元件電性連接該封裝基板。 The method of manufacturing a package stack structure according to claim 9, wherein the electronic device is electrically connected to the package substrate by the conductive elements. 如申請專利範圍第9項所述之封裝堆疊結構之製法,其中,該絕緣塊係為塑料球。 The method of manufacturing a package stack structure according to claim 9, wherein the insulating block is a plastic ball. 如申請專利範圍第9項所述之封裝堆疊結構之製法,其中,該導電材係為銲錫材。 The method of manufacturing a package stack structure according to claim 9, wherein the conductive material is a solder material. 如申請專利範圍第9項所述之封裝堆疊結構之製法,其中,該電子裝置係為另一封裝基板或半導體元件。 The method of manufacturing a package stack structure according to claim 9, wherein the electronic device is another package substrate or a semiconductor element. 如申請專利範圍第9項所述之封裝堆疊結構之製法,其中,該半導體元件位於該電子裝置與該封裝基板之間。 The method of fabricating a package stack structure according to claim 9, wherein the semiconductor component is located between the electronic device and the package substrate. 如申請專利範圍第9項所述之封裝堆疊結構之製法,復包括形成底膠於該封裝基板與該半導體元件之間。 The method of fabricating a package stack structure according to claim 9 further comprising forming a primer between the package substrate and the semiconductor element. 如申請專利範圍第9項所述之封裝堆疊結構之製法,復包括於對應結合該些導電元件與該些第一電性接觸 墊之後,形成封裝材於該電子裝置與該封裝基板之間,以包覆該些導電元件。 The method for manufacturing a package stack structure according to claim 9 is further included in the corresponding combination of the conductive elements and the first electrical contacts. After the pad, a package material is formed between the electronic device and the package substrate to encapsulate the conductive elements.
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