TW201535653A - Metal interconnect structure and method of fabricating the same - Google Patents

Metal interconnect structure and method of fabricating the same Download PDF

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TW201535653A
TW201535653A TW103108856A TW103108856A TW201535653A TW 201535653 A TW201535653 A TW 201535653A TW 103108856 A TW103108856 A TW 103108856A TW 103108856 A TW103108856 A TW 103108856A TW 201535653 A TW201535653 A TW 201535653A
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conductor
barrier layer
layer
metal interconnect
dielectric layer
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TW103108856A
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TWI605560B (en
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Chia-Chann Shiue
Yung-Tai Hung
Yi-Huei Chu
Ya-Jung Tsai
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Macronix Int Co Ltd
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Abstract

A metal interconnect structure is provided, which includes a substrate, a dielectric layer, a conductive damascene, a first barrier layer, and a second barrier layer. The dielectric layer is on the substrate. The dielectric layer has an opening. The conductive damascene is located in the opening. A top surface of the conductive damascene is lower than a top surface of the dielectric layer. The first barrier layer is located between the dielectric layer and the conductive damascene, and between the substrate and the conductive damascene. The second barrier layer is located in the opening and covers the top surface of the conductive damascene.

Description

金屬內連線結構及其製造方法Metal interconnect structure and manufacturing method thereof

本發明是有關於一種金屬內連線結構及其製造方法。The present invention relates to a metal interconnect structure and a method of fabricating the same.

隨著半導體產業的發展,當積體電路的積集度增加,晶片的表面無法提供足夠的面積來製作所需的金屬內連線時,為了配合金氧半(MOS)電晶體縮小後所增加的內連線需求,兩層以上的金屬層設計,便逐漸的成為許多積體電路所必須採用的方式。特別是一些功能較複雜的產品,如微處理器,甚至需要四層或五層的金屬層,才得以完成微處理器內各個元件間的連接。而對於不同金屬層之間的連接,「插塞」扮演了重要的角色。With the development of the semiconductor industry, when the accumulation of integrated circuits increases, the surface of the wafer cannot provide sufficient area to make the required metal interconnects, and is increased in order to reduce the alloyed oxygen half (MOS) transistors. The need for interconnects, the design of two or more metal layers, has gradually become the way that many integrated circuits must be used. In particular, some more complex products, such as microprocessors, even require four or five layers of metal to complete the connection between the various components in the microprocessor. The "plug" plays an important role in the connection between different metal layers.

在金屬內連線的製程中,以鑲嵌的方式形成金屬線之後,在後續形成介層窗的製程中,金屬線會暴露於空氣中而發生氧化或造成腐蝕,抑或是在後續的高溫製程中發生形變或流失。In the process of forming a metal interconnect, after the metal wire is formed by damascene, in the subsequent process of forming the via, the metal wire is exposed to the air to cause oxidation or corrosion, or in a subsequent high temperature process. Deformation or loss.

本發明的實施例提供一種金屬內連線結構,其具有更佳可靠度與穩定性。Embodiments of the present invention provide a metal interconnect structure that provides better reliability and stability.

本發明的實施例又提供一種金屬內連線結構的製造方法,此製造方法可與現有製程整合,所製造的金屬內連線結構具有更佳可靠度與穩定性。The embodiment of the invention further provides a method for manufacturing a metal interconnect structure, which can be integrated with an existing process, and the fabricated metal interconnect structure has better reliability and stability.

本發明提供一種金屬內連線結構,包括基底、介電層、導體鑲嵌結構、第一阻障層與第二阻障層。所述介電層位於基底上。所述介電層具有開口。所述導體鑲嵌結構位於所述開口中。所述導體鑲嵌結構的頂面低於所述介電層的頂面。所述第一阻障層位於所述介電層與所述導體鑲嵌結構之間以及所述基底與所述導體鑲嵌結構之間。所述第二阻障層位於所述開口中,覆蓋所述導體鑲嵌結構的頂面。The invention provides a metal interconnect structure comprising a substrate, a dielectric layer, a conductor damascene structure, a first barrier layer and a second barrier layer. The dielectric layer is on the substrate. The dielectric layer has an opening. The conductor damascene structure is located in the opening. The top surface of the conductor damascene structure is lower than the top surface of the dielectric layer. The first barrier layer is between the dielectric layer and the conductor damascene structure and between the substrate and the conductor damascene structure. The second barrier layer is located in the opening to cover a top surface of the conductor damascene structure.

依照本發明實施例所述,所述第一阻障層與所述第二阻障層的材料包括鉑、銥、鈦、氮化鈦、鉭、氮化鉭、鎢、氮化鎢或其組合。According to an embodiment of the invention, the material of the first barrier layer and the second barrier layer comprises platinum, tantalum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or a combination thereof. .

依照本發明實施例所述,上述金屬內連線結構更包括導體結構,所述導體結構覆蓋所述第二阻障層,且電性連接所述導體鑲嵌結構。According to an embodiment of the invention, the metal interconnect structure further includes a conductor structure covering the second barrier layer and electrically connecting the conductor damascene structure.

依照本發明實施例所述,上述導體結構包括導體插塞。According to an embodiment of the invention, the conductor structure comprises a conductor plug.

依照本發明實施例所述,上述導體結構包括導線。According to an embodiment of the invention, the conductor structure comprises a wire.

本發明又提供一種金屬內連線結構的製造方法。在介電層中形成開口,並於所述開口中形成第一阻障層。之後,在所述開口中的所述第一阻障層上形成導體鑲嵌結構。接著,在所述開口中形成第二阻障層,其中所述第二阻障層覆蓋所述導體鑲嵌結構的頂面。The present invention further provides a method of fabricating a metal interconnect structure. An opening is formed in the dielectric layer, and a first barrier layer is formed in the opening. Thereafter, a conductor damascene structure is formed on the first barrier layer in the opening. Next, a second barrier layer is formed in the opening, wherein the second barrier layer covers a top surface of the conductor damascene structure.

依照本發明實施例所述,所述第一阻障層與所述第二阻障層包括鉑、銥、鈦、氮化鈦、鉭、氮化鉭、鎢、氮化鎢或其組合。According to an embodiment of the invention, the first barrier layer and the second barrier layer comprise platinum, tantalum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or a combination thereof.

依照本發明實施例所述,上述形成所述導體鑲嵌結構的方法包括形成一導體層,以覆蓋所述介電層並填入於所述開口中,接著,移除部分的所述導體層,使所形成的所述導體鑲嵌結構的頂面低於所述介電層的頂面。According to an embodiment of the invention, the method for forming the conductor damascene structure includes forming a conductor layer to cover the dielectric layer and filling the opening, and then removing a portion of the conductor layer, The top surface of the formed conductor damascene structure is formed to be lower than the top surface of the dielectric layer.

依照本發明實施例所述,上述金屬內連線結構的製造方法更包括形成導線,覆蓋所述介電層與所述第二阻障層,以電性連接導體鑲嵌結構。According to an embodiment of the invention, the method for fabricating the metal interconnect structure further includes forming a wire covering the dielectric layer and the second barrier layer to electrically connect the conductor damascene structure.

依照本發明實施例所述,上述金屬內連線結構的製造方法更包括在所述第二阻障層上形成導體插塞,以電性連接所述導體鑲嵌結構。According to an embodiment of the invention, the method for fabricating the metal interconnect structure further includes forming a conductor plug on the second barrier layer to electrically connect the conductor damascene structure.

基於上述,本發明實施例的金屬內連線結構中的導體鑲嵌結構被阻障層完全覆蓋,不僅可以避免金屬原子的擴散與遷移,還可防止氧化、腐蝕、形變或流失,因此,可以增加金屬內連線結構的穩定性與可靠度。Based on the above, the conductor damascene structure in the metal interconnect structure of the embodiment of the present invention is completely covered by the barrier layer, which not only avoids diffusion and migration of metal atoms, but also prevents oxidation, corrosion, deformation or loss, and thus can be increased. The stability and reliability of the metal interconnect structure.

此外,本發明實施例的金屬內連線結構的製程可以與現有的製程整合,且可以不需要增加太多製程步驟,即可增加金屬內連線結構的穩定性與可靠度。In addition, the process of the metal interconnect structure of the embodiment of the present invention can be integrated with the existing process, and the stability and reliability of the metal interconnect structure can be increased without adding too many process steps.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.

圖1A至圖1G是依據本發明實施例之一種金屬內連線結構的製造方法的流程剖面圖。圖2是依據本發明另一實施例之一種金屬內連線結構的剖面圖。1A through 1G are cross-sectional views showing the steps of a method of fabricating a metal interconnect structure in accordance with an embodiment of the present invention. 2 is a cross-sectional view showing a metal interconnect structure in accordance with another embodiment of the present invention.

請參照圖1A,提供基底10。基底10可由選自於Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs與InP所組成的族群中的至少一種半導體或半導體化合物材料形成。基底10的材料也可以是絕緣層上有矽(SOI)。基底10可以是在其上已形成各種構件的半導體、半導體化合物或絕緣層上有矽。所述各種構件例如是金氧半電晶體、金屬內連線的接觸窗、導線或介層窗、矽晶基材、介電層或其組合,於圖式中並未繪示出來。Referring to Figure 1A, a substrate 10 is provided. The substrate 10 may be formed of at least one semiconductor or semiconductor compound material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. The material of the substrate 10 may also be tantalum (SOI) on the insulating layer. The substrate 10 may be germanium on a semiconductor, semiconductor compound or insulating layer on which various members have been formed. The various components are, for example, gold oxide semi-transistors, metal interconnected contact windows, wire or vias, twinned substrates, dielectric layers, or combinations thereof, which are not shown in the drawings.

接著,在基底10上形成介電層12。介電層12的材料例如是氧化矽、旋塗式玻璃(SOG)、磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)或是介電常數小於4的低介電常數材料。介電層12的形成方法例如是旋塗法或化學氣相沉積法。介電層12的厚度例如是1000埃至6000埃。Next, a dielectric layer 12 is formed on the substrate 10. The material of the dielectric layer 12 is, for example, ruthenium oxide, spin-on glass (SOG), phosphoric bismuth glass (PSG), borophosphoquinone glass (BPSG) or a low dielectric constant material having a dielectric constant of less than 4. The method of forming the dielectric layer 12 is, for example, a spin coating method or a chemical vapor deposition method. The thickness of the dielectric layer 12 is, for example, 1000 angstroms to 6000 angstroms.

然後,在介電層12上形成硬罩幕層13。硬罩幕層13可以是單層材料或是多層材料,例如是氮化矽或磷矽玻璃。之後,在硬罩幕層13上形成圖案化的光阻層15。在另一實施例中,也可以不形成硬罩幕層13,而直接形成圖案化的光阻層15。Then, a hard mask layer 13 is formed on the dielectric layer 12. The hard mask layer 13 may be a single layer material or a multilayer material such as tantalum nitride or phosphor haze. Thereafter, a patterned photoresist layer 15 is formed on the hard mask layer 13. In another embodiment, the patterned photoresist layer 15 may be formed directly without forming the hard mask layer 13.

之後,請參照圖1B,以圖案化的光阻層15為罩幕,進行蝕刻製程,以蝕刻硬罩幕層13,形成硬罩幕層13a。之後,繼續進行蝕刻製程,以在介電層12中形成開口14。開口14裸露出基底10。之後,將圖案化的光阻層15移除。Thereafter, referring to FIG. 1B, the patterned photoresist layer 15 is used as a mask to perform an etching process to etch the hard mask layer 13 to form a hard mask layer 13a. Thereafter, an etching process is continued to form openings 14 in the dielectric layer 12. The opening 14 exposes the substrate 10. Thereafter, the patterned photoresist layer 15 is removed.

其後,請參照圖1C,在基底10上形成阻障層16,以覆蓋開口14的側壁與底部以及硬罩幕層13a。阻障層16的材料例如是鉑(Pt)、銥(Ir)、鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、鎢(W)、氮化鎢(WN)或其組合。形成阻障層16的方法例如是化學氣相沉積法或物理氣相沉積法,厚度例如是10埃至500埃。Thereafter, referring to FIG. 1C, a barrier layer 16 is formed on the substrate 10 to cover the sidewalls and the bottom of the opening 14 and the hard mask layer 13a. The material of the barrier layer 16 is, for example, platinum (Pt), iridium (Ir), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride. (WN) or a combination thereof. The method of forming the barrier layer 16 is, for example, a chemical vapor deposition method or a physical vapor deposition method, and the thickness is, for example, 10 Å to 500 Å.

之後,在基底10上形成導體層18,以覆蓋阻障層16並填入於開口14之中。導體層18的材料可以是金屬或是合金,例如是鎢、鋁、銅或其合金,形成的方法例如是電鍍法或物理氣相沉積法,厚度例如是100埃至5000埃。Thereafter, a conductor layer 18 is formed on the substrate 10 to cover the barrier layer 16 and fill the opening 14. The material of the conductor layer 18 may be a metal or an alloy such as tungsten, aluminum, copper or an alloy thereof, and is formed by, for example, electroplating or physical vapor deposition, and has a thickness of, for example, 100 Å to 5000 Å.

之後,請參照圖1D,移除介電層12上方的導體層18,裸露出阻障層16,並在開口14之中形成導體鑲嵌結構18a。導體鑲嵌結構18a具有凹口22。更具體地說,導體鑲嵌結構18a的頂面26的高度低於介電層12的頂面24的高度。移除導體層18的方法包括例如是化學機械研磨法或回蝕法。特別注意的是,當將部分導體層18移除而暴露出部分的阻障層16後,更過度研磨或過度蝕刻,以繼續移除部分的導體層18,直到形成具有凹口22的導體鑲嵌結構18a。凹口22的形狀可以不限於圖中所示的碟狀,亦可以是具有平坦頂面的形狀(未繪示),只要凹口22的頂面26的高度低於介電層12的頂面24的高度即可。在一實施例中,凹口22的深度例如是50埃至1000埃。Thereafter, referring to FIG. 1D, the conductor layer 18 over the dielectric layer 12 is removed, the barrier layer 16 is exposed, and a conductor damascene structure 18a is formed in the opening 14. The conductor damascene structure 18a has a recess 22. More specifically, the height of the top surface 26 of the conductor damascene structure 18a is lower than the height of the top surface 24 of the dielectric layer 12. The method of removing the conductor layer 18 includes, for example, a chemical mechanical polishing method or an etch back method. It is particularly noted that after removing a portion of the conductor layer 18 to expose a portion of the barrier layer 16, it is more over-grinded or over-etched to continue removing portions of the conductor layer 18 until a conductor inlay having the recess 22 is formed. Structure 18a. The shape of the recess 22 may not be limited to the dish shape shown in the drawing, or may have a shape with a flat top surface (not shown) as long as the height of the top surface 26 of the recess 22 is lower than the top surface of the dielectric layer 12. The height of 24 can be. In an embodiment, the depth of the recess 22 is, for example, 50 angstroms to 1000 angstroms.

然後,請參照圖1E,在基底10上形成阻障層28。阻障層28覆蓋阻障層16,且覆蓋導體鑲嵌結構18a的頂面26。阻障層28的材料可與阻障層16的材料相同或相異。阻障層28的材料例如是鉑、銥、鈦、氮化鈦、鉭、氮化鉭、鎢、氮化鎢或其組合。形成阻障層28的方法例如是化學氣相沉積法或物理氣相沉積法,厚度例如是200埃至2000埃。Then, referring to FIG. 1E, a barrier layer 28 is formed on the substrate 10. The barrier layer 28 covers the barrier layer 16 and covers the top surface 26 of the conductor damascene structure 18a. The material of the barrier layer 28 may be the same as or different from the material of the barrier layer 16. The material of the barrier layer 28 is, for example, platinum, tantalum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or a combination thereof. The method of forming the barrier layer 28 is, for example, a chemical vapor deposition method or a physical vapor deposition method, and the thickness is, for example, 200 angstroms to 2000 angstroms.

之後,請參照圖1F,移除介電層12上的阻障層28、阻障層16以及硬罩幕層13a,留下開口14之中的阻障層28a與阻障層16a。阻障層28a的厚度T例如是介於100埃與1000埃之間。移除介電層12上的阻障層28以及阻障層16的方法例如是化學機械研磨法或回蝕法。Thereafter, referring to FIG. 1F, the barrier layer 28, the barrier layer 16 and the hard mask layer 13a on the dielectric layer 12 are removed, leaving the barrier layer 28a and the barrier layer 16a in the opening 14. The thickness T of the barrier layer 28a is, for example, between 100 angstroms and 1000 angstroms. The method of removing the barrier layer 28 and the barrier layer 16 on the dielectric layer 12 is, for example, a chemical mechanical polishing method or an etch back method.

其後,請參照圖1G,在基底10上形成導體結構34與介電層36。在一實施例中,導體鑲嵌結構18a為縱向延伸的導體插塞。導體結構34為水平延伸的導線(或稱金屬線),其覆蓋介電層12、阻障層16a與28a,且電性連接導體鑲嵌結構18a。導體結構34與介電層36的形成方法可以是在基底10上先形成導體層(未繪示),然後,將導體層圖案化,以形成導體結構34(導線)。之後,再形成介電層36。導體結構34的材料例如是銅或其合金,形成的方法例如是電鍍法或物理氣相沉積法。介電層36的材料例如是氧化矽、旋塗式玻璃、磷矽玻璃、硼磷矽玻璃或是介電常數小於4的低介電常數材料。Thereafter, referring to FIG. 1G, a conductor structure 34 and a dielectric layer 36 are formed on the substrate 10. In an embodiment, the conductor damascene structure 18a is a longitudinally extending conductor plug. The conductor structure 34 is a horizontally extending wire (or metal wire) covering the dielectric layer 12, the barrier layers 16a and 28a, and electrically connected to the conductor damascene structure 18a. The conductor structure 34 and the dielectric layer 36 may be formed by first forming a conductor layer (not shown) on the substrate 10, and then patterning the conductor layer to form the conductor structure 34 (wire). Thereafter, a dielectric layer 36 is formed. The material of the conductor structure 34 is, for example, copper or an alloy thereof, and is formed by, for example, electroplating or physical vapor deposition. The material of the dielectric layer 36 is, for example, ruthenium oxide, spin-on glass, phosphoric glass, borophosphon glass or a low dielectric constant material having a dielectric constant of less than 4.

請參照圖2,在另一實施例中,在移除圖1F所示的介電層12上的阻障層28、阻障層16以及硬罩幕層13a之後,可以在基底10上形成導體結構134與介電層136。更具體地說,導體鑲嵌結構18a為水平延伸的導線(或稱金屬線),導體結構134包括縱向延伸的導體插塞138與阻障層140。導體結構134與介電層136的形成方法可以在基底10上先形成介電層136,然後在介電層136中形成介層孔142。之後,在介層孔142的側壁與底部形成阻障層140,再於介層孔142中形成導體插塞138。介電層136的材料例如是氧化矽、旋塗式玻璃、磷矽玻璃、硼磷矽玻璃或是介電常數小於4的低介電常數材料。阻障層140的材料例如是鉑、銥、鈦、氮化鈦、鉭、氮化鉭、鎢、氮化鎢或其組合。形成阻障層140的方法例如是化學氣相沉積法或物理氣相沉積法,厚度例如是10埃至500埃。導體插塞138的材料例如是銅、鎢或鋁銅化合物等。形成導體插塞138的方法例如是電鍍法或是物理氣相沉積法。Referring to FIG. 2, in another embodiment, after removing the barrier layer 28, the barrier layer 16 and the hard mask layer 13a on the dielectric layer 12 shown in FIG. 1F, a conductor may be formed on the substrate 10. Structure 134 and dielectric layer 136. More specifically, the conductor damascene structure 18a is a horizontally extending wire (or metal wire) that includes a longitudinally extending conductor plug 138 and a barrier layer 140. The method of forming the conductor structure 134 and the dielectric layer 136 may first form a dielectric layer 136 on the substrate 10 and then form a via hole 142 in the dielectric layer 136. Thereafter, a barrier layer 140 is formed on the sidewalls and the bottom of the via hole 142, and a conductor plug 138 is formed in the via hole 142. The material of the dielectric layer 136 is, for example, ruthenium oxide, spin-on glass, phosphorous glass, borophosphon glass or a low dielectric constant material having a dielectric constant of less than 4. The material of the barrier layer 140 is, for example, platinum, tantalum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or a combination thereof. The method of forming the barrier layer 140 is, for example, a chemical vapor deposition method or a physical vapor deposition method, and the thickness is, for example, 10 Å to 500 Å. The material of the conductor plug 138 is, for example, copper, tungsten or aluminum copper compound or the like. The method of forming the conductor plug 138 is, for example, electroplating or physical vapor deposition.

在本實施例中,在移除圖1E所示的介電層12上的阻障層28、阻障層16以及硬罩幕層13a之後,導體鑲嵌結構18a的表面已經被阻障層28a完全覆蓋,阻障層28a可以保護導體鑲嵌結構18a,因此,在形成圖1G所示導體結構34或圖2所示的介電層136之前,可以不需要再於基底10上形成保護層(例如是氮化矽層)或銅抑制層。而且由於阻障層28a為導體,可以與後續形成的導體結構34或導體結構134電性連接,因此,導體鑲嵌結構18a上的阻障層28a毋須移除,可以避免導體鑲嵌結構18a在後續製程中遭受氧化或蝕刻腐蝕。In the present embodiment, after the barrier layer 28, the barrier layer 16 and the hard mask layer 13a on the dielectric layer 12 shown in FIG. 1E are removed, the surface of the conductor damascene structure 18a has been completely blocked by the barrier layer 28a. Covering, the barrier layer 28a can protect the conductor damascene structure 18a. Therefore, before forming the conductor structure 34 shown in FIG. 1G or the dielectric layer 136 shown in FIG. 2, it is not necessary to form a protective layer on the substrate 10 (for example, a tantalum nitride layer or a copper suppression layer. Moreover, since the barrier layer 28a is a conductor, it can be electrically connected to the subsequently formed conductor structure 34 or the conductor structure 134. Therefore, the barrier layer 28a on the conductor damascene structure 18a need not be removed, and the conductor damascene structure 18a can be avoided in subsequent processes. It suffers from oxidation or etching corrosion.

請參照圖1F,本發明實施例之金屬內連線結構包括介電層12、導體鑲嵌結構18a、阻障層16a與阻障層28a。Referring to FIG. 1F, the metal interconnect structure of the embodiment of the present invention includes a dielectric layer 12, a conductor damascene structure 18a, a barrier layer 16a, and a barrier layer 28a.

介電層12位於基底10上。介電層12具有開口14,裸露出基底10。導體鑲嵌結構18a位於開口14中,導體鑲嵌結構18a的頂面26低於介電層12的頂面24。阻障層16a與阻障層28a均位於開口14之中,且將導體鑲嵌結構18a完全包覆。更具體地說,導體鑲嵌結構18a的側壁與底部被阻障層16a包覆;而導體鑲嵌結構18a的頂面26被阻障層28a覆蓋。換言之,阻障層16a位於介電層12與導體鑲嵌結構18a之間以及基底10與導體鑲嵌結構18a之間。阻障層28a位於導體鑲嵌結構18a的頂面26上。阻障層16a與阻障層28a的材料可以相同或相異。阻障層16a與阻障層28a的材包括鉑、銥、鈦、氮化鈦、鉭、氮化鉭、鎢、氮化鎢或其組合。The dielectric layer 12 is on the substrate 10. Dielectric layer 12 has an opening 14 that exposes substrate 10. The conductor damascene structure 18a is located in the opening 14, and the top surface 26 of the conductor damascene structure 18a is lower than the top surface 24 of the dielectric layer 12. The barrier layer 16a and the barrier layer 28a are both located in the opening 14, and the conductor damascene structure 18a is completely covered. More specifically, the side walls and bottom of the conductor damascene structure 18a are covered by the barrier layer 16a; and the top surface 26 of the conductor damascene structure 18a is covered by the barrier layer 28a. In other words, the barrier layer 16a is located between the dielectric layer 12 and the conductor damascene structure 18a and between the substrate 10 and the conductor damascene structure 18a. The barrier layer 28a is located on the top surface 26 of the conductor damascene structure 18a. The material of the barrier layer 16a and the barrier layer 28a may be the same or different. The material of the barrier layer 16a and the barrier layer 28a includes platinum, tantalum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or a combination thereof.

請參照圖1G,在一實施例中,金屬內連線結構可以更包括導體結構34與介電層36。導體鑲嵌結構18a為縱向延伸的導體插塞。導體結構34為水平延伸的導線(或稱金屬線),其覆蓋介電層12、阻障層16a與28a,且電性連接導體鑲嵌結構18a。導體結構34的材料例如是銅或其合金。介電層36的材料例如是氧化矽、旋塗式玻璃、磷矽玻璃、硼磷矽玻璃或是介電常數小於4的低介電常數材料。Referring to FIG. 1G , in an embodiment, the metal interconnect structure may further include a conductor structure 34 and a dielectric layer 36 . The conductor damascene structure 18a is a longitudinally extending conductor plug. The conductor structure 34 is a horizontally extending wire (or metal wire) covering the dielectric layer 12, the barrier layers 16a and 28a, and electrically connected to the conductor damascene structure 18a. The material of the conductor structure 34 is, for example, copper or an alloy thereof. The material of the dielectric layer 36 is, for example, ruthenium oxide, spin-on glass, phosphoric glass, borophosphon glass or a low dielectric constant material having a dielectric constant of less than 4.

請參照圖2,在另一實施例中,金屬內連線結構可以更包括導體結構134與介電層136。導體鑲嵌結構18a為水平延伸的導線(或稱金屬線)。導體結構134可以包括縱向延伸的導體插塞138與阻障層140。介電層136的材料例如是氧化矽、旋塗式玻璃、磷矽玻璃、硼磷矽玻璃或是介電常數小於4的低介電常數材料。阻障層140的材料例如是鉑、銥、鈦、氮化鈦、鉭、氮化鉭、鎢、氮化鎢或其組合。形成阻障層140的方法例如是化學氣相沉積法或物理氣相沉積法,厚度例如是50埃至500埃。導體插塞138的材料例如是銅、鎢或鋁銅。Referring to FIG. 2 , in another embodiment, the metal interconnect structure may further include a conductor structure 134 and a dielectric layer 136 . The conductor damascene structure 18a is a horizontally extending wire (or metal wire). The conductor structure 134 can include a longitudinally extending conductor plug 138 and a barrier layer 140. The material of the dielectric layer 136 is, for example, ruthenium oxide, spin-on glass, phosphorous glass, borophosphon glass or a low dielectric constant material having a dielectric constant of less than 4. The material of the barrier layer 140 is, for example, platinum, tantalum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride or a combination thereof. The method of forming the barrier layer 140 is, for example, a chemical vapor deposition method or a physical vapor deposition method, and the thickness is, for example, 50 Å to 500 Å. The material of the conductor plug 138 is, for example, copper, tungsten or aluminum copper.

本發明實施例中,藉由阻障層28a與阻障層16a將導體鑲嵌結構18a完全包覆,可以將導體鑲嵌結構18a限制在開口14之中,避免導體鑲嵌結構18a在後續的高溫製程中形變或流失。In the embodiment of the present invention, the conductor damascene structure 18a is completely covered by the barrier layer 28a and the barrier layer 16a, and the conductor damascene structure 18a can be confined in the opening 14 to avoid the conductor damascene structure 18a in the subsequent high-temperature process. Deformed or lost.

綜上所述,由於本發明實施例的導體鑲嵌結構的頂面覆蓋有阻障層、且導體鑲嵌結構完全包覆於阻障層材料中,而且由於阻障層為導體,在後續的過程中,覆蓋導體鑲嵌結構的阻障層無須移除,導體鑲嵌結構並未暴露於空氣之中,因此可預防導體鑲嵌結構在製程中接觸到空氣(尤其是氧氣)而產生氧化的現象,且可避免導體鑲嵌結構的材料在高溫時擴散、形變或流失。此外,由於本發明可預防導體鑲嵌結構材料的擴散,因此可進而避免導體鑲嵌結構的短路現象。另外,在形成導體鑲嵌結構之後的後續製程(例如清洗製程)中,由於導體鑲嵌結構的頂面被阻障層覆蓋,並未裸露出來,因此可避免導體鑲嵌結構與研漿(slurry)或濕式剝除法(wet strip)使用的溶液反應而發生腐蝕。故,本發明可有效地提升導體鑲嵌結構的穩定性。In summary, since the top surface of the conductor damascene structure of the embodiment of the present invention is covered with a barrier layer, and the conductor damascene structure is completely covered in the barrier layer material, and since the barrier layer is a conductor, in a subsequent process The barrier layer covering the conductor mosaic structure does not need to be removed, and the conductor mosaic structure is not exposed to the air, thereby preventing the conductor mosaic structure from being exposed to air (especially oxygen) during the process and causing oxidation, and can be avoided. The material of the conductor mosaic structure diffuses, deforms or is lost at high temperatures. In addition, since the present invention can prevent the diffusion of the conductor mosaic structure material, the short circuit phenomenon of the conductor mosaic structure can be further avoided. In addition, in the subsequent process (for example, the cleaning process) after the formation of the conductor damascene structure, since the top surface of the conductor damascene structure is covered by the barrier layer and is not exposed, the conductor mosaic structure and the slurry or the wet can be avoided. The solution used in the wet strip reacts to cause corrosion. Therefore, the present invention can effectively improve the stability of the conductor mosaic structure.

此外,本發明實施例的金屬內連線(導體鑲嵌結構)的製程可以與現有的製程整合,且可以不需要增加太多製程步驟即可製造出穩定性提升的導體鑲嵌結構,是一種裨益產業界的發明。In addition, the process of the metal interconnect (conductor damascene structure) of the embodiment of the present invention can be integrated with the existing process, and the conductor mosaic structure with improved stability can be manufactured without adding too many process steps, which is a benefit industry. The invention of the world.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧基底
12、36、136‧‧‧介電層
13、13a‧‧‧硬罩幕層
14‧‧‧開口
15‧‧‧圖案化的光阻層
16、28、16a、28a、140‧‧‧阻障層
18‧‧‧導體層
18a‧‧‧導體鑲嵌結構
22‧‧‧凹口
24、26‧‧‧頂面
34、134‧‧‧導體結構
138‧‧‧導體插塞
142‧‧‧介層孔
T‧‧‧厚度
10‧‧‧Base
12, 36, 136‧‧ dielectric layers
13, 13a‧‧‧ hard mask layer
14‧‧‧ openings
15‧‧‧ patterned photoresist layer
16, 28, 16a, 28a, 140‧‧‧ barrier layers
18‧‧‧Conductor layer
18a‧‧‧Conductor mosaic structure
22‧‧‧ Notch
24, 26‧‧‧ top
34, 134‧‧‧ conductor structure
138‧‧‧ Conductor plug
142‧‧‧Intermediate hole
T‧‧‧ thickness

圖1A至圖1G是依據本發明實施例之一種金屬內連線結構的製造方法的流程剖面圖。1A through 1G are cross-sectional views showing the steps of a method of fabricating a metal interconnect structure in accordance with an embodiment of the present invention.

圖2是依據本發明另一實施例之一種金屬內連線結構的剖面圖。2 is a cross-sectional view showing a metal interconnect structure in accordance with another embodiment of the present invention.

10‧‧‧基底 10‧‧‧Base

12‧‧‧介電層 12‧‧‧Dielectric layer

14‧‧‧開口 14‧‧‧ openings

16a、28a‧‧‧阻障層 16a, 28a‧‧‧ barrier layer

18a‧‧‧導體鑲嵌結構 18a‧‧‧Conductor mosaic structure

24、26‧‧‧頂面 24, 26‧‧‧ top

T‧‧‧厚度 T‧‧‧ thickness

Claims (10)

一種金屬內連線結構,包括: 一介電層,位於一基底上,該介電層具有一開口,裸露出該基底; 一導體鑲嵌結構,位於該開口中,該導體鑲嵌結構的頂面低於該介電層的頂面; 一第一阻障層,位於該介電層與該導體鑲嵌結構之間以及該基底與該導體鑲嵌結構之間;以及 一第二阻障層,位於該開口中,覆蓋該導體鑲嵌結構的頂面。A metal interconnect structure includes: a dielectric layer on a substrate, the dielectric layer having an opening to expose the substrate; a conductor damascene structure located in the opening, the top surface of the conductor damascene structure is low a top surface of the dielectric layer; a first barrier layer between the dielectric layer and the conductor damascene structure and between the substrate and the conductor damascene structure; and a second barrier layer located at the opening Covering the top surface of the conductor mosaic structure. 如申請專利範圍第1項所述的金屬內連線結構,其中該第一阻障層與該第二阻障層的材料包括鉑、銥、鈦、氮化鈦、鉭、氮化鉭、鎢、氮化鎢或其組合。The metal interconnect structure of claim 1, wherein the material of the first barrier layer and the second barrier layer comprises platinum, tantalum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten , tungsten nitride or a combination thereof. 如申請專利範圍第1項所述的金屬內連線結構,更包括一導體結構,該導體結構覆蓋該第二阻障層,電性連接該導體鑲嵌結構。The metal interconnect structure of claim 1, further comprising a conductor structure covering the second barrier layer and electrically connecting the conductor damascene structure. 如申請專利範圍第1項所述的金屬內連線結構,其中該導體結構包括一導體插塞。The metal interconnect structure of claim 1, wherein the conductor structure comprises a conductor plug. 如申請專利範圍第1項所述的金屬內連線結構,其中該導體結構包括一導線。The metal interconnect structure of claim 1, wherein the conductor structure comprises a wire. 一種金屬內連線結構的製造方法,包括: 在一介電層中形成一開口; 在該開口中形成一第一阻障層; 在該開口中的該第一阻障層上形成一導體鑲嵌結構;以及 在該開口中形成一第二阻障層,該第二阻障層覆蓋該導體鑲嵌結構的頂面。A method for fabricating a metal interconnect structure includes: forming an opening in a dielectric layer; forming a first barrier layer in the opening; forming a conductor inlay on the first barrier layer in the opening a structure; and forming a second barrier layer in the opening, the second barrier layer covering a top surface of the conductor damascene structure. 如申請專利範圍第6項所述的金屬內連線結構的製造方法,其中該第一阻障層與該第二阻障層包括鉑、銥、鈦、氮化鈦、鉭、氮化鉭、鎢、氮化鎢或其組合。The method for fabricating a metal interconnect structure according to claim 6, wherein the first barrier layer and the second barrier layer comprise platinum, tantalum, titanium, titanium nitride, tantalum, tantalum nitride, Tungsten, tungsten nitride or a combination thereof. 如申請專利範圍第6項所述的金屬內連線結構的製造方法,其中形成該導體鑲嵌結構的方法包括: 形成一導體層,以覆蓋該介電層並填入於該開口中;以及 移除部分的該導體層,使所形成的該導體鑲嵌結構的頂面低於該介電層的頂面。The method of fabricating a metal interconnect structure according to claim 6, wherein the method of forming the conductor damascene structure comprises: forming a conductor layer to cover the dielectric layer and filling the opening; and shifting In addition to a portion of the conductor layer, the top surface of the conductor damascene structure formed is lower than the top surface of the dielectric layer. 如申請專利範圍第6項所述的金屬內連線結構的製造方法,更包括形成一導線,覆蓋該介電層與該第二阻障層,以電性連接該導體鑲嵌結構。The method for fabricating a metal interconnect structure according to claim 6, further comprising forming a wire covering the dielectric layer and the second barrier layer to electrically connect the conductor damascene structure. 如申請專利範圍第6項所述的金屬內連線結構的製造方法,更包括在該第二阻障層上形成一導體插塞,以電性連接該導體鑲嵌結構。The method for fabricating a metal interconnect structure according to claim 6, further comprising forming a conductor plug on the second barrier layer to electrically connect the conductor damascene structure.
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