JP2006135220A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing technique capable of preventing the dissipation of material, forming a wiring, through pinholes in a cleaning process. <P>SOLUTION: The wiring 41 is formed so as to be buried into a silicon oxide film 37. Subsequently, a nitride silicon carbide film 43 is formed on the silicon oxide film 37 including a region on the wiring 41. In this case, the nitride silicon carbide film 43 is formed with such a degree of thickness that pinholes 43a will not penetrate. Next, the nitride silicon carbide film 43 is worked so that the thickness of the silicon carbonitride film 43 on the silicon oxide film 37 becomes thinner than the thickness of the silicon carbonitride film 43 formed on the wiring 41 and the vicinity thereof. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having damascene wiring.

Japanese Patent Application Laid-Open No. 2004-128050 (Patent Document 1) describes a technique for forming a multilayer copper wiring that can prevent deterioration of the shape of the copper wiring. Specifically, a diffusion preventing insulating film is formed on the copper wiring, and an etching stopper film is formed on the diffusion preventing insulating film. A technique is disclosed in which an interlayer insulating film is formed on the etching stopper film, and a plug and a copper wiring are formed in the diffusion preventing insulating film, the etching stopper film, and the interlayer insulating film using a dual damascene method. According to this technique, since the etching of the interlayer insulating film is stopped at the etching stopper film, it is possible to prevent the insulating film for diffusion prevention from being etched. Therefore, variations in the thickness of the diffusion preventing insulating film can be suppressed. That is, in the subsequent step, the diffusion preventing insulating film is etched to expose the underlying copper wiring, but if there is a variation in the thickness of the diffusion preventing insulating film, the film thickness of the diffusion preventing insulating film The copper wiring existing under the thin region is excessively etched. As a result, there arises a problem of shape deterioration of the copper wiring. However, according to the technique described above, variation in the film thickness of the diffusion preventing insulating film can be suppressed, so that deterioration of the shape of the copper wiring can be suppressed.
JP 2004-128050 A

  In recent years, copper having a resistance value lower than that of aluminum has been used as a wiring material, and a wiring forming technique called damascene has been studied as a technique for forming wiring by processing this copper. . This damascene method can be broadly divided into a single-damascene method and a dual-damascene method.

  In the single damascene method, for example, after forming a wiring groove in an insulating film, a copper film for wiring formation is deposited on the insulating film and in the wiring groove, and this copper film is further subjected to, for example, a chemical mechanical polishing method ( In this method, the embedded wiring is formed in the wiring groove by polishing so as to remain only in the wiring groove by CMP (Chemical Mechanical Polishing).

  In the dual damascene method, a connection hole for connecting a wiring groove and a lower layer wiring is formed in an insulating film, and then a copper film for wiring formation is deposited on the insulating film in the wiring groove and the connecting hole. Further, the buried copper film is polished by CMP so as to remain only in the wiring groove and the connection hole, thereby forming a buried wiring in the wiring groove and the connection hole.

  Problems that occur when wiring and plugs are manufactured by the damascene method will be described with reference to the drawings. FIG. 1 is a diagram showing a process of forming wiring on a semiconductor substrate using a damascene method. In FIG. 1, an insulating film 1 made of, for example, a silicon oxide film is formed on a semiconductor substrate (not shown), and an insulating film 2 made of, for example, a silicon carbonitride film (SiCN) is formed on the insulating film 1. Is formed. An insulating film 3 made of, for example, a silicon oxide film is formed on the insulating film 2. In the insulating film 3, a wiring 4 embedded using, for example, a single damascene method is formed. The wiring 4 is composed of a conductive barrier film 4a and a copper film 4b that prevent copper diffusion. FIG. 1 shows a step of forming a plug and a wiring layer on the wiring 4 by using a dual damascene method. First, the insulating films 5 to 8 are sequentially formed on the insulating film 3 including the wiring 4. The insulating films 5 and 7 are made of, for example, a silicon carbonitride film, and the insulating films 6 and 8 are made of, for example, a silicon oxide film. Here, in the formation of the insulating film, a defect may be formed. For example, the insulating film 5 has a pinhole (defect) 5 a penetrating the insulating film 5.

  Subsequently, after an insulating film 9 made of, for example, a silicon nitride film is formed on the insulating film 8, the insulating film 9 is patterned. The patterning is performed so as to open a region where a wiring groove (trench groove) is to be formed. Then, after forming a resist film (not shown) on the insulating film 8 and the insulating film 9, the resist film is patterned. The patterning is performed so as to open a region where the connection hole (via hole) 10 is formed. Next, the connection hole 10 penetrating the insulating films 6 to 8 is formed by etching using the patterned resist film as a mask. At the bottom of the connection hole 10, the insulating film 5 in which the pinhole 5a is formed is exposed.

  Next, the patterned resist film is removed. In the steps so far, the foreign matter 11 as shown in FIG. 1 may adhere. Subsequently, as shown in FIG. 2, a wiring groove 12 is formed in the insulating film 8 using the patterned insulating film 9 as a mask. Here, since the foreign material 11 adheres on the insulating film 8, the wiring groove 12 is not normally formed. For this reason, there is a problem that the wiring is not formed normally.

  Therefore, it is conceivable to add a step of cleaning the semiconductor substrate after forming the connection hole 10 and removing the resist film used to form the connection hole 10. That is, it is conceivable to remove the foreign material 11 by cleaning the surface of the semiconductor substrate. If the foreign material 11 can be removed, the wiring groove 12 can be formed normally.

  However, when the cleaning process is added, the following problems occur. As shown in FIG. 3, the insulating film 5 is exposed at the bottom of the connection hole 10, and for example, a pinhole 5 a is formed in the insulating film 5. Then, there is a problem that cleaning liquid or the like enters the wiring 4 from the pinhole 5a and copper forming the wiring 4 disappears.

  An object of the present invention is to provide a semiconductor device capable of preventing a material forming a wiring from disappearing through a pinhole and a manufacturing technique thereof in a cleaning process.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  One invention disclosed in the present application includes (a) an insulating film formed on a semiconductor substrate, (b) a metal wiring layer embedded in the insulating film, and (c) the metal wiring layer. A diffusion preventing insulating film formed on the insulating film; and (d) a plug penetrating the diffusion preventing insulating film and connected to the metal wiring layer, the diffusion preventing formed on the metal wiring. The thickness of the insulating film for use is greater than the thickness of the diffusion insulating film formed on the insulating film.

  Further, one invention disclosed in the present application includes: (a) a step of forming an insulating film on a semiconductor substrate; (b) a step of forming a metal wiring layer so as to be embedded in the insulating film; Forming a first diffusion preventing insulating film on the insulating film and the metal wiring layer; (d) forming an etching stopper film on the first diffusion preventing insulating film; and (e) the etching. Forming a second diffusion preventing insulating film on the stopper film; and (f) the second diffusion preventing film formed on the insulating film via the first diffusion preventing insulating film and the etching stopper film. A step of removing the insulating film for forming, while leaving the second insulating film for preventing diffusion formed on the metal wiring layer through the first insulating film for preventing diffusion and the etching stopper film. is there.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the thickness of the insulating film exposed at the bottom of the connection hole is relatively increased, it is possible to prevent the formation of a pinhole penetrating the insulating film. Therefore, it is possible to prevent the wiring material from being lost through the pinhole that penetrates when cleaning.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 4 is a cross-sectional view showing the semiconductor device according to the first embodiment. In FIG. 4, a plurality of element isolation regions 21 are formed in the semiconductor substrate 20, and a p-type well 22 is formed in the active region isolated by the element isolation regions 21. An n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on the p-type well 22. Specifically, a gate insulating film 23 made of, for example, a silicon oxide film is formed on the p-type well 22, and a gate electrode 24 is formed on the gate insulating film 23. The gate electrode 24 is composed of, for example, a laminated film of a polysilicon film 24 a and a cobalt silicide film 30.

  Sidewalls 27 are formed on the side walls on both sides of the gate electrode 24, and low-concentration n-type impurity diffusion regions 25 and 26 are formed in the p-type well 22 below the sidewalls 27. High-concentration n-type impurity diffusion regions 28 and 29 are formed outside the low-concentration n-type impurity diffusion regions 25 and 26, and the cobalt silicide film 30 is formed on the high-concentration n-type impurity diffusion regions 28 and 29. Is formed.

  The low-concentration n-type impurity diffusion region 25, the high-concentration n-type impurity diffusion region 28, and the cobalt silicide film 30 form the source region of the n-channel MISFET. Similarly, the drain region of the n-channel MISFET is formed by the low concentration n-type impurity diffusion region 26, the high concentration n-type impurity diffusion region 29 and the cobalt silicide film 30.

  Next, a silicon nitride film 31 and a silicon oxide film 32 are formed on the semiconductor substrate 20 on which the n-channel MISFET is formed. The silicon nitride film 31 and the silicon oxide film 32 are films that function as interlayer insulating films. The silicon nitride film 31 and the silicon oxide film 32 have plugs 35 that pass through these films and are connected to the source region or the drain region. Is formed. For example, the plug 35 is formed of a laminated film of a titanium nitride film and a tungsten film.

  A silicon carbonitride film 36 and a silicon oxide film (insulating film) 37 are formed on the silicon oxide film 32 on which the plugs 35 are formed. A wiring (metal wiring layer) 41 and a wiring 42 are formed in the silicon carbonitride film 36 and the silicon oxide film 37 so as to be embedded. The wiring 41 and the wiring 42 are made of, for example, a tantalum film as a barrier conductor film and a copper film formed on the tantalum film. The wiring 41 and the wiring 42 are formed so as to be connected to the plug 35.

  Next, a silicon carbonitride film 43 is formed on the silicon oxide film 37 including the wirings 41 and 42. The silicon carbonitride film 43 has a function of preventing the copper atoms constituting the wirings 41 and 42 from diffusing into other regions. That is, the silicon carbonitride film 43 is an insulating film for preventing diffusion of copper atoms.

  Here, one feature of the semiconductor device in the first embodiment is that the film thickness of the silicon carbonitride film 43 formed on the wiring 41 and the vicinity thereof is formed on another region, for example, the silicon oxide film 37. This is that the thickness is relatively larger than the thickness of the silicon carbonitride film 43 formed. Thus, by relatively increasing the film thickness of the silicon carbonitride film 43 formed on the wiring 41, the generation of pinholes penetrating the silicon carbonitride film 43 can be prevented.

  When the silicon carbonitride film 43 is formed, defects such as pinholes may occur. When this pinhole penetrates the silicon carbonitride film 43, a problem as described below occurs. That is, as shown in FIG. 4, a plug 52 connected to the wiring 41 is formed on the wiring 41, and a connection hole (via hole) is formed to make this plug 52. The connection hole is formed so as to expose the silicon carbonitride film 43 formed on the wiring 41, and then a cleaning process is performed. Therefore, if a pin hole penetrating the silicon carbonitride film 43 is formed in the silicon carbonitride film 43, the cleaning liquid enters the wiring 41 from this pinhole. Then, the problem that the copper film which comprises the wiring 41 lose | disappears will generate | occur | produce.

  Therefore, in the first embodiment, the generation of penetrating pins is prevented by increasing the thickness of the silicon carbonitride film 43 formed on the wiring 41. If the occurrence of pinholes penetrating in this way can be prevented, the disappearance of the copper film constituting the wiring 41 can be prevented. On the other hand, if the thickness of the silicon carbonitride film 43 is increased not only on the wiring 41 but also in other regions, the capacitance between the wirings formed in multiple layers increases. For this reason, in the first embodiment, only the film thickness of the silicon carbonitride film 43 formed on the wiring 41 and the vicinity thereof is made thicker than the film thickness of the silicon carbonitride film 43 formed in other regions. . As a result, it is possible to prevent the generation of pinholes penetrating on the wiring 41 and to suppress an increase in inter-wiring capacitance.

  Next, a silicon oxide film 44 serving as an interlayer insulating film is formed on the silicon carbonitride film 43, and a silicon carbonitride film 45 and a silicon oxide film 46 are formed on the silicon oxide film 44. A plug 52 is formed in the silicon oxide film 44, and the plug 52 penetrates the silicon carbonitride film 43 and is connected to the wiring 41. In addition, a wiring 53 embedded in the silicon carbonitride film 45 and the silicon oxide film 46 is formed on the plug 52. Although not shown in FIG. 4, a multilayer wiring may be formed in an upper layer than the wiring 53.

  The semiconductor device according to the first embodiment is configured as described above, and a manufacturing method thereof will be described below.

  As shown in FIG. 5, for example, a semiconductor substrate 20 having a specific resistance of about 1 to 10 Ωcm is prepared. The semiconductor substrate 20 is made of p-type single crystal silicon, and an element isolation region 21 is formed on the main surface thereof. The element isolation region 21 is made of a silicon oxide film, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization Of Silicon).

Next, a p-type well 22 is formed in a region divided by the element isolation region 21, that is, a region where an n-channel MISFET is formed. The p-type well 22 is formed by introducing boron (B) or boron fluoride (BF ₂ ) by, for example, ion implantation.

  Subsequently, a gate insulating film 23 is formed on the p-type well 22. The gate insulating film 23 is made of, for example, a thin silicon oxide film, and can be formed using, for example, a thermal oxidation method.

  Then, a gate electrode 24 is formed on the gate insulating film 23. The gate electrode 24 is formed as follows. First, a polysilicon film 24a is formed on the gate insulating film 23 of the semiconductor substrate 20, and an n-type impurity such as phosphorus (P) is implanted into the formed polysilicon film 24a using, for example, an ion implantation method. After forming the low resistance polysilicon film 24a in this manner, the polysilicon film 24a is patterned by using the photolithography technique and the etching technique, thereby forming the gate electrode 24 made of the polysilicon film 24a.

  Next, lightly doped n-type impurity diffusion regions 25 and 26 are formed in regions on both sides of the gate electrode 24. The low-concentration n-type impurity diffusion regions 25 and 26 are formed by introducing an n-type impurity such as phosphorus into the p-well 22 using an ion implantation method, for example.

  Subsequently, a sidewall 27 is formed on the sidewall of the gate electrode 24. The sidewall 27 can be formed by depositing a silicon oxide film on the semiconductor substrate 20 by using, for example, a CVD (Chemical Vapor Deposition) method and anisotropically etching the deposited silicon oxide film.

  After the sidewall 27 is formed, high-concentration n-type impurity diffusion regions 28 and 29 are formed in regions on both sides of the gate electrode 24. The high-concentration n-type impurity diffusion regions 28 and 29 are formed by introducing an n-type impurity such as phosphorus using an ion implantation method, for example. The high concentration n-type impurity diffusion regions 28 and 29 have a higher impurity concentration than the low concentration n-type impurity diffusion regions 25 and 26 described above.

  Next, after exposing the surfaces of the gate electrode 24 and the high-concentration n-type impurity diffusion regions 28 and 29, a cobalt (Co) film is deposited on the semiconductor substrate 20 by using, for example, a sputtering method. A cobalt silicide film 30 is formed on the gate electrode 24 and the high-concentration n-type impurity diffusion regions 28 and 29 by performing heat treatment. Thereby, since the gate electrode 24 is formed from a laminated film of the polysilicon film 24a and the cobalt silicide film 30, the resistance of the gate electrode 24 can be reduced. Further, the diffusion resistance and contact resistance of the high-concentration n-type impurity diffusion regions 28 and 29 can be reduced. Thereafter, the unreacted cobalt film is removed.

  In this way, an n-channel MISFET can be formed on the p-type well 22.

  Subsequently, a silicon nitride film 31 and a silicon oxide film 32 are sequentially deposited on the semiconductor substrate 20 by using, for example, a CVD method. Thereafter, a contact hole 33 penetrating the silicon nitride film 31 and the silicon oxide film 32 is formed by using a photolithography technique and an etching technique. At the bottom of the contact hole 33, the cobalt silicide film 30 formed on the high-concentration n-type impurity diffusion regions 28 and 29 is exposed.

  Next, the plug 35 in which the tungsten film 34 b is embedded in the contact hole 33 is formed. The plug 35 can be formed as follows, for example. First, a titanium nitride film 34a is formed on the silicon oxide film 32 including the inside of the contact hole 33 by using, for example, a sputtering method, and then the tungsten film 34b is embedded in the contact hole 33 by using, for example, a CVD method. To form. Then, the unnecessary titanium nitride film 34a and tungsten film 34b formed on the silicon oxide film 32 are removed by using a CMP (Chemical Mechanical Polishing) method or an etch back method, whereby the plug 35 is formed.

  6 to 20 are sectional views of the semiconductor device manufacturing process following FIG. For the sake of easy understanding, the structures below the silicon oxide film 32 are not shown in FIGS.

  First, as shown in FIG. 6, a silicon carbonitride film 36 is formed on the silicon oxide film 32 on which the plugs 35 are formed by using, for example, a CVD method. The silicon carbonitride film 36 becomes a stopper film for subsequent etching. That is, the silicon carbonitride film 36 is formed in order to prevent damage to the lower layer due to excessive etching or deterioration in processing dimensional accuracy when forming a wiring forming groove in the silicon oxide film 37.

  Thereafter, a silicon oxide film (insulating film) 37 is formed on the silicon carbonitride film 36 by using, for example, a CVD method. When the silicon oxide film 37 is formed, fluorine may be added. By adding fluorine to the silicon oxide film 37, the dielectric constant of the silicon oxide film 37 can be lowered, so that wiring delay can be suppressed. Instead of the silicon oxide film 37, an organic low dielectric constant material may be used.

  Next, as shown in FIG. 7, a wiring trench (trench trench) 38 is formed in the silicon carbonitride film 36 and the silicon oxide film 37 by using a photolithography technique and an etching technique. At the bottom of the wiring trench 38, the plug 35 in which the titanium nitride film 34a and the tungsten film 34b are embedded is exposed.

  Subsequently, as shown in FIG. 8, a tantalum film 39 is formed on the main surface of the semiconductor substrate 20. The tantalum film 39 can be formed using, for example, a sputtering method. The tantalum film 39 has a function as a conductive barrier film. That is, as will be described later, it has a function of preventing diffusion of copper embedded in the wiring groove 21 into silicon or the like. As such a conductive barrier film, instead of the tantalum film 39, for example, a tantalum nitride film, a titanium (Ti) film, a titanium nitride (TiN) film, a tungsten (W) film, a tungsten nitride (WN) film, a nitride film A titanium silicide film, a tungsten nitride silicide film, or the like may be used. Moreover, the film | membrane which uses these alloys for the main material may be sufficient. Furthermore, not only the above-described single film but also a laminated film can be used.

  Next, a relatively thin seed film 40 a made of a copper (Cu) film is formed on the tantalum film 39. The seed film 40a can be formed using, for example, a sputtering method. This seed film 40a is formed in order to improve the adhesion between a copper film 40, which will be described later, and a tantalum film 39. The seed film 40a also has a role as an electrode when performing an electroplating method to be described later.

  Thereafter, as shown in FIG. 9, a copper film 40 that is relatively thicker than the seed film 40 a is formed on the entire surface of the semiconductor substrate 20 so as to be embedded in the wiring trench 38. The copper film 40 is formed using a plating method such as electrolytic plating or electroless plating. Moreover, after forming the copper film 40 directly on the conductive barrier film by the sputtering method, it can be formed by flattening the surface by reflowing, or the copper film 40 is deposited by using the CVD method. You may make it make it.

  The material of the copper film 40 is made of copper, but may be made of a copper alloy. For example, as a copper alloy, one containing copper as a main component and containing Mg, Ag, Pd, Ti, Ta, Al, Nb, Zr, Zn, or the like can be given.

  Subsequently, as shown in FIG. 10, while leaving the tantalum film 39 and the copper film 40 embedded in the wiring groove 38, the unnecessary tantalum film 39 and the copper film 40 formed on the silicon oxide film 37 are removed. Thereby, the wiring (metal wiring layer) 41 and the wiring 42 are formed. The unnecessary tantalum film 39 and copper film 40 can be removed by polishing using, for example, CMP. The wirings 41 and 42 are electrically connected to the source region and the drain region through the plug 35.

  Here, in FIG. 9, the seed film 40 a and the copper film 40 that is the main conductive film are separately described. However, since the seed film 40 a and the copper film 40 are integrated, in the subsequent drawings Described as membrane 40.

  Next, as shown in FIG. 11, a silicon carbonitride film (diffusion prevention insulating film) 43 is formed on the silicon oxide film 37 including the wirings 41 and 42. The silicon carbonitride film 43 can be formed by, for example, a CVD method. The silicon carbonitride film 43 has a function of preventing copper, which is the main component of the wirings 41 and 42, from diffusing into other regions. That is, the silicon carbonitride film 43 functions as a diffusion preventing insulating film that prevents copper diffusion.

  When the silicon carbonitride film 43 is formed, a defect called a pinhole 43a may occur. When the pinhole 43a is large, the silicon carbonitride film 43 may be penetrated. Thus, when the pinhole 43a penetrating the silicon carbonitride film 43 is formed, there arises a problem that the copper film constituting the wiring 41 disappears as will be described later.

  Therefore, in the first embodiment, even if a pinhole 43a is generated in the silicon carbonitride film 43, the film thickness of the silicon carbonitride film 43 is increased so that the pinhole 43a does not penetrate the silicon carbonitride film 43. ing. That is, as shown in FIG. 11, even if the pinhole 43 a is generated on the wiring 41, the film thickness of the silicon carbonitride film 43 is increased compared to the conventional case. Do not penetrate. Specifically, the film thickness of the silicon carbonitride film 43 is, for example, about 70 nm to about 100 nm.

  Subsequently, the silicon carbonitride film 43 is processed using a photolithography technique and an etching technique. Specifically, as shown in FIG. 12, the silicon carbonitride film 43 formed on the wiring 41 and the vicinity thereof is formed on the silicon oxide film 37 other than the wiring 41, for example, while the film thickness is increased. Processing is performed to reduce the thickness of the silicon carbonitride film 43. That is, the thickness of the silicon carbonitride film 43 formed on the wiring 41 and the silicon oxide film 37 in the vicinity of the wiring 41 is the same as the thickness of the silicon carbonitride film 43 formed on the silicon oxide film 37 away from the wiring 41. Thicker than that. The film thickness of this relatively thin silicon carbonitride film 43 is, for example, about 50 nm.

  Thus, while the film thickness of the silicon carbonitride film 43 formed on the wiring 41 and the vicinity thereof is relatively increased, the film thickness of the silicon carbonitride film 43 formed on other regions is relatively increased. It is thin. Thereby, it is possible to prevent the silicon carbonitride film 43 through which the pinholes 43a have passed from being formed on the wiring 41, and to suppress an increase in the capacitance between the wirings.

  Next, as shown in FIG. 13, a silicon oxide film 44, a silicon carbonitride film 45, a silicon oxide film 46, and a silicon nitride film 47 are sequentially formed on the silicon carbonitride film 43. Each film can be formed by, for example, a CVD method.

  Subsequently, as shown in FIG. 14, the silicon nitride film 47 is patterned by using a photolithography technique and an etching technique. The patterning is performed so as to open a region where a wiring groove (trench groove) is to be formed.

  Thereafter, as shown in FIG. 15, a connection hole (via hole) 48 penetrating the silicon oxide film 44, the silicon carbonitride film 45, and the silicon oxide film 46 is formed by using a photolithography technique and an etching technique. The silicon carbonitride film 43 is exposed at the bottom of the connection hole 48. Next, a cleaning process is performed to remove foreign substances on the semiconductor substrate 20. Here, the silicon carbonitride film 43 is exposed at the bottom of the connection hole 48. Since the silicon carbonitride film 43 is sufficiently thick, the pinhole 43a is formed in the silicon carbonitride film 43. Does not penetrate. Accordingly, during the cleaning process, the cleaning liquid does not enter the wiring 41 from the pinhole 43a, and the copper film that is the main component of the wiring 41 can be prevented from being lost by the cleaning liquid.

  Subsequently, as shown in FIG. 16, the silicon oxide film 46 is etched using the patterned silicon nitride film 47 as a mask, thereby forming a wiring groove 49. Then, as shown in FIG. 17, the silicon carbonitride film 43 exposed at the bottom of the connection hole 48, the silicon carbonitride film 45 exposed at the bottom of the wiring groove 49, and the patterned silicon nitride film 47 are etched. Remove.

  Next, as shown in FIG. 18, a tantalum film 50 is formed on the entire main surface of the semiconductor substrate 20 by using, for example, a sputtering method. The tantalum film 50 has a function similar to that of the tantalum film 39 described above, and has a function of preventing, for example, copper diffusion. At this time, the tantalum film 50 is also formed in the wiring groove 49 and the connection hole 48.

  Subsequently, a relatively thin seed film 51a made of a copper film is formed on the semiconductor substrate 20 on which the tantalum film 50 is formed by using, for example, a sputtering method. Then, as shown in FIG. 19, the copper film 51 is formed so as to be embedded in the wiring groove 49 and the connection hole 48. The copper film 51 can be formed using a plating method, for example, and is formed from copper or a copper alloy.

  Next, as shown in FIG. 20, while leaving the tantalum film 50 and the copper film 51 embedded in the wiring trench 49 and the connection hole 48, the unnecessary tantalum film 50 and the copper film formed on the silicon oxide film 46 are left. By removing 51, the plug 52 and the wiring 53 are formed. Unnecessary removal of the tantalum film 50 and the copper film 51 can be performed using, for example, a CMP method.

  Furthermore, by repeating the same manufacturing process, the wiring after the second layer wiring can be formed, but it is omitted here. In this way, a multilayer wiring can be formed on the n-channel MISFET.

  As described above, according to the first embodiment, the silicon carbonitride film 43 formed on the wiring 41 and the vicinity thereof is formed thicker than the silicon carbonitride film 43 formed in other regions. Thus, the generation of the pinhole 43a penetrating the silicon carbonitride film 43 on the wiring 41 can be prevented. Therefore, in the cleaning process performed after the connection hole 48 exposing the silicon carbonitride film 43 is formed, the cleaning liquid can be prevented from entering the wiring 41 through the pinhole 43a, so that the disappearance of the copper film can be prevented.

  In addition, since the silicon carbonitride film 43 formed in a region other than on the wiring 41 is formed relatively thin, an increase in capacitance between the multilayer wirings can be suppressed. That is, if the thickness of the silicon carbonitride film 43 is uniformly increased in order to prevent the occurrence of penetrating pinholes, the capacitance between the multilayer wirings is increased. Therefore, in the first embodiment, the silicon carbonitride film 43 is thickened in a region (a region on the wiring 41) where it is necessary to prevent pinhole penetration, while in other regions, silicon carbonitride is used. The film 43 is made thinner.

  Furthermore, since the cleaning process can be added after the connection hole 48 is formed, the foreign matter adhering to the semiconductor substrate 20 can be removed. Therefore, the occurrence of pattern defects can be suppressed and the yield of products can be improved.

(Embodiment 2)
In the first embodiment, the example in which the silicon carbonitride film functioning as the diffusion-preventing insulating film is formed in one step has been described. That is, after a thick silicon carbonitride film is formed in a single process, the film thickness of the silicon carbonitride film formed on the region other than the wiring 41 is increased by using a photolithography technique and an etching technique. It was thin. In Embodiment 2, an example in which a silicon carbonitride film is formed over two layers will be described.

  5 to 10 are the same as those in the first embodiment. Subsequently, as shown in FIG. 21, a silicon carbonitride film (first diffusion preventing insulating film) 55 is formed on the silicon oxide film 37 including the wirings 41 and 42. The silicon carbonitride film 55 can be formed using, for example, a CVD method, and has a film thickness of about 35 nm, for example. Thus, the film thickness of the silicon carbonitride film 55 formed in the second embodiment is thinner than the film thickness of the silicon carbonitride film 43 formed in the first embodiment. Therefore, in the second embodiment, pinholes 55 a penetrating the silicon carbonitride film 55 are formed in the silicon carbonitride film 55.

  Then, as shown in FIG. 22, a silicon carbonitride film (second diffusion prevention insulating film) 56 is formed on the silicon carbonitride film 55 by using, for example, a CVD method. The film thickness of the silicon carbonitride film 56 is, for example, about 35 nm, and pinholes 56 a penetrating the silicon carbonitride film 56 are formed.

  Here, the silicon carbonitride film 55 and the silicon carbonitride film 56 are formed in separate steps. For this reason, the position of the pinhole 55a formed in the silicon carbonitride film 55 and the position of the pinhole 56a formed in the silicon carbonitride film 56 are shifted. Therefore, it is possible to prevent the generation of pinholes that penetrate both the silicon carbonitride film 55 and the silicon carbonitride film 56. As described above, in the second embodiment, by forming the thin silicon carbonitride film over two layers, generation of penetrating pinholes is prevented.

  In the first embodiment, since the silicon carbonitride film 43 is formed in one layer, it is necessary to increase the film thickness sufficiently to prevent penetration when the pinhole 43a is generated. In contrast, in the second embodiment, the silicon carbonitride film 55 and the silicon carbonitride film 56 are formed in separate steps. That is, in the second embodiment, the silicon carbonitride film is formed over two layers. Therefore, the pinhole generation position is shifted between the two layers of films, so that an effect of preventing pinhole penetration with a thin film as compared with the first embodiment can be obtained.

  Next, as shown in FIG. 23, the silicon carbonitride film 56 is patterned by using a photolithography technique and an etching technique. The patterning is performed so that the silicon carbonitride film 56 remains on the wiring 41 and its vicinity, and the silicon carbonitride film 56 does not remain in other regions. Thereby, it is possible to prevent the generation of pinholes penetrating through the silicon carbonitride films 55 and 56 formed on the wiring 41. In addition, since the silicon carbonitride film 56 is removed in regions other than the wiring 41 and the vicinity thereof, an increase in capacitance between the multilayer wirings can be suppressed.

  Subsequently, as shown in FIG. 24, a silicon oxide film 44, a silicon carbonitride film 45, a silicon oxide film 46, and a silicon nitride film 47 are sequentially formed on the silicon carbonitride films 55 and 56. Then, after patterning the silicon nitride film 47 as shown in FIG. 25, the silicon oxide film 44, the silicon carbonitride film 45, and the silicon oxide film are used using the photolithography technique and the etching technique as shown in FIG. A connection hole 48 penetrating 46 is formed. Thereafter, a cleaning process is performed in order to remove foreign matters attached to the semiconductor substrate 20.

  At this time, the silicon carbonitride film 56 is exposed at the bottom of the connection hole 48. A pinhole 56 a is formed in the exposed silicon carbonitride film 56, but since the silicon carbonitride film 55 is formed in the lower layer of the silicon carbonitride film 56, the pinhole 56 a is connected to the wiring 41. It has not penetrated until. Therefore, in the cleaning process described above, the cleaning liquid can be prevented from entering the wiring 41 through the pinhole 56a, and the disappearance of the copper film can be prevented.

  Next, as shown in FIG. 27, a wiring groove 49 is formed in the silicon oxide film 46 by etching using the patterned silicon nitride film 47 as a mask. Then, as shown in FIG. 28, the silicon carbonitride films 55 and 56 exposed at the bottom of the connection hole 48, the silicon carbonitride film 45 exposed at the bottom of the wiring groove 49, and the patterned silicon nitride film 47 are removed.

  Thereafter, as shown in FIG. 29, plug 52 and wiring 53 are formed by embedding tantalum film 50 and copper film 51 in connection hole 48 and wiring groove 49. In this way, a multilayer wiring can be formed.

(Embodiment 3)
In the second embodiment, the example in which the silicon carbonitride film serving as the diffusion preventing insulating film is formed in a two-layer structure has been described. In the third embodiment, an example will be described in which a silicon carbonitride film serving as a diffusion preventing insulating film is formed in a two-layer structure, and an etching stopper film is further formed therebetween.

  The steps up to FIG. 21 are the same as those in the second embodiment. Subsequently, as shown in FIG. 30, an etching stopper film 57 is formed on the silicon carbonitride film (first diffusion prevention insulating film) 55. This etching stopper film is made of, for example, a silicon oxide film, and has a film thickness of, for example, about 5 nm to about 10 nm.

  Thereafter, a silicon carbonitride film (second diffusion preventing insulating film) 56 as shown in FIG. 31 is formed on the etching stopper film 57. The film thickness of the silicon carbonitride film 56 is, for example, about 35 nm, and pinholes 56 a penetrating the silicon carbonitride film 56 are formed.

  Next, as shown in FIG. 32, the silicon carbonitride film 56 is patterned by using a photolithography technique and an etching technique. The patterning is performed so that the silicon carbonitride film 56 remains on the wiring 41 and its vicinity, and the silicon carbonitride film 56 does not remain in other regions. Thereby, it is possible to prevent the generation of pinholes penetrating through the silicon carbonitride films 55 and 56 formed on the wiring 41. In addition, since the silicon carbonitride film 56 is removed in regions other than the wiring 41 and the vicinity thereof, an increase in capacitance between the multilayer wirings can be suppressed.

  Here, the patterning of the silicon carbonitride film 56 is performed by etching. That is, the silicon carbonitride film 56 formed in the region other than the wiring 41 and the vicinity thereof is removed by etching. At this time, unlike the second embodiment, in the third embodiment, an etching stopper film 57 is formed under the silicon carbonitride film 56. Therefore, the etching of the silicon carbonitride film 56 is performed until the etching stopper film 57 is exposed, and the subsequent etching does not proceed. Thus, by forming the etching stopper film 57, the silicon carbonitride film 56 can be etched with good controllability. That is, by providing the etching stopper film 57, the silicon carbonitride film 56 can be etched uniformly. The etching stopper film 57 is not limited to the above-described silicon oxide film as long as it is a material that can have a high selectivity when the silicon carbonitride film 56 is etched.

  Subsequently, as shown in FIG. 33, a silicon oxide film 44, a silicon carbonitride film 45, a silicon oxide film 46, and a silicon nitride film 47 are sequentially formed on the silicon carbonitride film 56 and the etching stopper film 57. Then, after patterning the silicon nitride film 47, as shown in FIG. 34, a connection hole 48 that penetrates the silicon oxide film 44, the silicon carbonitride film 45, and the silicon oxide film 46 using a photolithography technique and an etching technique. Form. Thereafter, a cleaning process is performed in order to remove foreign matters attached to the semiconductor substrate 20.

  At this time, the silicon carbonitride film 56 is exposed at the bottom of the connection hole 48. A pinhole 56 a is formed in the exposed silicon carbonitride film 56, but since an etching stopper film 57 is formed in the lower layer of the silicon carbonitride film 56, the pinhole 56 a is connected to the wiring 41. Not penetrated until. Therefore, in the cleaning process described above, the cleaning liquid can be prevented from entering the wiring 41 through the pinhole 56a, and the disappearance of the copper film can be prevented.

  Next, as shown in FIG. 35, a wiring groove 49 is formed in the silicon oxide film 46 by etching using the patterned silicon nitride film 47 as a mask. 36, the silicon carbonitride films 55 and 56 exposed at the bottom of the connection hole 48, the silicon carbonitride film 45 exposed at the bottom of the wiring groove 49, and the patterned silicon nitride film 47 are removed.

  Thereafter, as shown in FIG. 37, plug 52 and wiring 53 are formed by embedding tantalum film 50 and copper film 51 in connection hole 48 and wiring groove 49. In this way, a multilayer wiring can be formed.

(Embodiment 4)
In the second embodiment, the example in which the silicon carbonitride film serving as the diffusion preventing insulating film is formed in a two-layer structure has been described. In the third embodiment, an example will be described in which a silicon carbonitride film serving as a diffusion-preventing insulating film is formed in a two-layer structure, and a diffusion-preventing insulating film is not formed in a region other than on the wiring and its neighboring region. .

  The steps up to FIG. 22 are the same as those in the second embodiment. Subsequently, as shown in FIG. 38, the silicon carbonitride film 55 and the silicon carbonitride film 56 are patterned by using a photolithography technique and an etching technique. The patterning is performed so that the silicon carbonitride films 55 and 56 remain only on the wirings 41 and 42 and their neighboring regions. In other words, the silicon carbonitride films 55 and 56 formed on most regions of the silicon oxide film 37 are removed.

  Here, the thickness of the diffusion preventing insulating film including the silicon carbonitride film 55 and the silicon carbonitride film 56 is sufficient to prevent the formation of a penetrating pin hole. Thereby, it is possible to prevent the generation of pinholes penetrating through the silicon carbonitride films 55 and 56 formed on the wiring 41. In addition, since the silicon carbonitride films 55 and 56 functioning as a diffusion preventing insulating film are formed on the wirings 41 and 42, diffusion of copper atoms from the wirings 41 and 42 can be prevented. . Further, since both the silicon carbonitride films 55 and 56 are removed in the regions other than the wirings 41 and 42 and their neighboring regions, an increase in capacitance between the multilayer wirings is suppressed as compared with the second embodiment. can do.

  Subsequently, as shown in FIG. 39, a silicon oxide film 44, a silicon carbonitride film 45, a silicon oxide film 46, and a silicon nitride film 47 are sequentially formed on the silicon carbonitride films 55 and 56 and the silicon oxide film 37. . Then, after patterning the silicon nitride film 47, as shown in FIG. 40, a connection hole 48 that penetrates the silicon oxide film 44, the silicon carbonitride film 45, and the silicon oxide film 46 using a photolithography technique and an etching technique. Form. Thereafter, a cleaning process is performed in order to remove foreign matters attached to the semiconductor substrate 20.

  At this time, the silicon carbonitride film 56 is exposed at the bottom of the connection hole 48. A pinhole 56 a is formed in the exposed silicon carbonitride film 56, but since the silicon carbonitride film 55 is formed in the lower layer of the silicon carbonitride film 56, the pinhole 56 a is connected to the wiring 41. It has not penetrated until. Therefore, in the cleaning process described above, the cleaning liquid can be prevented from entering the wiring 41 through the pinhole 56a, and the disappearance of the copper film can be prevented.

  Next, as shown in FIG. 41, a wiring groove 49 is formed in the silicon oxide film 46 by etching using the patterned silicon nitride film 47 as a mask. 42, the silicon carbonitride films 55 and 56 exposed at the bottom of the connection hole 48, the silicon carbonitride film 45 exposed at the bottom of the wiring groove 49, and the patterned silicon nitride film 47 are removed.

  Thereafter, as shown in FIG. 43, plug 52 and wiring 53 are formed by embedding tantalum film 50 and copper film 51 in connection hole 48 and wiring groove 49. In this way, a multilayer wiring can be formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, the silicon carbonitride film has been described as an example of the diffusion preventing insulating film for preventing the diffusion of copper atoms. However, the present invention is not limited to this. May be.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is the figure which showed the manufacturing process of the semiconductor device which forms wiring using the damascene method on the semiconductor substrate with a foreign material. FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 1; It is sectional drawing which showed a mode that the cleaning liquid permeated into the wiring from the pinhole and copper forming the wiring disappeared. It is sectional drawing which showed the semiconductor device in Embodiment 1 of this invention. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 18; FIG. 20 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 19; 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 26; FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 28; 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the third embodiment. FIG. FIG. 31 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 30; FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 31; FIG. 33 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 32; FIG. 34 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 33; FIG. 35 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 34; FIG. 36 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 35; FIG. 37 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 36; FIG. 10 is a cross sectional view showing a manufacturing step of the semiconductor device in the fourth embodiment. FIG. 39 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 38; FIG. 40 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 39; FIG. 41 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 40; FIG. 42 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 41; FIG. 43 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 42;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating film 2 Insulating film 3 Insulating film 4 Wiring 4a Conductive barrier film 4b Copper film 5 Insulating film 5a Pinhole 6 Insulating film 7 Insulating film 8 Insulating film 9 Insulating film 10 Connection hole 11 Foreign material 12 Wiring groove 20 Semiconductor substrate 21 Element Isolation region 22 P-type well 23 Gate insulating film 24 Gate electrode 24a Polysilicon film 25 Low-concentration n-type impurity diffusion region 26 Low-concentration n-type impurity diffusion region 27 Side wall 28 High-concentration n-type impurity diffusion region 29 High-concentration n-type impurity Diffusion region 30 Cobalt silicide film 31 Silicon nitride film 32 Silicon oxide film 33 Contact hole 34a Titanium nitride film 34b Tungsten film 35 Plug 36 Silicon carbonitride film 37 Silicon oxide film 38 Wiring groove 39 Tantalum film 40 Copper film 40a Seed film 41 Wiring 42 Wiring 43 Silicon carbonitride film 3a pinhole 44 silicon oxide film 45 silicon carbonitride film 46 silicon oxide film 47 silicon nitride film 48 connection hole 49 wiring groove 50 tantalum film 51 copper film 51a seed film 52 plug 53 wiring 55 silicon carbonitride film 55a pinhole 56 carbonitriding Silicon film 56a Pinhole 57 Etching stopper film

Claims (5)

(A) an insulating film formed on the semiconductor substrate;
(B) a metal wiring layer embedded in the insulating film;
(C) a diffusion preventing insulating film formed on the insulating film including the metal wiring layer;
(D) including a plug that penetrates the diffusion-preventing insulating film and connects to the metal wiring layer;
The diffusion preventing insulating film formed on the metal wiring layer and on the insulating film in the vicinity of the metal wiring layer has a thickness for preventing the diffusion formed on the insulating film apart from the metal wiring layer. A semiconductor device that is thicker than the thickness of the insulating film. (A) an insulating film formed on the semiconductor substrate;
(B) a metal wiring layer embedded in the insulating film;
(C) a first diffusion preventing insulating film formed on the insulating film and on the metal wiring layer;
(D) a second diffusion preventing insulation formed on the first diffusion preventing insulating film on the metal wiring layer and on the first diffusion preventing insulating film on the insulating film near the metal wiring layer; A membrane,
(E) A semiconductor device comprising: a plug that penetrates the first diffusion preventing insulating film and the second diffusion preventing insulating film and is connected to the metal wiring layer. (A) an insulating film formed on the semiconductor substrate;
(B) a metal wiring layer embedded in the insulating film;
(C) a first diffusion preventing insulating film formed on the insulating film and on the metal wiring layer;
(D) a second diffusion preventing insulation formed on the first diffusion preventing insulating film on the metal wiring layer and on the first diffusion preventing insulating film on the insulating film near the metal wiring layer; A membrane,
(E) an etching stopper film formed between the first diffusion preventing insulating film and the second diffusion preventing insulating film;
(F) A semiconductor device comprising: a first diffusion preventing insulating film; a second diffusion preventing insulating film; and a plug that penetrates the etching stopper film and connects to the metal wiring layer. (A) an insulating film formed on the semiconductor substrate;
(B) a metal wiring layer embedded in the insulating film;
(C) a diffusion preventing insulating film formed on the metal wiring layer and on the insulating film in the vicinity of the metal wiring layer;
(D) including a plug that penetrates the diffusion-preventing insulating film and connects to the metal wiring layer;
The diffusion preventing insulating film is a semiconductor device having a thickness that prevents the generation of pinholes penetrating the diffusion preventing insulating film. (A) forming an insulating film on the semiconductor substrate;
(B) forming a metal wiring layer so as to be embedded in the insulating film;
(C) forming a first diffusion preventing insulating film on the insulating film and the metal wiring layer;
(D) forming an etching stopper film on the first diffusion preventing insulating film;
(E) forming a second diffusion preventing insulating film on the etching stopper film;
(F) etching the second diffusion preventing insulating film to form the second diffusion preventing insulating film on the metal wiring layer via the first diffusion preventing insulating film and the etching stopper film; And a step of leaving the second diffusion preventing insulating film on the insulating film in the vicinity of the metal wiring layer via the first diffusion preventing insulating film and the etching stopper film.

Images