JP2006253460A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device and a manufacturing method thereof wherein such wiring faultiness as a short circuit generated between its wirings is prevented. <P>SOLUTION: The manufacturing method of the semiconductor device has a process for depositing first successively on a semiconductor substrate 101 an interlayer insulation film 102 and a diffusion preventing insulation film 103, a process for forming then wiring grooves 104 in the diffusion preventing insulation film 103 and the interlayer insulation film 102, a process for forming next a barrier metal film 105a to cover the wiring grooves 104 with it, a process for removing next in a polishing way the barrier metal film 105a present on the diffusion preventing insulation film 103 to leave each barrier metal 105 in each wiring groove 104, a process for forming next a Cu film 106a to fill it into the wiring grooves 104, a process for removing next in a polishing way the Cu film 106a present on the diffusion preventing insulation film 103 to leave each Cu film 106 in each wiring groove 104 having each recess B, a process for forming next a cap film 108a to fill it into the recesses B, and a process for polishing thereafter the cap film 108a to leave selectively in each recess B each cap film 108. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having copper wiring and a method for manufacturing the same.

  In recent years, along with the high integration of semiconductor integrated circuits and the reduction in chip size, miniaturization and multilayering of wiring have been promoted. As the pitch between wirings is narrowed, the RC delay due to an increase in wiring resistance and an increase in capacitance between wirings cannot be ignored. For this reason, it is necessary to reduce the electric parasitic resistance generated in the wiring when the miniaturization of the semiconductor integrated circuit is advanced. In order to reduce the electrical parasitic resistance of the wiring, it is necessary to reduce the specific resistance of the wiring material.

For devices with a gate length of 0.13 μm, Al (aluminum) has been changed to Cu (copper) in order to reduce the specific resistance of the wiring material. By adopting Cu wiring by the damascene method, the specific resistance of the wiring has been reduced to about 2/3 of the conventional one. However, in Cu wiring, Cu atoms diffuse quickly into an insulating film such as a SiO ₂ film (silicon oxide film), so that Cu atoms enter the transistor and cause breakdown of the transistor. In addition, when Cu atoms diffuse between the wirings and an unexpected cross-linking structure is formed between the wirings, a defective phenomenon such as deterioration of dielectric strength between the wirings occurs. It was necessary to provide a barrier film for preventing the diffusion of Cu atoms around. Currently, a conductive barrier film (hereinafter referred to as WN (tungsten nitride), TaN (tantalum nitride), TiN (titanium nitride) or the like is generally formed on the bottom and side surfaces of the Cu film to cover the periphery of the wiring Cu film. In addition, an insulating barrier film made of SiN (silicon nitride) or SiC (silicon carbide) is used on the upper surface of the Cu film (for example, Patent Document 1). reference).

  In general, since Cu wiring is difficult to etch compared with Al wiring, the damascene method is used as a manufacturing method. That is, after forming a wiring groove having a wiring pattern in the deposited interlayer insulating film, the bottom and side surfaces of the wiring groove are covered with a barrier metal film, and subsequently, the wiring groove is embedded with a Cu film by electrolytic plating, The Cu film and the barrier metal film are polished and planarized by a CMP (Chemical Mechanical Polishing) method to complete the Cu wiring.

  Hereinafter, a conventional method for manufacturing a semiconductor device having a copper wiring will be described.

  FIG. 5A to FIG. 6B are cross-sectional views showing respective steps of a conventional method for manufacturing a semiconductor device having copper wiring. In FIGS. 5A to 6B, the left side shows a region with a narrow wiring interval, and the right side shows a region with a wide wiring interval.

  First, an interlayer insulating film 502 is formed on a semiconductor substrate 501 as shown in FIG.

  Next, as shown in FIG. 5B, a wiring trench 503 is formed in the interlayer insulating film 502.

  Next, as shown in FIG. 5C, a barrier metal film 504a is deposited on the interlayer insulating film 502 so as to cover the wiring groove 503, and then the wiring groove 503 is buried on the barrier metal film 504a. A Cu film 505a is formed.

  Next, as shown in FIG. 5D, the Cu film 505a and the barrier metal film 504a protruding from the wiring trench 503 are polished by CMP to expose the interlayer insulating film 502 in portions other than the wiring trench 503. Then, leaving the Cu film 505 and the barrier metal film 504 in the wiring trench 503, a metal wiring 506 made of the barrier metal film 504 and the Cu film 505 is formed. At this time, even after the interlayer insulating film 502 is exposed by polishing, polishing is continued until the barrier metal film 504 is almost completely removed from the interlayer insulating film 502 (overetching). Therefore, the surface of the Cu film 505 in the wiring groove 503 is depressed, and a recess A is formed.

  Next, as shown in FIG. 5E, a cap film 507 a is formed on the interlayer insulating film 502 so as to fill the depression A on the Cu film 505 in the wiring groove 503.

  Next, as shown in FIG. 6A, the cap film 507 a protruding from the wiring groove 503 is etched back to expose the interlayer insulating film 502 in portions other than the wiring groove 503, and the cap film is formed in the wiring groove 503. Leave 507. As a result, the Cu film 505 is surrounded by the barrier metal film 504 and the cap film 507.

Next, as shown in FIG. 6B, an insulating film 508 is deposited on the entire surface of the semiconductor substrate 501.
Japanese Patent Application Laid-Open No. 10-188952

  However, the conventional semiconductor device having a copper wiring and its manufacturing method have the following problems.

  In the conventional method for manufacturing a semiconductor device having a copper wiring, in the step shown in FIG. 5D, a first polishing for removing the Cu film 505, a second polishing for removing the barrier metal film 504, And subsequent over-polishing. The second polishing includes a large amount of abrasive grains for polishing the barrier metal film 504, which is a hard film, and the subsequent overpolishing is performed using the same abrasive as the second polishing. Here, in the second polishing and overpolishing, the Cu film 505 is exposed above the wiring trench 503. Therefore, in the second polishing and overpolishing, the Cu film 505 that is softer than the barrier metal film 504 is scratched, and metal scraps are generated. When this metal scrap is rubbed by polishing and extends onto the interlayer insulating film 502 to form a bridge structure between adjacent wirings, a short circuit between the wirings occurs.

  In addition, so-called dishing occurs by over-polishing subsequent to the first polishing and the second polishing. When dishing occurs, the recess of the Cu film 505 increases in a region where the wiring interval is narrow, and the recess of the Cu film 505 decreases in a region where the wiring interval is wide. As a result, the recess A on the Cu film 505 in the wiring trench 503 becomes shallow in a region where the wiring interval is wide, and the cap film 507 is not sufficiently embedded. For this reason, the Cu film 505 is not reliably covered with the cap film 507 in a region where the wiring interval is wide, and the Cu atoms ooze out from the Cu film 505 easily.

  In the step shown in FIG. 6B, the interface between the interlayer insulating film 502 and the insulating film 508 is at the same position as the upper end of the side wall of the barrier metal film 504. Here, the interface between the interlayer insulating film 502 and the insulating film 508 becomes a main diffusion path of Cu atoms when Cu atoms of the Cu film 505 ooze out. Therefore, when Cu atoms ooze out from the connection portion between the barrier metal film 504 and the cap film 507 surrounding the Cu film 505, the Cu atoms enter the diffusion path as they are, and the diffusion of Cu atoms is prevented. It tends to happen.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same by preventing occurrence of wiring defects such as a short circuit between wirings due to cross-linking structure, Cu atom leaching, and diffusion.

  A semiconductor device according to the present invention includes an insulating film formed on a semiconductor substrate, a wiring groove formed in the insulating film, a conductive barrier film formed so as to cover the wiring groove, and a conductive barrier film A metal film formed so as to fill the wiring trench from above and a cap film formed on the metal film in the wiring trench, and the insulating film includes an interlayer insulating film formed on the semiconductor substrate, And a first diffusion preventing insulating film formed on the interlayer insulating film, and a connecting portion between the cap film and the conductive barrier film is located above the interface between the interlayer insulating film and the diffusion preventing film. .

  As a result, the connecting portion between the cap film and the conductive barrier film is not directly connected to the interface between the interlayer insulating film and the diffusion prevention film. Atoms can be prevented from entering, and leaching of metal atoms into the interlayer insulating film can be prevented.

  In the semiconductor device according to the present invention, the upper end portion of the cap film is located below the upper end portion of the conductive barrier film.

  Thereby, since the cap film is sufficiently embedded in the wiring groove, the metal film can be reliably covered with the cap film.

  Further, in the semiconductor device according to the present invention, the diffusion preventing insulating film fills the interlayer insulating film between the metal wirings on the metal wiring formed of the metal film, the conductive barrier film, and the cap film formed in the wiring trench. It is formed as follows.

  As a result, the connection between the cap film and the conductive barrier film is covered with the diffusion prevention film, and the connection between the cap film and the conductive barrier film is directly connected to the interface between the interlayer insulating film and the diffusion prevention film. Therefore, it is possible to prevent metal atoms from entering the interface between the interlayer insulating film serving as a diffusion path and the diffusion preventing film, and to prevent the metal atoms from seeping into the interlayer insulating film.

  In the semiconductor device according to the present invention, the diffusion prevention insulating film includes at least one of SiC, SiN, SiCN, and SiCO.

  In the semiconductor device according to the present invention, the conductive barrier film is made of any one of Ta, TaN, Ta and TaN, Ti, TiN, and Ti and TiN.

  In the semiconductor device according to the present invention, the cap film is made of any one of W, Ta, TaN, Ta and TaN, Ti, TiN, Ti, TiN, Co alloy, and Ni alloy. .

  The method for manufacturing a semiconductor device according to the present invention includes: (a) forming an insulating film on a semiconductor substrate; (b) forming a wiring groove in the insulating film; and (b) covering the wiring groove on the insulating film. A step of forming a conductive barrier film as described above (c), a step of polishing the conductive barrier film to leave the conductive barrier film on the bottom and side surfaces of the wiring groove, and exposing the insulating film to portions other than the wiring groove ( d) and a step (e) of forming a metal film so as to embed the wiring groove on the insulating film after the step (d), and polishing the metal film to leave the metal film in the wiring groove, And a step (f) of exposing the insulating film in the portion.

  Accordingly, since no metal film is deposited in the polishing step (d) of the conductive barrier film, it is possible to avoid the occurrence of scratches on the metal film due to the polishing of the conductive barrier film. Occurrence can be prevented.

  In the method for manufacturing a semiconductor device according to the present invention, the step (a) includes a step (a1) of forming an interlayer insulating film on the semiconductor substrate and a first diffusion preventing insulating film on the interlayer insulating film. Forming (a2).

  In addition, the method for manufacturing a semiconductor device according to the present invention includes a step (g) of selectively forming a cap film on the metal film in the wiring trench after the step (f).

  In the method of manufacturing a semiconductor device according to the present invention, the step (g) includes a step (g1) of depositing a cap film on the insulating film so as to fill the metal film in the wiring trench, And a step (g2) of polishing to leave a cap film on the metal film in the wiring groove and exposing the insulating film to a portion other than the wiring groove.

  In addition, the method for manufacturing a semiconductor device according to the present invention includes a step (h) of forming an insulating film so as to cover the entire surface of the semiconductor substrate after the step (g).

  Also, in the method of manufacturing a semiconductor device according to the present invention, after the step (g), the step (i) of removing the first diffusion preventing insulating film and exposing the interlayer insulating film is formed in the wiring trench. And a step (j) of forming a second diffusion preventing insulating film on the metal wiring composed of the metal film, the conductive barrier film, and the cap film so as to fill the interlayer insulating film between the metal wirings.

  Thereby, the connection portion between the cap film and the conductive barrier film is covered with the second diffusion prevention film, and the connection portion between the cap film and the conductive barrier film is formed between the interlayer insulating film and the second diffusion prevention film. Since it is not directly connected to the interface, metal atoms can be prevented from entering the interface between the interlayer insulation film serving as the diffusion path and the second diffusion prevention film, and the metal atoms can seep into the interlayer insulation film. Can be prevented.

  In the method for manufacturing a semiconductor device according to the present invention, the conductive barrier film is made of any one of Ta, TaN, Ta and TaN, Ti, TiN, and Ti and TiN.

  In the method for manufacturing a semiconductor device according to the present invention, the first diffusion preventing insulating film and the second diffusion preventing insulating film include at least one of SiC, SiN, SiCN, and SiCO.

  In the method for manufacturing a semiconductor device according to the present invention, the cap film is any one of W, Ta, TaN, Ta and TaN, Ti, TiN, Ti, TiN, Co alloy, and Ni alloy. It consists of one.

  According to the present invention, it is possible to reliably embed the cap film on the Cu film without causing scratches in the Cu, and to keep the Cu film away from the diffusion path. It is possible to prevent the occurrence of wiring defects such as a short circuit between wirings by preventing lead-out and diffusion.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below. FIG. 1A to FIG. 2D are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. In FIG. 1A to FIG. 2D, the left side shows a region with a narrow wiring interval, and the right side shows a region with a wide wiring interval.

  First, as shown in FIG. 1A, an interlayer insulating film 102 is formed with a thickness of about 450 nm on a semiconductor substrate 101 by a CVD method. Here, as the interlayer insulating film 102, SiOC (silicon oxide carbide) is used. Subsequently, a diffusion preventing insulating film 103 is formed to a thickness of about 50 nm on the interlayer insulating film 102 by a CVD method. Here, SiC is used as the diffusion preventing insulating film 103.

  Next, as shown in FIG. 1B, a photoresist (not shown) having a wiring pattern is formed on the diffusion prevention insulating film 103 by photolithography. Next, by using this photoresist as an etching mask, the diffusion preventing insulating film 103 and the interlayer insulating film 102 are removed by a dry etching method to form a wiring groove 104. Thereafter, the photoresist is removed by ashing.

  Next, as shown in FIG. 1C, a barrier metal film 105a is formed to a thickness of about 30 nm on the diffusion prevention insulating film 103 so as to cover the wiring groove 104 by sputtering. Here, Ti (titanium) is used as the barrier metal film 105a.

  Next, as shown in FIG. 1D, the barrier metal film 105a protruding from the wiring groove 104 is polished by CMP to expose the diffusion prevention insulating film 103 in a portion other than the wiring groove 104, thereby forming the wiring groove. A barrier metal film 105 is left in 104.

Next, as shown in FIG. 1E, a seed Cu film (not shown) is formed on the diffusion prevention insulating film 103 so as to cover the wiring trench 104 from above the barrier metal 105 by sputtering. . Thereafter, a Cu film 106a is formed by electrolytic plating so as to fill the wiring trench 104 from above the seed Cu film. Thereafter, the seed Cu film and the Cu film 106a are integrated by heat treatment at 450 ° C. for 30 minutes in an N ₂ / H ₂ atmosphere.

  Next, as shown in FIG. 2A, the Cu film 106 a protruding from the wiring groove 104 is polished by CMP to expose the diffusion preventing insulating film 103 in a portion other than the wiring groove 104, and the wiring groove 104. A metal wiring 107 made of a barrier metal film 105 and a Cu film 106 is formed, leaving the Cu film 106 therein. At this time, even after the diffusion prevention insulating film 103 is exposed by polishing, the polishing is continued until the Cu film 106 is almost completely removed from the diffusion prevention insulating film 103 (overetching). Therefore, the surface of the Cu film 106 in the wiring trench 104 is depressed and a dent B is formed.

  Next, as shown in FIG. 2B, a cap film 108a is formed on the diffusion prevention insulating film 103 so as to fill the depression B on the Cu film 106 in the wiring groove 104 by sputtering. Here, Ti is used for the cap film 108a.

  Next, as shown in FIG. 2C, the cap film 108 a protruding from the wiring groove 104 is polished by CMP to expose the diffusion preventing insulating film 103 in a portion other than the wiring groove 104, and the wiring groove 104. The cap film 108 is selectively left inside.

  Next, as shown in FIG. 2D, an insulating film 109 is deposited to a thickness of about 80 nm on the entire surface of the semiconductor substrate 101 by the CVD method. Here, SiN is used as the insulating film 109.

  In the first embodiment, the polishing process of the barrier metal film 105 shown in FIG. 1D and the polishing process of the Cu film 106 shown in FIG. Thereby, since the Cu film 106 is not deposited when the barrier metal film 105 is polished, it is possible to avoid the occurrence of scratches in the Cu film 106 due to the polishing of the barrier metal film 105 and to prevent the occurrence of a short circuit between wirings. be able to.

  In the first embodiment, when the Cu film 106 is polished, the Cu film 106 can be polished in a state where the barrier metal film 105 has already been removed from the diffusion preventing insulating film 103. Therefore, the occurrence of dishing can be controlled, and the recess B having a relatively uniform depth regardless of the wiring width interval can be formed on the Cu film 106 in the wiring groove 104. As a result, the cap film 108 is sufficiently embedded in the recess B, and the upper end portion of the cap film 108 is positioned below the upper end portion of the barrier metal film 105, so that the Cu film 106 can be reliably covered with the cap film 108.

  In the first embodiment, single damascene has been described. However, the present invention can also be used for dual damascene in which a via hole and a wiring groove are formed and a via plug and a wiring are simultaneously formed. Further, although SiC is used as the diffusion preventing insulating film 103, SiN, SiCN (silicon carbonitride), or SiCO may be used. Further, Ti is used as the barrier metal film 105a, but TiN, a laminated film of Ti and TiN, Ta (tantalum), TaN, or a laminated film of Ta and TaN may be used. Further, although Ti is used as the cap film 108a, W (tungsten), TiN, a laminated film of Ti and TiN, Ta, TaN, a laminated film of Ta and TaN, a Co alloy, or a Ni alloy may be used. Good. When W is used for the cap film 108a, the adhesion with the Cu film 106 is enhanced. For this reason, EM (electromigration) tolerance etc. improve and the reliability of wiring improves.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below. FIG. 3A to FIG. 4E are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. In FIGS. 3A to 4E, the left side shows a region with a narrow wiring interval, and the right side shows a region with a wide wiring interval.

  First, as shown in FIG. 3A, an interlayer insulating film 202 is formed with a thickness of about 450 nm on a semiconductor substrate 201 by a CVD method. Here, SiOC is used for the interlayer insulating film 202. Subsequently, a first diffusion prevention insulating film 203 is formed to a thickness of about 50 nm on the interlayer insulating film 202 by a CVD method. Here, SiC is used as the first diffusion preventing insulating film 203.

  Next, as shown in FIG. 3B, a photoresist (not shown) having a wiring pattern is formed on the first diffusion prevention insulating film 203 by photolithography. Next, by using this photoresist as an etching mask, the first diffusion preventing insulating film 203 and the interlayer insulating film 202 are removed by dry etching to form a wiring groove 204. Thereafter, the photoresist is removed by ashing.

  Next, as shown in FIG. 3C, a barrier metal film 205a is formed to a thickness of about 30 nm on the first diffusion prevention insulating film 203 so as to cover the wiring groove 204 by sputtering. Here, Ti is used for the barrier metal film 205a.

  Next, as shown in FIG. 3D, the barrier metal film 205 a protruding from the wiring trench 204 is polished by CMP to expose the first diffusion prevention insulating film 203 in a portion other than the wiring trench 204. The barrier metal film 205 is left in the wiring trench 204.

Next, as shown in FIG. 3E, a seed Cu film (not shown) is formed on the first diffusion prevention insulating film 203 so as to cover the wiring trench 204 from above the barrier metal 205 by sputtering. Form a film. Thereafter, a Cu film 206a is formed by electrolytic plating so as to fill the wiring groove 204 from above the seed Cu film. Thereafter, the seed Cu film and the Cu film 206a are integrated by a heat treatment at 450 ° C. for 30 minutes in an N ₂ / H ₂ atmosphere.

  Next, as shown in FIG. 4A, the Cu film 206a protruding from the wiring trench 204 is polished by CMP to expose the first diffusion prevention insulating film 203 in a portion other than the wiring trench 204, A metal wiring 207 composed of a barrier metal film 205 and a Cu film 206 is formed leaving the Cu film 206 in the wiring trench 204. At this time, even after the first diffusion prevention insulating film 203 is exposed by polishing, the polishing is continued until the Cu film 206 is almost completely removed from the first diffusion prevention insulating film 203 (overetching). . Therefore, the surface of the Cu film 206 in the wiring trench 204 is depressed, and a dent B is formed.

  Next, as shown in FIG. 4B, a cap film 208a is formed on the first diffusion prevention insulating film 203 so as to fill the depression B on the Cu film 206 in the wiring trench 204 by sputtering. Here, Ti is used for the cap film 208a.

  Next, as shown in FIG. 4C, the cap film 208a protruding from the wiring trench 204 is polished by CMP to expose the first diffusion prevention insulating film 203 in a portion other than the wiring trench 204, The cap film 208 is selectively left in the wiring trench 204.

Next, as shown in FIG. 4D, the first diffusion prevention insulating film 203 is removed by wet etching to expose the interlayer insulating film 202. Here, as the wet etching solution, H ₃ PO ₄ (phosphoric acid), HF (hydrofluoric acid), hydrofluoric acid, or the like is used. As a result, the position of the connection portion between the barrier metal film 205 and the cap film 208 becomes higher than the upper surface of the interlayer insulating film 202.

  Next, as shown in FIG. 4E, a second diffusion-preventing insulating film 209 is deposited on the entire surface of the semiconductor substrate 201 by a CVD method so as to fill the space between the metal wirings 207 with a thickness of about 150 nm. Here, SiC is used as the second diffusion prevention insulating film 209.

  In the second embodiment, the polishing process of the barrier metal film 205 shown in FIG. 3D and the polishing process of the Cu film 206 shown in FIG. 4A are separate processes. Thereby, since the Cu film 206 is not deposited at the time of polishing the barrier metal film 205, it is possible to avoid the occurrence of scratches on the Cu film 206 due to the polishing of the barrier metal film 205, and to prevent the occurrence of a short circuit between wirings. be able to.

  In the second embodiment, when the Cu film 206 is polished, the Cu film 206 can be polished with the barrier metal film 205 already removed from the diffusion prevention insulating film 203. Therefore, the occurrence of dishing can be controlled, and the recess B having a relatively uniform depth regardless of the wiring width interval can be formed on the Cu film 206 in the wiring groove 204. As a result, the cap film 208 is sufficiently embedded in the recess B, and the upper end portion of the cap film 208 is positioned below the upper end portion of the barrier metal film 205, so that the Cu film 206 can be reliably covered with the cap film 208.

  Furthermore, in the second embodiment, the connection portion between the barrier metal film 205 and the cap film 208 is covered with the diffusion preventing insulating film 209, and the connection portion between the barrier metal film 205 and the cap film 208 becomes a diffusion path. It is not directly connected to the interface between the interlayer insulating film 202 and the diffusion preventing insulating film 203. That is, the portion where the Cu atoms ooze out and the diffusion path are not directly connected. Thereby, even if Cu atoms ooze out, it is difficult to spread in the diffusion path, and it is possible to prevent the occurrence of leakage current and the occurrence of a short circuit between the wirings due to the diffusion of Cu atoms.

  In the second embodiment, the single damascene has been described. However, the present invention can also be used for a dual damascene in which a via hole and a wiring groove are formed and a via plug and a wiring are simultaneously formed. Further, although SiC is used as the diffusion preventing insulating film 203, SiN, SiCN, or SiCO may be used. Further, although Ti is used as the barrier metal film 205a, TiN, a laminated film of Ti and TiN, Ta, TaN, or a laminated film of Ta and TaN may be used. Further, although Ti is used as the cap film 208a, W, TiN, a laminated film of Ti and TiN, Ta, TaN, a laminated film of Ta and TaN, a Co alloy, or a Ni alloy may be used. When W is used for the cap film 208a, the adhesion with the Cu film 206 is enhanced. For this reason, EM tolerance etc. improve and the reliability of wiring improves.

  The present invention is useful for a semiconductor device having a copper wiring and a method for manufacturing the same.

Sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows each process of the manufacturing method of the semiconductor device which has the conventional copper wiring Sectional drawing which shows each process of the manufacturing method of the semiconductor device which has the conventional copper wiring

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 Interlayer insulating film 103 Diffusion prevention insulating film 104 Wiring groove 105a Barrier metal film 105 Barrier metal film 106a Cu film 106 Cu film 107 Metal wiring 108a Cap film 108 Cap film 109 Insulating film 201 Semiconductor substrate 202 Interlayer insulating film 203 1 diffusion prevention insulating film 204 wiring groove 205a barrier metal film 205 barrier metal film 206a Cu film 206 Cu film 207 metal wiring 208a cap film 208 cap film 209 second diffusion prevention insulating film B

Claims (15)

An insulating film formed on the semiconductor substrate;
A wiring groove formed in the insulating film;
A conductive barrier film formed to cover the wiring trench;
A metal film formed so as to fill the wiring trench from above the conductive barrier film;
A cap film formed on the metal film in the wiring trench,
The insulating film includes an interlayer insulating film formed on the semiconductor substrate and a first diffusion preventing insulating film formed on the interlayer insulating film, and includes a cap film and a conductive barrier film. The semiconductor device according to claim 1, wherein the connecting portion is located above an interface between the interlayer insulating film and the diffusion prevention film. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein an upper end portion of the cap film is located lower than an upper end portion of the conductive barrier film. The semiconductor device according to claim 1 or 2,
The diffusion preventing insulating film is formed on the metal wiring formed of the metal film, the conductive barrier film, and the cap film formed in the wiring groove so as to fill the interlayer insulating film between the metal wirings. A semiconductor device which is characterized by being made. In the semiconductor device as described in any one of Claims 1-3,
The diffusion preventing insulating film includes at least one of SiC, SiN, SiCN, and SiCO. In the semiconductor device according to claim 1,
The semiconductor device is characterized in that the conductive barrier film is formed of any one of Ta, TaN, Ta and TaN, Ti, TiN, or Ti and TiN. In the semiconductor device according to any one of claims 1 to 5,
The cap film is made of any one of W, Ta, TaN, Ta and TaN, Ti, TiN, Ti, TiN, Co alloy, and Ni alloy. A step of forming an insulating film on the semiconductor substrate;
Forming a wiring trench in the insulating film; and (b).
Forming a conductive barrier film on the insulating film so as to cover the wiring trench; and (c),
Polishing the conductive barrier film to leave a conductive barrier film on the bottom and side surfaces of the wiring groove, and exposing the insulating film in a portion other than the wiring groove;
After the step (d), a step (e) of forming a metal film so as to fill the wiring groove on the insulating film;
And a step (f) of polishing the metal film to leave the metal film in the wiring groove and exposing the insulating film to a portion other than the wiring groove. In the manufacturing method of the semiconductor device according to claim 7,
The step (a) includes a step (a1) of forming an interlayer insulating film on the semiconductor substrate and a step (a2) of forming a first diffusion prevention insulating film on the interlayer insulating film. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 7 or 8,
A step (g) of selectively forming a cap film on the metal film in the wiring groove after the step (f);
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 9,
The step (g) includes a step (g1) of depositing a cap film on the insulating film so as to fill the metal film in the wiring trench.
Polishing the cap film to leave the cap film on the metal film in the wiring groove, and exposing the insulating film to a portion other than the wiring groove (g2). Device manufacturing method. In the manufacturing method of the semiconductor device according to claim 9 or 10,
After the step (g), the method for manufacturing a semiconductor device includes a step (h) of forming an insulating film so as to cover the entire surface of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 9 or 10,
After the step (g), the step (i) of removing the first diffusion preventing insulating film to expose the interlayer insulating film, the metal film and the conductive barrier film formed in the wiring trench And a step (j) of forming a second diffusion prevention insulating film on the metal wiring made of the cap film so as to fill the interlayer insulating film between the metal wirings. Production method. In the manufacturing method of the semiconductor device as described in any one of Claims 7-12,
The method of manufacturing a semiconductor device, wherein the conductive barrier film is formed of any one of a stacked layer of Ta, TaN, Ta and TaN, Ti, TiN, or a stacked layer of Ti and TiN. In the manufacturing method of the semiconductor device as described in any one of Claims 8-13,
The method of manufacturing a semiconductor device, wherein the first diffusion preventing insulating film and the second diffusion preventing insulating film include at least one of SiC, SiN, SiCN, and SiCO. In the manufacturing method of the semiconductor device as described in any one of Claims 9-14,
The cap film is made of any one of W, Ta, TaN, Ta and TaN, Ti, TiN, Ti, TiN, Co alloy, and Ni alloy. Method.

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