TW201533815A - Reverse wire-bonding structure in semiconductor package - Google Patents

Abstract

Disclosed is a reverse wire-bonding structure in semiconductor package, comprising a substrate, a chip, a stud bump and a bonding wire. The stud bump is disposed on a bonding pad of the chip and has a bonding base and a wire-cut platform protruded from the center of the bonding base, where the bonding base has an edge ring exposed from the wire-cut platform. The bonding wire is formed by wire-bonding and connects from an connect pad on the substrate to the stud bump. The bonding wire has a wire-bumped end and a wire-stitch end. The wire-bumped end is located on the connect pad. The wire-stitch end is bonded to a portion of the edge ring toward the connect pad so that the bonding wire does not extend over the center of the bonding base.

Description

Inverse wire structure of semiconductor package

The present invention relates to a semiconductor package structure, and more particularly to a reverse-wire structure of a semiconductor package, and is particularly applicable to a wire bonding connection of a stacked thin wafer.

The thinning and miniaturization of the semiconductor package structure is inevitable. In particular, the multi-wafer stacked package product not only needs to use a thinned wafer but also needs to perform a reverse wire-bonding process corresponding thereto to reduce the wire bonding height of the bonding wire. At present, the difference between the reverse line (or reverse line) process and the positive line process is that the positive line process is connected to the substrate by the wafer, and the reverse line process is connected to the wafer by the substrate, when the reverse line process is used. The height of the line arc can be reduced to a minimum, so the reverse line process can reduce the package thickness of the wire connection wafer, but the bonding force between the wire end of the wire and the wafer pad in the reverse wire process is relatively weak. Recently, some people have It is proposed to pre-stack a stud bump on the wafer pad to increase the bond strength of the bond wire on the wafer.

1 is a diagram showing a reverse-wire structure 100 of a conventional semiconductor package, and FIG. 2 is a view showing a wire bonding state of a reverse-wire structure 100 of a conventional semiconductor package. A bonding wire 140 is electrically connected to the pad 111 of the substrate 110 and the pad 121 of the wafer 120. The bonding wire 140 has a wire end bump end 141 on the pad 111 and a wire tail end 142 electrically connected to the bonding pad 121. The bonding wire 121 is pre-set on the bonding pad 121 by a ball bonding technique. hit Line bumps 130. The bonding base 131 of the wire bonding block 130 is bonded to the bonding pad 121, and a wire drawing platform 132 is cut by a soldering pin (or a wire-punching porcelain nozzle), and the wire tail end 142 of the bonding wire 140 is bonded to the wire bonding wire. Above the section 132 of the bump 130. As shown in FIG. 2, the soldering pin 10 for guiding the bonding wire 140 stretches the bonding wire 140 and beyond the center of the bonding base 131, so that the pressing end 11 of the soldering pin 10 is aligned with the cutting line 132. The wire is then depressed and the wire is cut so that the wire 140 can form the wire end 142 joined to the wire platform 132. As shown in FIG. 3, when the wire end 142 is joined to the wire cutting platform 132, the wire cutting platform 132 generates a flashing portion 133 to raise the height of the wire 140, so the wire 140 is The height of the reverse-wire contact on the pad 121 includes three heights of the height H1 of the joint base 131, the height H2 of the wire-drawing platform 132, and the diameter H3 of the wire 140, and the minimum height is also 28 micrometers. When applied to a thinned multi-wafer stack product, the upper wafer is easily touched by the bonding wire 140 when stacked, thereby forming an electrical short.

In order to solve the above problems, the main object of the present invention is to provide a reverse-wire structure of a semiconductor package, which can reduce the height of the reverse-wire contact, and is particularly applicable to a multi-wafer stack product and then to a thin wafer process, thereby increasing the stacking process. The distance between the reverse wire bonding and the upper wafer prevents the bonding wire from touching the wafer to avoid electrical short circuit.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a reverse-wire structure of a semiconductor package, which comprises a substrate, a wafer, a wire bump and a bonding wire. The substrate has a pad. The wafer has a pad. The wire bonding bump is disposed on the soldering pad, the wire bonding bump has a joint base and a wire cutting platform, wherein the wire drawing platform protrudes from a center of the joint base, and the joint base has an exposed line The edge of the platform. The wire is made up of The pad of the substrate is wire-bonded to the wire bump located on the pad of the wafer, the wire has a wire end bump end and a wire tail end, and the wire end bump end is located on the pad. The end of the wire is bonded to the portion of the ring facing the pad such that the wire does not exceed the center of the joint.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In one embodiment of the reverse threading structure described above, the cross-section of the wire end can be joined to the side edge of the wire-drawing platform.

In one embodiment of the foregoing reverse wire structure, the cross section of the wire end may be wrapped between the wire cutting platform and the joint base.

In one embodiment of the reverse threading structure, the height of the bonding wire on the bonding pad may be no more than 25 microns.

In an embodiment of the foregoing reverse-wire structure, at least one stacked wafer may be further disposed on the wafer. When the gap between the stacked wafer and the wafer is no more than 50 micrometers, the stacked wafer does not touch the stacked wafer. Welding wire.

10‧‧‧ welding needle

11‧‧‧ Pressing end

20‧‧‧ soldering needle

21‧‧‧ Pressing end

100‧‧‧ Reversed-wire structure of semiconductor package

110‧‧‧Substrate

111‧‧‧ pads

120‧‧‧ wafer

121‧‧‧ solder pads

130‧‧‧Wire bumps

131‧‧‧Joining base

132‧‧‧Wireline platform

133‧‧‧Floating parts

140‧‧‧welding line

141‧‧‧ wire end bump end

142‧‧‧End of the line

200‧‧‧ Reversed-wire structure of semiconductor package

210‧‧‧Substrate

211‧‧‧ pads

220‧‧‧ wafer

221‧‧‧ solder pads

230‧‧‧Wire bumps

231‧‧‧ joint base

231A‧‧‧

231B‧‧‧ parts

232‧‧‧Wireline platform

232A‧‧‧ side edge

240‧‧‧welding line

241‧‧‧ wire end bump end

242‧‧‧End of the line

243‧‧‧ Section

300‧‧‧ Reversed-wire structure of semiconductor package

350‧‧‧Stacked wafer

351‧‧‧ Spacer

360‧‧‧Upper substrate

H1‧‧‧The height of the joint base

H2‧‧‧ height of the cutting platform

H3‧‧‧Diameter diameter

Figure 1: Schematic cross-sectional view of a reversed-wire structure of a conventional semiconductor package.

Fig. 2 is a partial cross-sectional view showing the reverse-wire structure of a conventional semiconductor package in a wire bonding state.

Fig. 3 is a perspective view showing the end of the wire of the bonding wire in the reverse wire structure of the conventional semiconductor package combined with the wire bump.

4 is a partial cross-sectional view showing a reverse-wire structure of a semiconductor package in accordance with an embodiment of the present invention.

Fig. 5 is a partial cross-sectional view showing the reverse wire structure in a wire bonding state according to an embodiment of the present invention.

Figure 6 is a perspective view showing the end of the wire of the wire in the reverse wire structure combined with the wire bump according to an embodiment of the present invention.

Figure 7 is a top plan view of a wire bump in the reverse wire structure in accordance with an embodiment of the present invention.

Figure 8 is a partial cross-sectional view showing the reverse-wire structure of another semiconductor package in accordance with an application example of one embodiment of the present invention.

Figure 9 is a SEM enlarged image view of the reverse-twisted structure at its lined bumps in accordance with an embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to an embodiment of the present invention, a reverse-wire structure of a semiconductor package is illustrated in a partial cross-sectional view of FIG. 4 and a partial cross-sectional view of FIG. 5 in a wire bonding state. The reverse-wire structure 200 of the semiconductor package includes a substrate 210, a wafer 220, a wire bump 230, and a bonding wire 240. Although only a single number of the wire bumps 230 and the wire 240 are shown in the drawing, the actual number of the wire bumps 230 and the wire 240 may be plural. .

The substrate 210 has a pad 211. The substrate 210 can be a printed circuit board, a ceramic circuit board, a lead frame or a composite wafer carrier, and even the substrate 210 can be a lower layer wafer. The pad 211 is specifically a nickel-plated copper pad on the surface, and the shape thereof can be Fingers.

The wafer 220 has a pad 221 . The wafer 220 can be a processor die, a special application integrated circuit die, or a memory die. The pad 221 can be an I/O pad or a power/ground pad that is connected to an integrated circuit inside the wafer 220.

The wire bumps 230 are disposed on the bonding pads 221 . The wire bumps 230 are formed by wire bonding, and are usually made of gold (Au), silver (Ag), copper (Cu), Pd (palladium) or alloys thereof. The wire bonding block 230 has a joint base 231 and a wire cutting platform 232. The wire drawing platform 232 protrudes from the center of the joint base 231. The joint base 231 has a rim exposed to the wire cutting platform 232. 231A (as shown in Figures 6 and 7). The wire bump 230 may be a bell-shaped cross section before the wire 240 is joined.

The bonding wire 240 is wire-bonded by the pad 211 of the substrate 210 to the wire bump 230 located on the pad 221 of the wafer 220. The bonding wire 240 can be a gold wire, a copper wire or a conductive metal thin wire formed by a single wire. The wire 240 has a wire end bump end 241 and a wire tail end 242. The wire end bump end 241 is located on the pad 211, and the wire end bump end 241 is directly coupled to the pad 211. The wire end 242 is joined to the portion 231B of the ring edge 231A facing the pad 211 (as shown in FIG. 7). In other words, the junction of the wire tail end 242 is located beside the wire cutting platform 232. The center point of the wire drawing platform 232 is not aligned so that the wire 240 does not exceed the center of the joint base 231.

FIG. 6 is a perspective view showing the wire tail end 242 of the bonding wire 240 bonded to the wire bonding bump 230 in the reverse wire structure. FIG. 7 is a top view of the wire bump 230. More specifically, the section 243 of the wire end 242 is engageable to the side edge 232A of the wirescope platform 232. More specifically, the most flattened section 243 of the wire end 242 can be wrapped between the wire drawing platform 232 and the joint base 231.

In a preferred embodiment, the height of the bonding wire 240 on the bonding pad 221 can be no more than 25 micrometers (μm), which can be reduced by more than 20%, specifically 22 micrometers, than the height of the conventional reverse wire bonding.

As shown in FIG. 5 , in the reverse-wire process, the wire bonding bumps 230 are disposed on the bonding pad 221 by using a wire bonding technique, and the bonding base 231 of the wire bonding bumps 230 is bonded to the bonding pads 221 . The wire cutting platform 232 is cut by a welding pin. The soldering pin 20 of the bonding wire 240 is formed on the pad 211 to form the wire end bump end 241 of the bonding wire 240. After the bonding wire 240 is derived, the soldering pin 20 stretches the bonding wire 240. The wire end 242 of the bonding wire 231 is bonded to the portion 231B of the bonding pad 231 toward the pad 211, that is, the wire bar 230 is located at the center of the bonding pad 231. The side of the section platform 232 is not aligned with the center of the section platform 232. The pressing end 21 of the soldering pin 20 is aligned with the edge 231A of the ring 231A toward the portion 231B of the pad 211, and then pressed and cut off the bonding wire 240, so that the bonding wire 240 can be formed not to be bonded to the wire cutting platform 232. The upper end 242 of the line. As shown in FIG. 6, the height of the reverse wire contact of the bonding wire 240 on the bonding pad 221 is only the sum of the height H1 of the bonding base 231 and the height H2 of the sectional platform 232. One of the two sums of the height H1 of the base 231 and the diameter of the wire 240 is taken to be a larger value, so that the height of the reverse wire contact of the present invention can be controlled to not exceed 25 microns.

According to an application example of the above specific embodiment of the present invention, another reverse-wire structure of a semiconductor package is illustrated in a partial cross-sectional view of FIG. 8 to illustrate the form in which the present invention can be applied to a multi-wafer 220 stack. The main components of the present embodiment and their connection relationships are the same as those of the foregoing specific embodiments, and the same reference numerals will not be used. The reverse-wire structure 300 of the semiconductor package includes a substrate 210, a wafer 220, a wire bump 230, and a bonding wire 240.

The wire bonding block 230 is disposed on the bonding pad 221 , and the wire bonding protrusion 230 has a bonding base 231 and a wire cutting platform 232 , wherein the wire drawing platform 232 protrudes from the center of the bonding base 231 , and the bonding The base 231 has a rim that is exposed to the cutting platform 232. The bonding wire 240 is connected by the pad 211 of the substrate 210 to the wire bump 230 located on the pad 221 of the wafer 220. The bonding wire 240 has a wire end bump end 241 and a tail end. The end 242 is located on the pad 211. The wire end 242 is bonded to the edge of the ring 211 so that the wire 240 does not exceed the joint 231. central.

The reverse-wire structure 300 can further include at least one stacked wafer 350 disposed on the wafer 220, and can be interposed between the stacked wafer 350 and the wafer 220 by a spacer 351 to maintain a gap therebetween. The sheet 351 can be an adhesive tape, a spacer die-bonding material, or a cross-stacked intermediate layer wafer. When the gap between the stacked wafer 350 and the wafer 220 is no more than 50 micrometers, the back surface of the stacked wafer 350 does not touch the bonding wire 240. In addition, an upper substrate 360 may be further disposed on the stacked wafer 350. The upper substrate 360 may be another wafer, a line carrier, a heat sink or another semiconductor package. FIG. 9 is a SEM enlarged image of the anti-wire structure 300 in the wire bump 230. It can be seen that the wire end of the wire is not aligned with the wire-drawing platform of the wire bump and is bonded to the wire bump. The base is engaged to reduce the height of the reverse wire joint.

Therefore, the reverse-wire structure of the semiconductor package provided by the present invention can effectively reduce the height of the reverse-wire contact, and is particularly applicable to a multi-wafer stack product and further to a thin wafer process, and increases the reverse-wire contact and the upper layer in the stacking process. The distance of the wafer prevents the wire from touching the wafer to avoid electrical shorting.

The above description is only a preferred embodiment of the present invention, and The present invention is not limited to the scope of the present invention, and is not intended to limit the present invention, and any one skilled in the art can do without departing from the technical scope of the present invention. Simple modifications, equivalent changes, and modifications are still within the technical scope of the present invention.

200‧‧‧ Reversed-wire structure of semiconductor package

210‧‧‧Substrate

211‧‧‧ pads

220‧‧‧ wafer

221‧‧‧ solder pads

230‧‧‧Wire bumps

231‧‧‧ joint base

232‧‧‧Wireline platform

240‧‧‧welding line

241‧‧‧ wire end bump end

242‧‧‧End of the line

Claims (5)

An anti-wire structure of a semiconductor package, comprising: a substrate having a pad; a wafer having a pad; a wire bump disposed on the pad, the wire bump having a joint base and a cutting platform, wherein the cutting platform protrudes from a center of the joint base, the joint base has a rim exposed to the cutting platform; and a wire is connected by the pad of the substrate to the wire a wire bump on the pad of the wafer, the wire has a wire end bump end and a wire tail end, the wire end bump end is on the pad, and the wire end is coupled to the ring The edge faces the portion of the pad such that the wire does not exceed the center of the joint. The reverse-wire structure of the semiconductor package of claim 1, wherein the cross-section of the wire end is joined to a side edge of the wire-drawing platform. The reverse-wire structure of the semiconductor package of claim 2, wherein the cross-section of the wire end is wrapped between the wire-drawing platform and the joint base. The reverse-wire structure of the semiconductor package according to claim 1, wherein the bonding wire has a height of not more than 25 μm on the bonding pad. The reverse-wire structure of the semiconductor package according to claim 1, 2, 3 or 4, further comprising at least one stacked wafer disposed on the wafer, wherein a gap between the stacked wafer and the wafer is not more than 50 In micrometers, the stacked wafer does not touch the bonding wire.