TW201525099A - Adhesive film for semiconductor bonding - Google Patents

Adhesive film for semiconductor bonding Download PDF

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TW201525099A
TW201525099A TW103139986A TW103139986A TW201525099A TW 201525099 A TW201525099 A TW 201525099A TW 103139986 A TW103139986 A TW 103139986A TW 103139986 A TW103139986 A TW 103139986A TW 201525099 A TW201525099 A TW 201525099A
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wafer
adhesive film
bonding
film
semiconductor
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TW103139986A
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TWI646165B (en
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Sayaka Wakioka
Minoru Suezaki
Toshio Enami
Kouhei Takeda
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Sekisui Chemical Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2203/00Applications of adhesives in processes or use of adhesives in the form of films or foils
    • C09J2203/326Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54453Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446Located in scribe lines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136Covering only the central area of the surface to be connected, i.e. central arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Adhesive Tapes (AREA)
  • Dicing (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The purpose of the present invention is to provide an adhesive film for semiconductor bonding which, when laminated to a wafer surface and diced along a scribe line (dicing line), is less apt to peel off at the interface between the adhesive film and the wafer, in particular, at the interface between the adhesive film and the wafer having an aluminum wiring pattern present on the scribe line. This adhesive film for semiconductor bonding is to be laminated to a wafer having an aluminum wiring pattern formed thereon and has the following feature (1) and/or (2). (1) The adhesive film has a storage modulus of 7.5 GPa or less at a frequency corresponding to the rotation speed of the dicing blade; and (2) the surface of the adhesive film which is to be laminated to the wafer having an aluminum wiring pattern formed thereon has a surface free energy [gamma] when examined using two or more analysis reagents each having a known surface energy, the surface free energy [gamma] including a dispersion component ([gamma]sd) of 30 mJ/m2 or greater.

Description

半導體接合用接著膜 Adhesive film for semiconductor bonding

本發明係關於一種於以貼合於晶圓表面之狀態沿劃線(切割線)進行切割時,難以於與晶圓之界面、特別是與劃線(scribe line)上存在鋁配線圖案之晶圓之界面難以產生剝離之半導體接合用接著膜。 The present invention relates to a crystal which is difficult to form an aluminum wiring pattern on an interface with a wafer, particularly a scribe line, when being cut along a scribe line (cut line) in a state of being attached to a surface of a wafer. It is difficult to cause peeling of the adhesive film for semiconductor bonding at the round interface.

近年來,為了應對逐漸發展之半導體裝置之小型化、高積體化,關注使用有具有由焊料等構成之突起電極(凸塊)之半導體晶片之倒裝晶片安裝。 In recent years, in order to cope with the miniaturization and high integration of semiconductor devices which are gradually being developed, attention has been paid to flip chip mounting using a semiconductor wafer having bump electrodes (bumps) made of solder or the like.

於倒裝晶片安裝時,通常使用如下方法:於將半導體晶片之突起電極、與其他半導體晶片或基板之電極接合後,注入底膠(underfill)而進行樹脂密封(例如,專利文獻1)。 In flip chip mounting, a method of bonding a bump electrode of a semiconductor wafer to an electrode of another semiconductor wafer or a substrate, and then injecting an underfill to perform resin sealing is generally used (for example, Patent Document 1).

然而,近年來伴隨半導體晶片之小型化不斷發展,電極間之間距亦逐漸變窄,又,伴隨該等情形而半導體晶片彼此或半導體晶片與基板之間之間隙變窄,因此於注入底膠時夾帶空氣而變得易於產生空隙。因此,使用如下方法:於電極接合後,並非注入底膠而是預先於基板或半導體晶片貼附熱硬化型接著膜,藉由加熱而同時進行電極接合與接著膜之硬化(例如,專利文獻2)。 However, in recent years, as the miniaturization of semiconductor wafers has progressed, the distance between electrodes has been gradually narrowed, and the gap between semiconductor wafers or semiconductor wafers and substrates has been narrowed along with such cases, so that when the primer is injected, Entrained air becomes easy to create voids. Therefore, after the electrode bonding, the thermosetting type bonding film is attached to the substrate or the semiconductor wafer in advance, and the electrode bonding and the bonding film hardening are simultaneously performed by heating (for example, Patent Document 2) ).

作為預先於半導體晶片貼附接著膜之方法,可使用如下方法:於矽晶圓表面貼合接著膜,自接著膜之表面沿劃線(切割線)進行切 割,藉此獲得貼附有接著膜之半導體晶片。於圖1中表示模式性地表示形成有劃線之矽晶圓表面之一區域之俯視圖。如圖1所示,於矽晶圓1上,劃線2形成為格子狀,藉由沿劃線2進行切割而獲得半導體晶片3。於半導體晶片3上,設置有多個突起電極4。 As a method of attaching a bonding film to a semiconductor wafer in advance, a method of bonding a bonding film to the surface of the bonding wafer and cutting the surface of the bonding film along a scribe line (cutting line) can be used. Cutting, thereby obtaining a semiconductor wafer to which an adhesive film is attached. FIG. 1 is a plan view schematically showing a region of a wafer surface on which a scribe line is formed. As shown in FIG. 1, on the wafer 1, the scribe line 2 is formed in a lattice shape, and the semiconductor wafer 3 is obtained by dicing along the scribe line 2. On the semiconductor wafer 3, a plurality of bump electrodes 4 are provided.

然而,於自接著膜之表面進行刀片切割之情形時,存在於接著膜與矽晶圓之界面產生剝離之情況。 However, in the case where the blade is cut from the surface of the bonding film, there is a case where peeling occurs at the interface between the bonding film and the germanium wafer.

特別是,如圖1所示,於在劃線2上存在稱為輔助件(accessory)且用作對準標記等之金屬配線圖案5之情形時,於該部分特別易於產生與接著膜界面之剝離,從而存在因剝離引起之接合可靠性之降低、或於剝離之部分混入切割之碎屑等問題。進而,於在金屬配線圖案5之最表面存在鋁之情形時,鋁易於在表面形成氧化膜,氧化鋁密接力較差,故存在易於在此種鋁配線圖案與接著膜之界面產生剝離之問題。 In particular, as shown in FIG. 1, when a metal wiring pattern 5 called an auxiliary member is used as an alignment mark on the scribe line 2, it is particularly easy to cause peeling from the adhesive film interface at the portion. There is a problem that the joint reliability due to peeling is lowered or the cut scrap is mixed in the peeled portion. Further, when aluminum is present on the outermost surface of the metal wiring pattern 5, aluminum tends to form an oxide film on the surface, and the adhesion of the aluminum oxide is inferior, so that there is a problem that peeling occurs at the interface between the aluminum wiring pattern and the adhesive film.

專利文獻1:日本特開2010-278334號公報 Patent Document 1: Japanese Laid-Open Patent Publication No. 2010-278334

專利文獻2:日本特開2011-29392號公報 Patent Document 2: Japanese Laid-Open Patent Publication No. 2011-29392

本發明之目的在於提供一種於以貼合於晶圓表面之狀態沿劃線(切割線)進行切割時,難以於與晶圓之界面、特別是與劃線上存在鋁配線圖案之晶圓之界面難以產生剝離之半導體接合用接著膜。 It is an object of the present invention to provide an interface which is difficult to interface with a wafer, particularly a wafer having an aluminum wiring pattern on a scribe line, when dicing along a scribe line (cut line) in a state of being bonded to the surface of the wafer. It is difficult to cause peeling of the adhesive film for semiconductor bonding.

本發明係一種半導體接合用接著膜,其係貼合於附有鋁配線圖案之晶圓者,且(1)在相當於切割刀片之轉數之頻率下之儲存彈性模數為7.5GPa以下,及/或(2)使用2種以上表面能為既知之測定試劑進行測定,所得到之貼合於附有鋁配線圖案之晶圓的面之表面自由能γ中之分散成分(γsd)為30mJ/m2以上。 The present invention relates to a film for bonding a semiconductor, which is attached to a wafer having an aluminum wiring pattern, and (1) has a storage elastic modulus of 7.5 GPa or less at a frequency corresponding to the number of revolutions of the dicing blade. And/or (2) using two or more types of surface energy to measure the known measurement reagent, and the obtained dispersion component (γsd) of the surface free energy γ of the surface of the wafer to which the aluminum wiring pattern is attached is 30 mJ. /m 2 or more.

以下,對本發明進行詳述。 Hereinafter, the present invention will be described in detail.

本發明者等人係發現如下情形而以至完成本發明:將貼合於附有鋁配線圖案之晶圓之半導體接合用接著膜之(1)在相當於切割刀片之轉數之頻率下之儲存彈性模數、及/或(2)表面自由能γ中之分散成分(γsd)調整為特定範圍,藉此可抑制半導體接合用接著膜於與晶圓之界面、特別是抑制與劃線上存在鋁配線圖案之晶圓之界面發生剝離。 The inventors of the present invention have found that the (1) of the bonding film for semiconductor bonding bonded to the wafer with the aluminum wiring pattern is stored at a frequency corresponding to the number of revolutions of the dicing blade. The elastic modulus, and/or (2) the dispersion component (γsd) in the surface free energy γ is adjusted to a specific range, whereby the interface for the semiconductor bonding can be suppressed from interfacing with the wafer, particularly suppressing the presence of aluminum on the scribe line. The interface of the wafer of the wiring pattern is peeled off.

本發明之半導體接合用接著膜係貼合於附有鋁配線圖案之晶圓者。 The adhesive film for semiconductor bonding of the present invention is bonded to a wafer having an aluminum wiring pattern.

上述附有鋁配線圖案之晶圓並無特別限定,例如可列舉如下等晶圓:由矽、砷化鎵等半導體所構成,並劃線形成為格子狀,於該劃線上存在鋁配線圖案。藉由沿劃線對此種晶圓進行切割而可獲得半導體晶片。較佳為於獲得之半導體晶片設置有由焊料等構成之複數個突起電極。 The wafer to which the aluminum wiring pattern is attached is not particularly limited, and examples thereof include a wafer made of a semiconductor such as germanium or gallium arsenide, and a scribe line formed in a lattice shape, and an aluminum wiring pattern is formed on the scribe line. A semiconductor wafer can be obtained by cutting the wafer along the scribe line. Preferably, the obtained semiconductor wafer is provided with a plurality of bump electrodes composed of solder or the like.

本發明之半導體接合用接著膜中,(1)在相當於切割刀片之轉數之頻率下之儲存彈性模數為7.5GPa以下,及/或(2)使用2種以上表面能為既知之測定試劑進行測定,所得到之貼合於附有鋁配線圖案之晶圓的面之表面自由能γ中之分散成分(γsd)為30mJ/m2以上。 In the adhesive film for semiconductor bonding of the present invention, (1) the storage elastic modulus at a frequency corresponding to the number of revolutions of the dicing blade is 7.5 GPa or less, and/or (2) the use of two or more kinds of surface energy is known. The reagent was measured, and the obtained dispersion component (γsd) in the surface free energy γ of the surface of the wafer to which the aluminum wiring pattern was attached was 30 mJ/m 2 or more.

藉由將上述(1)之在相當於切割刀片之轉數之頻率下之儲存彈性模數、及/或上述(2)之表面自由能γ中之分散成分(γsd)調整為上述範圍,而可抑制半導體接合用接著膜於與晶圓之界面、特別是抑制與劃線上存在鋁配線圖案之晶圓之界面發生剝離。本發明之半導體接合用接著膜可滿足上述(1)及上述(2)之兩者,亦可僅滿足任一者。 By adjusting the storage elastic modulus of the above (1) at a frequency corresponding to the number of revolutions of the dicing blade, and/or the dispersion component (γsd) of the surface free energy γ of the above (2) to the above range, It is possible to suppress peeling of the interface film for semiconductor bonding at the interface with the wafer, particularly to suppress the interface with the wafer having the aluminum wiring pattern on the scribe line. The adhesive film for semiconductor bonding of the present invention satisfies both of the above (1) and (2), and may satisfy only one of them.

若上述(1)之在相當於切割刀片之轉數之頻率下之儲存彈性模數超過7.5GPa,則半導體接合用接著膜變得易於在與晶圓之界面、特別是與劃線上存在鋁配線圖案之晶圓之界面發生剝離。上述儲存彈性模數較佳為7.4GPa以下,更佳為7.3GPa以下。 When the storage elastic modulus of the above (1) at a frequency corresponding to the number of revolutions of the dicing blade exceeds 7.5 GPa, the adhesive film for semiconductor bonding becomes easy to have aluminum wiring at the interface with the wafer, particularly with respect to the scribe line. The interface of the patterned wafer is peeled off. The storage elastic modulus is preferably 7.4 GPa or less, more preferably 7.3 GPa or less.

上述儲存彈性模數之下限並無特別限定,但若考慮以於晶圓表面貼合 有半導體接合用接著膜之狀態切割、或此後將貼附有半導體接合用接著膜之半導體晶片熱壓接至基板等之情形,則較佳之下限為3.5GPa,更佳之下限為4.0GPa。若上述儲存彈性模數未達3.5GPa,則存在切割時之切削性降低之情形。 The lower limit of the storage elastic modulus is not particularly limited, but it is considered to be applied to the surface of the wafer. In the case where the semiconductor wafer for semiconductor bonding is diced or the semiconductor wafer to which the semiconductor bonding bonding film is attached is thermally bonded to the substrate or the like, the lower limit is preferably 3.5 GPa, and more preferably 4.0 GPa. If the storage elastic modulus is less than 3.5 GPa, the machinability at the time of cutting may be lowered.

上述(1)之在相當於切割刀片之轉數之頻率下之儲存彈性模數可藉由如下方式估測:使用動態黏彈性測定裝置(例如,IT計測控制公司製造之DVA-200等)進行頻率分散測定,製作切割時之水溫(例如,5~50℃左右)下之主曲線,於主曲線上讀取特定頻率下之儲存彈性模數。 The storage elastic modulus at the frequency corresponding to the number of revolutions of the dicing blade of the above (1) can be estimated by using a dynamic viscoelasticity measuring apparatus (for example, DVA-200 manufactured by IT Measurement and Control Co., Ltd.). The frequency dispersion measurement is performed to prepare a main curve under water temperature at the time of cutting (for example, about 5 to 50 ° C), and the storage elastic modulus at a specific frequency is read on the main curve.

再者,通常於測定黏彈性時,在頻率與溫度之間存在固定之關係(溫度-時間換算法則),故例如可將溫度之變化換算成頻率之變化,調查固定溫度下之黏彈性特性之頻率依存性。根據該方法,可將無法實測之較廣之頻率區域內之黏彈性特性預測為任意溫度下之特性。 Furthermore, in the measurement of viscoelasticity, there is usually a fixed relationship between frequency and temperature (temperature-time conversion algorithm). Therefore, for example, the change in temperature can be converted into a change in frequency, and the viscoelastic property at a fixed temperature can be investigated. Frequency dependence. According to this method, the viscoelastic property in a wide frequency region which cannot be measured can be predicted as a characteristic at an arbitrary temperature.

上述所謂相當於切割刀片之轉數之頻率,係指相當於以晶圓表面貼合有半導體接合用接著膜之狀態進行刀片切割時的切割刀片之通常之轉數(單位為rpm)的頻率(單位為Hz),通常為10000~60000rpm(換算成頻率為167~1000Hz),較佳為20000~50000rpm(換算成頻率為333~833Hz)。 The frequency corresponding to the number of revolutions of the dicing blade is a frequency corresponding to the normal number of revolutions (in rpm) of the dicing blade when the blade is diced in a state in which the semiconductor bonding bonding film is bonded to the wafer surface ( The unit is Hz), usually 10000~60000rpm (converted to frequency 167~1000Hz), preferably 20,000~50000rpm (converted to frequency 333~833Hz).

若上述(2)之表面自由能γ中之分散成分(γsd)未達30mJ/m2,則半導體接合用接著膜變得易於在與晶圓之界面、特別是與劃線上存在鋁配線圖案之晶圓之界面發生剝離。上述分散成分(γsd)較佳為32mJ/m2以上,更佳為35mJ/m2以上。 When the dispersion component (γsd) in the surface free energy γ of the above (2) is less than 30 mJ/m 2 , the film for semiconductor bonding becomes easy to have an aluminum wiring pattern on the interface with the wafer, particularly on the scribe line. The interface of the wafer is peeled off. The dispersion component (γsd) is preferably 32 mJ/m 2 or more, and more preferably 35 mJ/m 2 or more.

上述分散成分(γsd)之上限並無特別限定,但若考慮以晶圓表面貼合有半導體接合用接著膜之狀態切割、或此後將貼附有半導體接合用接著膜之半導體晶片熱壓接至基板等之情形,則較佳之上限為55mJ/m2,更佳之上限為50mJ/m2The upper limit of the dispersion component (γsd) is not particularly limited. However, it is considered that the semiconductor wafer to which the semiconductor bonding bonding film is bonded is bonded to the surface of the wafer, or the semiconductor wafer to which the semiconductor bonding bonding film is attached is thermally bonded thereto. In the case of a substrate or the like, the upper limit is preferably 55 mJ/m 2 , and the upper limit is more preferably 50 mJ/m 2 .

又,表面自由能γ中之極性成分(γsp)並無特別限定,但較佳之下限為0.01mJ/m2,較佳之上限為5mJ/m2。若上述極性成分(γsp)未達0.01mJ/m2或超過5mJ/m2,則存在如下情形:半導體接合用接著膜與鋁之極性差變大,半導體接合用接著膜變得易於在與晶圓之界面、特別是與劃線上存在鋁配線圖案之晶圓之界面發生剝離。上述極性成分(γsp)之更佳之下限為0.02mJ/m2,更佳之上限為4mJ/m2Further, the polar component (γsp) in the surface free energy γ is not particularly limited, but a preferred lower limit is 0.01 mJ/m 2 , and a preferred upper limit is 5 mJ/m 2 . When the polar component (γsp) is less than 0.01 mJ/m 2 or more than 5 mJ/m 2 , the difference in polarity between the semiconductor-bonding adhesive film and aluminum becomes large, and the film for semiconductor bonding becomes easy to crystallize. The interface between the circles, in particular, the interface with the wafer on which the aluminum wiring pattern is present on the scribe line is peeled off. A more preferred lower limit of the above polar component (γsp) is 0.02 mJ/m 2 , and a more preferred upper limit is 4 mJ/m 2 .

又,表面自由能γ可藉由上述分散成分(γsd)與上述極性成分(γsp)之和而求出。上述表面自由能γ並無特別限定,但較佳之下限為30mJ/m2,較佳之上限為55mJ/m2。若上述表面自由能γ未達30mJ/m2,則存在半導體接合用接著膜變得易於在與晶圓之界面、特別是與劃線上存在鋁配線圖案之晶圓之界面發生剝離之情形。上述表面自由能γ之更佳之下限為35mJ/m2,更佳之上限為50mJ/m2Further, the surface free energy γ can be obtained by the sum of the dispersion component (γsd) and the polar component (γsp). The surface free energy γ is not particularly limited, but a preferred lower limit is 30 mJ/m 2 , and a preferred upper limit is 55 mJ/m 2 . When the surface free energy γ is less than 30 mJ/m 2 , the semiconductor bonding adhesive film may be easily peeled off at the interface with the wafer, particularly at the interface of the wafer having the aluminum wiring pattern on the scribe line. A lower limit of the above surface free energy γ is preferably 35 mJ/m 2 , and a more preferred upper limit is 50 mJ/m 2 .

上述表面自由能γ、以及該表面自由能γ中之分散成分(γsd)及極性成分(γsp)係使用接觸角計測定2種以上之測定試劑相對於半導體接合用接著膜之貼合於附有鋁配線圖案之晶圓的面(固體表面)之接觸角,根據所獲得之接觸角,使用幾何學平均法而算出。 The surface free energy γ and the dispersion component (γsd) and the polar component (γsp) in the surface free energy γ are measured by using a contact angle meter to measure the adhesion of two or more kinds of measurement reagents to the semiconductor bonding adhesive film. The contact angle of the surface (solid surface) of the wafer of the aluminum wiring pattern was calculated using a geometrical average method based on the obtained contact angle.

上述2種以上之測定試劑只要表面能為既知,則並無特別限定,例如可列舉水、二碘甲烷、溴萘、乙二醇等。例如,於將水與二碘乙烷用作測定試劑之情形時,表面自由能、以及該表面自由能γ中之分散成分(γsd)及極性成分(γsp)可基於下述式(1)~(3)而算出。 The above two or more kinds of measurement reagents are not particularly limited as long as the surface energy is known, and examples thereof include water, diiodomethane, bromine naphthalene, and ethylene glycol. For example, when water and diiodoethane are used as the measuring reagent, the surface free energy and the dispersed component (γsd) and the polar component (γsp) in the surface free energy γ can be based on the following formula (1)~ (3) and calculate.

γ=γsd+γsp 式(1) γ=γsd+γsp (1)

72.8(1+cosθH)=2(21.8×γsd)1/2+2(51.0×γsp)1/2 式(2) 72.8(1+cosθ H )=2(21.8×γsd) 1/2 +2(51.0×γsp) 1/2 (2)

50.8(1+cosθI)=2(48.5×γsd)1/2+2(2.3×γsp)1/2 式(3) 50.8(1+cosθ I )=2(48.5×γsd) 1/2 +2(2.3×γsp) 1/2 (3)

θH=水相對於固體表面之接觸角 θ H = contact angle of water relative to the solid surface

θI=二碘甲烷相對於固體表面之接觸角 θ I = contact angle of diiodomethane relative to the solid surface

為了將上述(1)之在相當於切割刀片之轉數之頻率下之儲存彈性模數、及/或上述(2)之表面自由能γ中之分散成分(γsd)調整為上述範圍,本發明之半導體接合用接著膜較佳為含有熱硬化性樹脂、熱硬化劑、及高分子量化合物,亦可視需要含有無機填料或添加劑等。其中,較佳為將常溫(25℃)下為液狀之成分與玻璃轉移溫度(Tg)為0℃以下之高分子量化合物相加所得之含量為5~15重量%、或含有20~60重量%之藉由矽烷偶合劑而進行過表面處理之無機填料。 In order to adjust the storage elastic modulus of the above (1) at a frequency corresponding to the number of revolutions of the dicing blade, and/or the dispersion component (γsd) in the surface free energy γ of the above (2) to the above range, the present invention The adhesive film for semiconductor bonding preferably contains a thermosetting resin, a heat curing agent, and a high molecular weight compound, and may contain an inorganic filler or an additive as needed. Preferably, the content of the liquid component at normal temperature (25 ° C) and the high molecular weight compound having a glass transition temperature (Tg) of 0 ° C or less are preferably 5 to 15% by weight or 20 to 60% by weight. % of an inorganic filler which has been surface treated by a decane coupling agent.

再者,常溫(25℃)下為液狀之成分可為熱硬化性樹脂、熱硬化劑、高分子量化合物,亦可為除該等外之成分(例如,稀釋劑、偶合劑、密接性賦予劑等添加劑等)。 Further, the component which is liquid at normal temperature (25 ° C) may be a thermosetting resin, a thermosetting agent, a high molecular weight compound, or may be a component other than the above (for example, a diluent, a coupling agent, and adhesion). Additives such as agents, etc.).

上述熱硬化性樹脂並無特別限定,例如可列舉藉由加成聚合、聚縮合、聚加成、加成縮合、開環聚合等反應而硬化之化合物。具體而言,作為上述熱硬化性樹脂,例如可列舉脲樹脂、三聚氰胺樹脂、酚樹脂、間苯二酚樹脂、環氧樹脂、丙烯酸樹脂、聚酯樹脂、聚醯胺樹脂、聚苯并咪唑樹脂、鄰苯二甲酸二烯丙酯樹脂、二甲苯樹脂、烷基-苯樹脂、環氧丙烯酸酯樹脂、矽樹脂、胺酯樹脂(urethane resin)等。其中,就確保半導體接合用接著膜之硬化物之強度及接合可靠性之觀點而言,較佳為環氧樹脂、丙烯酸樹脂。 The thermosetting resin is not particularly limited, and examples thereof include a compound which is cured by a reaction such as addition polymerization, polycondensation, polyaddition, addition condensation, or ring-opening polymerization. Specifically, examples of the thermosetting resin include a urea resin, a melamine resin, a phenol resin, a resorcin resin, an epoxy resin, an acrylic resin, a polyester resin, a polyamide resin, and a polybenzimidazole resin. , diallyl phthalate resin, xylene resin, alkyl-benzene resin, epoxy acrylate resin, oxime resin, urethane resin, and the like. Among these, from the viewpoint of securing the strength and bonding reliability of the cured product of the semiconductor bonding underlayer film, an epoxy resin or an acrylic resin is preferable.

上述環氧樹脂並無特別限定,例如可列舉:雙酚A型、雙酚F型、雙酚AD型、雙酚S型等雙酚型環氧樹脂、苯酚酚醛清漆型、甲酚酚醛清漆型等酚醛清漆型環氧樹脂、間苯二酚型環氧樹脂、三苯酚甲烷三環氧丙醚等芳香族環氧樹脂、萘型環氧樹脂、茀型環氧樹脂、二環戊二烯型環氧樹脂、聚醚改質環氧樹脂、NBR改質環氧樹脂、CTBN改質環氧 樹脂、及該等之氫化物等。該等環氧樹脂可單獨使用,亦可併用2種以上。 The epoxy resin is not particularly limited, and examples thereof include a bisphenol type epoxy resin such as a bisphenol A type, a bisphenol F type, a bisphenol AD type, and a bisphenol S type, a phenol novolac type, and a cresol novolak type. Aromatic epoxy resin such as novolak type epoxy resin, resorcinol type epoxy resin, trisphenol methane triepoxypropyl ether, naphthalene type epoxy resin, fluorene type epoxy resin, dicyclopentadiene type Epoxy resin, polyether modified epoxy resin, NBR modified epoxy resin, CTBN modified epoxy Resins, and such hydrides. These epoxy resins may be used singly or in combination of two or more.

上述環氧樹脂可為常溫下為液狀之環氧樹脂、常溫下為固體之環氧樹脂,亦可將該等適當地組合使用。 The epoxy resin may be an epoxy resin which is liquid at normal temperature and an epoxy resin which is solid at normal temperature, and these may be used in combination as appropriate.

上述常溫下為液狀之環氧樹脂中,作為市售品,例如可列舉:EPICLON 840、840-S、850、850-S、EXA-850CRP(以上為DIC公司製造)等雙酚A型環氧樹脂、EPICLON 830、830-S、EXA-830CRP(以上為DIC公司製造)等雙酚F型環氧樹脂、EPICLON HP-4032、HP-4032D(以上為DIC公司製造)等萘型環氧樹脂、EPICLON EXA-7015(DIC公司製造)、EX-252(長瀨化成公司製造)等氫化雙酚A型環氧樹脂、EX-201(長瀨化成公司製造)等間苯二酚型環氧樹脂等。 In the epoxy resin which is liquid at the normal temperature, a bisphenol A type ring such as EPICLON 840, 840-S, 850, 850-S, EXA-850CRP (manufactured by DIC Corporation) may be mentioned as a commercial item. Naphthalene type epoxy resin such as bisphenol F type epoxy resin such as oxygen resin, EPICLON 830, 830-S, EXA-830CRP (manufactured by DIC Corporation), EPICLON HP-4032, HP-4032D (manufactured by DIC Corporation) Hydrogenated bisphenol A epoxy resin such as EPICLON EXA-7015 (manufactured by DIC Corporation) and EX-252 (manufactured by Changchun Chemical Co., Ltd.), and resorcinol epoxy resin such as EX-201 (manufactured by Changchun Chemical Co., Ltd.) Wait.

上述常溫下為固體之環氧樹脂中,作為市售品,例如可列舉:EPICLON 860、10550、1055(以上為DIC公司製造)等雙酚A型環氧樹脂、EPICLON EXA-1514(DIC公司製造)等雙酚S型環氧樹脂、EPICLON HP-4700、HP-4710、HP-4770(以上為DIC公司製造)等萘型環氧樹脂、EPICLON HP-7200系列(DIC公司製造)等二環戊二烯型環氧樹脂、EPICLON HP-5000、EXA-9900(以上為DIC公司製造)等甲酚酚醛清漆型環氧樹脂等。 In the above-mentioned epoxy resin which is a solid at a normal temperature, a bisphenol A type epoxy resin such as EPICLON 860, 10550, 1055 (manufactured by DIC Corporation) or EPICLON EXA-1514 (manufactured by DIC Corporation) is mentioned as a commercial item. ) such as bisphenol S-type epoxy resin, EPICLON HP-4700, HP-4710, HP-4770 (manufactured by DIC Corporation), etc., such as naphthalene epoxy resin, EPICLON HP-7200 series (manufactured by DIC), etc. A cresol novolac type epoxy resin such as a diene type epoxy resin, an EPICLON HP-5000, or an EXA-9900 (manufactured by DIC Corporation).

上述熱硬化劑並無特別限定,可配合上述熱硬化性樹脂而適當選擇先前公知之熱硬化劑。於使用環氧樹脂作為上述熱硬化性樹脂之情形時,作為上述熱硬化劑,例如可列舉酸酐系硬化劑、酚系硬化劑、胺系硬化劑、雙氰胺等潛伏性硬化劑、陽離子系觸媒型硬化劑等。該等熱硬化劑可單獨使用,亦可併用2種以上。其中,就硬化速度、硬化物之物性等優異之方面而言,較佳為酸酐系硬化劑。 The above-mentioned thermosetting agent is not particularly limited, and a conventionally known thermosetting agent can be appropriately selected in combination with the above thermosetting resin. In the case of using the epoxy resin as the thermosetting resin, examples of the thermosetting agent include an acid anhydride curing agent, a phenol curing agent, an amine curing agent, a latent curing agent such as dicyandiamide, and a cationic system. Catalyst type hardener, etc. These thermosetting agents may be used singly or in combination of two or more. Among these, an acid anhydride-based curing agent is preferred in terms of excellent curing speed and physical properties of the cured product.

上述酸酐系硬化劑中,作為市售品,例如可列舉YH-306、YH-307(以上為三菱化學公司製造,常溫(25℃)下為液狀)、YH-309(三菱化學公司製造,常溫(25℃)下為固體)等。 In the above-mentioned acid anhydride-based curing agent, for example, YH-306, YH-307 (the above is manufactured by Mitsubishi Chemical Corporation, liquid at normal temperature (25 ° C)), and YH-309 (manufactured by Mitsubishi Chemical Corporation, It is a solid at room temperature (25 ° C) and the like.

上述熱硬化劑之含量並無特別限定,於使用環氧樹脂作為上述熱硬化性樹脂,且使用與環氧基進行等量反應之熱硬化劑之情形時,上述熱硬化劑之含量相對於半導體接合用接著膜中所含之環氧基之總量的較佳下限為60當量,較佳上限為110當量。若含量未達60當量,則存在無法使半導體接合用接著膜充分硬化之情形。即便含量超過110當量,亦不會特別有助於半導體接合用接著膜之硬化性,存在因過多之熱硬化劑揮發而成為空隙之原因之情況。含量之更佳之下限為70當量,更佳之上限為100當量。 The content of the above-mentioned thermosetting agent is not particularly limited. When an epoxy resin is used as the thermosetting resin and a thermosetting agent which reacts in an equal amount with an epoxy group is used, the content of the above-mentioned thermosetting agent is relative to the semiconductor. A preferred lower limit of the total amount of the epoxy groups contained in the bonding film for bonding is 60 equivalents, and a preferred upper limit is 110 equivalents. When the content is less than 60 equivalents, the film for semiconductor bonding may not be sufficiently cured. Even if the content exceeds 110 equivalents, it does not particularly contribute to the curability of the adhesive film for semiconductor bonding, and may cause voids due to excessive evaporation of the thermal curing agent. A lower limit of the content is preferably 70 equivalents, and a more preferred upper limit is 100 equivalents.

本發明之半導體接合用接著膜亦能夠以調整硬化速度、硬化物之物性等為目的而進而含有硬化促進劑。 The adhesive film for semiconductor bonding of the present invention can further contain a curing accelerator for the purpose of adjusting the curing rate, the physical properties of the cured product, and the like.

上述硬化促進劑並無特別限定,例如可列舉咪唑系硬化促進劑、三級胺系硬化促進劑等。其中,就易於實現用以調整硬化速度、硬化物之物性等的反應系統之控制之方面而言,較佳為咪唑系硬化促進劑。 The hardening accelerator is not particularly limited, and examples thereof include an imidazole-based hardening accelerator and a tertiary amine-based curing accelerator. Among them, an imidazole-based hardening accelerator is preferred in terms of easy control of the reaction system for adjusting the curing rate and the physical properties of the cured product.

上述咪唑系硬化促進劑並無特別限定,例如可列舉Fujicure 7000(T&K TOKA公司製造,常溫(25℃)下為液狀)、以氰乙基保護咪唑之1位之1-氰乙基-2-苯基咪唑、以異三聚氰酸保護鹼性之咪唑系硬化促進劑(商品名「2MA-OK」、四國化成工業公司製造、常溫(25℃)下為固體)、2MZ、2MZ-P、2PZ、2PZ-PW、2P4MZ、C11Z-CNS、2PZ-CNS、2PZCNS-PW、2MZ-A、2MZA-PW、C11Z-A、2E4MZ-A、2MAOK-PW、2PZ-OK、2MZ-OK、2PHZ、2PHZ-PW、2P4MHZ、2P4MHZ-PW、2E4MZ-BIS、VT、VT-OK、MAVT、MAVT-OK(以上為四國化成工業公司製造)等。該等咪唑系硬化促進劑可單獨使用,亦可併用2種以上。 The imidazole-based hardening accelerator is not particularly limited, and examples thereof include Fujicure 7000 (manufactured by T&K TOKA Co., Ltd., liquid at room temperature (25 ° C)), and 1-cyanoethyl-2 which protects the imidazole by cyanoethyl group. -Phenyl imidazole, an imidazole-based hardening accelerator which protects alkaline with iso-cyanuric acid (trade name "2MA-OK", manufactured by Shikoku Kasei Kogyo Co., Ltd., solid at room temperature (25 ° C)), 2MZ, 2MZ- P, 2PZ, 2PZ-PW, 2P4MZ, C11Z-CNS, 2PZ-CNS, 2PZCNS-PW, 2MZ-A, 2MZA-PW, C11Z-A, 2E4MZ-A, 2MAOK-PW, 2PZ-OK, 2MZ-OK, 2PHZ, 2PHZ-PW, 2P4MHZ, 2P4MHZ-PW, 2E4MZ-BIS, VT, VT-OK, MAVT, MAVT-OK (above, manufactured by Shikoku Chemical Industry Co., Ltd.). These imidazole-based hardening accelerators may be used singly or in combination of two or more.

上述硬化促進劑之含量並無特別限定,相對於100重量份之熱硬化劑之較佳下限為2重量份,較佳上限為50重量份。若含量未達2重量份,則存在為了半導體接合用接著膜之熱硬化而需要於高溫長時間加熱 之情形。若含量超過50重量份,則存在半導體接合用接著膜之儲存穩定性變得不充分、或因過多之硬化促進劑揮發而成為空隙之原因之情形。含量之更佳下限為3重量份,更佳上限為30重量份。 The content of the above-mentioned hardening accelerator is not particularly limited, and a preferred lower limit of the thermal curing agent per 100 parts by weight is 2 parts by weight, and a preferred upper limit is 50 parts by weight. If the content is less than 2 parts by weight, there is a need for heating at a high temperature for a long time in order to thermally harden the film for semiconductor bonding. The situation. When the content is more than 50 parts by weight, the storage stability of the film for semiconductor bonding is insufficient, or the excessive curing accelerator volatilizes to cause voids. A more preferred lower limit of the content is 3 parts by weight, and a still more preferred upper limit is 30 parts by weight.

上述高分子量化合物並無特別限定,例如可列舉:脲樹脂、三聚氰胺樹脂、酚樹脂、間苯二酚樹脂、環氧樹脂、丙烯酸樹脂、聚酯樹脂、聚醯胺樹脂、聚苯并咪唑樹脂、鄰苯二甲酸二烯丙酯樹脂、二甲苯樹脂、烷基-苯樹脂、環氧丙烯酸酯樹脂、矽樹脂、胺酯樹脂等公知之高分子量化合物。其中,較佳為具有環氧基之高分子量化合物。 The high molecular weight compound is not particularly limited, and examples thereof include a urea resin, a melamine resin, a phenol resin, a resorcin resin, an epoxy resin, an acrylic resin, a polyester resin, a polyamide resin, and a polybenzimidazole resin. A known high molecular weight compound such as diallyl phthalate resin, xylene resin, alkyl-benzene resin, epoxy acrylate resin, oxime resin or amine ester resin. Among them, a high molecular weight compound having an epoxy group is preferred.

藉由添加上述具有環氧基之高分子量化合物,可使半導體接合用接著膜之硬化物表現優異之可撓性。即,半導體接合用接著膜之硬化物兼具源自作為上述熱硬化性樹脂之環氧樹脂之優異機械強度、耐熱性及耐濕性、與源自上述具有環氧基之高分子量化合物之優異可撓性,因此成為耐冷熱循環性、耐回流焊性、尺寸穩定性等優異者,表現較高之接合可靠性及較高之導通可靠性。 By adding the above-mentioned high molecular weight compound having an epoxy group, the cured product of the adhesive film for semiconductor bonding can exhibit excellent flexibility. In other words, the cured product of the adhesive film for semiconductor bonding has excellent mechanical strength, heat resistance and moisture resistance derived from the epoxy resin as the thermosetting resin, and is excellent in the high molecular weight compound derived from the above epoxy group. Since it is flexible, it is excellent in cold cycle resistance, reflow resistance, dimensional stability, etc., and exhibits high joint reliability and high conduction reliability.

上述具有環氧基之高分子量化合物只要為於末端及/或側鏈(側位)具有環氧基之高分子量化合物,則無特別限定,例如可列舉:含環氧基之丙烯酸橡膠、含環氧基之丁二烯橡膠、雙酚型高分子量環氧樹脂、含環氧基之苯氧基樹脂、含環氧基之丙烯酸樹脂、含環氧基之胺酯樹脂、含環氧基之聚酯樹脂等。其中,就可獲得含有較多環氧基之高分子量化合物,成為硬化物之機械強度及耐熱性更優異者之方面而言,較佳為含環氧基之丙烯酸樹脂。該等具有環氧基之高分子量化合物可單獨使用,亦可併用2種以上。 The high molecular weight compound having an epoxy group is not particularly limited as long as it is a high molecular weight compound having an epoxy group at the terminal and/or side chain (lateral position), and examples thereof include an epoxy group-containing acrylic rubber and a ring-containing compound. Oxygen butadiene rubber, bisphenol type high molecular weight epoxy resin, epoxy group-containing phenoxy resin, epoxy group-containing acrylic resin, epoxy group-containing amine ester resin, epoxy group-containing poly Ester resin and the like. Among them, a high molecular weight compound containing a large amount of an epoxy group can be obtained, and an epoxy group-containing acrylic resin is preferable because the mechanical strength and heat resistance of the cured product are more excellent. These high molecular weight compounds having an epoxy group may be used singly or in combination of two or more.

於使用上述具有環氧基之高分子量化合物、特別是使用含環氧基之丙烯酸樹脂作為上述高分子量化合物之情形時,上述具有環氧基之高分子量化合物之重量平均分子量之較佳下限為1萬,較佳上限為100萬。 若重量平均分子量未達1萬,則存在半導體接合用接著膜之製膜性變得不充分、或半導體接合用接著膜之硬化物之可撓性未能充分提高之情況。若重量平均分子量超過100萬,則存在高分子量化合物於溶劑中之溶解性降低而操作性降低之情況。 When the above-mentioned high molecular weight compound having an epoxy group, particularly an epoxy group-containing acrylic resin, is used as the above high molecular weight compound, the preferred lower limit of the weight average molecular weight of the above epoxy group-containing high molecular weight compound is 1 Ten thousand, the upper limit is 1 million. When the weight average molecular weight is less than 10,000, the film forming property of the film for semiconductor bonding is insufficient, and the flexibility of the cured product of the film for bonding semiconductor is not sufficiently improved. When the weight average molecular weight exceeds 1,000,000, the solubility of a high molecular weight compound in a solvent may fall and workability may fall.

於使用上述具有環氧基之高分子量化合物、特別是使用含環氧基之丙烯酸樹脂作為上述高分子量化合物之情形時,上述具有環氧基之高分子量化合物之環氧當量之較佳下限為200,較佳上限為1000。若環氧當量未達200,則存在半導體接合用接著膜之硬化物之可撓性不會充分提高之情況。若環氧當量超過1000,則存在半導體接合用接著膜之硬化物之機械強度或耐熱性變得不充分之情況。 In the case of using the above-mentioned high molecular weight compound having an epoxy group, particularly an epoxy group-containing acrylic resin as the above high molecular weight compound, the preferred lower limit of the epoxy equivalent of the above epoxy group-containing high molecular weight compound is 200. The upper limit is preferably 1000. When the epoxy equivalent is less than 200, the flexibility of the cured product of the semiconductor bonding adhesive film may not be sufficiently improved. When the epoxy equivalent is more than 1,000, the mechanical strength or heat resistance of the cured product of the semiconductor bonding adhesive film may be insufficient.

本發明之半導體接合用接著膜中之上述高分子量化合物之含量並無特別限定,於本發明之半導體接合用接著膜中之較佳下限為3重量%,較佳上限為30重量%。若含量未達3重量%,則存在無法獲得對熱應變之充分可靠性之情況。若含量超過30重量%,則存在半導體接合用接著膜之耐熱性降低之情況。 The content of the high molecular weight compound in the adhesive film for semiconductor bonding of the present invention is not particularly limited, and a preferred lower limit of the adhesive film for semiconductor bonding of the present invention is 3% by weight, and a preferred upper limit is 30% by weight. If the content is less than 3% by weight, sufficient reliability against thermal strain cannot be obtained. When the content is more than 30% by weight, the heat resistance of the film for semiconductor bonding may be lowered.

本發明之半導體接合用接著膜亦可進而含有無機填料。於含有無機填料之情形時,較佳為含有20~60重量%之藉由矽烷偶合劑而進行過表面處理之無機填料。若含量超過60重量%,則存在半導體接合用接著膜之製膜性變得不充分、在相當於切割刀片之轉數之頻率下之儲存彈性模數變高、或於切割時變得易於剝離之情況。於本發明之半導體接合用接著膜中之上述無機填料之含量下限並無特別限定,但就確保半導體接合用接著膜之硬化物之強度及接合可靠性之觀點而言,較佳之下限為20重量%。 The adhesive film for semiconductor bonding of the present invention may further contain an inorganic filler. In the case of containing an inorganic filler, it is preferred to contain 20 to 60% by weight of an inorganic filler which has been surface-treated by a decane coupling agent. When the content is more than 60% by weight, the film forming property of the film for semiconductor bonding is insufficient, the storage elastic modulus at a frequency corresponding to the number of revolutions of the dicing blade is increased, or the film is easily peeled off at the time of cutting. The situation. The lower limit of the content of the inorganic filler in the adhesive film for semiconductor bonding of the present invention is not particularly limited. However, from the viewpoint of securing the strength and bonding reliability of the cured product of the semiconductor bonding adhesive film, the lower limit is preferably 20% by weight. %.

上述無機填料並無特別限定,例如可列舉二氧化矽(silica)、氧化鋁、氮化鋁、氮化硼、氮化矽、碳化矽、氧化鎂、氧化鋅等。其中,就流動性優異之方面而言,較佳為球狀二氧化矽,更佳為藉由甲基矽烷偶 合劑、苯基矽烷偶合劑、乙烯基矽烷偶合劑、甲基丙烯醯基矽烷偶合劑等而進行過表面處理之球狀二氧化矽。其中,特別是就控制表面自由能γ中之分散成分(γsd)之觀點而言,較佳為藉由苯基矽烷偶合劑而進行過表面處理之球狀二氧化矽。藉由使用經表面處理之球狀二氧化矽,可提高半導體接合用接著膜之製膜性,並且可將儲存彈性模數與表面自由能調整為特定之範圍。 The inorganic filler is not particularly limited, and examples thereof include silica, alumina, aluminum nitride, boron nitride, tantalum nitride, niobium carbide, magnesium oxide, and zinc oxide. Among them, in terms of excellent fluidity, it is preferably spherical cerium oxide, more preferably by methyl decane A spherical cerium oxide which has been subjected to surface treatment with a mixture, a phenyl decane coupling agent, a vinyl decane coupling agent, a methacryl decyl decane coupling agent or the like. Among them, in particular, from the viewpoint of controlling the dispersion component (γsd) in the surface free energy γ, spherical cerium oxide which has been surface-treated by a phenyl decane coupling agent is preferred. By using the surface-treated spherical cerium oxide, the film forming property of the film for semiconductor bonding can be improved, and the storage elastic modulus and the surface free energy can be adjusted to a specific range.

上述無機填料之平均粒徑並無特別限定,但就半導體接合用接著膜之透明性、流動性、接合可靠性等觀點而言,較佳為0.01~1μm左右。 The average particle diameter of the inorganic filler is not particularly limited, but is preferably about 0.01 to 1 μm from the viewpoints of transparency, fluidity, and bonding reliability of the film for semiconductor bonding.

上述無機填料可單獨使用,亦可混合多種無機填料而使用。 The above inorganic filler may be used singly or in combination of a plurality of inorganic fillers.

本發明之半導體接合用接著膜亦可視需要進而含有稀釋劑、觸變性賦予劑、溶劑、無機離子交換體、防滲劑、咪唑矽烷偶合劑等接著性賦予劑、密接性賦予劑、橡膠粒子等應力緩和劑等其他添加劑。 The adhesive film for semiconductor bonding of the present invention may further contain a binder, a thixotropy-imparting agent, a solvent, an inorganic ion exchanger, a barrier agent, an imidazole oxime coupling agent, and the like, an adhesion imparting agent, a rubber particle, etc., if necessary. Other additives such as stress relieving agents.

本發明之半導體接合用接著膜之厚度並無特別限定,但較佳之下限為5μm,較佳之上限為60μm,更佳之下限為10μm,更佳之上限為50μm。 The thickness of the adhesive film for semiconductor bonding of the present invention is not particularly limited, but a preferred lower limit is 5 μm, a preferred upper limit is 60 μm, a more preferred lower limit is 10 μm, and a more preferred upper limit is 50 μm.

製造本發明之半導體接合用接著膜之方法並無特別限定,例如可列舉如下等方法:視需要而將其他添加劑以特定量調配混合至熱硬化性樹脂、熱硬化劑及高分子量化合物,將所獲得之樹脂組成物塗佈至脫模膜上,使其乾燥而製造膜。上述混合之方法並無特別限定,例如可列舉使用勻相分散機、萬能攪拌機、班布里攪拌機、捏合機等之方法。 The method for producing the adhesive film for semiconductor bonding of the present invention is not particularly limited, and examples thereof include a method in which other additives are blended and blended in a specific amount to a thermosetting resin, a thermosetting agent, and a high molecular weight compound, as needed. The obtained resin composition was applied onto a release film and dried to produce a film. The method of mixing described above is not particularly limited, and examples thereof include a method using a homogeneous phase disperser, a universal mixer, a Banbury mixer, and a kneader.

本發明之半導體接合用接著膜係貼合於附有鋁配線圖案之晶圓者,以貼合於晶圓表面之狀態沿劃線(切割線)被切割。藉此,可獲得貼附有本發明之半導體接合用接著膜之半導體晶片。所獲得之半導體晶片係藉由本發明之半導體接合用接著膜而熱壓接至基板等。 The adhesive film for semiconductor bonding of the present invention is bonded to a wafer having an aluminum wiring pattern, and is cut along a scribe line (cut line) while being bonded to the surface of the wafer. Thereby, a semiconductor wafer to which the adhesive film for semiconductor bonding of the present invention is attached can be obtained. The obtained semiconductor wafer is thermocompression-bonded to a substrate or the like by the adhesive film for semiconductor bonding of the present invention.

將本發明之半導體接合用接著膜貼合於上述附有鋁配線圖案之晶圓之方法並無特別限定,例如可列舉常壓下之層疊、真空層疊等。常壓下之層疊存在夾帶空氣之情形,但亦可於貼合後,使用加壓固化烘箱(例如,PCO-083TA(NTT Advanced Technology公司製造))等,於加壓環境下加熱而去除空隙。 The method of bonding the film for semiconductor bonding of the present invention to the wafer having the aluminum wiring pattern is not particularly limited, and examples thereof include lamination under normal pressure, vacuum lamination, and the like. The laminating air may be present in the lamination under normal pressure, but it may be heated in a pressurized environment to remove voids after being bonded, using a pressure curing oven (for example, PCO-083TA (manufactured by NTT Advanced Technology)).

切割之方法並無特別限定,例如可列舉先前公知之刀片切割等。 The method of cutting is not particularly limited, and examples thereof include previously known blade cutting and the like.

根據本發明,可提供一種於以貼合於晶圓表面之狀態沿劃線(切割線)進行切割時,難以於與晶圓之界面、特別是與劃線上存在鋁配線圖案之晶圓之界面難以產生剝離之半導體接合用接著膜。 According to the present invention, it is possible to provide an interface which is difficult to interface with a wafer, particularly a wafer having an aluminum wiring pattern on a scribe line, when being cut along a scribe line (cut line) in a state of being attached to the surface of the wafer. It is difficult to cause peeling of the adhesive film for semiconductor bonding.

1‧‧‧矽晶圓 1‧‧‧矽 wafer

2‧‧‧劃線 2‧‧‧dick

3‧‧‧半導體晶片 3‧‧‧Semiconductor wafer

4‧‧‧突起電極 4‧‧‧ protruding electrode

5‧‧‧金屬配線圖案 5‧‧‧Metal wiring pattern

6‧‧‧切入線之交點 6‧‧‧The intersection of the entry line

圖1係模式性地表示形成有劃線之矽晶圓表面之一區域的俯視圖。 Fig. 1 is a plan view schematically showing a region of a wafer surface on which a scribe line is formed.

圖2係模式性地說明使用附有鋁膜之晶圓的切割評價之評價方法之俯視圖。 2 is a plan view schematically illustrating an evaluation method of cutting evaluation using a wafer with an aluminum film.

以下,揭示實施例而進一步詳細地對本發明進行說明,但本發明並不僅限定於該等實施例。 Hereinafter, the present invention will be described in further detail by explaining the examples, but the invention is not limited to the examples.

(實施例1) (Example 1)

使用表1中記載之材料。根據表2中記載之調配組成,將各材料添加至作為溶劑之甲基乙基酮(MEK),使用勻相分散機進行攪拌混合,藉此製造接著劑溶液。使用敷抹器(applicator)以乾燥後之厚度成為20μm之方式將所獲得之接著劑溶液塗佈至脫模PET膜上,並進行乾燥,藉此製造接著膜。以脫模PET膜(保護膜)保護所獲得之接著劑層之表面直至使用時 為止。 The materials described in Table 1 were used. According to the blending composition described in Table 2, each material was added to methyl ethyl ketone (MEK) as a solvent, and the mixture was stirred and mixed using a homodisperser to prepare an adhesive solution. The obtained adhesive solution was applied onto a release PET film by using an applicator so as to have a thickness of 20 μm after drying, and dried, whereby an adhesive film was produced. Protecting the surface of the obtained adhesive layer with a release PET film (protective film) until use until.

使用動態黏彈性測定裝置(IT計測控制公司製造之DVA-200),於-50~130℃之溫度範圍內進行步進升溫,以頻率分散模式進行儲存彈性模數測定。假定切割時之水溫而製作於23℃之主曲線,作為相當於切割刀片之轉數之頻率而採用40000rpm/60=667Hz,從而讀取在該頻率下之儲存彈性模數。 The dynamic viscoelasticity measuring device (DVA-200 manufactured by IT Measurement and Control Co., Ltd.) was used to carry out stepwise temperature rise in a temperature range of -50 to 130 ° C, and the storage elastic modulus was measured in a frequency dispersion mode. The main curve of 23 ° C was prepared assuming the water temperature at the time of cutting, and 40000 rpm / 60 = 667 Hz was used as the frequency corresponding to the number of revolutions of the dicing blade, thereby reading the storage elastic modulus at this frequency.

使用接觸角計(KSV Instruments公司製造之KSV CAM200),測定水及二碘甲烷相對於接著膜之貼合於附有鋁配線圖案之晶圓的面(固體表面)的接觸角,根據所獲得之接觸角,使用幾何學平均法而藉由上述式(1)~(3)算出表面自由能γ、該表面自由能γ中之分散成分(γsd)及極性成分(γsp)。再者,滴加2μL之水、3μL之二碘甲烷,測定滴加30秒後之接觸角。 Using a contact angle meter (KSV CAM200 manufactured by KSV Instruments Co., Ltd.), the contact angle of water and diiodomethane with respect to the surface of the film attached to the wafer with the aluminum wiring pattern (solid surface) was measured, according to the obtained The contact angle is calculated by the above-described equations (1) to (3) using the geometric mean method, and the dispersion component (γsd) and the polar component (γsp) in the surface free energy γ are calculated. Further, 2 μL of water and 3 μL of diiodomethane were added dropwise, and the contact angle after the dropwise addition for 30 seconds was measured.

(實施例2~7、比較例1~2) (Examples 2 to 7 and Comparative Examples 1 to 2)

除設為表2中記載之調配組成外,與實施例1相同地獲得接著膜。 An adhesive film was obtained in the same manner as in Example 1 except that the composition shown in Table 2 was used.

<評價> <evaluation>

對實施例、比較例中獲得之接著膜進行以下之評價。將結果示於表2。 The following films obtained in the examples and the comparative examples were subjected to the following evaluations. The results are shown in Table 2.

(1)使用附有鋁膜之晶圓之切割評價 (1) Cutting evaluation using a wafer with an aluminum film

準備附有鋁膜之晶圓(8英吋大小,厚度為725μm)。鋁膜係如下者:形成於晶圓整個面,於熱氧化膜(1000ű10%)上形成有Al-Cu膜(5000ű10%)。其次,使用真空貼合機(Takatori公司製造之ATM-812),於80℃、100Pa之真空度下,將切割成50mm×50mm尺寸之接著膜(厚度為20μm)貼合於晶圓表面。 Prepare a wafer with an aluminum film (8 inches in size and 725 μm in thickness). The aluminum film is formed on the entire surface of the wafer, and an Al-Cu film (5000 Å ± 10%) is formed on the thermal oxide film (1000 Å ± 10%). Next, using a vacuum laminator (ATM-812 manufactured by Takatori Co., Ltd.), an adhesive film (thickness: 20 μm) cut into a size of 50 mm × 50 mm was bonded to the surface of the wafer at a vacuum of 100 °C at 80 °C.

於圖2中表示模式性地說明使用附有鋁膜之晶圓的切割評價之評價方法之俯視圖。使用切割刀片(DISCO公司製造之ZH05-SD4800N1-70),以23℃之水溫、40000rpm之刀片轉數、20mm/sec之進給速度,如圖2所示般 按照5mm之間隔,於XY方向上自接著膜之表面對晶圓1進行切割。此時之晶圓之切入深度係設為100μm。對晶圓之切入線之交點6之25個部位進行顯微鏡觀察,對於與切入線相接之接著膜有無剝離,以4分(實質上為零)、2分(存在數個部位)、0分(產生多個)3個等級進行評分,將綜合得分設為點數(0~100pt)。如下般進行○×判定。 FIG. 2 is a plan view schematically illustrating an evaluation method of cutting evaluation using a wafer with an aluminum film. Using a cutting blade (ZH05-SD4800N1-70 manufactured by DISCO), with a water temperature of 23 ° C, a number of revolutions of 40,000 rpm, and a feed speed of 20 mm/sec, as shown in Fig. 2 The wafer 1 was cut from the surface of the bonding film in the XY direction at intervals of 5 mm. The dicing depth of the wafer at this time was set to 100 μm. Microscopic observation of 25 parts of the intersection point 6 of the incision line of the wafer, and whether there is peeling of the film adjacent to the incision line, with 4 points (substantially zero), 2 points (there are several parts), 0 points (Generate multiple) 3 levels for scoring, and the comprehensive score is set to the number of points (0~100pt). The ○× determination was performed as follows.

×:0~30pt ×: 0~30pt

△:31~60pt △: 31~60pt

○:61~90pt ○: 61~90pt

◎:91~100pt ◎: 91~100pt

(2)使用附有鋁配線圖案之晶圓之切割評價 (2) Cutting evaluation using a wafer with an aluminum wiring pattern

使用於劃線上形成有鋁配線圖案之晶圓(12英吋大小,厚度為100μm)進行切割評價。於使用真空貼合機(Takatori公司製造之ATM-812),以80℃、100Pa之真空度將接著膜貼合於晶圓表面整體後,使用切割刀片(DISCO公司製造之ZH05-SD4800N1-70),以23℃之水溫、40000rpm之刀片轉數、20mm/sec之進給速度,沿劃線對晶圓進行全切(full-cut)而切割。 A wafer having an aluminum wiring pattern formed on a scribe line (12-inch size, thickness: 100 μm) was used for the evaluation of the cut. After using a vacuum laminator (ATM-812 manufactured by Takatori Co., Ltd.), the adhesive film was bonded to the entire surface of the wafer at a vacuum of 80 ° C and 100 Pa, and a dicing blade (ZH05-SD4800N1-70 manufactured by DISCO Corporation) was used. The wafer was cut by a full-cut along the scribe line at a water temperature of 23 ° C, a number of blade revolutions of 40,000 rpm, and a feed speed of 20 mm/sec.

藉由目視觀察有無接著膜之剝離,將有剝離部位者判定為×,將無剝離部位者判定為○。 The presence or absence of peeling of the adhesive film was visually observed, and the peeled portion was judged as ×, and the non-peeled portion was judged as ○.

[產業上之可利用性] [Industrial availability]

根據本發明,可提供一種於以貼合於晶圓表面之狀態沿劃線(切割線)進行切割時,難以於與晶圓之界面、特別是與劃線上存在鋁配線圖案之晶圓之界面難以產生剝離之半導體接合用接著膜。 According to the present invention, it is possible to provide an interface which is difficult to interface with a wafer, particularly a wafer having an aluminum wiring pattern on a scribe line, when being cut along a scribe line (cut line) in a state of being attached to the surface of the wafer. It is difficult to cause peeling of the adhesive film for semiconductor bonding.

1‧‧‧矽晶圓 1‧‧‧矽 wafer

2‧‧‧劃線 2‧‧‧dick

3‧‧‧半導體晶片 3‧‧‧Semiconductor wafer

4‧‧‧突起電極 4‧‧‧ protruding electrode

5‧‧‧金屬配線圖案 5‧‧‧Metal wiring pattern

Claims (1)

一種半導體接合用接著膜,其係貼合於附有鋁配線圖案之晶圓者,其特徵在於:(1)在相當於切割刀片之轉數之頻率下之儲存彈性模數為7.5GPa以下,及/或(2)使用2種以上表面能為既知之測定試劑進行測定,所得到之貼合於附有鋁配線圖案之晶圓的面之表面自由能γ中之分散成分(γsd)為30mJ/m2以上。 An adhesive film for semiconductor bonding, which is bonded to a wafer having an aluminum wiring pattern, wherein: (1) the storage elastic modulus at a frequency corresponding to the number of revolutions of the dicing blade is 7.5 GPa or less. And/or (2) using two or more types of surface energy to measure the known measurement reagent, and the obtained dispersion component (γsd) of the surface free energy γ of the surface of the wafer to which the aluminum wiring pattern is attached is 30 mJ. /m 2 or more.
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