TW201517210A - 在銅金屬化中用於自形成阻障製程之電子遷移增進方法 - Google Patents

在銅金屬化中用於自形成阻障製程之電子遷移增進方法 Download PDF

Info

Publication number
TW201517210A
TW201517210A TW103118744A TW103118744A TW201517210A TW 201517210 A TW201517210 A TW 201517210A TW 103118744 A TW103118744 A TW 103118744A TW 103118744 A TW103118744 A TW 103118744A TW 201517210 A TW201517210 A TW 201517210A
Authority
TW
Taiwan
Prior art keywords
layer
manganese
forming
via hole
based insulating
Prior art date
Application number
TW103118744A
Other languages
English (en)
Other versions
TWI556351B (zh
Inventor
Moosung Chae
Larry Zhao
Original Assignee
Globalfoundries Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Us Inc filed Critical Globalfoundries Us Inc
Publication of TW201517210A publication Critical patent/TW201517210A/zh
Application granted granted Critical
Publication of TWI556351B publication Critical patent/TWI556351B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

提供一種形成阻障在導孔之側壁及底部上之方法及所產生的元件。實施例包括:形成金屬線在基板中;形成矽基絕緣層在該金屬線及該基板上方;向下形成導孔在該矽基絕緣層中直到該金屬線;形成雙層的錳(Mn)/氮化錳(MnN)在該導孔的側壁及底面上;以及以金屬填充該導孔。

Description

在銅金屬化中用於自形成阻障製程之電子遷移增進方法
本發明係關於半導體互連。本發明特別可應用於在半導體互連中形成擴散阻障
銅是用於微電子元件之接線的已知材料。擴散阻障防止例如銅、氧(O2)及水擴散進入微電子元件的二氧化矽表面(silica surface)。在現今的半導體工業趨勢中,矽酸錳鹽(MnSiOx)是一種最新引進的自形成阻障(self-forming barrier;SFB),用來取代傳統的擴散阻障。
一種SFB的已知方法包括藉由錳(Mn)的化學汽相沉積(CVD)的自形成阻障製程,其中錳擴散進入矽基(Si-based)絕緣層中以形成矽酸錳鹽(MnSiOx)阻障在導孔的側壁上,如第1A-1F圖所示。特別的是,金屬線101(例如由銅形成)係形成在基板103中。接著,覆蓋層(capping layer)121(例如氮化矽(SiN))係形成在基板103上,如第1B圖所示。然後,矽基絕緣層123係形成在覆蓋層121上。 注意到第1C圖,導孔被形成在矽基絕緣層123中,向下直到金屬線101。之後,使用化學氣相沉積,錳金屬層141係形成在矽基絕緣層123的側壁和金屬線101上,如第1D圖所示。注意到第1E圖,由於有足夠高的沉積溫度或熱退火,所以錳金屬層141會與矽基絕緣層123反應而形成矽酸錳鹽阻障層143在導孔的側壁上。然而,在導孔底部上的錳金屬層141並不會同樣地與金屬線101反應。之後,如第1F圖所示,導孔係用金屬161(譬如銅)填充。譬如由於電子遷移,在導孔底部上缺少矽酸錳鹽阻障層會造成元件可靠度的退化。
因此,需要一種能夠形成自形成阻障的方法及所產生之元件,其係保護導孔的底部及側壁以防止不需要的擴散及/或電子遷移。
本發明之一態樣是一種藉由原子層沉積製程在導孔的側壁及底部上原位形成雙層的Mn/MnN的方法。
本發明之另一態樣是一種元件,其包含形成在導孔的側壁及底部上之雙層的Mn/MnN。
本發明之另外態樣及其它特徵將會在下列實施方式中提出,而且對本技術領域中具有通常知識者而言,在檢視完下列實施方式後部分內容將變得顯而易見,或者可藉由實施本發明而了解。如申請專利範圍中特別指出者,可了解及獲得本發明之優點。
依照本發明,藉由下述方法可部分達到某些技術效果,該方法包括:在基板中形成金屬線;在金屬線及基板上方形成矽基絕緣層;向下形成導孔在矽基絕緣層中直到金屬線;在導孔的側壁及底面上形成雙層的Mn/MnN;以及用金屬填充導孔。
本發明之態樣包括在原子層沉積腔室中藉由原子層沉積製程或是在化學氣相沉積腔室中藉由化學氣相沉積製程而原位形成雙層。其他態樣包括:在原子層沉積腔室中藉由沉積錳而形成雙層;以及在原子層沉積製程期間添加含氮氣體至腔室。額外態樣包括使用例如氮氣(N2)或氨氣(NH3)的含氮氣體。另一態樣包括在200℃到450℃的溫度形成雙層。其它態樣包括在0.1托爾(Torr)到10托爾的壓力形成雙層。進一步態樣包括形成由二氧化矽(SiO2)或是極低介電常數的介電材料組成之矽基絕緣層。額外態樣包括錳層在導孔之側壁處與二氧化矽或極低介電常數(ULK)的介電材料反應而形成厚度為3埃(Å)至30埃(Å)的矽酸錳鹽(MnSiOx)層,以及在矽酸錳鹽層上和在導孔之底面上的錳層上形成厚度為3埃(Å)至30埃(Å)的氮化錳層。其他態樣包括進行熱退火,其中錳與矽基絕緣層在側壁處反應而形成矽酸錳鹽阻障層。額外態樣包括在形成矽基介電層之前先在金屬線及基板上方形成覆蓋層,然後形成導孔穿過覆蓋層。
本發明之另一態樣是一種元件,包括:在基板中之金屬線;在基板及金屬線上之矽基絕緣層;向下 穿過矽基絕緣層直至金屬線而形成的導孔;在導孔之底面的金屬線上形成的錳層;在導孔的側壁上形成的矽酸錳鹽(MnSiOx)層;在矽酸錳鹽層及錳層上形成的氮化錳(MnN)層;以及填充導孔之金屬。該元件的態樣包括厚度形成為3埃(Å)到30埃(Å)的矽酸錳鹽層。其它的態樣包括厚度形成為3埃(Å)到30埃(Å)的氮化錳層。另外的態樣包括由二氧化矽或極低介電常數的介電材料形成之矽基絕緣層。另外的態樣包括形成在基板上、矽基介電層之下的覆蓋層。另外的態樣包括由氮化矽(SiN)、金屬蓋層、鈷(Co)或鈷/鎢/鋁(CoWAl)形成之覆蓋層。其它的態樣包括填充由銅形成之導孔的金屬。
本發明之另一態樣是一種方法,包括:形成金屬線在基板中;形成矽基絕緣層在金屬線及基板上方;向下形成導孔在矽基絕緣層中直到金屬線;在原子層沉積腔室中藉由原子層沉積或是在化學氣相沉積腔室中藉由化學氣相沉積製程而在導孔之側壁和底面上沉積錳;在原子層沉積期間添加含氮氣體至原子層沉積腔室,從而在導孔的側壁及底面上沉積形成厚度3埃(Å)至30埃(Å)的氮化錳(MnN)層;以及實施熱退火,其中,錳(Mn)與矽基絕緣層在導孔的側壁處反應,形成厚度自3埃(Å)到30埃(Å)的矽酸錳鹽阻障層。其它態樣包括使用含氮氣體,譬如氮氣(N2)或氨氣(NH3)。更進一步態樣包括形成由二氧化矽(SiO2)或極低介電常數的介電材料組成的矽基絕緣層
對於本技術領域中具有通常知識者而言在 參閱下列實施方式後,本發明之額外態樣及技術效果將變得顯而易見,其中本發明之實施例係僅藉由所思及用以實施本發明的最佳模式來加以描述。將能了解到的是,本發明能有其他及不同的實施例,而其數個細節能就各種明顯重點加以修改,全都不偏離本發明之揭露。所以,圖式及描述本質上應被視作例示性,而非限制性。
101‧‧‧金屬線
103‧‧‧基板
121‧‧‧覆蓋層
123‧‧‧矽基絕緣層
141‧‧‧錳金屬層
143‧‧‧矽酸錳鹽阻障層
161‧‧‧金屬
201‧‧‧金屬線
203‧‧‧基板
205‧‧‧二氧化矽或極低介電常數的介電材料
301‧‧‧覆蓋層
303‧‧‧矽基絕緣層
501‧‧‧錳(Mn)層
601‧‧‧矽酸錳鹽(Manganese silicate)
701‧‧‧氮化錳(MnN)
801‧‧‧金屬
本發明是藉由隨附圖式中的實例來做說明,而不是藉此限制,其中相同的元件符號指代類似的元件,且其中:第1A至1F圖示意地說明利用化學氣相沉積錳的自形成阻障製程之先前方法的一系列步驟;以及第2至8圖係根據例示實施例示意地說明在原子層沉積腔室中藉由原子層沉積製程或是在化學氣相沉積腔室中藉由化學氣相沉積製程而原位形成雙層的錳/氮化錳之方法的一系列步驟。
在下列實施方式中,為了解釋的目的,係提出許多的特定細節以提供對於例示實施例的詳盡了解。然而,顯然地,沒有這些特定細節或等效配置也能夠實施這些例示實施例。在其它的實例中,為了避免不必要地模糊例示實施例,係以方塊圖形式顯示大家所熟悉的結構及元件。此外,除非特別指出,在說明書及申請專利範圍中用來表示數量、比例及成份的數值特性、反應條件等等的 所有數字應該被理解為在所有實例中被修飾成大約的說法。
本發明提出並且解決現今自形成阻障製程(例如錳的化學氣相沉積)伴隨而來的元件可靠度下降的問題(例如,電子遷移),其中,矽酸錳鹽阻障最終會在導孔的側壁上形成,但不會在導孔的底部中形成。藉由在導孔形成雙層的Mn/MnN,係在導孔的所有表面上(包括底面)形成阻障。
根據本發明之實施例的方法包括形成金屬線在基板中。矽基絕緣層係形成在金屬線及基板上方。導孔是向下形成在矽基絕緣層中直到金屬線。雙層的Mn/MnN是形成在導孔的側壁及導孔的底面上。導孔是用金屬填充。
對本技術領域中具有通常知識者而言,從下列實施方式能立刻了解到仍然有其他的態樣、特徵及技術功效,其中,簡單藉由說明所思及之最佳模式來顯示及描述較佳實施例。本發明能有其它以及不同的實施例,並且其中一些細節能夠以各個明顯重點修改。因此,圖示及描述本質上應被視為例示性,而非限制性。
第2至8圖係根據例示實施例示意地圖示一種藉由ALD製程在ALD腔室中或藉由CVD製程而在原地(in situ)形成Mn/MnN的双層阻障的方法的一系列步驟。注意第2圖,相似於在第1A至1F圖所討論的先前技術製程,金屬線(例如,銅)係形成在基板203中。然後,由氮化矽 (SiN)、鈷(Co)、金屬蓋層或鈷鎢鋁(CoWAl)形成的覆蓋層係形成在金屬線201及基板203上,接著將矽基絕緣層303(例如,二氧化矽(SiO2)或極低介電常數(ULK)的介電材料)形成在覆蓋層301之頂部上,如第3圖所示。注意第4圖導孔被向下形成在矽基絕緣層303中直至金屬線201。
接著,雙層的Mn/MnN形成在導孔中,係在ALD腔室(為了說明的方便,未圖示)中藉由ALD製程或在CVD腔室(為了說明的方便,也未圖示)中藉由CVD製程而形成。首先,如第5圖所示,藉著原子層沉積,錳(Mn)層501被沉積在,譬如,導孔的側壁上(在矽基絕緣層303上)以及導孔的底面上(在金屬線201上)。錳(Mn)係以範圍從200℃到450℃的溫度沉積,並且壓力範圍在0.1托爾(Torr)到10托爾(Torr),因此,如第6圖所示,錳(Mn)層501在導孔的側壁與二氧化矽(SiO2)或極低介電常數(ULK)的介電材料205反應,以形成一層厚度從3Å到30Å的矽酸錳鹽(MnSiOx)601。或者,在之後的退火期間,錳(Mn)層與在導孔側壁的上的二氧化矽(SiO2)反應,形成矽酸錳鹽(MnSiOx)層601。
注意第7圖,之後,,在矽酸錳鹽(MnSiOx)601及錳(Mn)層501上原位沉積氮化錳(MnN)層701至3Å到30Å的厚度。特別是,當繼續錳的ALD沉積時,藉著添加適量的含氮氣體(譬如氮氣(N2)、氨氣(NH3))而形成氮化錳(MnN)層701。最後,如第8圖所示,導孔係以金屬801(譬如,銅)填充。
本發明的實施例能夠達到數種技術效果,包括改善元件的可靠度,也就是說,降低電子遷移,並且有一個更強健的阻障以防止銅(Cu)及氧在導孔中的擴散。本發明之實施例,在各種工業應用中享有它的實用性,例如,微處理器、智慧手機、行動電話、機上盒(set-top boxes)、數位影音記錄及播放機、自動導航、影印機及其週邊、網路及通訊設備、遊戲系統和數位相機,因此,本發明在包含銅互連結構之任何不同類型的積體電路中享有工業實用性。
在前述的描述中,本發明係參照特定例示實施例加以描述。然而,顯然在沒有偏離本發明之較寬的精神及範圍下,如申請專利範圍中提出者,也能進行各種修改。因此,本發明之說明書及圖式應被視為例示性而非限制性。應理解,本發明係能使用各種其他組合和實施例,並且能在此表示之發明概念範圍內進行任何的改變及修正。
201‧‧‧金屬線
203‧‧‧基板
205‧‧‧二氧化矽或極低介電常數的介電材料
301‧‧‧覆蓋層
501‧‧‧錳(Mn)層
601‧‧‧矽酸錳鹽(Manganese silicate)
701‧‧‧氮化錳(MnN)
801‧‧‧金屬

Claims (20)

  1. 一種方法,包括:形成金屬線在基板中;形成矽基絕緣層在該金屬線及該基板上方;向下形成導孔在該矽基絕緣層中直至該金屬線;形成雙層的錳(Mn)/氮化錳(MnN)在該導孔的側壁上及底面上;以及以金屬填充該導孔。
  2. 如申請專利範圍第1項所述之方法,包括:在原子層沉積腔室中藉由原子層沉積製程或是在化學氣相沉積腔室中藉由化學氣相沉積製程而原位形成該雙層。
  3. 如申請專利範圍第2項所述之方法,包括:藉由在該原子層沉積腔室中沉積錳而形成該雙層;以及在該原子層沉積製程期間,添加含氮氣體至該腔室。
  4. 如申請專利範圍第3項所述之方法,其中,該含氮氣體包括氮氣(N2)或是氨氣(NH3)。
  5. 如申請專利範圍第3項之方法,包括以200℃到450℃的溫度形成該雙層。
  6. 如申請專利範圍第3項所述之方法,包括以0.1托爾到10托爾的壓力形成該雙層。
  7. 如申請專利範圍第3項所述之方法,包括形成二氧化 矽(SiO2)或是極低介電常數的介電材料的該矽基絕緣層。
  8. 如申請專利範圍第7項之方法,其中,該氮化錳層與該二氧化矽或是該極低介電常數的介電材料在該導孔的該側壁反應,以形成厚度為3埃(Å)到30埃(Å)的矽酸錳鹽(MnSiOx),以及形成厚度為3埃(Å)到30埃(Å)的錳層在該矽酸錳鹽上以及在該導孔的該底面上之該錳層上。
  9. 如申請專利範圍第1項所述之方法,實施熱退火,其中,該錳與該矽基絕緣層在該導孔的該側壁反應,以形成該矽酸錳鹽阻障層。
  10. 如申請專利範圍第1項所述之方法,更包括在形成該矽基絕緣層之前在該金屬線及基板上方形成覆蓋層,以及形成該導孔穿過該覆蓋層。
  11. 一種元件,包括:在基板中之金屬線;在該基板及該金屬線上之矽基絕緣層;向下穿過該矽基絕緣層直至該金屬線所形成的導孔;在該導孔之底面的該金屬線上所形成的錳層;在該導孔的側壁上所形成的矽酸錳鹽(MnSiOx)層;在該矽酸錳鹽層及錳層上所形成的氮化錳(MnN)層;以及填充該導孔之金屬。
  12. 如申請專利範圍第11項所述之元件,其中,該矽酸錳鹽層具有3埃(Å)到30埃(Å)的厚度。
  13. 如申請專利範圍第12項所述之元件,其中,該氮化錳層具有3埃(Å)到30埃(Å)的厚度。
  14. 如申請專利範圍第11項所述之元件,其中,該矽基絕緣層包括二氧化矽(SiO2)或是極低介電常數的介電材料。
  15. 如申請專利範圍第11項所述之元件,更包括在該基板上而在該矽基絕緣層下方的覆蓋層。
  16. 如申請專利範圍第15項所述之元件,其中,該覆蓋層係由氮化矽(SiN)、金屬覆蓋、鈷(Co)或鈷/鎢/鋁(CoWAl)形成。
  17. 如申請專利範圍第11項所述之元件,其中,填充該導孔的金屬包括銅。
  18. 一種方法,包括:形成金屬線在基板中;形成矽基絕緣層在該金屬線及該基板上方;向下形成導孔在該矽基絕緣層中直到該金屬線,在原子層沉積腔室中藉由原子層沉積或是在化學氣相沉積腔室中藉由化學氣相沉積製程而在該導孔的側壁及底面上沉積錳;在該原子層沉積期間添加含氮氣體至該原子層沉積腔室,以在該導孔的該側壁及該底面上形成厚度為3埃(Å)到30埃(Å)的氮化錳(MnN)層;以及 進行熱退火,其中,該錳與該矽基絕緣層在該導孔之該側壁反應,以形成厚度為3埃(Å)到30埃(Å)的矽酸錳鹽(MnSiOx)層。
  19. 如申請專利範圍第18項所述之元件,其中,該含氮氣體包括氮氣(N2)或是氨氣(NH3)。
  20. 如申請專利範圍第19項所述之元件,包括形成二氧化矽(SiO2)或是極低介電常數的介電材料之該矽基絕緣層。
TW103118744A 2013-10-22 2014-05-29 在銅金屬化中用於自形成阻障製程之電子遷移增進方法 TWI556351B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/059,498 US9362228B2 (en) 2013-10-22 2013-10-22 Electro-migration enhancing method for self-forming barrier process in copper metalization

Publications (2)

Publication Number Publication Date
TW201517210A true TW201517210A (zh) 2015-05-01
TWI556351B TWI556351B (zh) 2016-11-01

Family

ID=52825491

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103118744A TWI556351B (zh) 2013-10-22 2014-05-29 在銅金屬化中用於自形成阻障製程之電子遷移增進方法

Country Status (3)

Country Link
US (2) US9362228B2 (zh)
CN (1) CN104576420B (zh)
TW (1) TWI556351B (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997457B2 (en) * 2013-12-20 2018-06-12 Intel Corporation Cobalt based interconnects and methods of fabrication thereof
US9275952B2 (en) * 2014-01-24 2016-03-01 International Business Machines Corporation Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects
US9847289B2 (en) * 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9564356B2 (en) * 2015-04-16 2017-02-07 International Business Machines Corporation Self-forming metal barriers
KR102420087B1 (ko) 2015-07-31 2022-07-12 삼성전자주식회사 반도체 소자의 제조 방법
US9972529B2 (en) * 2015-09-28 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming metal interconnection
US9349687B1 (en) 2015-12-19 2016-05-24 International Business Machines Corporation Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect
US9711456B2 (en) 2015-12-19 2017-07-18 International Business Machines Corporation Composite manganese nitride/low-K dielectric cap
US9719167B2 (en) 2015-12-31 2017-08-01 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Cobalt-containing film forming compositions, their synthesis, and use in film deposition
US10011903B2 (en) 2015-12-31 2018-07-03 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Manganese-containing film forming compositions, their synthesis, and use in film deposition
US10446496B2 (en) 2016-02-17 2019-10-15 International Business Machines Corporation Self-forming barrier for cobalt interconnects
US10438847B2 (en) * 2016-05-13 2019-10-08 Lam Research Corporation Manganese barrier and adhesion layers for cobalt
US10256191B2 (en) 2017-01-23 2019-04-09 International Business Machines Corporation Hybrid dielectric scheme for varying liner thickness and manganese concentration
KR102403731B1 (ko) 2017-11-01 2022-05-30 삼성전자주식회사 가변 저항 메모리 소자
US10224284B1 (en) 2018-01-05 2019-03-05 Globalfoundries Inc. Soluble self aligned barrier layer for interconnect structure
US11004736B2 (en) 2019-07-19 2021-05-11 International Business Machines Corporation Integrated circuit having a single damascene wiring network
US11164778B2 (en) 2019-11-25 2021-11-02 International Business Machines Corporation Barrier-free vertical interconnect structure
US20220068708A1 (en) * 2020-08-26 2022-03-03 Macom Technology Solutions Holdings, Inc. Atomic layer deposition of barrier metal layer for electrode of gallium nitride material device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090117731A1 (en) * 2007-11-01 2009-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor interconnection structure and method for making the same
US7651943B2 (en) * 2008-02-18 2010-01-26 Taiwan Semicondcutor Manufacturing Company, Ltd. Forming diffusion barriers by annealing copper alloy layers
US8106512B2 (en) * 2008-02-29 2012-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Low resistance high reliability contact via and metal line structure for semiconductor device
US8013445B2 (en) * 2008-02-29 2011-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Low resistance high reliability contact via and metal line structure for semiconductor device
US7932176B2 (en) * 2008-03-21 2011-04-26 President And Fellows Of Harvard College Self-aligned barrier layers for interconnects
WO2011050073A1 (en) * 2009-10-23 2011-04-28 President And Fellows Of Harvard College Self-aligned barrier and capping layers for interconnects
US8637390B2 (en) * 2010-06-04 2014-01-28 Applied Materials, Inc. Metal gate structures and methods for forming thereof
JP5755471B2 (ja) * 2011-03-10 2015-07-29 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9048294B2 (en) * 2012-04-13 2015-06-02 Applied Materials, Inc. Methods for depositing manganese and manganese nitrides

Also Published As

Publication number Publication date
CN104576420A (zh) 2015-04-29
CN104576420B (zh) 2017-12-12
US9666524B2 (en) 2017-05-30
US20160225712A1 (en) 2016-08-04
US20150108646A1 (en) 2015-04-23
US9362228B2 (en) 2016-06-07
TWI556351B (zh) 2016-11-01

Similar Documents

Publication Publication Date Title
TWI556351B (zh) 在銅金屬化中用於自形成阻障製程之電子遷移增進方法
US7507659B2 (en) Fabrication process of a semiconductor device
TWI643292B (zh) 形成金屬內連線的方法以及使用該方法製造半導體裝置的方法
US7935624B2 (en) Fabrication method of semiconductor device having a barrier layer containing Mn
JP7066929B2 (ja) インターコネクトのためのルテニウムメタルによるフィーチャ充填
US7498242B2 (en) Plasma pre-treating surfaces for atomic layer deposition
US8072075B2 (en) CuSiN/SiN diffusion barrier for copper in integrated-circuit devices
US20110256715A1 (en) Barrier layer for copper interconnect
US20150017800A1 (en) Interconnect Structure for Semiconductor Devices
US9059259B2 (en) Hard mask for back-end-of-line (BEOL) interconnect structure
CN104733378A (zh) 半导体结构及其制造方法
US20150228585A1 (en) Self-forming barrier integrated with self-aligned cap
US9947580B2 (en) Interconnect structures with enhanced electromigration resistance
US20100090342A1 (en) Metal Line Formation Through Silicon/Germanium Soaking
CN108063117B (zh) 互连结构及其形成方法
US9613906B2 (en) Integrated circuits including modified liners and methods for fabricating the same
CN108122821B (zh) 互连结构及其形成方法
JP2009094477A (ja) 半導体素子の金属配線形成方法
TW202123385A (zh) 積體電路結構及其形成方法
JP5917603B2 (ja) 半導体装置およびその製造方法
KR100895811B1 (ko) 반도체 소자의 금속배선 형성방법
KR20050003024A (ko) 다마신 공정을 이용한 반도체소자 제조방법
TW201824450A (zh) 基板中之凹陷特徵部的金屬填充方法