TW201513307A - Method of manufacturing a device - Google Patents

Abstract

A method of manufacturing a device includes a step of forming a plurality of device isolation regions each of which has a protruding portion protruding upward from an upper surface of a semiconductor substrate and forming a first recessed portion between every two adjacent protruding portions, a step of forming and laminating a charge trap layer and a protective insulating film so as to cover a bottom surface of the first recessed portion and side surfaces and an upper surface of the protruding portion and forming, in the first recessed portion, a second recessed portion constructed of the protective insulating film, a step of forming a sacrificing film throughout an entire surface so as to fill the second recessed portion, and a step of etching and removing the sacrificing film, the protective insulating film, the charge trap layer and the protruding portion until a surface of the protective insulating film, which defines a bottom of the second recessed portion, is exposed.

Description

Device manufacturing method

The present invention relates to a method of fabricating a device, and more particularly to a method of fabricating a charge trapping NAND flash memory device.

In recent years, NAND type flash memory has been put into practical use as a large-capacity semiconductor memory device. NAND type flash memory has two types of floating gate type and charge trap type. For example, Patent Document 1 discloses a floating gate type flash memory. Further, for example, Patent Document 2 or 3 discloses a charge trap type flash memory. Further, Patent Document 4 discloses a flash memory device in which a charge trap layer is formed on the side surface of the element-separating insulating film which is formed in a protruding manner, and a method of manufacturing the same.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2007-193862

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2010-10323

[Patent Document 3] Japanese Patent Laid-Open Publication No. 2011-23097

[Patent Document 4] US Patent Application Publication No. 2011/0195578

In terms of miniaturization of the flash memory device, the charge trapping type is more suitable than the floating gate type. In order to achieve further miniaturization of the charge trap type flash memory device, it is disclosed that in the flash memory device of Patent Document 4, the element isolation insulating film is protruded above the upper surface of the semiconductor substrate and formed on the active region. The charge trap layer extends to the side of its projection.

The formation of the charge trap layer is performed by performing etch back by separating the charge trap layer into each unit after the entire formation of the charge film as the charge trap layer. At this time, the protrusion from the element-separating insulating film is etched from the upper side to reduce the height thereof. The height (the height of the side edge portion) of the charge trap layer formed on the side of the protruding portion of the element isolation region coincides with the height of the protruding portion of the element isolation region.

Here, the height of the side edge portion of the charge trap layer greatly affects the characteristics of the memory cell. Therefore, the etch back of the charge trap layer must be such that the height of the side edge portion becomes a predetermined height.

However, in the method of manufacturing a related semiconductor device, etch back is performed by time control. Therefore, when the height of the protruding portion of the element isolation insulating film before the etch back varies due to variations or the like, the protruding portion after etching The height and the height of the side edge portion of the charge trap layer also vary. As a result, there is a problem that the semiconductor device having the desired characteristics cannot be stably manufactured.

A method of manufacturing a device according to an embodiment of the present invention is characterized by comprising: forming a plurality of element isolation regions having protrusions protruding above the upper surface of the semiconductor substrate, and forming a first portion between the adjacent protrusions a recessed portion; a charge trap layer and a protective insulating film are laminated to cover a bottom surface of the first recess and a side surface and an upper surface of the protruding portion, and the protective insulating film is formed in the first recess The second concave portion is formed; the sacrificial film is entirely formed by embedding the second concave portion; and the sacrificial film, the protective insulating film, the charge trap layer, and the protruding portion are removed by etching using a dry etching method. The bottom surface of the second recess is a process until the surface of the protective insulating film is exposed.

According to the invention, the second concave portion is formed by laminating the charge trap layer and the protective insulating film in the first recess formed between the protruding portions of the adjacent element isolation regions. Further, a sacrificial film in which the second concave portion is buried is formed. Then, the sacrificial film, the protective insulating film, the charge trap layer, and the protruding portion are removed by dry etching until the bottom surface of the second recess is the surface of the protective insulating film. Accordingly, the height of the protrusion before the dry etching is not dependent, and the side edge of the charge trap layer formed on the side of the protrusion can be controlled. Height, and can safely manufacture devices with expected characteristics.

1‧‧‧Semiconductor substrate

1a‧‧‧above

1b‧‧‧ trench

2‧‧‧Component separation area

2a‧‧‧Component separation insulating film

2b‧‧‧Protruding

2c‧‧‧above

2d‧‧‧ side

3‧‧‧Active area

4, 4a‧‧‧ pad oxide film

5‧‧‧ nitride film

6‧‧‧ bottom oxide film

7‧‧‧ Charge trapping layer

7a‧‧‧lateral edge

8‧‧‧Protective insulation film

8a‧‧‧Surface

9‧‧‧Sacrificial film

10‧‧‧Top yttrium oxide film

11‧‧‧Polysilicon layer

12‧‧‧ Telluride layer

13‧‧‧ nitride film

14‧‧‧Interlayer insulating film

15‧‧‧Metal wiring

16‧‧‧Contacts

20‧‧‧ONO gate insulating film

21‧‧‧ core gate electrode (character line)

23‧‧‧1st recess

24‧‧‧2nd recess

24a‧‧‧ bottom

100‧‧‧Semiconductor device

1 is a cross-sectional view showing a state in the middle of manufacture of a semiconductor device according to a comparative example.

Fig. 2 is a cross-sectional view showing a state in which an etch back process and a sacrificial film removal process are performed after the state shown in Fig. 1 is shown.

3 is a cross-sectional view showing a state in which the height of the protruding portion is lower than that of the semiconductor device shown in FIG. 1 .

Fig. 4 is a cross-sectional view showing a state in which an etch back process and a sacrificial film removal process are performed after the state shown in Fig. 3;

Fig. 5 is a plan view showing a device according to a first embodiment of the present invention.

Figure 6 is a cross-sectional view taken along line A-A' of Figure 5;

Fig. 7 is a cross-sectional view showing the construction of the apparatus shown in Figs. 5 and 6;

Figure 8 is a cross-sectional view for explaining the process continued from Figure 7.

Figure 9 is a cross-sectional view for explaining the process continued from Figure 8.

Figure 10 is a cross-sectional view for explaining the process continued from Figure 9.

Figure 11 is a cross-sectional view for explaining the construction continued from Figure 10.

Figure 12 is a cross-sectional view for explaining the process continued from Figure 11.

Before explaining the embodiments of the present invention, the comparative examples studied by the inventors will be described, and the problems to be solved by the present invention will be more clearly defined. Further, here, as the semiconductor device, a charge trap type NAND flash nonvolatile memory (hereinafter referred to as a CT type memory) is assumed.

(Comparative example)

In order to achieve the miniaturization of the CT-type memory, a part of the insulating film is formed so as to protrude above the upper surface of the semiconductor substrate, and the memory cell is formed by separating the side faces of the protruding portions of the insulating film (see Patent Document 4). .

The charge trapping layer in such a configuration is formed on the upper surface and the side surface of the protruding portion including the element isolation insulating film, and the interlayer is formed as an insulating film of a charge trap layer, such as a SiRN (Silicon Rich Nitride) film, and protective insulation. After the film, etch back is performed by removing unnecessary portions.

1 is a cross-sectional view showing a state in the middle of manufacture of a semiconductor device according to a comparative example. Specifically, a state in which the sacrificial film 9 used for etchback is formed on the protective insulating film 8 is completed. As shown in the figure, the trench 1b formed in the semiconductor substrate 1 is buried in the element isolation insulating film 2a via the pad oxide film 4a. One portion of the element isolation insulating film 2a protrudes above the upper surface 1a of the semiconductor substrate 1. Further, a bottom yttrium oxide film (bottom insulating film) 6 is formed on the upper surface of the semiconductor substrate 1. And, to cover the protrusion of the bottom yttrium oxide film 6 and the element isolation insulating film 2a On the upper surface 2c and the side surface 2d of the portion 2b, a SiRN (Silicon Rich Nitride) film and a protective insulating film 8 serving as the charge trap layer 7 are laminated. In addition to this, the sacrificial film 9 covering the protective insulating film 8 is formed by coating.

The etch back is performed using the dry etching method under the conditions that the etching rates of the sacrificial film 9, the protective insulating film 8, the charge trap layer 7, and the element isolation insulating film 2a are completely equal. This etchback is composed of a first etching in which the upper surface 2c of the protruding portion 2b of the element isolation insulating film 2a is the end point, and a second etching (over etching) having a fixed time set in advance. The over-etching is performed for the purpose of adjusting the height of the portion (side edge portion 7a, see FIG. 2) formed on the side surface 2d of the protruding portion 2b of the element isolation insulating film 2a of the charge trap layer 7.

Fig. 1 shows a case where the height of the protruding portion 2b of the element isolation insulating film 2a is H1-1 [nm]. At this time, the height of the protruding portion 2b of the element isolation insulating film 2a is reduced to H2-1 (<H1-1) [nm] as shown in FIG. 2 by the above etching. Further, Fig. 2 shows a state in which all of the sacrificial film 9 is removed after the etch back process.

In addition, FIG. 3 shows a case where the height of the protruding portion 2b of the element isolation insulating film 2a is H1-2 (<H1-1) [nm]. At this time, the height of the protruding portion 2b of the element isolation insulating film 2a is reduced to H2-2 (<H2-1) [nm] as shown in FIG. 4 by the above etching. 4 shows the state in which all of the sacrificial film 9 is removed after the etch back process.

Here, the reason for the fact that H2-2 [nm] < H2-1 [nm] is based on the over-etching performed after the detection of the elapsed time control end point is performed only at a fixed time set in advance. That is, in the manufacture of a typical semiconductor device In the process, the overetching time is set such that the height of the protruding portion 2b of the element isolation insulating film 2a before the etch back coincides with the target value H1T. Since the height of the protruding portion 2b of the element isolation insulating film 2a before the etch back is high or lower than the target value H1T due to the manufacturing variation, the height of the protruding portion 2b of the element isolation insulating film 2a after the etch back is also The target value H2T deviates. As a result, the height WH of the side edge portion 7a of the charge trap layer 7 formed on the side surface 2b of the protruding portion 2b of the element isolation insulating film 2a is also deviated from the target value WHT.

The height WH of the side edge portion 7a of the charge trap layer 7 is affected by the characteristics of the semiconductor element. Specifically, when the height WH of the side edge portion 7a of the charge trap layer 7 becomes high, the time required for erasing the memory data becomes long. Further, when the height WH of the side edge portion 7a of the charge trap layer 7 becomes low, the time required for writing of the material becomes long.

The height WH of the side edge portion 7a of the charge trap layer 7 is determined by the time required for writing the data and the time required for erasing, and the operating speed of the entire semiconductor device is set to be as high as possible. However, in the method of manufacturing a semiconductor device described above, the height WH of the side edge portion 7a of the charge trap layer 7 depends on the height of the protruding portion 2b of the element isolation insulating film 2a before etch back. In addition to this, it is difficult to eliminate the variation in the height of the protruding portion 2b of the element isolation insulating film 2a before the etch back. Then, a method of manufacturing a semiconductor device in which the height WH of the side edge portion 7a of the charge trap layer 7 and the target value WHT can be made uniform without depending on the height of the protruding portion 2b of the element isolation insulating film 2a before the etch back is required.

(first embodiment) Next, a method of manufacturing the apparatus according to the first embodiment of the present invention will be described with reference to Figs. 5 to 12 .

Fig. 5 is a partial plan view showing a part (semiconductor unit) 100 of the CT type memory, and Fig. 6 is a cross-sectional view taken along line A-A' thereof. .

Referring to FIG. 5, the semiconductor device 100 includes a plurality of active regions 3 extending in the X direction in the same manner as the plurality of element isolation regions 2 extending continuously in the X direction. The plurality of element separation regions 2 and the plurality of active regions 3 are alternately arranged in the Y direction at equal intervals and at equal intervals.

A plurality of element lines (core gate electrodes) 21 extending continuously in the Y direction are arranged at equal intervals and at equal intervals in the X direction across the plurality of element isolation regions 2 and the plurality of active regions 3.

The active region 3 is connected to a metal wiring (not shown) by a contact member 16.

Next, referring to FIG. 6, the trench 1b for element isolation is formed on the semiconductor substrate 1. A pad oxide film 4a is formed on the surface of the semiconductor substrate 1 constituting the bottom surface and the side surface of the trench 1b. The element isolation insulating film 2a is buried in the trench 1b in which the pad oxide film 4a is formed on the bottom surface and the side surface. As a result, the plurality of trenches 1b are buried in the element isolation region 2 of the element isolation insulating film 2a. Further, the active region 3 is defined on the semiconductor substrate 1 by the formation of the element isolation region 2.

The element isolation insulating film 2a is formed on the upper portion thereof than the semiconductor substrate The upper surface 1a of the board 1 is more prominent above. The height H2 [nm] of the protruding portion 2b of the element isolation insulating film 2a is different from the target value H2T due to the manufacturing variation. The target value H2T is set to an appropriate value in consideration of the write characteristics and erasing characteristics of the obtained semiconductor device 100.

A bottom yttrium oxide film 6 is formed on the active region 3 of the semiconductor substrate 1. Further, a charge trap layer 7 serving as a charge storage layer is formed so as to cover the upper surface of the bottom yttrium oxide film 6 and the upper surface 2c and the side surface 2d of the protruding portion 2b. Further, a top yttrium oxide film (wafer insulating film) 10 is formed so as to cover the surface of the charge trap layer 7. The ONO (oxide film-nitride film-oxide film) gate insulating film 20 is formed by a laminated structure of the bottom oxide film 6, the charge trap layer 7, and the top oxide film 10.

A polysilicon layer 11 belonging to a conductive layer is formed on the ONO gate insulating film 20 and the element isolation insulating film 2a. A vaporized layer 12 using nickel or the like is formed on the polysilicon layer 11. The core gate electrode (character line) 21 is formed by the polysilicon layer 11 and the germanide layer 12.

A tantalum nitride film 13 is formed in such a manner as to cover the core gate electrode 21. Further, the interlayer insulating film 14 is formed to cover the tantalum nitride film 13. A metal wiring 15 is formed on the upper portion of the interlayer insulating film 14. The metal wiring 15 is formed with a contact hole (not shown) that is formed to penetrate the interlayer insulating film 14 and the tantalum nitride film 13. That is, the metal wiring 15 and the contact 16 (Fig. 5) are formed by the same process. The contact 16 is connected to a selective transistor (not shown) formed in the active region.

Hereinafter, referring to FIG. 7 to FIG. 12, FIG. 5 to FIG. A method of manufacturing the semiconductor device 100 will be described. 7 to 12 are views showing a state in the middle of the manufacture of the semiconductor device 100, and are cross-sectional views corresponding to the position of the line A-A' in Fig. 1.

First, as shown in FIG. 7, a pad oxide film 4 having a film thickness T1 [nm] is formed on the upper surface of the semiconductor substrate 1. Next, a tantalum nitride film 5 is deposited on the formed pad oxide film 4, and the deposited tantalum nitride film 5 is patterned into a predetermined pattern. The width and spacing of the predetermined pattern are set to the line and space pattern of W[nm]. Next, when the patterned tantalum nitride film 5 is used as a hard mask, the element isolation region 2 is formed by a well-known STI (Shallow Trench Isolation) method. That is, the trench 1b is formed on the semiconductor substrate 1, and the pad oxide film 4a is formed on the inner surface thereof. Then, the trench 1b and the opening of the hard mask are buried in the element isolation insulating film 2a composed of the hafnium oxide film.

The active region 3 is defined on the semiconductor substrate 1 by the formation of the element isolation region 2. The widths of the element isolation region 2 and the active region 3 are both W [nm].

Next, as shown in FIG. 8, the hard mask and the pad oxide film 4 composed of the tantalum nitride film 5 are sequentially removed. The removal of the tantalum nitride film 5 can be performed by immersing the semiconductor substrate 1 in a hot phosphoric acid solution. Further, the removal of the pad oxide film 4 can be performed by immersing the semiconductor substrate 1 in a hydrofluoric acid aqueous solution.

When the pad oxide film 4 is removed, the exposed portion of the element isolation insulating film 2a composed of the hafnium oxide film is also etched in the same manner as the pad oxide film. That is, it is more prominent to the upper side than the upper surface 1a of the semiconductor substrate 1. In the protruding portion 2b of the insulating film 2a, only the portion of the film thickness T1 [nm] of the pad oxide film 4 is side-etched in the left-right direction of FIG. As a result, the width W1 of the protruding portion 2b becomes W1 = W - 2‧ T1 [nm]. Furthermore, the height of the protruding portion 2b becomes H1 [nm]. Then, a first recess 23 having a width W2 = W + 2‧ T1 [nm] is formed between the adjacent protruding portions 2b.

Next, as shown in FIG. 9, a bottom yttrium oxide film 6 is formed on the upper surface 1a of the semiconductor substrate 1. Next, the charge trap layer 7 serving as a charge storage layer is formed so as to cover the bottom oxide film 6 and the upper surface 2c and the side surface 2d of the protruding portion 2b. Further, the protective insulating film 8 is formed to cover the charge trap layer 7. The film and the layer are formed by the total thickness of the bottom yttrium oxide film 6 and the charge trap layer 7 and the protective insulating film 8 (hereinafter, simply referred to as the total film thickness) T2 [nm], and the semiconductor device 100. The height target value WHT [nm] of the side edge portion 7a of the charge trap layer at the time of completion is identical. Here, the height target value WHT [nm] of the side edge portion 7a of the charge trap layer 7 is determined in consideration of the writing and erasing characteristics of the semiconductor device 100.

The formation of the protective insulating film 8 is performed so as not to be completely buried in the first recess 23 . Thereby, the second recess 24 formed of the protective insulating film 8 is formed in the first recess 23 . Further, as described above, the protective insulating film 8 is formed at a height from the upper surface 1a of the semiconductor substrate 1 which is the surface 8a of the protective insulating film 8 which becomes the bottom surface 24a of the second recess 24 (total film thickness T2 [nm] It is performed so as to match the height target value WHT [nm] of the side edge portion 7a of the charge trap layer when the semiconductor device 100 is completed. Further, since the film thickness of the protective insulating film 8 is controlled with high precision, Therefore, the film formation can be performed by a CVD method.

Here, since the second concave portion 24 can be formed in the first concave portion 23, the film thickness T1 [nm] of the pad oxide film 4 must be set to satisfy W2 (= W + 2‧ T1) > 2‧ T2 [nm] and W>2‧T1[nm]. Further, the height H2 of the protruding portion 2b must be set to satisfy H1 > H2 [nm].

Next, as shown in FIG. 10, the protective insulating film 8 is covered, and the sacrificial film 9 is applied so as to embed the second recess 24. The sacrificial film 9 is formed such that its surface becomes flat. The surface of the sacrificial film 9 is planarized by CMP (Chemical Mechanical Polishing) or the like.

Then, as shown in FIG. 11, the etch back is performed under the condition that the etching rates of all of the sacrificial film 9, the protective insulating film 8, the charge trap layer 7, and the element isolation insulating film 2a are equal. This etch back can use dry etching techniques. The etch back is about to disappear when the sacrificial film 9 is broken, and the bottom surface 24a of the second recess 24 is the point at which the surface 8a of the protective insulating film 8 is exposed. As a result, the height H2 of the protruding portion 2b of the element isolation insulating film 2a from the upper surface 1a of the semiconductor substrate 1 is equal to the total film thickness T2 [nm]. At this time, the height WH of the side edge portion 7a of the charge trap layer 7 is equal to the height H2 of the protruding portion 2b of the element isolation insulating film 2a, so that the height WH of the side edge portion 7a of the charge trap layer 7 is also equal to the total film thickness. T2 [nm].

Next, as shown in FIG. 12, the protective insulating film 8 is removed using a wet etching technique. Next, the top tantalum oxide film 10 is formed by thermal oxidation or CVD to cover the surface of the charge trap layer 7. Accordingly, the ONO gate insulating film 20 having a three-layer structure composed of the bottom tantalum oxide film 6, the charge trap layer 7, and the top oxide film 10 is formed.

Next, a polysilicon layer 11 which is a part of the core gate electrode is deposited on the ONO gate insulating film 20 and the element isolation insulating film 2a. Further, a vaporized layer 12 containing nickel or the like is provided on the polysilicon layer 11. The polysilicon layer 11 and the germanide layer 12 constitute a core gate electrode 21.

Thereafter, as shown in FIG. 6, a tantalum nitride film 13 is formed so as to cover the core gate electrode 21. Thereafter, the interlayer insulating film 14 is formed to cover the tantalum nitride film 13. Then, although not shown, a contact hole penetrating the interlayer insulating film 14 and the tantalum nitride film 13 is formed, and at the same time, a contact 16 (FIG. 1) and a metal wiring 15 for burying the contact hole are formed.

As described above, the semiconductor device 100 is completed.

In the present embodiment, the total thickness T2 of the bottom yttrium oxide film 6, the charge trap layer 7, and the protective insulating film 8 is the same as the target value WHT of the height of the side edge portion 7a of the etched charge trap layer 7. In this manner, the films and layers are formed. Then, when the bottom surface 24a of the second recess 24 is the surface 8a of the protective insulating film 8, the etch back of the charge trap layer 7 is separated into unit cells, so that the side edge of the charge trap layer 7 can be made. The height WH of 7a coincides with the total film thickness T2. The variation in the total film thickness T2 depends on the film formation precision, and is small enough to be negligible compared to the height accuracy of the protruding portion 2b of the element isolation insulating film 2a. Therefore, regardless of the deviation of the height H1 of the protruding portion 2b of the element isolation insulating film 2a before the etch back, the height H2 of the protruding portion 2b after the etch back can be substantially uniformly formed. According to this, it is possible to stably manufacture a semiconductor device having desired characteristics.

Above, although the present invention is described in an implementation form It is to be understood that the invention is not limited to the embodiments described above, and various modifications and changes can be made without departing from the scope of the invention.

The application claims priority on the basis of Japanese Patent Application No. 2013-90356, filed on Apr. 23, 2013, the entire contents of which is incorporated herein.

1a‧‧‧above

2b‧‧‧Protruding

2c‧‧‧above

2d‧‧‧ side

6‧‧‧ bottom oxide film

7‧‧‧ Charge trapping layer

8‧‧‧Protective insulation film

8a‧‧‧Surface

24‧‧‧2nd recess

24a‧‧‧ bottom

Claims (8)

A method of manufacturing a device, comprising: forming a plurality of element isolation regions having protrusions protruding above an upper surface of a semiconductor substrate, and forming a first recess between adjacent protrusions; a charge trapping layer and a protective insulating film are laminated on the bottom surface of the first recess and the side surface and the upper surface of the protruding portion, and a second recessed portion formed of the protective insulating film is formed in the first recess; a method of embedding the second concave portion to completely form a sacrificial film; and etching and removing the sacrificial film, the protective insulating film, the charge trap layer, and the protruding portion by dry etching, to the bottom surface of the second concave portion The work of protecting the surface of the insulating film from exposure. The method for manufacturing the device according to the first aspect of the invention, wherein the second concave portion is formed such that a bottom surface of the second concave portion, that is, a position of a surface of the protective insulating film is left after the etching removal process The target values of the heights of the lower protrusions are the same. The method for producing a device according to the second aspect of the invention, wherein the protective insulating film is formed by a CVD method. A method of manufacturing a device as recited in claim 1, 2 or 3, wherein Further, it includes: a process of removing all of the protective insulating film after the etching removal process; and a process of forming a top insulating film to cover the exposed surface of the charge trap layer. The method of manufacturing a device according to claim 4, further comprising: forming a conductive layer along a second direction crossing the first direction in which the plurality of element isolation regions extend. The method of manufacturing the device according to the first, second or third aspect of the invention, further comprising: forming a bottom portion of the exposed surface of the semiconductor substrate exposed in the first recess before the step of forming the second recess Engineering of insulating film. A film forming method of forming a first recess and forming a pair of protruding portions at a predetermined interval to cover the inner surface of the first recess to form the first film and the second film a laminated film formed in the first recess, wherein a second recess is formed in the first recess, and a sacrificial film covering the second film is formed so as to be embedded in the second recess, and the protruding portion and the first portion are formed Etching the sacrificial film, the second film, the first film, and the protruding portion to the bottom of the second concave portion under the same conditions as the etching rate of the film, the second film, and the sacrificial film In other words, the first film is removed, and the first film having a height equal to the film thickness of the laminated film remains on the side surface of the protruding portion. A film forming method of forming a laminated film from a first film and a second film with a predetermined film thickness on the first surface so as to cover a side surface and an upper surface of a protruding portion protruding from the first surface. a sacrificial film is formed on the laminated film so that the upper surface thereof is flat, and the sacrificial film is etched under the same conditions as the etching rate of the protruding portion, the first film, the second film, and the sacrificial film. The second film, the first film, and the protruding portion are removed from the upper surface of the second film on the first surface, and the second film is removed to have a height equal to the predetermined film thickness 1 film remains on the side of the above-mentioned protrusion.