JP2005072380A - Nonvolatile semiconductor memory device and its manufacturing method, and electronic card and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a NAND type EEPROM capable of decreasing variations in coupling ratio. <P>SOLUTION: An upper layer conductive part 23 of a charge storage layer 17 of a memory cell has an inner side surface 29 and an outer side surface 31 composed of a pair of rising parts 27 formed at intervals each other. A bottom face height adjusting layer 43 is on an inner side surface 29 side and an element isolation insulating layer 5 is on an outer side surface 31 side. This can conform an area of a region in which a charge storage layer 17 and a controlling gate CG face even the height of the rising part 27 is different between the memory cells of a position (A) and a position (B) of the substrate 9. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting data and a method for manufacturing the same.

  Conventionally, as one of semiconductor memories, a nonvolatile semiconductor memory device (EEPROM) in which data can be electrically rewritten is known. In particular, a NAND-type EEPROM having a NAND cell formed by connecting a plurality of memory cells, which are units for storing 1 bit, in series is attracting attention as being highly integrated. The NAND type is used, for example, in a memory card for storing image data of a digital still camera.

  A memory cell of a NAND type EEPROM has a FET-MOS structure in which a gate insulating layer, a charge storage layer, a dielectric layer, and a control gate are stacked on a semiconductor substrate that becomes a channel region. The control gate is connected to the word line. A NAND cell is configured by connecting a plurality of memory cells in series so that adjacent ones share a source / drain. The source / drain is an impurity region that functions as at least one of a source and a drain.

Here, an example of a data writing method in the NAND type will be briefly described.
(1) Writing “0”
In the state where the voltage of the channel region is 0V, the control gate of the memory cell to which “0” is to be written is selected, the voltage of this control gate is set to 20V, for example, and the voltage of the control gate other than this control gate is set to 10V, for example To do. Since the potential difference between the selected control gate and the channel region is large, electrons are injected into the charge storage layer of the memory cell by a tunnel current. As a result, the threshold value of the memory cell becomes a positive state (a state in which “0” is written).
(2) Writing “1”
After the channel region is set in a floating state with a predetermined voltage higher than 0V, the control gate of the memory cell to which “1” is to be written is selected and the voltage of this control gate is set to 20V as in the case of writing “0”. The voltage of control gates other than this control gate is set to 10V, for example. As a result, the voltage of the channel region rises due to capacitive coupling with the selected control gate, for example, about 8V. In this case, unlike the case of writing “0”, since the potential difference between the selected control gate and the channel region is small, the charge accumulation layer of the memory cell to which “1” is to be written is caused by the tunnel current. Electron injection does not occur. Therefore, the threshold value of the memory cell is maintained in a negative state (a state where “1” is written).

  As can be seen from the above, a high voltage (for example, 20 V) is applied to the control gate when writing either “0” or “1” data. In order to reduce the power consumption of the EEPROM, it is necessary to make the write voltage applied to the control gate as small as possible. For this purpose, the coupling ratio may be increased.

  Here, the coupling ratio will be described. The coupling ratio is a value defined by C2 / (C1 + C2), where C1 is the capacitance between the semiconductor substrate and the charge storage layer, and C2 is the capacitance between the charge storage layer and the control gate. is there. Electrons are injected into the charge storage layer by a voltage generated between the charge storage layer and the semiconductor substrate based on the high voltage applied to the control gate. If the voltage generated between them is large, electrons are easily injected into the charge storage layer.

  The coupling ratio indicates how efficiently the voltage applied to the control gate is used to inject electrons into the charge storage layer. If this ratio is large, the voltage applied to the control gate can be lowered. On the other hand, if this ratio is small, the voltage applied to the control gate must be increased. Therefore, the coupling ratio is an index representing the ease of writing to the memory cell. As can be seen from the above equation, the coupling ratio increases as the capacitance C2 between the charge storage layer and the control gate increases.

For example, there are the following two techniques for increasing the capacitance C2. First, in the charge storage layer having a two-layer structure, the width of the upper conductive portion is made wider than that of the lower conductive portion, thereby increasing the area where the control gate and the upper conductive portion face each other (for example, Patent Document 1). The other is that, by providing a wide groove in the upper conductive portion of the charge storage layer having a two-layer structure, the control gate and the upper conductive portion face each other so that the inner surface of the groove faces the control gate. The area to be increased is increased (for example, Patent Document 2).
JP 2001-284556 A ([0101], FIG. 7B) JP 2002-203919 A ([0069], FIG. 11 (d))

  An object of the present invention is to provide a nonvolatile semiconductor memory device that can increase the coupling ratio and can be miniaturized, and a method for manufacturing the same.

  Another object of the present invention is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same, which can reduce variations in coupling ratio.

  Still another object of the present invention is to provide a nonvolatile semiconductor memory device that is less susceptible to noise and a method for manufacturing the same.

  One aspect of a nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate including an element formation region, a gate insulating layer formed on the element formation region, and a lower layer conductive formed on the gate insulating layer. And an upper conductive portion having an inner surface and an outer surface constituted by a pair of rising portions formed on the lower conductive portion and spaced apart from each other and having a height greater than the width. A layer, an element isolation insulating layer formed on the semiconductor substrate so as to sandwich the element formation region, a dielectric layer formed on the inner surface and the outer surface, and an upper surface of the dielectric layer And a control gate formed on the substrate.

  Another aspect of the nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate including an element forming region, a gate insulating layer formed on the element forming region, and a lower layer formed on the gate insulating layer. A charge storage layer including a conductive portion and an upper conductive portion having an inner surface and an outer surface formed by a pair of rising portions disposed on the lower conductive portion and spaced apart from each other; and the outer surface side And an element isolation insulating layer formed on the semiconductor substrate so as to sandwich the element formation region, and a bottom surface height adjustment layer formed on the bottom surface of the upper conductive portion located on the inner surface side, A plurality of memory cells having a dielectric layer formed on the inner side surface, the outer side surface, and the bottom surface height adjustment layer, and a control gate formed on the dielectric layer. And

  Still another aspect of the nonvolatile semiconductor memory device according to the present invention is formed on a semiconductor substrate including an element formation region, a gate insulating layer formed on the element formation region, and the gate insulating layer. A charge storage layer comprising: a lower conductive portion; and an upper conductive portion having an inner surface and an outer surface constituted by a pair of rising portions disposed on the lower conductive portion with a space therebetween, and the outer surface An element isolation insulating layer formed on the semiconductor substrate so as to sandwich the element formation region, a dielectric layer formed on the inner surface and the outer surface, and on the outer surface side And a control gate formed on the dielectric layer so as to extend to a position facing the lower conductive portion.

  One aspect of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming a gate insulating layer on a semiconductor substrate, and a lower-layer conductive portion that is a component of a charge storage layer on the gate insulating layer. A step of forming and selectively etching the lower conductive portion, the gate insulating layer, and the semiconductor substrate to leave the gate insulating layer and the lower conductive portion on the element formation region of the semiconductor substrate, and Forming a trench in the semiconductor substrate so as to sandwich an element formation region; forming an element isolation insulating layer in the trench so that a length protruding from the trench is larger than a distance between the trenches; The charge accumulation on the element isolation insulating layer and the lower conductive portion so that a portion protruding from the trench of the element isolation insulating layer is not filled. Forming an upper conductive portion that is a constituent element of the upper conductive portion, and removing the portion located on the upper surface of the element isolation insulating layer from the upper conductive portion, thereby forming a space between the lower conductive portions. Patterning the upper conductive portion having an inner surface and an outer surface constituted by a pair of raised portions, and etching the element isolation insulating layer so that the element isolation insulating layer remains in the trench. Exposing the outer surfaces of the pair of rising portions, forming a dielectric layer on the inner surface and the outer surface, and forming a control gate on the dielectric layer; It is characterized by providing.

  Another aspect of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is a method for manufacturing a nonvolatile semiconductor memory device having a plurality of memory cells, the step of forming a gate insulating layer on a semiconductor substrate; Forming a lower conductive portion that is a component of a charge storage layer on the gate insulating layer; and selectively etching the lower conductive portion, the gate insulating layer, and the semiconductor substrate, thereby forming the semiconductor substrate Forming a trench in the semiconductor substrate so as to leave the gate insulating layer and the lower conductive portion on the element forming region and sandwiching the element forming region; and isolating and isolating the element in the trench so as to protrude from the trench Forming the layer and the element isolation insulating layer and the lower layer so as not to fill a gap between the element isolation insulating layer and the portion protruding from the trench. Forming an upper conductive portion as a component of the charge storage layer on the electric portion; and etching the element isolation insulating layer so that the element isolation insulating layer remains in the trench Exposing the inner side surface of the upper conductive portion by etching the bottom surface height adjusting layer so that the bottom surface height adjusting layer remains on the bottom surface of the upper conductive portion, Forming a dielectric layer on a side surface and the outer surface; and forming a control gate on the dielectric layer.

  Still another aspect of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming a gate insulating layer on a semiconductor substrate, and a lower conductive layer that constitutes a charge storage layer on the gate insulating layer. Forming a portion and selectively etching the lower conductive portion, the gate insulating layer, and the semiconductor substrate, thereby leaving the gate insulating layer and the lower conductive portion on the element formation region of the semiconductor substrate. And a step of forming a trench in the semiconductor substrate so as to sandwich the element formation region, a step of forming an element isolation insulating layer in the trench so as to protrude from the trench, and a part of the element isolation insulating layer from the trench An upper conductive portion serving as a component of the charge storage layer is formed on the element isolation insulating layer and the lower conductive portion so as not to fill a gap between the protruding portions. And a pair of rising portions formed on the lower conductive portion so as to be spaced apart from each other by removing a portion of the upper conductive portion located on the upper surface of the element isolation insulating layer. Patterning the upper conductive portion having a side surface and an outer surface; and until the upper surface of the element isolation insulating layer is below the lower conductive portion so that the element isolation insulating layer remains in the trench. Etching the isolation insulating layer to expose the outer surfaces of the pair of rising portions; forming a dielectric layer on the inner surface and the outer surface; and on the dielectric layer Forming a control gate.

  According to one embodiment of the present invention, a nonvolatile semiconductor memory device that can increase the coupling ratio and can be miniaturized and a method for manufacturing the same can be provided. According to another aspect of the present invention, it is possible to provide a nonvolatile semiconductor memory device and a method for manufacturing the same that can reduce the variation in the coupling ratio. According to still another aspect of the present invention, it is possible to provide a nonvolatile semiconductor memory device that is less susceptible to noise and a method for manufacturing the same.

The embodiment of the present invention will be described by dividing it into the following items.
[First Embodiment]
1. Structure of NAND-type EEPROM according to the first embodiment
2. Manufacturing method of NAND-type EEPROM according to the first embodiment
(Production method 1 of the first embodiment)
(Manufacturing method 2 of the first embodiment)
(Manufacturing method 3 of the first embodiment)
(Manufacturing method 4 of the first embodiment)
[Second Embodiment]
1. Structure of NAND-type EEPROM according to Second Embodiment
2. Manufacturing method of NAND-type EEPROM according to the second embodiment
(Manufacturing method 1 of 2nd Embodiment)
(Manufacturing method 2 of 2nd Embodiment)
(Manufacturing method 3 of 2nd Embodiment)
[Third Embodiment]
1. Structure of NAND-type EEPROM according to the third embodiment
2. Manufacturing Method of NAND-type EEPROM according to Third Embodiment [Application to Electronic Card and Electronic Device]
Note that, in the drawings for explaining the embodiments, the same components as those shown in the drawings already described are denoted by the same reference numerals, and the description thereof is omitted.

[First Embodiment]
One of the features of the first embodiment is that the height of the upper conductive portion of the lower conductive portion and the upper conductive portion constituting the stack type charge storage layer (floating gate) is larger than the width.
1. Structure of NAND-type EEPROM according to First Embodiment FIG. 1 is a plan view showing a part of a memory cell array 1 of the NAND-type EEPROM according to the first embodiment. The memory cell array 1 includes a selection gate SG1, control gates CG0 to CG15, and a selection gate SG2. These gates are arranged in the order of the selection gate SG1, the control gates CG0 to CG15, and the selection gate SG2, and extend in the row direction. The memory cell array 1 includes element formation regions 3 and element isolation insulating layers 5 that are alternately arranged and extend in the column direction.

  A selection transistor Tr1, memory cells MC0 to MC15, and a selection transistor Tr2 are formed where the element formation region 3 intersects the selection gate SG1, the control gates CG0 to CG15, and the selection gate SG2. A NAND cell 7 is constituted by a set of MC0 to MC15. A memory cell array 1 includes a plurality of NAND cells 7 arranged in a matrix.

  Next, the structure of the NAND cell 7 will be described with reference to FIGS. FIG. 2 is a schematic diagram of a section taken along the line II (a) -II (b) of FIG. FIG. 3 is an equivalent circuit diagram of the NAND cell 7 of FIG. The NAND cell 7 has a structure in which 16 memory cells MC <b> 0 to 15 are formed on a p− type semiconductor substrate 9. The NAND cell 1 may be formed in a p-type well in the semiconductor substrate 9.

  The memory cell is also called a memory transistor, and is a non-volatile cell in which data can be electrically rewritten. Each memory cell has the same configuration. For example, when the memory cell MC0 is taken as an example, an n + -type impurity region 11 (source / drain) formed at a predetermined interval on the surface of the substrate 9 and the substrate 9 Of these, a channel region 13 located between the impurity regions 11, a charge storage layer 17 formed on the channel region 13 via a gate insulating layer 15, and a dielectric layer 19 formed on the charge storage layer 17. Control gate CG0. Impurity region 11 and channel region 13 constitute element formation region 3. The charge storage layer 17 has a structure in which a lower conductive portion 21 and an upper conductive portion 23 are stacked.

  The NAND7 cell is configured by connecting 16 memory cells in series so that adjacent memory cells share a source / drain. Although the case where the number of memory cells constituting the NAND cell 7 is 16 has been described, the number of memory cells may be 8, 32, 64, or the like. Control gates CG0 to CG15 are connected to corresponding word lines.

  The selection transistor Tr1 is disposed on the memory cell MC0 side. One of the pair of impurity regions 11 of the transistor Tr1 is shared with the memory cell MC0, and the other is connected to the common source line CELSRC. The transistor Tr1 controls connection and disconnection between the NAND cell 7 and the common source line CELSRC.

  A selection transistor Tr2 is formed on the memory cell MC15 side. Of the pair of impurity regions 11 constituting the transistor Tr2, one is shared with the memory cell MC15 and the other is connected to the bit line BL. The transistor Tr2 controls connection and disconnection between the NAND cell 7 and the bit line BL.

  As described first, the first embodiment is characterized in that the height of the upper conductive portion 23 of the charge storage layer 17 is larger than the width. Hereinafter, this point will be described in detail with reference to FIGS. 4 and 5. FIG. 4 is a schematic diagram of a section taken along line IV (a) -IV (b) in FIG. FIG. 5 is a perspective view of the charge storage layer 17 of FIG.

  An element isolation insulating layer 5 is formed on the semiconductor substrate 9 so as to sandwich the element formation region 3 of the semiconductor substrate 9 (for example, a silicon substrate). The element isolation insulating layer 5 is embedded in the trench 25 of the semiconductor substrate 9, and a part thereof protrudes from the trench 25. On the element formation region 3, a gate insulating layer 15 (tunnel oxide film) made of, for example, a silicon oxide film is formed.

  On the gate insulating layer 15, a charge storage layer 17 (floating gate) made of, for example, polysilicon is disposed. The charge storage layer 17 has a lower conductive portion 21 formed on the gate insulating layer 15. The thickness of the lower conductive part 21 is, for example, 20 to 50 nm.

  On the lower conductive portion 21, an upper conductive portion 23 having a substantially U-shaped cross section electrically connected thereto is formed. Specifically, the upper conductive portion 23 has a pair of rising portions 27 formed on the lower conductive portion 21 with a space therebetween. The rising portion 27 constitutes the inner side surface 29 and the outer side surface 31 of the upper conductive portion 23. The bottom surface 33 of the upper conductive portion 23 is located on the inner side surface 29 side, and the element isolation insulating layer 5 is located on the outer side surface 31 side. The upper conductive portion 23 has a height H (for example, 0.1 to 0.2 μm) larger than a width W (for example, 50 to 90 nm).

  The dielectric layer 19 (interpoly insulating layer) is formed on the inner side surface 29 and the outer side surface 31 of the upper conductive portion 23. The dielectric layer 19 is composed of, for example, an ONO film (silicon oxide film, silicon nitride film, silicon oxide film). A control gate CG made of, for example, polysilicon is formed on the dielectric layer 19.

The main effects of the first embodiment will be described. According to the first embodiment, the inner side surface 29 and the outer side surface 31 of the upper conductive portion 23 constituting the charge storage layer 17 are opposed to the control gate CG. For this reason, since the electrostatic capacitance between the charge storage layer 17 and the control gate CG can be increased, the coupling ratio can be increased. Therefore, the write voltage applied to the control gate CG can be reduced, so that the power consumption of the EEPROM can be reduced. In the first embodiment, since the height H of the upper conductive portion 23 is larger than the width W, the capacitance between the charge storage layer 17 and the control gate CG is increased and the EEPROM is miniaturized. , Can achieve both. The effects described above can be applied to the second and third embodiments described later.
2. Manufacturing Method of NAND Type EEPROM According to First Embodiment There are manufacturing methods 1 to 4 in this method. Hereinafter, it demonstrates in order.

(Production method 1 of the first embodiment)
6 to 10 are views showing the manufacturing method 1 in the order of steps, and correspond to the cross section of FIG. 4, that is, the IV (a) -IV (b) cross section of FIG. As shown in FIG. 6, the gate insulating layer 15 is formed on the semiconductor substrate 9 by, for example, thermal oxidation. A lower conductive portion 21 made of polysilicon is formed on the gate insulating layer 15 by, for example, CVD.

  Then, a mask material 35 made of, for example, a silicon nitride film is formed on the lower conductive portion 21. The mask material 35 is selectively exposed and then developed to remove the mask material 35 located on the region where the element isolation insulating layer is formed. Using this mask material as a mask, the lower conductive portion 21 and the gate insulating layer 15 are selectively removed by dry etching, and the semiconductor substrate 9 is selectively removed. As a result, the trench 25 is formed in the semiconductor substrate 9 so as to leave the gate insulating layer 15 and the lower conductive portion 21 on the element formation region 3 and sandwich the element formation region 3.

  The thickness of the mask material 35 substantially corresponds to the height H of the upper conductive portion 23, and the distance D between the trenches 25 corresponds to the width W of the upper conductive portion 23. Since the height of the upper conductive portion 23 is larger than the width, the thickness of the mask material 35 is larger than the distance D between the trenches 25. In addition, since the lower conductive layer 21 and the trench 25 are formed using the mask material 35 as a mask, the end portions of the lower conductive portion 21 and the end portions of the element formation region 3 are aligned in the horizontal direction.

  As shown in FIG. 7, a thin oxide layer (not shown) is formed on the side and bottom surfaces of the trench 25 and the side surface of the lower conductive portion 21 by thermal oxidation. Then, a silicon oxide layer to be the element isolation insulating layer 5 is formed on the mask material 35 so as to fill the trench 25 by, for example, CVD. Next, the silicon oxide layer to be the element isolation insulating layer 5 is etched back by dry etching until the mask material 35 is exposed. CMP (chemical mechanical polishing) may be used instead of etch back.

  As shown in FIG. 8, the mask material 35 is removed. As a result, the element isolation insulating layer 5 embedded in the trench 25 and partially protruding from the trench 25 is completed. As described in the explanation of FIG. 6, the thickness of the mask material 35 is larger than the distance D between the trenches 25. For this reason, the element isolation insulating layer 5 is formed in the trench 25 so that the length protruding from the trench 25 is larger than the distance D between the trenches 25.

  Thereafter, an upper conductive portion 23 made of polysilicon is formed on the element isolation insulating layer 5 and the lower conductive portion 21 by, for example, CVD so that the portion 37 protruding from the trench 25 in the element isolation insulating layer 5 is not filled. To do. As a result, the upper conductive portion 23 is formed in the element formation region 3 in a self-aligning manner.

  As shown in FIG. 9, for example, a portion of the upper conductive portion 23 located on the upper surface of the element isolation insulating layer 5 is removed by CMP. Thus, the upper conductive layer 23 having the inner side surface 29 and the outer side surface 31 constituted by the pair of rising portions 27 formed on the lower conductive layer 21 with a space therebetween is patterned.

  As shown in FIG. 10, the outer surfaces 31 of the pair of rising portions 27 are exposed by, for example, reactive ion etching of the element isolation insulating layer 5 so that the element isolation insulating layer 5 remains in the trench 25.

  Then, as shown in FIG. 4, a dielectric layer 19 made of an ONO film is formed so as to cover the upper conductive portion 23 and the element isolation insulating layer 5. Thus, the dielectric layer 19 is formed on the inner side surface 29 and the outer side surface 31 (see FIG. 10) of the upper layer conductive portion 23. Of the pair of rising portions 27, the gap G (see FIG. 10) between one rising portion and the other rising portion is set to be larger than twice the thickness of the dielectric layer 19. As a result, the gap G is not filled with the dielectric film 19, and the control gate CG is opposed to the inner side surface 29. Finally, a control gate CG made of polysilicon is formed on the dielectric layer 19 by, for example, CVD.

(Manufacturing method 2 of the first embodiment)
Next, manufacturing method 2 will be described. FIGS. 11-14 is a figure which shows the manufacturing method 2 in process order, and respond | corresponds with the IV (a) -IV (b) cross section of FIG. According to the manufacturing method 2, as shown in FIG. 14, the upper conductive portion 23 is extended to the element isolation insulating layer 5 side, so that the width of the upper conductive portion 23 is larger than the width of the lower conductive portion 21.

  First, FIG. 11 will be described. FIG. 11 shows a state where the mask material 35 is removed from the structure shown in FIG. As shown in FIG. 12, the portion 37 protruding from the trench 25 in the element isolation insulating layer 5 is isotropically etched with an aqueous solution such as hydrofluoric acid or ammonium fluoride. Thereby, the protruding part 37 becomes thin, and the space | interval of the protruding part 37 spreads.

  Next, as shown in FIG. 13, the upper conductive portion 23 made of polysilicon, for example, by CVD is connected to the element isolation insulating layer 5 and the element isolation insulating layer 5 so that the portion 37 protruding from the trench 25 of the element isolation insulating layer 5 is not filled. It is formed on the lower conductive part 21. Thereby, the upper conductive portion 23 extending to the element isolation insulating layer 5 side is formed. And the structure shown in FIG. 14 is completed through the process similar to the process demonstrated in FIG.9, FIG.10, FIG.4 of the manufacturing method 1 of 1st Embodiment.

  As described above, according to the manufacturing method 2, the upper conductive portion 23 can be extended to the element isolation insulating layer 5 side. Therefore, according to the structure shown in FIG. 14, since the width of the upper conductive portion 23 is larger than the width of the lower conductive portion 21, the capacitance between the charge storage layer 17 and the control gate CG can be further increased. it can.

(Manufacturing method 3 of the first embodiment)
In the manufacturing method 3, as in the manufacturing method 2, the upper conductive portion 23 can be extended to the element isolation insulating layer 5 side. 15 to 19 are views showing the manufacturing method 3 in the order of steps, and correspond to the IV (a) -IV (b) cross section of FIG.

  FIG. 15 corresponds to FIG. 6, and the difference from FIG. 6 is that the mask material 35 has a two-layer structure of an upper layer mask material 39 and a lower layer mask material 41.

  As shown in FIG. 16, the element isolation insulating layer 5 is formed by the method described in FIG. Next, as shown in FIG. 17 and as shown in FIG. 18, this portion 37 of the element isolation insulating layer 5 protruding from the trench 25 is etched using the lower layer mask material 41 as a mask. 37 is thinned. This etching is the same as the etching described in FIG. As shown in FIG. 19, the upper conductive portion 23 is formed using the method described in FIG. The subsequent steps are the same as in manufacturing method 2.

(Manufacturing method 4 of the first embodiment)
20 and 21 are views showing the manufacturing method 4 in the order of steps, and correspond to the IV (a) -IV (b) cross section of FIG. As shown in FIG. 21, according to the manufacturing method 4, since the protective layer 47 is formed between the pair of rising portions 27, the inner side surface 29 is damaged when the upper conductive portion 23 is polished by CMP. You can prevent it. Hereinafter, the production method 4 will be described in detail.

  After the step of FIG. 8 described in the manufacturing method 1 of the first embodiment, as shown in FIG. 20, a portion of the element isolation insulating layer 5 that protrudes from the trench 25 is formed with a protective layer 47 made of a silicon oxide layer by CVD, for example. It is formed on the upper conductive portion 23 so as to fill the gap 37. Then, the protective layer 47 is etched back by anisotropic etching such as reactive ion etching to leave the protective layer 47 between the pair of rising portions 27.

As shown in FIG. 21, the upper conductive layer 23 is polished by CMP. Then, as shown in FIG. 10 of the manufacturing method 1 of the first embodiment, when the element isolation insulating layer 5 is etched, the protective layer 47 is also etched to leave the protective layer 47 left between the pair of rising portions 27. Remove. When the element isolation insulating layer 5 and the protective layer 47 are made of different materials, the etching of the protective layer 47 may be performed separately from the etching of the element isolation insulating layer 5. The subsequent steps are the same as those of the manufacturing method 1 of the first embodiment.
[Second Embodiment]
1. Structure of NAND-type EEPROM According to Second Embodiment FIG. 22 is a schematic diagram showing a cross-sectional structure of a NAND-type EEPROM according to the second embodiment, and shows a cross section along the control gate CG like the cross section shown in FIG. Show. In the second embodiment, the bottom surface of the upper conductive portion 23 located on the inner surface 29 side of the upper conductive portion 23 constituting the charge storage layer 17 (in other words, the bottom surface of the recessed portion of the pair of rising portions 27) is the bottom surface. One feature is that the height adjusting layer 43 is formed. Thereby, the dispersion | variation in a coupling ratio can be made small.

  First, the problem of variation in coupling ratio will be described. If the variation in coupling ratio between memory cells is large, overprogramming and erroneous writing are likely to occur. Overprogramming means that the threshold value of a memory cell in which “0” is written becomes too large. In the NAND cell, the writing speed is increased by collectively writing (for example, simultaneous writing of data of 2 kbytes or 512 bytes) to the memory cells commonly connected to one word line. Among these commonly connected memory cells, the memory cell to which “0” is written repeats the write operation (write pulse application) until a threshold value corresponding to “0” write is reached. For a memory cell that has reached a desired threshold value, further writing is prevented by raising the bit line potential by the same operation as the above-described "1" writing. However, it is conceivable that a memory cell having a high coupling ratio will exceed a desired threshold value with the first pulse. When such a phenomenon occurs, even if the read voltage applied to the unselected word line at the time of reading is 4 V, for example, the memory cell (transistor) connected to this word line cannot be made conductive. For example, all 16 memory cells belonging to the column may be defective.

  Next, for erroneous writing, writing should not occur because the potential difference between the control gate and the channel is originally small in the above-described "1" writing state, but if the coupling ratio is too large compared to other memory cells, the threshold value is negative. This is a phenomenon in which the erase state cannot be maintained, and the threshold value rises to become the write threshold value of “0”. In addition, a memory cell having a coupling ratio larger than that of other memory cells has a problem that a so-called read disturb failure is likely to occur because the erase threshold becomes a write threshold due to repeated read operations. If memory cells with a small coupling ratio exist, the chip write voltage and erase voltage are set high so that these memory cells can be written and erased within a desired time. Cells with a high ratio are more likely to be overprogrammed or miswritten.

  According to the second embodiment, the fact that the variation in the coupling ratio can be reduced will be described in comparison with a comparative example. FIG. 23 is a schematic diagram showing a cross-sectional structure of a NAND-type EEPROM according to a comparative example, and corresponds to FIG. Unlike the second embodiment, the comparative example has no bottom height adjustment layer.

  As shown in FIGS. 22 and 23, the height of the rising portion 27 is formed between the memory cell formed at the position indicated by (A) of the semiconductor substrate 9 and the memory cell formed at the position indicated by (B). Different. This is because the height of the rising portion 27 inevitably varies depending on the position on the semiconductor substrate 9.

  Therefore, in the comparative example of FIG. 23, the area where the charge storage layer 17 and the control gate CG face each other is larger in the memory cell (A) on the inner side surface 29 side than in the memory cell (B). . Accordingly, the capacitance between the charge storage layer 17 and the control gate CG is larger in the memory cell (A) than in the memory cell (B). Therefore, the coupling ratio of the memory cell of (A) becomes larger than that of the memory cell of (B), and the coupling ratio varies. Since the element isolation insulating layer 5 is on the outer surface 31 side, the region where the charge storage layer 17 and the control gate CG face each other on the outer surface 31 side is the memory cell (A) and the memory cell (B). Is the same.

  On the other hand, in the second embodiment shown in FIG. 22, the bottom surface height adjustment layer 43 is positioned on the inner surface 29 side of the upper conductive portion 23, and the element isolation insulating layer 5 is positioned on the outer surface 31 side. Therefore, in the region where the charge storage layer 17 and the control gate CG face each other, the inner surface 29 side is from the upper surface of the rising portion 27 to the bottom surface height adjustment layer 43, and the outer surface 31 side is separated from the upper surface of the rising portion 27. Up to the insulating layer 5. Therefore, even if the rising portion 27 has a different height, the area where the charge storage layer 17 and the control gate CG face each other on the inner surface 29 side is the same in the memory cell (A) and the memory cell (B). Can be. Therefore, since the electrostatic capacitance between the charge storage layer 17 and the control gate CG can be made uniform, the variation in the coupling ratio can be reduced.

  In the second embodiment, since the bottom surface height adjustment layer 43 is provided, the distance between the bottom surface of the upper conductive portion 23 and the control gate CG is relatively large. Therefore, the location of the bottom surface does not function as a capacitor, and therefore hardly affects the coupling ratio.

  Here, it will be described with a graph that the second embodiment can reduce the variation in the coupling ratio as compared with the comparative example. FIG. 24 is a graph showing the relationship between the variation in the height of the rising portion and the coupling ratio. In the second embodiment shown in FIG. 22, the dimension from the upper surface of the rising portion 27 to the bottom surface height adjustment layer 43 is 0.1 μm, and the dimension from the upper surface of the rising portion 27 to the element isolation insulating layer 5 is also 0.1 μm. . The dielectric layer 19 has a thickness of 15 nm, and the gate insulating layer (tunnel oxide film) 15 has a thickness of 9 nm.

  As shown in FIG. 24, in the second embodiment, it can be seen that the coupling ratio is constant even if the height of the rising portion 27 varies by 10%. On the other hand, in the comparative example, when the height of the rising portion 27 varies by 10%, the variation in the coupling ratio increases.

As shown in FIG. 22, according to the second embodiment, the height of the upper conductive portion 23 is made larger than the width as in the first embodiment, but the height value is equal to or less than the width value. But you can.
2. Manufacturing method of NAND-type EEPROM according to the second embodiment (Manufacturing method 1 of the second embodiment)
25 to 28 are views showing the manufacturing method 1 in the order of steps, and correspond to the cross section of FIG. After the step of FIG. 8 described in the manufacturing method 1 of the first embodiment, as shown in FIG. 25, for example, a silicon oxide layer 45 having a thickness of 0.2 to 0.4 μm is formed on the element isolation insulating layer 5 by CVD. Of these, it is formed on the entire surface of the upper conductive portion 23 so as to fill a space between the portions 37 protruding from the trench 25. The silicon oxide layer 45 becomes the bottom surface height adjustment layer 43.

  As shown in FIG. 26, the silicon oxide layer 45 is removed by, for example, reactive ion etching until the upper conductive portion 23 located on the upper surface of the element isolation insulating layer 5 is exposed. Thereby, the bottom surface height adjustment layer 43 is formed on the upper conductive portion 23 located between the portions 37 so as to fill the space between the portions 37 protruding from the trench 25.

  As shown in FIG. 27, the exposed upper conductive portion 23 is removed by, for example, CMP. Thus, the upper conductive layer 23 having the inner side surface 29 and the outer side surface 31 constituted by the pair of rising portions 27 formed on the lower conductive layer 21 with a space therebetween is patterned. Since the bottom surface height adjustment layer 43 is between the pair of rising portions 27, the inner surface 29 is not damaged during CMP.

  As shown in FIG. 28, the element isolation insulating layer 5 and the bottom surface height adjustment layer 43 are subjected to, for example, reactive ion etching. As a result, the element isolation insulating layer 5 is etched so that the element isolation insulating layer 5 remains in the trench 25, and the outer surfaces 31 of the pair of rising portions 27 are exposed. Further, the bottom surface height adjustment layer 43 is etched so that the bottom surface height adjustment layer 43 remains on the bottom surface of the upper layer conductive portion 23, and the inner side surfaces 29 of the pair of rising portions 27 are exposed.

  Since the amount of etching of the element isolation insulating layer 5 is substantially the same at any position on the semiconductor substrate 9, the distance d1 from the upper surface of the rising portion 27 to the element isolation insulating layer 5 is substantially the same for all the memory cells. . The same applies to the distance d2 from the top surface of the rising portion 27 to the bottom surface height adjustment layer 43.

  Further, since the element isolation insulating layer 5 and the bottom surface height adjustment layer 43 are etched simultaneously, the distance d1 and the distance d2 are linked. For example, if the element isolation insulating layer 5 has the same etching rate as the bottom surface height adjustment layer 43, d2 = d1 + α. Here, α is the difference in height between the upper surface of the element isolation insulating layer 5 and the upper surface of the bottom surface height adjustment layer 43 in the stage before this etching. If there is no difference, α = 0. On the other hand, if the ratio of the etching rates of the element isolation insulating layer 5 and the bottom surface height adjustment layer 43 is β, d2 = βd1 + α.

  After the step of FIG. 28, as shown in FIG. 22, the dielectric layer 19 is formed on the inner side surface 29, the outer side surface 31, and the bottom surface height adjustment layer 43 in the same manner as in the first embodiment. Here, the distance d <b> 2 (FIG. 28) from the top surface of the rising portion 27 to the bottom surface height adjustment layer 43 is made larger than the thickness of the dielectric layer 19. This is because if the distance d2 is smaller than the thickness of the dielectric layer 19, the space between the inner side surfaces 29 of the pair of rising portions 27 is filled with the dielectric layer 19, so that the control gate CG cannot be formed in this space. It is. Finally, a control gate CG is formed on the dielectric layer 19.

(Manufacturing method 2 of 2nd Embodiment)
29 to 31 are views showing the manufacturing method 2 in the order of steps, and correspond to the cross section of FIG. In the manufacturing method 2, as shown in FIG. 30, the patterning step of the upper conductive portion 23 is first, and the step of forming the bottom surface height adjustment layer 43 is later.

  First, the steps shown in FIGS. 29 and 30 are performed. These steps correspond to the steps shown in FIGS. 8 and 9 described in the manufacturing method 1 of the first embodiment. As shown in FIG. 31, a silicon oxide layer 45 to be the bottom surface height adjustment layer 43 is formed in the same manner as the method described in FIG. 25 (Manufacturing method 1 of the second embodiment). Then, for example, when the silicon oxide layer 45 and the element isolation insulating layer 5 are removed by reactive ion etching, the structure shown in FIG. 28 can be obtained. The subsequent steps are the same as in manufacturing method 1 of the second embodiment.

(Manufacturing method 3 of 2nd Embodiment)
FIG. 32 is a schematic cross-sectional view of a NAND-type EEPROM according to the second embodiment manufactured by this manufacturing method 3. By extending the upper conductive portion 23 toward the element isolation insulating layer 5 by the same method as the manufacturing method 2 of the first embodiment, the width of the upper conductive portion 23 is made larger than the width of the lower conductive portion 21.

In the manufacturing method 3 of the second embodiment, after the steps of FIGS. 11 to 13 (manufacturing method 2 of the first embodiment), the steps of FIGS. 25 to 28 (manufacturing method 1 of the second embodiment) or FIGS. The process of FIG. 31 (manufacturing method 2 of the second embodiment) is performed. In addition, the manufacturing method 3 (FIGS. 15-19) of 1st Embodiment may be sufficient as the method of making the width | variety of the upper layer electroconductive part 23 larger than the width | variety of the lower layer electroconductive part 21. FIG.
[Third Embodiment]
1. Structure of NAND-type EEPROM According to Third Embodiment FIG. 33 is a schematic diagram showing a cross-sectional structure of a NAND-type EEPROM according to the third embodiment, and shows a cross section along the control gate CG like the cross section shown in FIG. Show. In the third embodiment, the control gate CG is formed to extend to a position facing the lower layer conductive portion 21 on the outer surface 31 side of the upper layer conductive portion 23. The effect produced by this will be described in detail.

  As shown in FIG. 34, adjacent memory cells MC0 are electrically isolated by element isolation insulating layer 5. However, when the memory cell is miniaturized and the distance between adjacent memory cells is shortened, there is a problem of interference (noise) between the memory cells. That is, when a voltage change occurs in the charge storage layer 17 of the memory cell when data is written to the memory cell MC0 (a), the voltage of the charge storage layer 17 of the adjacent memory cell MC0 (b) due to capacitive coupling. May change. When such a change occurs, the electric field applied to the gate insulating layer (tunnel oxide film) 15 of the memory cell MC0 (b) differs from the originally intended value, and the tunnel current changes. As a result, the amount of charge in the charge storage layer 17 of the memory cell MC0 (b) does not become a desired value, and the threshold value of the memory cell MC0 (b) deviates from the desired value, resulting in an erroneous write state. Sometimes.

  In the third embodiment shown in FIG. 33, the control gate CG is formed on the outer surface 31 side of the upper conductive portion 23 so as to extend to a position facing the lower conductive portion 21. Therefore, the charge storage layer 17 is electrostatically shielded by the control gate CG. Therefore, the third embodiment can enhance the effect of preventing capacitive coupling in the lower conductive portion 21 than the first embodiment or the second embodiment. As a result, adjacent memory cells can be made less susceptible to noise.

  In the third embodiment, the width of the upper conductive portion 23 is made larger than the width of the lower conductive portion 21, and as indicated by an arrow X, the control gate CG on the outer surface 31 side and the gate insulating layer 15 below The element isolation insulating layer 5 is positioned between the semiconductor substrate 9 and the semiconductor substrate 9. For this reason, the element isolation insulating layer 5 and the dielectric layer 19 are located between the control gate CG and the semiconductor substrate 9. Therefore, compared with the case where only the dielectric layer 19 is located between them (that is, when the control gate CG on the element isolation insulating layer 5 is extended to a position facing the lower conductive portion 21 in FIG. 4), The effect of maintaining the withstand voltage can be improved. Since a relatively large potential difference is generated between the control gate CG and the semiconductor substrate 9, the above structure is useful.

  In the third embodiment, the element isolation insulating layer 5 is embedded in the trench 25, and the control gate CG has a structure located above the upper surface of the trench 25. If the control gate CG extends into the trench 25, an inversion layer is formed on the semiconductor substrate 9, and the adjacent memory cells may not be electrically isolated from each other. According to the above structure, such a situation can be prevented.

As shown in FIG. 33, in the third embodiment, the height of the upper conductive portion 23 is larger than the width as in the first embodiment, but the height value may be equal to or less than the width value.
2. Manufacturing Method of NAND Type EEPROM According to Third Embodiment FIGS. 35 and 36 are diagrams showing this manufacturing method in the order of steps, and correspond to FIG. 11 to 13 (manufacturing method 2 of the first embodiment) or FIGS. 15 to 19 (manufacturing method 3 of the first embodiment), the width of the upper conductive portion 23 is made larger than the width of the lower conductive portion 21. Enlarge.

  Then, as shown in FIG. 35, the upper conductive portion 23 located in the portion 37 protruding from the trench 25 is polished by, for example, CMP. Thus, the upper conductive layer 23 is patterned to have the inner side surface 29 and the outer side surface 31 constituted by a pair of rising portions 27 formed on the lower conductive layer 21 with a space therebetween.

  As shown in FIG. 36, for example, reactive ion etching is performed on the element isolation insulating layer 5 until the upper surface of the element isolation insulating layer 5 is below the lower conductive portion 21 so that the element isolation insulating layer 5 remains in the trench 25. To do. Thereby, the outer side surfaces 31 of the pair of rising portions 27 are exposed.

Thereafter, in the same manner as described above, the dielectric layer 19 is formed on the inner surface 29 and the outer surface 31, and finally, the control gate CG is formed on the dielectric layer 19.
[Application to electronic cards and electronic devices]
Next, an electronic card according to an embodiment of the present invention and an electronic device using the electronic card will be described. FIG. 37 shows the configuration of an electronic card and an electronic device according to an embodiment of the present invention. Here, the electronic device indicates a digital still camera 101 as an example of a portable electronic device. The electronic card is a memory card 119 used as a recording medium for the digital still camera 101. The memory card 119 includes an IC package PK1 in which the nonvolatile semiconductor memory device described in the embodiment of the present invention is integrated and sealed.

  The case of the digital still camera 101 houses a card slot 102 and a circuit board (not shown) connected to the card slot 102. The memory card 119 is removably attached to the card slot 102. When the memory card 119 is inserted into the card slot 102, it is electrically connected to an electric circuit on the circuit board.

  When the electronic card is, for example, a non-contact type IC card, the electronic card is connected to the electric circuit on the circuit board by a radio signal by being stored in or close to the card slot 102.

  FIG. 38 shows a basic configuration of a digital still camera. Light from the subject is collected by the lens 103 and input to the imaging device 104. The imaging device 104 is, for example, a CMOS image sensor, photoelectrically converts input light, and outputs an analog signal. The analog signal is amplified by an analog amplifier (AMP) and then digitally converted by an A / D converter. The converted signal is input to the camera signal processing circuit 105, and is subjected to, for example, automatic exposure control (AE), automatic white balance control (AWB), and color separation processing, and then converted into a luminance signal and a color difference signal.

  When monitoring an image, the signal output from the camera signal processing circuit 105 is input to the video signal processing circuit 106 and converted into a video signal. An example of the video signal system is NTSC (National Television System Committee). The video signal is output to the display unit 108 attached to the digital still camera 101 via the display signal processing circuit 107. The display unit 108 is a liquid crystal monitor, for example.

  The video signal is given to the video output terminal 110 via the video driver 109. An image captured by the digital still camera 101 can be output to an image device such as a television via the video output terminal 110. As a result, the captured image can be displayed even outside the display unit 108. The imaging device 104, analog amplifier (AMP), A / D converter (A / D), and camera signal processing circuit 105 are controlled by the microcomputer 111.

  When capturing an image, the operator presses an operation button such as the shutter button 112. Thereby, the microcomputer 111 controls the memory controller 113, and the signal output from the camera signal processing circuit 105 is written in the video memory 114 as a frame image. The frame image written in the video memory 114 is compressed based on a predetermined compression format by the compression / expansion processing circuit 115 and recorded on the memory card 119 mounted in the card slot 102 via the card interface 116. .

  When reproducing the recorded image, the image recorded on the memory card 119 is read out via the card interface 116, decompressed by the compression / decompression processing circuit 115, and then written into the video memory 114. The written image is input to the video signal processing circuit 106 and displayed on the display unit 108 and the image device in the same manner as when monitoring the image.

  In this configuration, the card slot 102, the imaging device 104, the analog amplifier (AMP), the A / D converter (A / D), the camera signal processing circuit 105, the video signal processing circuit 106, and the memory controller 113 are provided on the circuit board 100. A video memory 114, a compression / decompression processing circuit 115, and a card interface 116 are mounted.

  However, the card slot 102 does not need to be mounted on the circuit board 100 and may be connected to the circuit board 100 by a connector cable or the like.

  A power supply circuit 117 is further mounted on the circuit board 100. The power supply circuit 117 is supplied with power from an external power supply or a battery, and generates an internal power supply voltage used inside the digital still camera. A DC-DC converter may be used as the power supply circuit 117. The internal power supply voltage is supplied to the strobe 118 and the display unit 108 in addition to the circuits described above.

  As described above, the electronic card according to the embodiment of the present invention can be used for a portable electronic device such as a digital still camera. Further, this electronic card can be applied not only to portable electronic devices but also to various other electronic devices as shown in FIGS. 39A to 39J. 39A, the television shown in FIG. 39B, the audio equipment shown in FIG. 39C, the game equipment shown in FIG. 39D, the electronic musical instrument shown in FIG. 39E, the mobile phone shown in FIG. 39F, and the personal computer shown in FIG. The electronic card can be used for a personal digital assistant (PDA) shown in FIG. 39H, a voice recorder shown in FIG. 39I, a PC card shown in FIG. 39J, and the like.

FIG. 3 is a plan view showing a part of the memory cell array of the NAND type EEPROM according to the first embodiment. It is a schematic diagram of the II (a) -II (b) cross section of FIG. FIG. 3 is an equivalent circuit diagram of the NAND cell of FIG. 2. FIG. 4 is a schematic diagram of a cross section IV (a) -IV (b) in FIG. 1. 2 is a perspective view of a charge storage layer provided in the NAND-type EEPROM according to the first embodiment. FIG. FIG. 6 is a first process diagram for explaining the manufacturing method 1 of the NAND type EEPROM according to the first embodiment. It is the 2nd process drawing. It is the 3rd process drawing. It is the 4th process drawing. It is the same 5th process drawing. FIG. 6 is a first process diagram for explaining the manufacturing method 2 of the NAND type EEPROM according to the first embodiment. It is the 2nd process drawing. It is the 3rd process drawing. It is the 4th process drawing. It is a 1st process figure for demonstrating the manufacturing method 3 of the NAND type EEPROM which concerns on 1st Embodiment. It is the 2nd process drawing. It is the 3rd process drawing. It is the 4th process drawing. It is the same 5th process drawing. It is a 1st process figure for demonstrating the manufacturing method 4 of the NAND type EEPROM which concerns on 1st Embodiment. It is the 2nd process drawing. It is a schematic diagram of the cross section along the control gate CG of the NAND type EEPROM according to the second embodiment. It is a schematic diagram which shows the cross section of the NAND type EEPROM which concerns on a comparative example. It is a graph which shows the relationship between the dispersion | variation in the height of a rising part, and a coupling ratio. It is a 1st process figure for demonstrating the manufacturing method 1 of the NAND type EEPROM which concerns on 2nd Embodiment. It is the 2nd process drawing. It is the 3rd process drawing. It is the 4th process drawing. It is a 1st process figure for demonstrating the manufacturing method 2 of the NAND type EEPROM which concerns on 2nd Embodiment. It is the 2nd process drawing. It is the 3rd process drawing. It is a schematic diagram which shows the cross section of the NAND type EEPROM produced with the manufacturing method 3 of 2nd Embodiment. It is a schematic diagram which shows the cross section of the NAND type EEPROM which concerns on 3rd Embodiment. It is a figure which shows the state in which capacitive coupling has arisen between adjacent memory cells. It is a 1st process figure for demonstrating the manufacturing method of the NAND type EEPROM which concerns on 3rd Embodiment. It is the 2nd process drawing. 1 is a configuration diagram of an electronic card and an electronic device according to an embodiment of the present invention. 1 is a basic configuration diagram of a digital still camera which is a first example of an electronic apparatus according to an embodiment of the present invention. It is a figure which shows the video camera which is the 2nd example of the electronic device which concerns on embodiment of this invention. It is a figure which shows the television which is a 3rd example of the electronic device which concerns on embodiment of this invention. It is a figure which shows the audio equipment which is the 4th example of the electronic device which concerns on embodiment of this invention. It is a figure which shows the game device which is the 5th example of the electronic device which concerns on embodiment of this invention. It is a figure which shows the electronic musical instrument which is the 6th example of the electronic device which concerns on embodiment of this invention. It is a figure which shows the mobile telephone which is the 7th example of the electronic device which concerns on embodiment of this invention. It is a figure which shows the personal computer which is the 8th example of the electronic device which concerns on embodiment of this invention. It is a figure which shows the personal digital assistant (PDA) which is the 9th example of the electronic device which concerns on embodiment of this invention. It is a figure which shows the voice recorder which is a 10th example of the electronic device which concerns on embodiment of this invention. It is a figure which shows the PC card | curd which is the 11th example of the electronic device which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 3 ... Element formation area, 5 ... Element isolation insulating layer, 7 ... NAND cell, 9 ... Semiconductor substrate, 11 ... Impurity region, 13 ... Channel Region 15, gate insulating layer 17, charge storage layer, 19 dielectric layer, 21 lower conductive portion, 23 upper conductive portion, 25 trench, 27 ..Rising part, 29 ... inner side surface, 31 ... outer side surface, 33 ... bottom surface, 35 ... mask material, 37 ... part protruding from trench, 39 ... upper mask material, 41 ... Lower layer mask material, 43 ... Bottom height adjusting layer, 45 ... Silicon oxide layer, 47 ... Protective layer, H ... Height of upper conductive layer, W ... Upper conductive layer Part width, D ... distance between trenches, G ... gap between rising parts, d1 ... upper surface of rising parts To the element isolation insulating layer, d2... Distance from the upper surface of the rising portion to the bottom height adjustment layer, MC0 to 15... Memory cell, CG0 to 15. Select gate, BL ... bit line, CELSRC ... common source line

Claims (27)

A semiconductor substrate including an element formation region;
A gate insulating layer formed on the element formation region;
It has an inner side surface and an outer side surface composed of a lower layer conductive part formed on the gate insulating layer and a pair of rising parts formed on the lower layer conductive part with a gap between each other, and has a width of A charge storage layer including a larger upper conductive portion,
An element isolation insulating layer formed on the semiconductor substrate so as to sandwich the element formation region;
A dielectric layer formed on the inner surface and the outer surface;
A control gate formed on the dielectric layer;
A non-volatile semiconductor memory device comprising: A semiconductor substrate including an element formation region;
A gate insulating layer formed on the element formation region;
A lower conductive layer formed on the gate insulating layer, and an upper conductive layer having an inner surface and an outer surface formed by a pair of rising portions disposed on the lower conductive portion with a space between each other; A charge storage layer comprising:
An element isolation insulating layer formed on the semiconductor substrate so as to sandwich the element formation region on the outer surface side;
A bottom surface height adjusting layer formed on the bottom surface of the upper conductive portion located on the inner surface side;
A dielectric layer formed on the inner surface, the outer surface, and the bottom surface height adjustment layer;
A control gate formed on the dielectric layer;
A non-volatile semiconductor memory device comprising a plurality of memory cells having   The nonvolatile semiconductor memory device according to claim 2, wherein the upper conductive portion has a height larger than a width.   4. The nonvolatile semiconductor memory device according to claim 2, wherein a distance from an upper surface of the pair of rising portions to the bottom surface height adjustment layer is substantially the same in the plurality of memory cells. 5.   5. The distance from the upper surface of the pair of rising portions to the bottom surface height adjustment layer is substantially equal to the distance from the upper surface of the pair of rising portions to the element isolation insulating layer. The nonvolatile semiconductor memory device according to any one of the above.   6. The nonvolatile semiconductor according to claim 2, wherein a distance from an upper surface of the pair of rising portions to the bottom surface height adjustment layer is larger than a thickness of the dielectric layer. Storage device.   7. The nonvolatile semiconductor memory device according to claim 2, wherein heights of the pair of rising portions vary among the plurality of memory cells. A semiconductor substrate including an element formation region;
A gate insulating layer formed on the element formation region;
A lower conductive layer formed on the gate insulating layer, and an upper conductive layer having an inner surface and an outer surface formed by a pair of rising portions disposed on the lower conductive portion with a space between each other; A charge storage layer comprising:
An element isolation insulating layer formed on the semiconductor substrate so as to sandwich the element formation region on the outer surface side;
A dielectric layer formed on the inner surface and the outer surface;
A control gate formed on the dielectric layer so as to extend to a position facing the lower conductive portion on the outer surface side;
A non-volatile semiconductor memory device comprising:   9. The nonvolatile semiconductor memory device according to claim 8, wherein the upper conductive portion has a height larger than a width.   10. The nonvolatile semiconductor memory according to claim 8, wherein the element isolation insulating layer is located between the control gate on the outer surface side and the semiconductor substrate under the gate insulating layer. 11. apparatus. The element isolation insulating layer is embedded in a trench of the semiconductor substrate;
The control gate is located above the upper surface of the trench;
The nonvolatile semiconductor memory device according to claim 8, wherein the nonvolatile semiconductor memory device is a non-volatile semiconductor memory device.   The nonvolatile semiconductor memory device according to claim 1, wherein a width of the upper conductive portion is larger than a width of the lower conductive portion.   The gap between one rising portion and the other rising portion in the pair of rising portions is larger than twice the thickness of the dielectric layer, according to any one of claims 1 to 12, The nonvolatile semiconductor memory device described.   The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a NAND type EEPROM.   An electronic card on which the nonvolatile semiconductor memory device according to claim 1 is mounted. A card interface;
A card slot connected to the card interface;
The electronic card according to claim 15, wherein the electronic card is electrically connectable to the card slot.
An electronic device comprising:   The electronic device according to claim 16, wherein the electronic device is a digital camera. Forming a gate insulating layer on the semiconductor substrate;
Forming a lower conductive portion which is a component of a charge storage layer on the gate insulating layer;
By selectively etching the lower conductive layer, the gate insulating layer, and the semiconductor substrate, the gate insulating layer and the lower conductive layer are left on the element forming region of the semiconductor substrate, and the element forming region is sandwiched therebetween. Forming a trench in the semiconductor substrate,
Forming an element isolation insulating layer in the trench such that a length protruding from the trench is greater than a distance between the trenches;
Forming an upper conductive portion serving as a component of the charge storage layer on the element isolation insulating layer and the lower conductive portion so that a portion of the element isolation insulating layer protruding from the trench is not filled. When,
By removing a portion of the upper conductive portion located on the upper surface of the element isolation insulating layer, an inner surface and an outer surface constituted by a pair of rising portions formed on the lower conductive portion with a space therebetween. Patterning the upper conductive portion having side surfaces;
Exposing the outer surfaces of the pair of rising portions by etching the element isolation insulating layer so that the element isolation insulating layer remains in the trench;
Forming a dielectric layer on the inner surface and the outer surface;
Forming a control gate on the dielectric layer;
A method for manufacturing a nonvolatile semiconductor memory device. Between the step of forming the upper conductive portion and the patterning step of the upper conductive portion,
19. The method of claim 18, further comprising a step of forming a protective layer on the upper conductive portion located in the element isolation insulating layer so as to fill a portion protruding from the trench. The manufacturing method of the non-volatile semiconductor memory device of description. A method of manufacturing a nonvolatile semiconductor memory device having a plurality of memory cells,
Forming a gate insulating layer on the semiconductor substrate;
Forming a lower conductive portion which is a component of a charge storage layer on the gate insulating layer;
By selectively etching the lower conductive portion, the gate insulating layer, and the semiconductor substrate, the gate insulating layer and the lower conductive portion are left on the element forming region of the semiconductor substrate and the element forming region is sandwiched therebetween. Forming a trench in the semiconductor substrate,
Forming an element isolation insulating layer in the trench so as to protrude from the trench;
Forming an upper conductive portion serving as a component of the charge storage layer on the element isolation insulating layer and the lower conductive portion so as not to fill a portion of the element isolation insulating layer protruding from the trench. When,
The outer surface of the upper conductive portion is exposed by etching the element isolation insulating layer so that the element isolation insulating layer remains in the trench, and the bottom surface height adjustment layer remains on the bottom surface of the upper conductive portion. Exposing the inner side surface of the upper conductive portion by etching the bottom surface height adjusting layer,
Forming a dielectric layer on the inner surface and the outer surface;
Forming a control gate on the dielectric layer;
A method for manufacturing a nonvolatile semiconductor memory device. Between the step of forming the upper conductive portion and the step of exposing the outer surface and the inner surface,
Forming the bottom surface height adjustment layer on the upper conductive portion located in the element isolation insulating layer so as to fill a portion protruding from the trench,
By removing a portion of the upper conductive portion located on the upper surface of the element isolation insulating layer, the inner side surface constituted by a pair of rising portions formed on the lower conductive portion with a space therebetween, and Patterning the upper conductive portion having the outer surface;
The method for manufacturing a nonvolatile semiconductor memory device according to claim 20, wherein Between the step of forming the upper conductive portion and the step of exposing the outer surface and the inner surface,
By removing a portion of the upper conductive portion located on the upper surface of the element isolation insulating layer, the inner side surface constituted by a pair of rising portions formed on the lower conductive portion with a space therebetween, and Patterning the upper conductive portion having the outer surface;
Forming the bottom surface height adjustment layer on the upper conductive portion located in the element isolation insulating layer so as to fill a portion protruding from the trench,
The method for manufacturing a nonvolatile semiconductor memory device according to claim 20, wherein   21. The element isolation insulating layer forming step of forming the element isolation insulating layer in the trench so that a length protruding from the trench is larger than a distance between the trenches. The method for manufacturing a nonvolatile semiconductor memory device according to any one of items 1 to 22. Forming a gate insulating layer on the semiconductor substrate;
Forming a lower conductive portion which is a component of a charge storage layer on the gate insulating layer;
By selectively etching the lower conductive layer, the gate insulating layer, and the semiconductor substrate, the gate insulating layer and the lower conductive layer are left on the element forming region of the semiconductor substrate, and the element forming region is sandwiched therebetween. Forming a trench in the semiconductor substrate,
Forming an element isolation insulating layer in the trench so as to protrude from the trench;
Forming an upper conductive portion serving as a component of the charge storage layer on the element isolation insulating layer and the lower conductive portion so as not to fill a portion of the element isolation insulating layer protruding from the trench. When,
By removing a portion of the upper conductive portion located on the upper surface of the element isolation insulating layer, an inner surface and an outer surface constituted by a pair of rising portions formed on the lower conductive portion with a space therebetween. Patterning the upper conductive portion having side surfaces;
Etching the element isolation insulating layer until the upper surface of the element isolation insulating layer is below the lower conductive portion so that the element isolation insulating layer remains in the trench, thereby Exposing the outer surface;
Forming a dielectric layer on the inner surface and the outer surface;
Forming a control gate on the dielectric layer;
A method for manufacturing a nonvolatile semiconductor memory device.   25. The step of forming the element isolation insulating layer includes forming the element isolation insulating layer in the trench so that a length protruding from the trench is larger than a distance between the trenches. A method for manufacturing a nonvolatile semiconductor memory device according to claim 1.   The step of thinning the portion of the element isolation insulating layer protruding from the trench by etching between the step of forming the element isolation insulating layer and the step of forming the upper conductive portion is characterized by comprising: The method for manufacturing a nonvolatile semiconductor memory device according to any one of 18 to 25. In the step of forming the trench, the trench is formed using a mask material including an upper layer mask material and a lower layer mask material as a mask,
Between the step of forming the element isolation insulating layer and the step of forming the upper conductive layer, after removing the upper layer mask material, masking the portion of the element isolation insulating layer protruding from the trench with the lower layer mask material The method of manufacturing a nonvolatile semiconductor memory device according to claim 18, further comprising: a step of thinning by etching and removing the lower layer mask material.

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