TW201509262A - Manufacturing method for multi-layer circuit board - Google Patents

Abstract

A manufacturing method for a multi-layer circuit board includes the following steps. Firstly, a substrate having a via penetrating the substrate is provided. Next, a patterned circuit layer is formed on a surface of the substrate by using the via as an alignment target. The patterned circuit layer includes a concentric-circle pattern. Next, a first stacking layer is formed on the surface. Then, a first through hole penetrating regions of the first stacking layer and the substrate where a first concentric circle from the center of the concentric-circle pattern is orthogonally projected thereon is formed. Next, a second stacking layer is formed on the first stacking layer. Afterward, a second through hole penetrating regions of the first, the second stacking layers and the substrate where a second concentric circle from the center of the concentric-circle pattern is orthogonally projected thereon is formed.

Description

Multilayer circuit board manufacturing method

The present invention relates to a method of fabricating a circuit board, and more particularly to a method of fabricating a multilayer circuit board.

As the integration of electronic products is getting higher and higher, the circuit boards used in high-accumulation electronic products have also changed from single layer and 2 layers to 6 layers, 8 layers, and even 10 Above the layer, the electronic components can be more densely mounted on the printed circuit board. In general, the most common circuit board process is a lamination process. When a circuit board is fabricated by a lamination method, the alignment accuracy between each circuit layer and the insulating layer must be well controlled. Therefore, in the circuit board process, usually, a plurality of alignment targets are formed by the lithography process in the previous stack, and after the layers are further added, the alignment targets of the previous stack are found by X-ray and milled. The target process is to form another alignment target for subsequent processes.

However, since the alignment target of the previous stack is formed by the lithography process, there is already a process error in itself, and when the X-ray is used for milling the target, an error in the milling target process is also generated. Thus, the alignment error generated by the alignment targets of each layer Will continue to accumulate. If the number of circuit layers of the board increases, the error accumulated by these alignment targets also increases, causing the interlayer alignment to be excessively shifted and the design of the via holes and the underlying pads cannot be miniaturized.

The invention provides a manufacturing method of a multi-layer circuit board, which can improve the interlayer alignment precision of the multi-layer circuit board, improve the wiring density and capability of the circuit layer, and the design of the via hole and the bottom layer pad can be improved due to the alignment accuracy. It tends to be miniaturized, and it is possible to make a pattern design with a single side alignment of less than 50 μm.

A method of fabricating a multilayer circuit board of the present invention includes the following steps: First, a substrate is provided that includes a first through hole penetrating the substrate. Next, a first patterned circuit layer is formed on the upper surface of the substrate by using the first via as the alignment target. The first patterned circuit layer includes a first concentric pattern surrounding the first via. Next, a first stacked layer is formed on the upper surface and covers the first patterned wiring layer. The first stacked layer includes a first dielectric layer and a first circuit layer covering the first dielectric layer. Thereafter, a first through hole is formed. The first uniform hole is projected through the first concentric circle pattern from the center to the inner diameter of the first concentric circle to the first stacked layer and the region of the substrate. Next, a second stacked layer is formed on the first stacked layer. The second stacked layer includes a second dielectric layer and a second wiring layer covering the second dielectric layer. Thereafter, a second through hole is formed. The second through hole extends through the first concentric circle pattern from the center to the inner diameter of the second concentric circle to the second stacked layer, the first stacked layer, and the region of the substrate.

Based on the above, the method for fabricating the multilayer circuit board of the present invention is prior to the innermost layer The surface of the substrate forms a concentric pattern, and the subsequent layers of the layers are aligned with the concentric pattern to form corresponding pairs of through holes, and the corresponding stacked layers are respectively formed by the opposite holes of each layer. For the subsequent process, for example, the patterned circuit layer and the via holes of each layer are formed by using the via holes as the alignment reference. Therefore, the manufacturing method of the present invention can reduce the accumulation of alignment errors between layers in the prior art, and can reduce the problem of layering of the multilayer circuit board. Therefore, the present invention can improve the alignment accuracy of the multilayer circuit board, improve the wiring density and capability of the circuit layer, and the design of the via hole and the underlying pad can be miniaturized due to the improvement of the alignment accuracy, and can be made. A pattern design with a single side alignment of less than 50 μm.

The above described features and advantages of the invention will be apparent from the following description.

110‧‧‧Substrate

112, 114‧‧‧ surface

116‧‧‧First through hole

118‧‧‧Second through hole

120‧‧‧First patterned circuit layer

122‧‧‧First concentric pattern

122a, 124a‧‧‧ first concentric circle

122b, 124b‧‧‧Second concentric circle

124‧‧‧Second concentric pattern

130‧‧‧First stacking layer

132‧‧‧First dielectric layer

134‧‧‧First line layer

134a‧‧‧first opening

140‧‧‧first through hole

150‧‧‧Second stacking layer

152‧‧‧Second dielectric layer

154‧‧‧Second circuit layer

154a‧‧‧second opening

160‧‧‧second through hole

170‧‧‧ sixth stacking layer

172‧‧‧ sixth dielectric layer

174‧‧‧ sixth circuit layer

174a, 194a‧‧

180‧‧‧six through hole

182‧‧‧Blind hole

190‧‧‧ seventh stack

192‧‧‧ seventh dielectric layer

194‧‧‧ seventh circuit layer

195‧‧‧ seventh through hole

D1‧‧‧through hole outer diameter

D2‧‧‧ concentric pattern outer diameter

G1‧‧‧ spacing

1A-1G are schematic flow diagrams of a method of fabricating a multilayer circuit board in accordance with an embodiment of the invention.

2 is a top plan view of a substrate and a first patterned circuit layer in accordance with an embodiment of the present invention.

3 is a top plan view of the first concentric pattern of FIG. 1E.

4 is a top plan view of the first concentric pattern of FIG. 1G.

5 is a top plan view of a substrate and a first patterned circuit layer in accordance with another embodiment of the present invention.

6A-6D are partial flow diagrams of a method of fabricating a multilayer circuit board in accordance with another embodiment of the present invention.

1A-1G are schematic flow diagrams of a method of fabricating a multilayer circuit board in accordance with an embodiment of the invention. 2 is a top plan view of a substrate and a first patterned circuit layer in accordance with an embodiment of the present invention. In the present embodiment, the method of fabricating the multilayer circuit board includes the following steps. First, as shown in FIG. 1A, a substrate 110 is provided, which includes opposing surfaces 112, 114 and a first through hole 116 penetrating the substrate 110. Next, referring to FIG. 1B and FIG. 2 , a first patterned circuit layer 120 is formed on the surface 112 by using the first via 116 as a target. In the present embodiment, as shown in FIG. 2, the outer diameter D1 of the first through hole 116 is substantially between 0.5 mm (mm) and 0.8 mm. It should be noted that the manufacturing flow shown in FIG. 1A to FIG. 1G is a cross-sectional view of the manufacturing process of the area A in FIG. 2 . The first patterned circuit layer 120 has a first concentric pattern 122 surrounding the first via 116 as shown in FIG. The first concentric circle pattern 122 includes a plurality of concentric circles, and the distance G1 between the concentric circles is substantially between 50 micrometers (μm) and 100 micrometers. Of course, the invention is not limited thereto, and the field generally has Knowledgers can make adjustments according to the actual product design and layout requirements.

Next, as shown in FIG. 1C, a first stacked layer 130 is formed on the surface 112, wherein the first stacked layer 130 includes a first dielectric layer 132 and a first wiring layer 134, and the first wiring layer 134 covers the first A dielectric layer 132. Thereafter, please refer to FIG. 1D and FIG. 1E simultaneously, and the first through hole 140 is formed by, for example, drilling with a CO ₂ laser. The first uniform hole 140 is projected from the center to the inner diameter of the first concentric circle 122a to the region of the first stacked layer 130 and the substrate 110 through the first concentric circle pattern 122 as shown in FIG. 1E. FIG. 3 is a plan view showing the first concentric pattern 122 penetrated by the first through hole 140.

In this embodiment, the material of the first patterned circuit layer 120 and the first circuit layer 134 is copper, and the copper absorbs only in the short wavelength region below the ultraviolet region (<0.3 μm), and the carbon dioxide laser The longer wavelength of light (about 10 microns or more) belongs to the infrared region, so it is less ablated by copper and ablated copper into holes. Therefore, the concentric pattern 122 of copper material can be regarded as a copper mask of the carbon dioxide laser to limit the range in which the carbon dioxide laser cuts the first stacked layer 130 and the substrate 110. That is to say, by drilling a hole outward from the center by using a carbon dioxide laser, the first through hole 140 formed by drilling the inner diameter of the first concentric circle 122a is drilled. It should be noted that if the first through hole 140 is formed by using a carbon dioxide laser, the first circuit layer 134 of FIG. 1C is first patterned to form a first opening 134a as shown in FIG. 1D, so that the first opening 134a A region in which the first concentric pattern 122 is projected onto the first dielectric layer 132 is exposed, and a subsequent drilling process is performed.

Of course, the invention is not limited thereto. In other embodiments of the present invention, the first through hole 140 may also be formed by direct laser drilling (DLD). If the first through hole 140 is formed by direct laser drilling, it is not necessary to form the opening 134a as shown in FIG. 1D, and direct laser drilling can be performed after the first wiring layer 134 shown in FIG. 1C is formed. To form the first through hole 140. In this implementation In one example, the formation of the first through holes 140 may be bored, for example, from the outer surface of the first stacked layer 130 to the direction of the substrate 110, respectively.

After that, the first through hole 140 can be used as a registration target to perform subsequent processing on the first stacked layer 130, for example, the first through hole 140 is used as a aligning target of the lithography process, and the first circuit layer 134 is patterned. The first patterned via layer is formed on the first stacked layer 130 by forming the first via hole with the first through hole 140 as an alignment target.

Thereafter, as shown in FIG. 1F, a second stacked layer 150 is formed on the first stacked layer 130. The second stacked layer 150 includes a second dielectric layer 152 and a second wiring layer 154, and the second wiring layer 154 covers the second dielectric layer 152. Thereafter, a second through hole 160 is formed as shown in FIG. 1G, and the second through hole 160 is projected through the first concentric circle pattern 120 from the center to the inner diameter of the second concentric circle 122b to the second stacked layer 150, The first stacked layer 130 and the region of the substrate 110. FIG. 4 is a plan view showing the first concentric pattern 122 penetrated by the second through hole 160.

As described in the method of forming the first through hole, the second through hole 160 may also be formed by means of carbon dioxide laser drilling. That is, after the carbon dioxide laser is bored outward from the center to ablate the substrate 110 between the first concentric circle 122a and the second concentric circle 122b as shown in FIG. 3, the first concentric circle 122a The self-concentric pattern 120 can be peeled off to form a second through hole 160 as shown in FIG. Similarly, if a carbon dioxide laser is used to form the second through hole 160, a second opening 154a as shown in FIG. 1F is formed to expose the second opening 154a to expose the first concentric pattern 122 to the second dielectric. The area of layer 152 is followed by a subsequent drilling procedure.

Of course, in other embodiments of the present invention, the second through hole 160 may be formed by using a direct laser Drill (DLD), so that the second opening 154a as shown in FIG. 1F does not need to be formed. A direct laser drilling can be performed immediately to form a second through hole 160. In the present embodiment, the method of forming the second through holes 160 may be bored from the outer surface of the second stacked layer 150 toward the direction of the substrate 110, respectively.

After that, the second through hole 160 can be used as a registration target to perform subsequent processing on the second stacked layer 150, for example, the second through hole 160 is used as an alignment target of the lithography process, and the second circuit layer 154 is patterned. Forming a third patterned circuit layer of the multilayer circuit board, or forming a second via hole on the second stacked layer 150 by using the second through hole 160 as an alignment target, wherein the second via hole is connected to the first The first via holes on the stacked layer 130.

This embodiment only exemplifies the fabrication flow of forming a two-layer structure on one side of the substrate. Of course, the present invention does not limit the number of layers of the stacked layer, the wiring layer, and the number of concentric circles of the concentric pattern. Those skilled in the art can continue to stack other stacked layers on the second stacked layer according to the foregoing fabrication method, and form the alignment holes of the layers by using the concentric pattern 122 as the alignment target, and then the alignment of the layers. The through holes are respectively subjected to a subsequent alignment process to form patterned circuit layers and/or via holes of the respective layers.

In this way, the stacked layers of each layer of the multi-layer circuit board are formed by the concentric circular pattern 122 on the surface of the innermost substrate 110 to form a corresponding pair of through holes, thereby reducing the accumulation of alignment errors between the layers in the conventional layer, and Reduce the problem of layering of multilayer boards. In addition, via holes connecting the layers can be formed in this way. Since the via holes of each layer are in the same lithography process, the concentric pattern 122 is used as the alignment mark. The target is formed, so that the conduction hole can be prevented from being aligned due to the accumulation error of the via hole, the wiring density and the capability of the circuit layer are improved, and the design of the via hole and the underlying pad is improved due to interlayer alignment accuracy. The miniaturization can be made, and a pattern design with a single side alignment of less than 50 μm can be produced.

In addition, if the number of layers of the circuit layer required for the multilayer circuit board is large, the number of times to be layered is also increased, and the number of concentric circles of the first concentric pattern 122 is accordingly increased. That is, the maximum outer diameter D2 of the first concentric pattern 122 is proportional to the number of build-ups of the multilayer circuit board. However, based on the maximum size limit readable by the image capture window of the production device's Charge-Coupled Device (CCD), the maximum outer diameter D2 of the first concentric pattern 122 should be substantially less than or equal to 3.175 mm ( Mm). Therefore, if the number of times of layering of the multilayer circuit board is greater than a predetermined value (for example, equal to or greater than 5 times), and the maximum outer diameter D2 of the first concentric pattern 122 approaches 3.175 mm, the stacked layer formed thereafter The alignment process is performed by using another concentric pattern as an alignment target.

5 is a top plan view of a substrate and a first patterned circuit layer in accordance with another embodiment of the present invention. 6A-6D are partial flow diagrams of a method of fabricating a multilayer circuit board in accordance with another embodiment of the present invention. Referring to FIG. 5, as described above, when the number of times of layering to be performed by the multilayer circuit board is greater than a predetermined value, two concentric circle patterns are designed. That is, in the present embodiment, the number of times of layering of the multilayer circuit board is greater than a predetermined value (for example, greater than M times, M is a positive integer greater than 2), and the substrate 110 has the aforementioned first through holes 116, More preferably, there is a second through hole 118 penetrating the substrate. Then, the first through hole 116 and the second through hole 118 are respectively used A first patterned wiring layer 120 is formed on the surface 112 for the alignment target. Each of the first patterned circuit layers 120 includes a first concentric pattern 122 surrounding the first vias 116 , and a second concentric pattern 124 surrounding the second vias 118 . Since the first concentric pattern 122 and the second concentric pattern 124 are formed by the same patterning process, the accumulation error of the multi-pass patterning process can be avoided. In this way, the stacked layers starting from the Mth layer are aligned with the second concentric pattern 124 for the subsequent alignment process, and the fabrication process is substantially the same as the fabrication process of FIGS. 1A to 1G.

In detail, referring to FIG. 5 and FIG. 6A simultaneously, after forming the second concentric circle pattern 124, the Mth stacked layer may be formed above the second stacked layer 150. In this embodiment, M is, for example, 6, That is to say, the multi-layer circuit board has sequentially formed the first to fifth stacked layers by using the first concentric circular pattern 122 as an alignment target, and the sixth stacked layer 170 (that is, the M-th stacked layer) correspondingly includes the sixth medium. The electrical layer 172 and the sixth circuit layer 174 covering the sixth dielectric layer 172. Next, as shown in FIGS. 5 and 6B, a sixth through hole 180 is formed which is projected through the second concentric circle pattern 124 from the center to the inner diameter of the first concentric circle 124a to the first to sixth stacked layers and the base. The area of the material 110.

It should be noted that, when the first concentric pattern 122 is used as the alignment target to form the through holes of the dielectric layers (for example, the first to fifth stacked layers), the second concentric pattern 124 may be respectively The two through holes 118 are projected onto the corresponding dielectric layer to form the blind holes 182, that is, the blind holes are respectively formed at the positions of the respective dielectric layers (for example, the first to fifth stacked layers) corresponding to the second through holes 118. 182, wherein the outer diameter of the blind hole 182 is smaller than the inner diameter of the first concentric circle 124a. So, because each stack layer has been pre- The blind holes are first formed to reduce the total thickness of the dielectric layer. Therefore, in the subsequent process, the laser can form the sixth through hole 180 without burning through the dielectric layer having a thick total thickness at one time.

After that, the sixth through hole 180 can be used as a registration target to perform subsequent processing on the sixth stacked layer 170, for example, the sixth through hole 180 is used as a aligning target of the lithography process, and the sixth circuit layer 174 is patterned. The patterning circuit layer is formed to form a multilayer circuit board, or the sixth via hole is formed on the sixth stacked layer 170 by using the sixth through hole 180 as an alignment target.

Referring to FIG. 6C, a seventh stacked layer 190 (that is, an M+1 stacked layer) is formed on the sixth stacked layer 170. The seventh stacked layer 190 includes a seventh dielectric layer 192 and a seventh wiring layer 194 covering the seventh dielectric layer 192. Then, as shown in FIG. 5 and FIG. 6D, a seventh through hole 195 is formed, which is projected from the center to the inner diameter of the second concentric circle 124b to the first to seventh stacks through the second concentric pattern 124. The layer and the area of the substrate 110.

After that, the seventh via 195 can be used as a aligning target to perform the subsequent processing on the seventh stacked layer 190, for example, the seventh through hole 195 is used as a aligning target of the lithography process, and the seventh circuit layer 194 is patterned. Forming a patterned circuit layer of the multilayer circuit board, or forming a seventh via hole on the seventh stacked layer 190 by using the seventh through hole 195 as an alignment target, wherein the seventh via hole is connected to the sixth stacked layer The sixth via hole on the 170, and the via holes of each layer are connected to each other.

As described above, the sixth through hole 180 and the seventh through hole 195 can also be formed by means of carbon dioxide laser drilling or direct laser drilling. Similarly, if a carbon dioxide laser is used to form the sixth through hole 180 and the seventh through hole 195, it is first formed as shown in the figure. The openings 174a and 194a shown in FIG. 6A and FIG. 6C are respectively projected to the regions of the sixth dielectric layer 172 and the second dielectric layer 192 which are projected to the second concentric pattern 124, and the drilling process is performed. If direct laser drilling is used, it is not necessary to form openings 174a, 194a, and direct laser drilling can be performed immediately.

In summary, the method for fabricating the multi-layer circuit board of the present invention is to form a concentric circle pattern on the surface of the innermost substrate, and then the stacked layers of each layer are aligned with the concentric pattern to form a corresponding target. For the via holes, the subsequent layers of the corresponding layers are respectively subjected to subsequent processes of the stacked layers, for example, the patterned circuit layers and via holes of the respective layers are formed by using the via holes as the alignment reference. Therefore, the manufacturing method of the present invention can reduce the accumulation of alignment errors between layers in the prior art, and can reduce the problem of layering of the multilayer circuit board. In addition, since the via holes of each layer are formed by using the concentric pattern formed by the same lithography process as the alignment target, the conduction hole may be offset due to the accumulation error of the alignment holes between the layers. Therefore, the present invention can improve the alignment accuracy of the multi-layer circuit board, improve the wiring density and capability of the circuit layer, and the design of the via hole and the pad can be miniaturized due to the improvement of the alignment accuracy, and the single can be made. A pattern design with an edge alignment of less than 50 μm.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

110‧‧‧Substrate

116‧‧‧First through hole

120‧‧‧First patterned circuit layer

122‧‧‧First concentric pattern

122a‧‧‧The first concentric circle

122b‧‧‧Second concentric circle

D1‧‧‧through hole outer diameter

D2‧‧‧ concentric pattern outer diameter

G1‧‧‧ spacing

Claims (14)

A method for fabricating a multilayer circuit board, comprising: providing a substrate, including a first through hole penetrating the substrate; forming a first patterned circuit layer on the substrate by using the first through hole as a target target On a surface of the first patterned circuit layer, a first concentric pattern surrounding the first via hole is formed; a first stacked layer is formed on the surface and covers the first patterned circuit layer, the first stack The layer includes a first dielectric layer and a first circuit layer covering the first dielectric layer; forming a first through hole, the first through hole runs through the first concentric pattern from the center to the first concentric An inner diameter of the circle is projected onto the first stacked layer and a region of the substrate; a second stacked layer is formed on the first stacked layer, the second stacked layer includes a second dielectric layer and covers the second a second wiring layer of the dielectric layer; and a second through hole extending through the first concentric circle pattern from the center to the inner diameter of the second concentric circle to the second stacked layer The first stacked layer and the region of the substrate. The method for fabricating a multilayer circuit board according to claim 1, further comprising: after forming the first through hole, patterning the first circuit layer with the first through hole as an alignment target; and forming the After the second through hole, the second through hole is used as the alignment target to pattern the second Line layer. The method of manufacturing the multi-layer circuit board of claim 1, further comprising: forming the first through hole, forming a first via hole on the first stack by using the first through hole as an alignment target After forming the second through hole, the second through hole is formed as a second conductive via on the second stacked layer, and the second conductive via is connected to the corresponding first via. The method of fabricating a multilayer circuit board according to claim 1, wherein the method of forming the first through hole and the second through hole comprises carbon dioxide laser drilling. The method of fabricating the multi-layer circuit board of claim 4, further comprising: forming a first opening on the first circuit layer before forming the first through hole, the first opening exposing the first a concentric pattern is projected onto the region of the first dielectric layer; and before the second via is formed, a second opening is formed on the second wiring layer, the first opening exposing the first concentric circle The pattern is projected onto the area of the second dielectric layer. The method for fabricating a multilayer circuit board according to claim 4, wherein the method of forming the first through hole comprises drilling a hole from an outer surface of the first stacked layer toward the substrate to form the second through The method of the hole includes drilling a hole from the outer surface of the second stacked layer toward the substrate. The method for fabricating a multilayer circuit board according to claim 4, wherein the material of the first patterned circuit layer, the first circuit layer and the second circuit layer is copper. The method of fabricating a multilayer circuit board according to claim 1, wherein the method of forming the first through hole and the second through hole comprises Direct Laser Drilling (DLD). The method for fabricating a multilayer circuit board according to claim 8, wherein the method of forming the first through hole comprises drilling a hole from an outer surface of the first stacked layer toward the substrate to form the second through The method of the hole includes drilling a hole from the outer surface of the second stacked layer toward the substrate. The method of fabricating a multi-layer circuit board according to claim 1, wherein the substrate further comprises a second through hole penetrating the substrate, the first patterned circuit layer further comprising a second through hole. a second concentric pattern, the method for fabricating the multi-layer circuit board further includes: forming an M-th stack layer over the second stack layer, comprising an M-th dielectric layer and covering the M-th dielectric layer An Mth circuit layer, wherein M is a positive integer greater than 2; forming an Mth through hole, the Mth through hole extending through the second concentric pattern from the center to the inner diameter of the first concentric circle a first to the Mth stacked layer and a region of the substrate; forming an M+1 stacked layer on the Mth stacked layer, the M+1 stacked layer including an M+1 dielectric layer and covering the An M+1 line of the M+1 dielectric layer And forming an M+1 through hole, the M+1 through hole extending through the second concentric circle pattern from the center outward to the inner diameter of the second concentric circle to the first to the M+1 Stacking layers and areas of the substrate. The method for fabricating a multilayer circuit board according to claim 10, further comprising: after forming the M through hole, patterning the Mth circuit layer by using the M through hole as a aligning target to form a first M+1 patterned circuit layer; and after forming the M+1 through hole, patterning the M+1th circuit layer with the M+1 through hole as a registration target to form an M+2 patterning Line layer. The method for fabricating a multilayer circuit board according to claim 10, further comprising: forming the M through hole, and forming an Mth through hole by the M through hole as an alignment target; After forming the M+1 through hole, forming an M+1 via hole on the M+1 stacked layer by using the M+1 through hole as an alignment target, the M+ A via hole is connected to the Mth via hole. A method of fabricating a multilayer circuit board according to claim 10, wherein M is substantially equal to or greater than 5. The method for fabricating a multilayer circuit board according to claim 10, wherein the method of forming the M through hole and the M+1 through hole comprises carbon dioxide laser drilling or direct laser drilling (Direct Laser Drilling) , DLD).